MouseCode - Mouse code for the MacroRat

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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f4xx_hal_dsi.c
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.5.0
sahilmgandhi	18:6a4db94011d3	6	* @date 06-May-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief DSI HAL module driver.
sahilmgandhi	18:6a4db94011d3	8	* This file provides firmware functions to manage the following
sahilmgandhi	18:6a4db94011d3	9	* functionalities of the DSI peripheral:
sahilmgandhi	18:6a4db94011d3	10	* + Initialization and de-initialization functions
sahilmgandhi	18:6a4db94011d3	11	* + IO operation functions
sahilmgandhi	18:6a4db94011d3	12	* + Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	13	* + Peripheral State and Errors functions
sahilmgandhi	18:6a4db94011d3	14	******************************************************************************
sahilmgandhi	18:6a4db94011d3	15	* @attention
sahilmgandhi	18:6a4db94011d3	16	*
sahilmgandhi	18:6a4db94011d3	17	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	18	*
sahilmgandhi	18:6a4db94011d3	19	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	20	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	21	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	22	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	24	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	25	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	27	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	28	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	29	*
sahilmgandhi	18:6a4db94011d3	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	40	*
sahilmgandhi	18:6a4db94011d3	41	******************************************************************************
sahilmgandhi	18:6a4db94011d3	42	*/
sahilmgandhi	18:6a4db94011d3	43
sahilmgandhi	18:6a4db94011d3	44	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	45	#include "stm32f4xx_hal.h"
sahilmgandhi	18:6a4db94011d3	46
sahilmgandhi	18:6a4db94011d3	47	/** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi	18:6a4db94011d3	48	* @{
sahilmgandhi	18:6a4db94011d3	49	*/
sahilmgandhi	18:6a4db94011d3	50	/** @addtogroup DSI
sahilmgandhi	18:6a4db94011d3	51	* @{
sahilmgandhi	18:6a4db94011d3	52	*/
sahilmgandhi	18:6a4db94011d3	53
sahilmgandhi	18:6a4db94011d3	54	#ifdef HAL_DSI_MODULE_ENABLED
sahilmgandhi	18:6a4db94011d3	55
sahilmgandhi	18:6a4db94011d3	56	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	57
sahilmgandhi	18:6a4db94011d3	58	/* Private types -------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	59	/* Private defines -----------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	60	/** @addtogroup DSI_Private_Constants
sahilmgandhi	18:6a4db94011d3	61	* @{
sahilmgandhi	18:6a4db94011d3	62	*/
sahilmgandhi	18:6a4db94011d3	63	#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
sahilmgandhi	18:6a4db94011d3	64
sahilmgandhi	18:6a4db94011d3	65	#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 \| DSI_ISR0_AE1 \| DSI_ISR0_AE2 \| DSI_ISR0_AE3 \| \
sahilmgandhi	18:6a4db94011d3	66	DSI_ISR0_AE4 \| DSI_ISR0_AE5 \| DSI_ISR0_AE6 \| DSI_ISR0_AE7 \| \
sahilmgandhi	18:6a4db94011d3	67	DSI_ISR0_AE8 \| DSI_ISR0_AE9 \| DSI_ISR0_AE10 \| DSI_ISR0_AE11 \| \
sahilmgandhi	18:6a4db94011d3	68	DSI_ISR0_AE12 \| DSI_ISR0_AE13 \| DSI_ISR0_AE14 \| DSI_ISR0_AE15)
sahilmgandhi	18:6a4db94011d3	69	#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 \| DSI_ISR0_PE1 \| DSI_ISR0_PE2 \| DSI_ISR0_PE3 \| DSI_ISR0_PE4)
sahilmgandhi	18:6a4db94011d3	70	#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
sahilmgandhi	18:6a4db94011d3	71	#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
sahilmgandhi	18:6a4db94011d3	72	#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE \| DSI_ISR1_ECCME)
sahilmgandhi	18:6a4db94011d3	73	#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
sahilmgandhi	18:6a4db94011d3	74	#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
sahilmgandhi	18:6a4db94011d3	75	#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
sahilmgandhi	18:6a4db94011d3	76	#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
sahilmgandhi	18:6a4db94011d3	77	#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE \| DSI_ISR1_GPWRE \| DSI_ISR1_GPTXE \| DSI_ISR1_GPRDE \| DSI_ISR1_GPRXE)
sahilmgandhi	18:6a4db94011d3	78	/**
sahilmgandhi	18:6a4db94011d3	79	* @}
sahilmgandhi	18:6a4db94011d3	80	*/
sahilmgandhi	18:6a4db94011d3	81
sahilmgandhi	18:6a4db94011d3	82	/* Private variables ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	83	/* Private constants ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	84	/* Private macros ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	85	/* Private function prototypes -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	86	static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
sahilmgandhi	18:6a4db94011d3	87
sahilmgandhi	18:6a4db94011d3	88	/* Private functions ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	89	/**
sahilmgandhi	18:6a4db94011d3	90	* @brief Generic DSI packet header configuration
sahilmgandhi	18:6a4db94011d3	91	* @param DSIx: Pointer to DSI register base
sahilmgandhi	18:6a4db94011d3	92	* @param ChannelID: Virtual channel ID of the header packet
sahilmgandhi	18:6a4db94011d3	93	* @param DataType: Packet data type of the header packet
sahilmgandhi	18:6a4db94011d3	94	* This parameter can be any value of :
sahilmgandhi	18:6a4db94011d3	95	* @ref DSI_SHORT_WRITE_PKT_Data_Type
sahilmgandhi	18:6a4db94011d3	96	* or @ref DSI_LONG_WRITE_PKT_Data_Type
sahilmgandhi	18:6a4db94011d3	97	* or @ref DSI_SHORT_READ_PKT_Data_Type
sahilmgandhi	18:6a4db94011d3	98	* or DSI_MAX_RETURN_PKT_SIZE
sahilmgandhi	18:6a4db94011d3	99	* @param Data0: Word count LSB
sahilmgandhi	18:6a4db94011d3	100	* @param Data1: Word count MSB
sahilmgandhi	18:6a4db94011d3	101	* @retval None
sahilmgandhi	18:6a4db94011d3	102	*/
sahilmgandhi	18:6a4db94011d3	103	static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
sahilmgandhi	18:6a4db94011d3	104	uint32_t ChannelID,
sahilmgandhi	18:6a4db94011d3	105	uint32_t DataType,
sahilmgandhi	18:6a4db94011d3	106	uint32_t Data0,
sahilmgandhi	18:6a4db94011d3	107	uint32_t Data1)
sahilmgandhi	18:6a4db94011d3	108	{
sahilmgandhi	18:6a4db94011d3	109	/* Update the DSI packet header with new information */
sahilmgandhi	18:6a4db94011d3	110	DSIx->GHCR = (DataType \| (ChannelID<<6U) \| (Data0<<8U) \| (Data1<<16U));
sahilmgandhi	18:6a4db94011d3	111	}
sahilmgandhi	18:6a4db94011d3	112
sahilmgandhi	18:6a4db94011d3	113	/* Exported functions --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	114	/** @addtogroup DSI_Exported_Functions
sahilmgandhi	18:6a4db94011d3	115	* @{
sahilmgandhi	18:6a4db94011d3	116	*/
sahilmgandhi	18:6a4db94011d3	117
sahilmgandhi	18:6a4db94011d3	118	/** @defgroup DSI_Group1 Initialization and Configuration functions
sahilmgandhi	18:6a4db94011d3	119	* @brief Initialization and Configuration functions
sahilmgandhi	18:6a4db94011d3	120	*
sahilmgandhi	18:6a4db94011d3	121	@verbatim
sahilmgandhi	18:6a4db94011d3	122	===============================================================================
sahilmgandhi	18:6a4db94011d3	123	##### Initialization and Configuration functions #####
sahilmgandhi	18:6a4db94011d3	124	===============================================================================
sahilmgandhi	18:6a4db94011d3	125	[..] This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	126	(+) Initialize and configure the DSI
sahilmgandhi	18:6a4db94011d3	127	(+) De-initialize the DSI
sahilmgandhi	18:6a4db94011d3	128
sahilmgandhi	18:6a4db94011d3	129	@endverbatim
sahilmgandhi	18:6a4db94011d3	130	* @{
sahilmgandhi	18:6a4db94011d3	131	*/
sahilmgandhi	18:6a4db94011d3	132
sahilmgandhi	18:6a4db94011d3	133	/**
sahilmgandhi	18:6a4db94011d3	134	* @brief Initializes the DSI according to the specified
sahilmgandhi	18:6a4db94011d3	135	* parameters in the DSI_InitTypeDef and create the associated handle.
sahilmgandhi	18:6a4db94011d3	136	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	137	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	138	* @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	139	* the PLL Clock structure definition for the DSI.
sahilmgandhi	18:6a4db94011d3	140	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	141	*/
sahilmgandhi	18:6a4db94011d3	142	HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef hdsi, DSI_PLLInitTypeDef PLLInit)
sahilmgandhi	18:6a4db94011d3	143	{
sahilmgandhi	18:6a4db94011d3	144	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	145	uint32_t unitIntervalx4 = 0U;
sahilmgandhi	18:6a4db94011d3	146	uint32_t tempIDF = 0U;
sahilmgandhi	18:6a4db94011d3	147
sahilmgandhi	18:6a4db94011d3	148	/* Check the DSI handle allocation */
sahilmgandhi	18:6a4db94011d3	149	if(hdsi == NULL)
sahilmgandhi	18:6a4db94011d3	150	{
sahilmgandhi	18:6a4db94011d3	151	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	152	}
sahilmgandhi	18:6a4db94011d3	153
sahilmgandhi	18:6a4db94011d3	154	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	155	assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
sahilmgandhi	18:6a4db94011d3	156	assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
sahilmgandhi	18:6a4db94011d3	157	assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
sahilmgandhi	18:6a4db94011d3	158	assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
sahilmgandhi	18:6a4db94011d3	159	assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
sahilmgandhi	18:6a4db94011d3	160
sahilmgandhi	18:6a4db94011d3	161	if(hdsi->State == HAL_DSI_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	162	{
sahilmgandhi	18:6a4db94011d3	163	/* Initialize the low level hardware */
sahilmgandhi	18:6a4db94011d3	164	HAL_DSI_MspInit(hdsi);
sahilmgandhi	18:6a4db94011d3	165	}
sahilmgandhi	18:6a4db94011d3	166
sahilmgandhi	18:6a4db94011d3	167	/* Change DSI peripheral state */
sahilmgandhi	18:6a4db94011d3	168	hdsi->State = HAL_DSI_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	169
sahilmgandhi	18:6a4db94011d3	170	/************** Turn on the regulator and enable the DSI PLL **************/
sahilmgandhi	18:6a4db94011d3	171
sahilmgandhi	18:6a4db94011d3	172	/* Enable the regulator */
sahilmgandhi	18:6a4db94011d3	173	__HAL_DSI_REG_ENABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	174
sahilmgandhi	18:6a4db94011d3	175	/* Get tick */
sahilmgandhi	18:6a4db94011d3	176	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	177
sahilmgandhi	18:6a4db94011d3	178	/* Wait until the regulator is ready */
sahilmgandhi	18:6a4db94011d3	179	while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
sahilmgandhi	18:6a4db94011d3	180	{
sahilmgandhi	18:6a4db94011d3	181	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	182	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	183	{
sahilmgandhi	18:6a4db94011d3	184	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	185	}
sahilmgandhi	18:6a4db94011d3	186	}
sahilmgandhi	18:6a4db94011d3	187
sahilmgandhi	18:6a4db94011d3	188	/* Set the PLL division factors */
sahilmgandhi	18:6a4db94011d3	189	hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV \| DSI_WRPCR_PLL_IDF \| DSI_WRPCR_PLL_ODF);
sahilmgandhi	18:6a4db94011d3	190	hdsi->Instance->WRPCR \|= (((PLLInit->PLLNDIV)<<2U) \| ((PLLInit->PLLIDF)<<11U) \| ((PLLInit->PLLODF)<<16U));
sahilmgandhi	18:6a4db94011d3	191
sahilmgandhi	18:6a4db94011d3	192	/* Enable the DSI PLL */
sahilmgandhi	18:6a4db94011d3	193	__HAL_DSI_PLL_ENABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	194
sahilmgandhi	18:6a4db94011d3	195	/* Get tick */
sahilmgandhi	18:6a4db94011d3	196	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	197
sahilmgandhi	18:6a4db94011d3	198	/* Wait for the lock of the PLL */
sahilmgandhi	18:6a4db94011d3	199	while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
sahilmgandhi	18:6a4db94011d3	200	{
sahilmgandhi	18:6a4db94011d3	201	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	202	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	203	{
sahilmgandhi	18:6a4db94011d3	204	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	205	}
sahilmgandhi	18:6a4db94011d3	206	}
sahilmgandhi	18:6a4db94011d3	207
sahilmgandhi	18:6a4db94011d3	208	/************************* Set the PHY parameters *************************/
sahilmgandhi	18:6a4db94011d3	209
sahilmgandhi	18:6a4db94011d3	210	/* D-PHY clock and digital enable*/
sahilmgandhi	18:6a4db94011d3	211	hdsi->Instance->PCTLR \|= (DSI_PCTLR_CKE \| DSI_PCTLR_DEN);
sahilmgandhi	18:6a4db94011d3	212
sahilmgandhi	18:6a4db94011d3	213	/* Clock lane configuration */
sahilmgandhi	18:6a4db94011d3	214	hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC \| DSI_CLCR_ACR);
sahilmgandhi	18:6a4db94011d3	215	hdsi->Instance->CLCR \|= (DSI_CLCR_DPCC \| hdsi->Init.AutomaticClockLaneControl);
sahilmgandhi	18:6a4db94011d3	216
sahilmgandhi	18:6a4db94011d3	217	/* Configure the number of active data lanes */
sahilmgandhi	18:6a4db94011d3	218	hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
sahilmgandhi	18:6a4db94011d3	219	hdsi->Instance->PCONFR \|= hdsi->Init.NumberOfLanes;
sahilmgandhi	18:6a4db94011d3	220
sahilmgandhi	18:6a4db94011d3	221	/********************** Set the DSI clock parameters **********************/
sahilmgandhi	18:6a4db94011d3	222
sahilmgandhi	18:6a4db94011d3	223	/* Set the TX escape clock division factor */
sahilmgandhi	18:6a4db94011d3	224	hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
sahilmgandhi	18:6a4db94011d3	225	hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv;
sahilmgandhi	18:6a4db94011d3	226
sahilmgandhi	18:6a4db94011d3	227	/* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
sahilmgandhi	18:6a4db94011d3	228	/* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
sahilmgandhi	18:6a4db94011d3	229	/* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
sahilmgandhi	18:6a4db94011d3	230	tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
sahilmgandhi	18:6a4db94011d3	231	unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
sahilmgandhi	18:6a4db94011d3	232
sahilmgandhi	18:6a4db94011d3	233	/* Set the bit period in high-speed mode */
sahilmgandhi	18:6a4db94011d3	234	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
sahilmgandhi	18:6a4db94011d3	235	hdsi->Instance->WPCR[0U] \|= unitIntervalx4;
sahilmgandhi	18:6a4db94011d3	236
sahilmgandhi	18:6a4db94011d3	237	/**************************** Error management ***************************/
sahilmgandhi	18:6a4db94011d3	238
sahilmgandhi	18:6a4db94011d3	239	/* Disable all error interrupts and reset the Error Mask */
sahilmgandhi	18:6a4db94011d3	240	hdsi->Instance->IER[0U] = 0U;
sahilmgandhi	18:6a4db94011d3	241	hdsi->Instance->IER[1U] = 0U;
sahilmgandhi	18:6a4db94011d3	242	hdsi->ErrorMsk = 0U;
sahilmgandhi	18:6a4db94011d3	243
sahilmgandhi	18:6a4db94011d3	244	/* Initialise the error code */
sahilmgandhi	18:6a4db94011d3	245	hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	246
sahilmgandhi	18:6a4db94011d3	247	/* Initialize the DSI state*/
sahilmgandhi	18:6a4db94011d3	248	hdsi->State = HAL_DSI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	249
sahilmgandhi	18:6a4db94011d3	250	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	251	}
sahilmgandhi	18:6a4db94011d3	252
sahilmgandhi	18:6a4db94011d3	253	/**
sahilmgandhi	18:6a4db94011d3	254	* @brief De-initializes the DSI peripheral registers to their default reset
sahilmgandhi	18:6a4db94011d3	255	* values.
sahilmgandhi	18:6a4db94011d3	256	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	257	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	258	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	259	*/
sahilmgandhi	18:6a4db94011d3	260	HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	261	{
sahilmgandhi	18:6a4db94011d3	262	/* Check the DSI handle allocation */
sahilmgandhi	18:6a4db94011d3	263	if(hdsi == NULL)
sahilmgandhi	18:6a4db94011d3	264	{
sahilmgandhi	18:6a4db94011d3	265	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	266	}
sahilmgandhi	18:6a4db94011d3	267
sahilmgandhi	18:6a4db94011d3	268	/* Change DSI peripheral state */
sahilmgandhi	18:6a4db94011d3	269	hdsi->State = HAL_DSI_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	270
sahilmgandhi	18:6a4db94011d3	271	/* Disable the DSI wrapper */
sahilmgandhi	18:6a4db94011d3	272	__HAL_DSI_WRAPPER_DISABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	273
sahilmgandhi	18:6a4db94011d3	274	/* Disable the DSI host */
sahilmgandhi	18:6a4db94011d3	275	__HAL_DSI_DISABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	276
sahilmgandhi	18:6a4db94011d3	277	/* D-PHY clock and digital disable */
sahilmgandhi	18:6a4db94011d3	278	hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE \| DSI_PCTLR_DEN);
sahilmgandhi	18:6a4db94011d3	279
sahilmgandhi	18:6a4db94011d3	280	/* Turn off the DSI PLL */
sahilmgandhi	18:6a4db94011d3	281	__HAL_DSI_PLL_DISABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	282
sahilmgandhi	18:6a4db94011d3	283	/* Disable the regulator */
sahilmgandhi	18:6a4db94011d3	284	__HAL_DSI_REG_DISABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	285
sahilmgandhi	18:6a4db94011d3	286	/* DeInit the low level hardware */
sahilmgandhi	18:6a4db94011d3	287	HAL_DSI_MspDeInit(hdsi);
sahilmgandhi	18:6a4db94011d3	288
sahilmgandhi	18:6a4db94011d3	289	/* Initialise the error code */
sahilmgandhi	18:6a4db94011d3	290	hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	291
sahilmgandhi	18:6a4db94011d3	292	/* Initialize the DSI state*/
sahilmgandhi	18:6a4db94011d3	293	hdsi->State = HAL_DSI_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	294
sahilmgandhi	18:6a4db94011d3	295	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	296	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	297
sahilmgandhi	18:6a4db94011d3	298	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	299	}
sahilmgandhi	18:6a4db94011d3	300
sahilmgandhi	18:6a4db94011d3	301	/**
sahilmgandhi	18:6a4db94011d3	302	* @brief Return the DSI error code
sahilmgandhi	18:6a4db94011d3	303	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	304	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	305	* @retval DSI Error Code
sahilmgandhi	18:6a4db94011d3	306	*/
sahilmgandhi	18:6a4db94011d3	307	uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	308	{
sahilmgandhi	18:6a4db94011d3	309	/* Get the error code */
sahilmgandhi	18:6a4db94011d3	310	return hdsi->ErrorCode;
sahilmgandhi	18:6a4db94011d3	311	}
sahilmgandhi	18:6a4db94011d3	312
sahilmgandhi	18:6a4db94011d3	313	/**
sahilmgandhi	18:6a4db94011d3	314	* @brief Enable the error monitor flags
sahilmgandhi	18:6a4db94011d3	315	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	316	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	317	* @param ActiveErrors: indicates which error interrupts will be enabled.
sahilmgandhi	18:6a4db94011d3	318	* This parameter can be any combination of @ref DSI_Error_Data_Type.
sahilmgandhi	18:6a4db94011d3	319	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	320	*/
sahilmgandhi	18:6a4db94011d3	321	HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
sahilmgandhi	18:6a4db94011d3	322	{
sahilmgandhi	18:6a4db94011d3	323	/* Process locked */
sahilmgandhi	18:6a4db94011d3	324	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	325
sahilmgandhi	18:6a4db94011d3	326	hdsi->Instance->IER[0U] = 0U;
sahilmgandhi	18:6a4db94011d3	327	hdsi->Instance->IER[1U] = 0U;
sahilmgandhi	18:6a4db94011d3	328
sahilmgandhi	18:6a4db94011d3	329	/* Store active errors to the handle */
sahilmgandhi	18:6a4db94011d3	330	hdsi->ErrorMsk = ActiveErrors;
sahilmgandhi	18:6a4db94011d3	331
sahilmgandhi	18:6a4db94011d3	332	if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
sahilmgandhi	18:6a4db94011d3	333	{
sahilmgandhi	18:6a4db94011d3	334	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	335	hdsi->Instance->IER[0U] \|= DSI_ERROR_ACK_MASK;
sahilmgandhi	18:6a4db94011d3	336	}
sahilmgandhi	18:6a4db94011d3	337
sahilmgandhi	18:6a4db94011d3	338	if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET)
sahilmgandhi	18:6a4db94011d3	339	{
sahilmgandhi	18:6a4db94011d3	340	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	341	hdsi->Instance->IER[0U] \|= DSI_ERROR_PHY_MASK;
sahilmgandhi	18:6a4db94011d3	342	}
sahilmgandhi	18:6a4db94011d3	343
sahilmgandhi	18:6a4db94011d3	344	if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
sahilmgandhi	18:6a4db94011d3	345	{
sahilmgandhi	18:6a4db94011d3	346	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	347	hdsi->Instance->IER[1U] \|= DSI_ERROR_TX_MASK;
sahilmgandhi	18:6a4db94011d3	348	}
sahilmgandhi	18:6a4db94011d3	349
sahilmgandhi	18:6a4db94011d3	350	if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
sahilmgandhi	18:6a4db94011d3	351	{
sahilmgandhi	18:6a4db94011d3	352	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	353	hdsi->Instance->IER[1U] \|= DSI_ERROR_RX_MASK;
sahilmgandhi	18:6a4db94011d3	354	}
sahilmgandhi	18:6a4db94011d3	355
sahilmgandhi	18:6a4db94011d3	356	if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
sahilmgandhi	18:6a4db94011d3	357	{
sahilmgandhi	18:6a4db94011d3	358	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	359	hdsi->Instance->IER[1U] \|= DSI_ERROR_ECC_MASK;
sahilmgandhi	18:6a4db94011d3	360	}
sahilmgandhi	18:6a4db94011d3	361
sahilmgandhi	18:6a4db94011d3	362	if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
sahilmgandhi	18:6a4db94011d3	363	{
sahilmgandhi	18:6a4db94011d3	364	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	365	hdsi->Instance->IER[1U] \|= DSI_ERROR_CRC_MASK;
sahilmgandhi	18:6a4db94011d3	366	}
sahilmgandhi	18:6a4db94011d3	367
sahilmgandhi	18:6a4db94011d3	368	if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
sahilmgandhi	18:6a4db94011d3	369	{
sahilmgandhi	18:6a4db94011d3	370	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	371	hdsi->Instance->IER[1U] \|= DSI_ERROR_PSE_MASK;
sahilmgandhi	18:6a4db94011d3	372	}
sahilmgandhi	18:6a4db94011d3	373
sahilmgandhi	18:6a4db94011d3	374	if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
sahilmgandhi	18:6a4db94011d3	375	{
sahilmgandhi	18:6a4db94011d3	376	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	377	hdsi->Instance->IER[1U] \|= DSI_ERROR_EOT_MASK;
sahilmgandhi	18:6a4db94011d3	378	}
sahilmgandhi	18:6a4db94011d3	379
sahilmgandhi	18:6a4db94011d3	380	if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
sahilmgandhi	18:6a4db94011d3	381	{
sahilmgandhi	18:6a4db94011d3	382	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	383	hdsi->Instance->IER[1U] \|= DSI_ERROR_OVF_MASK;
sahilmgandhi	18:6a4db94011d3	384	}
sahilmgandhi	18:6a4db94011d3	385
sahilmgandhi	18:6a4db94011d3	386	if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
sahilmgandhi	18:6a4db94011d3	387	{
sahilmgandhi	18:6a4db94011d3	388	/* Enable the interrupt generation on selected errors */
sahilmgandhi	18:6a4db94011d3	389	hdsi->Instance->IER[1U] \|= DSI_ERROR_GEN_MASK;
sahilmgandhi	18:6a4db94011d3	390	}
sahilmgandhi	18:6a4db94011d3	391
sahilmgandhi	18:6a4db94011d3	392	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	393	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	394
sahilmgandhi	18:6a4db94011d3	395	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	396	}
sahilmgandhi	18:6a4db94011d3	397
sahilmgandhi	18:6a4db94011d3	398	/**
sahilmgandhi	18:6a4db94011d3	399	* @brief Initializes the DSI MSP.
sahilmgandhi	18:6a4db94011d3	400	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	401	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	402	* @retval None
sahilmgandhi	18:6a4db94011d3	403	*/
sahilmgandhi	18:6a4db94011d3	404	__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
sahilmgandhi	18:6a4db94011d3	405	{
sahilmgandhi	18:6a4db94011d3	406	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	407	UNUSED(hdsi);
sahilmgandhi	18:6a4db94011d3	408	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	409	the HAL_DSI_MspInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	410	*/
sahilmgandhi	18:6a4db94011d3	411	}
sahilmgandhi	18:6a4db94011d3	412
sahilmgandhi	18:6a4db94011d3	413	/**
sahilmgandhi	18:6a4db94011d3	414	* @brief De-initializes the DSI MSP.
sahilmgandhi	18:6a4db94011d3	415	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	416	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	417	* @retval None
sahilmgandhi	18:6a4db94011d3	418	*/
sahilmgandhi	18:6a4db94011d3	419	__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
sahilmgandhi	18:6a4db94011d3	420	{
sahilmgandhi	18:6a4db94011d3	421	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	422	UNUSED(hdsi);
sahilmgandhi	18:6a4db94011d3	423	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	424	the HAL_DSI_MspDeInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	425	*/
sahilmgandhi	18:6a4db94011d3	426	}
sahilmgandhi	18:6a4db94011d3	427
sahilmgandhi	18:6a4db94011d3	428	/**
sahilmgandhi	18:6a4db94011d3	429	* @}
sahilmgandhi	18:6a4db94011d3	430	*/
sahilmgandhi	18:6a4db94011d3	431
sahilmgandhi	18:6a4db94011d3	432	/** @defgroup DSI_Group2 IO operation functions
sahilmgandhi	18:6a4db94011d3	433	* @brief IO operation functions
sahilmgandhi	18:6a4db94011d3	434	*
sahilmgandhi	18:6a4db94011d3	435	@verbatim
sahilmgandhi	18:6a4db94011d3	436	===============================================================================
sahilmgandhi	18:6a4db94011d3	437	##### IO operation functions #####
sahilmgandhi	18:6a4db94011d3	438	===============================================================================
sahilmgandhi	18:6a4db94011d3	439	[..] This section provides function allowing to:
sahilmgandhi	18:6a4db94011d3	440	(+) Handle DSI interrupt request
sahilmgandhi	18:6a4db94011d3	441
sahilmgandhi	18:6a4db94011d3	442	@endverbatim
sahilmgandhi	18:6a4db94011d3	443	* @{
sahilmgandhi	18:6a4db94011d3	444	*/
sahilmgandhi	18:6a4db94011d3	445	/**
sahilmgandhi	18:6a4db94011d3	446	* @brief Handles DSI interrupt request.
sahilmgandhi	18:6a4db94011d3	447	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	448	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	449	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	450	*/
sahilmgandhi	18:6a4db94011d3	451	void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	452	{
sahilmgandhi	18:6a4db94011d3	453	uint32_t ErrorStatus0, ErrorStatus1;
sahilmgandhi	18:6a4db94011d3	454
sahilmgandhi	18:6a4db94011d3	455	/* Tearing Effect Interrupt management ***************************************/
sahilmgandhi	18:6a4db94011d3	456	if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
sahilmgandhi	18:6a4db94011d3	457	{
sahilmgandhi	18:6a4db94011d3	458	if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
sahilmgandhi	18:6a4db94011d3	459	{
sahilmgandhi	18:6a4db94011d3	460	/* Clear the Tearing Effect Interrupt Flag */
sahilmgandhi	18:6a4db94011d3	461	__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
sahilmgandhi	18:6a4db94011d3	462
sahilmgandhi	18:6a4db94011d3	463	/* Tearing Effect Callback */
sahilmgandhi	18:6a4db94011d3	464	HAL_DSI_TearingEffectCallback(hdsi);
sahilmgandhi	18:6a4db94011d3	465	}
sahilmgandhi	18:6a4db94011d3	466	}
sahilmgandhi	18:6a4db94011d3	467
sahilmgandhi	18:6a4db94011d3	468	/* End of Refresh Interrupt management ***************************************/
sahilmgandhi	18:6a4db94011d3	469	if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
sahilmgandhi	18:6a4db94011d3	470	{
sahilmgandhi	18:6a4db94011d3	471	if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
sahilmgandhi	18:6a4db94011d3	472	{
sahilmgandhi	18:6a4db94011d3	473	/* Clear the End of Refresh Interrupt Flag */
sahilmgandhi	18:6a4db94011d3	474	__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
sahilmgandhi	18:6a4db94011d3	475
sahilmgandhi	18:6a4db94011d3	476	/* End of Refresh Callback */
sahilmgandhi	18:6a4db94011d3	477	HAL_DSI_EndOfRefreshCallback(hdsi);
sahilmgandhi	18:6a4db94011d3	478	}
sahilmgandhi	18:6a4db94011d3	479	}
sahilmgandhi	18:6a4db94011d3	480
sahilmgandhi	18:6a4db94011d3	481	/* Error Interrupts management ***********************************************/
sahilmgandhi	18:6a4db94011d3	482	if(hdsi->ErrorMsk != 0U)
sahilmgandhi	18:6a4db94011d3	483	{
sahilmgandhi	18:6a4db94011d3	484	ErrorStatus0 = hdsi->Instance->ISR[0U];
sahilmgandhi	18:6a4db94011d3	485	ErrorStatus0 &= hdsi->Instance->IER[0U];
sahilmgandhi	18:6a4db94011d3	486	ErrorStatus1 = hdsi->Instance->ISR[1U];
sahilmgandhi	18:6a4db94011d3	487	ErrorStatus1 &= hdsi->Instance->IER[1U];
sahilmgandhi	18:6a4db94011d3	488
sahilmgandhi	18:6a4db94011d3	489	if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	490	{
sahilmgandhi	18:6a4db94011d3	491	hdsi->ErrorCode \|= HAL_DSI_ERROR_ACK;
sahilmgandhi	18:6a4db94011d3	492	}
sahilmgandhi	18:6a4db94011d3	493
sahilmgandhi	18:6a4db94011d3	494	if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	495	{
sahilmgandhi	18:6a4db94011d3	496	hdsi->ErrorCode \|= HAL_DSI_ERROR_PHY;
sahilmgandhi	18:6a4db94011d3	497	}
sahilmgandhi	18:6a4db94011d3	498
sahilmgandhi	18:6a4db94011d3	499	if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	500	{
sahilmgandhi	18:6a4db94011d3	501	hdsi->ErrorCode \|= HAL_DSI_ERROR_TX;
sahilmgandhi	18:6a4db94011d3	502	}
sahilmgandhi	18:6a4db94011d3	503
sahilmgandhi	18:6a4db94011d3	504	if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	505	{
sahilmgandhi	18:6a4db94011d3	506	hdsi->ErrorCode \|= HAL_DSI_ERROR_RX;
sahilmgandhi	18:6a4db94011d3	507	}
sahilmgandhi	18:6a4db94011d3	508
sahilmgandhi	18:6a4db94011d3	509	if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	510	{
sahilmgandhi	18:6a4db94011d3	511	hdsi->ErrorCode \|= HAL_DSI_ERROR_ECC;
sahilmgandhi	18:6a4db94011d3	512	}
sahilmgandhi	18:6a4db94011d3	513
sahilmgandhi	18:6a4db94011d3	514	if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	515	{
sahilmgandhi	18:6a4db94011d3	516	hdsi->ErrorCode \|= HAL_DSI_ERROR_CRC;
sahilmgandhi	18:6a4db94011d3	517	}
sahilmgandhi	18:6a4db94011d3	518
sahilmgandhi	18:6a4db94011d3	519	if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	520	{
sahilmgandhi	18:6a4db94011d3	521	hdsi->ErrorCode \|= HAL_DSI_ERROR_PSE;
sahilmgandhi	18:6a4db94011d3	522	}
sahilmgandhi	18:6a4db94011d3	523
sahilmgandhi	18:6a4db94011d3	524	if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	525	{
sahilmgandhi	18:6a4db94011d3	526	hdsi->ErrorCode \|= HAL_DSI_ERROR_EOT;
sahilmgandhi	18:6a4db94011d3	527	}
sahilmgandhi	18:6a4db94011d3	528
sahilmgandhi	18:6a4db94011d3	529	if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	530	{
sahilmgandhi	18:6a4db94011d3	531	hdsi->ErrorCode \|= HAL_DSI_ERROR_OVF;
sahilmgandhi	18:6a4db94011d3	532	}
sahilmgandhi	18:6a4db94011d3	533
sahilmgandhi	18:6a4db94011d3	534	if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
sahilmgandhi	18:6a4db94011d3	535	{
sahilmgandhi	18:6a4db94011d3	536	hdsi->ErrorCode \|= HAL_DSI_ERROR_GEN;
sahilmgandhi	18:6a4db94011d3	537	}
sahilmgandhi	18:6a4db94011d3	538
sahilmgandhi	18:6a4db94011d3	539	/* Check only selected errors */
sahilmgandhi	18:6a4db94011d3	540	if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	541	{
sahilmgandhi	18:6a4db94011d3	542	/* DSI error interrupt user callback */
sahilmgandhi	18:6a4db94011d3	543	HAL_DSI_ErrorCallback(hdsi);
sahilmgandhi	18:6a4db94011d3	544	}
sahilmgandhi	18:6a4db94011d3	545	}
sahilmgandhi	18:6a4db94011d3	546	}
sahilmgandhi	18:6a4db94011d3	547
sahilmgandhi	18:6a4db94011d3	548	/**
sahilmgandhi	18:6a4db94011d3	549	* @brief Tearing Effect DSI callback.
sahilmgandhi	18:6a4db94011d3	550	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	551	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	552	* @retval None
sahilmgandhi	18:6a4db94011d3	553	*/
sahilmgandhi	18:6a4db94011d3	554	__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	555	{
sahilmgandhi	18:6a4db94011d3	556	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	557	UNUSED(hdsi);
sahilmgandhi	18:6a4db94011d3	558	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	559	the HAL_DSI_TearingEffectCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	560	*/
sahilmgandhi	18:6a4db94011d3	561	}
sahilmgandhi	18:6a4db94011d3	562
sahilmgandhi	18:6a4db94011d3	563	/**
sahilmgandhi	18:6a4db94011d3	564	* @brief End of Refresh DSI callback.
sahilmgandhi	18:6a4db94011d3	565	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	566	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	567	* @retval None
sahilmgandhi	18:6a4db94011d3	568	*/
sahilmgandhi	18:6a4db94011d3	569	__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	570	{
sahilmgandhi	18:6a4db94011d3	571	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	572	UNUSED(hdsi);
sahilmgandhi	18:6a4db94011d3	573	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	574	the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	575	*/
sahilmgandhi	18:6a4db94011d3	576	}
sahilmgandhi	18:6a4db94011d3	577
sahilmgandhi	18:6a4db94011d3	578	/**
sahilmgandhi	18:6a4db94011d3	579	* @brief Operation Error DSI callback.
sahilmgandhi	18:6a4db94011d3	580	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	581	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	582	* @retval None
sahilmgandhi	18:6a4db94011d3	583	*/
sahilmgandhi	18:6a4db94011d3	584	__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	585	{
sahilmgandhi	18:6a4db94011d3	586	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	587	UNUSED(hdsi);
sahilmgandhi	18:6a4db94011d3	588	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	589	the HAL_DSI_ErrorCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	590	*/
sahilmgandhi	18:6a4db94011d3	591	}
sahilmgandhi	18:6a4db94011d3	592
sahilmgandhi	18:6a4db94011d3	593	/**
sahilmgandhi	18:6a4db94011d3	594	* @}
sahilmgandhi	18:6a4db94011d3	595	*/
sahilmgandhi	18:6a4db94011d3	596
sahilmgandhi	18:6a4db94011d3	597	/** @defgroup DSI_Group3 Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	598	* @brief Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	599	*
sahilmgandhi	18:6a4db94011d3	600	@verbatim
sahilmgandhi	18:6a4db94011d3	601	===============================================================================
sahilmgandhi	18:6a4db94011d3	602	##### Peripheral Control functions #####
sahilmgandhi	18:6a4db94011d3	603	===============================================================================
sahilmgandhi	18:6a4db94011d3	604	[..] This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	605	(+)
sahilmgandhi	18:6a4db94011d3	606	(+)
sahilmgandhi	18:6a4db94011d3	607	(+)
sahilmgandhi	18:6a4db94011d3	608
sahilmgandhi	18:6a4db94011d3	609	@endverbatim
sahilmgandhi	18:6a4db94011d3	610	* @{
sahilmgandhi	18:6a4db94011d3	611	*/
sahilmgandhi	18:6a4db94011d3	612
sahilmgandhi	18:6a4db94011d3	613	/**
sahilmgandhi	18:6a4db94011d3	614	* @brief Configure the Generic interface read-back Virtual Channel ID.
sahilmgandhi	18:6a4db94011d3	615	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	616	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	617	* @param VirtualChannelID: Virtual channel ID
sahilmgandhi	18:6a4db94011d3	618	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	619	*/
sahilmgandhi	18:6a4db94011d3	620	HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
sahilmgandhi	18:6a4db94011d3	621	{
sahilmgandhi	18:6a4db94011d3	622	/* Process locked */
sahilmgandhi	18:6a4db94011d3	623	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	624
sahilmgandhi	18:6a4db94011d3	625	/* Update the GVCID register */
sahilmgandhi	18:6a4db94011d3	626	hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
sahilmgandhi	18:6a4db94011d3	627	hdsi->Instance->GVCIDR \|= VirtualChannelID;
sahilmgandhi	18:6a4db94011d3	628
sahilmgandhi	18:6a4db94011d3	629	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	630	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	631
sahilmgandhi	18:6a4db94011d3	632	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	633	}
sahilmgandhi	18:6a4db94011d3	634
sahilmgandhi	18:6a4db94011d3	635	/**
sahilmgandhi	18:6a4db94011d3	636	* @brief Select video mode and configure the corresponding parameters
sahilmgandhi	18:6a4db94011d3	637	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	638	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	639	* @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	640	* the DSI video mode configuration parameters
sahilmgandhi	18:6a4db94011d3	641	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	642	*/
sahilmgandhi	18:6a4db94011d3	643	HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef hdsi, DSI_VidCfgTypeDef VidCfg)
sahilmgandhi	18:6a4db94011d3	644	{
sahilmgandhi	18:6a4db94011d3	645	/* Process locked */
sahilmgandhi	18:6a4db94011d3	646	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	647
sahilmgandhi	18:6a4db94011d3	648	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	649	assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
sahilmgandhi	18:6a4db94011d3	650	assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
sahilmgandhi	18:6a4db94011d3	651	assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
sahilmgandhi	18:6a4db94011d3	652	assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
sahilmgandhi	18:6a4db94011d3	653	assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
sahilmgandhi	18:6a4db94011d3	654	assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
sahilmgandhi	18:6a4db94011d3	655	assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
sahilmgandhi	18:6a4db94011d3	656	assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
sahilmgandhi	18:6a4db94011d3	657	assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
sahilmgandhi	18:6a4db94011d3	658	assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
sahilmgandhi	18:6a4db94011d3	659	assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
sahilmgandhi	18:6a4db94011d3	660	assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
sahilmgandhi	18:6a4db94011d3	661	assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
sahilmgandhi	18:6a4db94011d3	662	/* Check the LooselyPacked variant only in 18-bit mode */
sahilmgandhi	18:6a4db94011d3	663	if(VidCfg->ColorCoding == DSI_RGB666)
sahilmgandhi	18:6a4db94011d3	664	{
sahilmgandhi	18:6a4db94011d3	665	assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
sahilmgandhi	18:6a4db94011d3	666	}
sahilmgandhi	18:6a4db94011d3	667
sahilmgandhi	18:6a4db94011d3	668	/* Select video mode by resetting CMDM and DSIM bits */
sahilmgandhi	18:6a4db94011d3	669	hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
sahilmgandhi	18:6a4db94011d3	670	hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
sahilmgandhi	18:6a4db94011d3	671
sahilmgandhi	18:6a4db94011d3	672	/* Configure the video mode transmission type */
sahilmgandhi	18:6a4db94011d3	673	hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
sahilmgandhi	18:6a4db94011d3	674	hdsi->Instance->VMCR \|= VidCfg->Mode;
sahilmgandhi	18:6a4db94011d3	675
sahilmgandhi	18:6a4db94011d3	676	/* Configure the video packet size */
sahilmgandhi	18:6a4db94011d3	677	hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
sahilmgandhi	18:6a4db94011d3	678	hdsi->Instance->VPCR \|= VidCfg->PacketSize;
sahilmgandhi	18:6a4db94011d3	679
sahilmgandhi	18:6a4db94011d3	680	/* Set the chunks number to be transmitted through the DSI link */
sahilmgandhi	18:6a4db94011d3	681	hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
sahilmgandhi	18:6a4db94011d3	682	hdsi->Instance->VCCR \|= VidCfg->NumberOfChunks;
sahilmgandhi	18:6a4db94011d3	683
sahilmgandhi	18:6a4db94011d3	684	/* Set the size of the null packet */
sahilmgandhi	18:6a4db94011d3	685	hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
sahilmgandhi	18:6a4db94011d3	686	hdsi->Instance->VNPCR \|= VidCfg->NullPacketSize;
sahilmgandhi	18:6a4db94011d3	687
sahilmgandhi	18:6a4db94011d3	688	/* Select the virtual channel for the LTDC interface traffic */
sahilmgandhi	18:6a4db94011d3	689	hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
sahilmgandhi	18:6a4db94011d3	690	hdsi->Instance->LVCIDR \|= VidCfg->VirtualChannelID;
sahilmgandhi	18:6a4db94011d3	691
sahilmgandhi	18:6a4db94011d3	692	/* Configure the polarity of control signals */
sahilmgandhi	18:6a4db94011d3	693	hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP \| DSI_LPCR_VSP \| DSI_LPCR_HSP);
sahilmgandhi	18:6a4db94011d3	694	hdsi->Instance->LPCR \|= (VidCfg->DEPolarity \| VidCfg->VSPolarity \| VidCfg->HSPolarity);
sahilmgandhi	18:6a4db94011d3	695
sahilmgandhi	18:6a4db94011d3	696	/* Select the color coding for the host */
sahilmgandhi	18:6a4db94011d3	697	hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
sahilmgandhi	18:6a4db94011d3	698	hdsi->Instance->LCOLCR \|= VidCfg->ColorCoding;
sahilmgandhi	18:6a4db94011d3	699
sahilmgandhi	18:6a4db94011d3	700	/* Select the color coding for the wrapper */
sahilmgandhi	18:6a4db94011d3	701	hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
sahilmgandhi	18:6a4db94011d3	702	hdsi->Instance->WCFGR \|= ((VidCfg->ColorCoding)<<1U);
sahilmgandhi	18:6a4db94011d3	703
sahilmgandhi	18:6a4db94011d3	704	/* Enable/disable the loosely packed variant to 18-bit configuration */
sahilmgandhi	18:6a4db94011d3	705	if(VidCfg->ColorCoding == DSI_RGB666)
sahilmgandhi	18:6a4db94011d3	706	{
sahilmgandhi	18:6a4db94011d3	707	hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
sahilmgandhi	18:6a4db94011d3	708	hdsi->Instance->LCOLCR \|= VidCfg->LooselyPacked;
sahilmgandhi	18:6a4db94011d3	709	}
sahilmgandhi	18:6a4db94011d3	710
sahilmgandhi	18:6a4db94011d3	711	/* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
sahilmgandhi	18:6a4db94011d3	712	hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
sahilmgandhi	18:6a4db94011d3	713	hdsi->Instance->VHSACR \|= VidCfg->HorizontalSyncActive;
sahilmgandhi	18:6a4db94011d3	714
sahilmgandhi	18:6a4db94011d3	715	/* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
sahilmgandhi	18:6a4db94011d3	716	hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
sahilmgandhi	18:6a4db94011d3	717	hdsi->Instance->VHBPCR \|= VidCfg->HorizontalBackPorch;
sahilmgandhi	18:6a4db94011d3	718
sahilmgandhi	18:6a4db94011d3	719	/* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
sahilmgandhi	18:6a4db94011d3	720	hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
sahilmgandhi	18:6a4db94011d3	721	hdsi->Instance->VLCR \|= VidCfg->HorizontalLine;
sahilmgandhi	18:6a4db94011d3	722
sahilmgandhi	18:6a4db94011d3	723	/* Set the Vertical Synchronization Active (VSA) */
sahilmgandhi	18:6a4db94011d3	724	hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
sahilmgandhi	18:6a4db94011d3	725	hdsi->Instance->VVSACR \|= VidCfg->VerticalSyncActive;
sahilmgandhi	18:6a4db94011d3	726
sahilmgandhi	18:6a4db94011d3	727	/* Set the Vertical Back Porch (VBP)*/
sahilmgandhi	18:6a4db94011d3	728	hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
sahilmgandhi	18:6a4db94011d3	729	hdsi->Instance->VVBPCR \|= VidCfg->VerticalBackPorch;
sahilmgandhi	18:6a4db94011d3	730
sahilmgandhi	18:6a4db94011d3	731	/* Set the Vertical Front Porch (VFP)*/
sahilmgandhi	18:6a4db94011d3	732	hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
sahilmgandhi	18:6a4db94011d3	733	hdsi->Instance->VVFPCR \|= VidCfg->VerticalFrontPorch;
sahilmgandhi	18:6a4db94011d3	734
sahilmgandhi	18:6a4db94011d3	735	/* Set the Vertical Active period*/
sahilmgandhi	18:6a4db94011d3	736	hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
sahilmgandhi	18:6a4db94011d3	737	hdsi->Instance->VVACR \|= VidCfg->VerticalActive;
sahilmgandhi	18:6a4db94011d3	738
sahilmgandhi	18:6a4db94011d3	739	/* Configure the command transmission mode */
sahilmgandhi	18:6a4db94011d3	740	hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
sahilmgandhi	18:6a4db94011d3	741	hdsi->Instance->VMCR \|= VidCfg->LPCommandEnable;
sahilmgandhi	18:6a4db94011d3	742
sahilmgandhi	18:6a4db94011d3	743	/* Low power largest packet size */
sahilmgandhi	18:6a4db94011d3	744	hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
sahilmgandhi	18:6a4db94011d3	745	hdsi->Instance->LPMCR \|= ((VidCfg->LPLargestPacketSize)<<16U);
sahilmgandhi	18:6a4db94011d3	746
sahilmgandhi	18:6a4db94011d3	747	/* Low power VACT largest packet size */
sahilmgandhi	18:6a4db94011d3	748	hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
sahilmgandhi	18:6a4db94011d3	749	hdsi->Instance->LPMCR \|= VidCfg->LPVACTLargestPacketSize;
sahilmgandhi	18:6a4db94011d3	750
sahilmgandhi	18:6a4db94011d3	751	/* Enable LP transition in HFP period */
sahilmgandhi	18:6a4db94011d3	752	hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
sahilmgandhi	18:6a4db94011d3	753	hdsi->Instance->VMCR \|= VidCfg->LPHorizontalFrontPorchEnable;
sahilmgandhi	18:6a4db94011d3	754
sahilmgandhi	18:6a4db94011d3	755	/* Enable LP transition in HBP period */
sahilmgandhi	18:6a4db94011d3	756	hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
sahilmgandhi	18:6a4db94011d3	757	hdsi->Instance->VMCR \|= VidCfg->LPHorizontalBackPorchEnable;
sahilmgandhi	18:6a4db94011d3	758
sahilmgandhi	18:6a4db94011d3	759	/* Enable LP transition in VACT period */
sahilmgandhi	18:6a4db94011d3	760	hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
sahilmgandhi	18:6a4db94011d3	761	hdsi->Instance->VMCR \|= VidCfg->LPVerticalActiveEnable;
sahilmgandhi	18:6a4db94011d3	762
sahilmgandhi	18:6a4db94011d3	763	/* Enable LP transition in VFP period */
sahilmgandhi	18:6a4db94011d3	764	hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
sahilmgandhi	18:6a4db94011d3	765	hdsi->Instance->VMCR \|= VidCfg->LPVerticalFrontPorchEnable;
sahilmgandhi	18:6a4db94011d3	766
sahilmgandhi	18:6a4db94011d3	767	/* Enable LP transition in VBP period */
sahilmgandhi	18:6a4db94011d3	768	hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
sahilmgandhi	18:6a4db94011d3	769	hdsi->Instance->VMCR \|= VidCfg->LPVerticalBackPorchEnable;
sahilmgandhi	18:6a4db94011d3	770
sahilmgandhi	18:6a4db94011d3	771	/* Enable LP transition in vertical sync period */
sahilmgandhi	18:6a4db94011d3	772	hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
sahilmgandhi	18:6a4db94011d3	773	hdsi->Instance->VMCR \|= VidCfg->LPVerticalSyncActiveEnable;
sahilmgandhi	18:6a4db94011d3	774
sahilmgandhi	18:6a4db94011d3	775	/* Enable the request for an acknowledge response at the end of a frame */
sahilmgandhi	18:6a4db94011d3	776	hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
sahilmgandhi	18:6a4db94011d3	777	hdsi->Instance->VMCR \|= VidCfg->FrameBTAAcknowledgeEnable;
sahilmgandhi	18:6a4db94011d3	778
sahilmgandhi	18:6a4db94011d3	779	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	780	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	781
sahilmgandhi	18:6a4db94011d3	782	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	783	}
sahilmgandhi	18:6a4db94011d3	784
sahilmgandhi	18:6a4db94011d3	785	/**
sahilmgandhi	18:6a4db94011d3	786	* @brief Select adapted command mode and configure the corresponding parameters
sahilmgandhi	18:6a4db94011d3	787	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	788	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	789	* @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	790	* the DSI command mode configuration parameters
sahilmgandhi	18:6a4db94011d3	791	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	792	*/
sahilmgandhi	18:6a4db94011d3	793	HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef hdsi, DSI_CmdCfgTypeDef CmdCfg)
sahilmgandhi	18:6a4db94011d3	794	{
sahilmgandhi	18:6a4db94011d3	795	/* Process locked */
sahilmgandhi	18:6a4db94011d3	796	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	797
sahilmgandhi	18:6a4db94011d3	798	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	799	assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
sahilmgandhi	18:6a4db94011d3	800	assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
sahilmgandhi	18:6a4db94011d3	801	assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
sahilmgandhi	18:6a4db94011d3	802	assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
sahilmgandhi	18:6a4db94011d3	803	assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
sahilmgandhi	18:6a4db94011d3	804	assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
sahilmgandhi	18:6a4db94011d3	805	assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
sahilmgandhi	18:6a4db94011d3	806	assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
sahilmgandhi	18:6a4db94011d3	807	assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
sahilmgandhi	18:6a4db94011d3	808
sahilmgandhi	18:6a4db94011d3	809	/* Select command mode by setting CMDM and DSIM bits */
sahilmgandhi	18:6a4db94011d3	810	hdsi->Instance->MCR \|= DSI_MCR_CMDM;
sahilmgandhi	18:6a4db94011d3	811	hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
sahilmgandhi	18:6a4db94011d3	812	hdsi->Instance->WCFGR \|= DSI_WCFGR_DSIM;
sahilmgandhi	18:6a4db94011d3	813
sahilmgandhi	18:6a4db94011d3	814	/* Select the virtual channel for the LTDC interface traffic */
sahilmgandhi	18:6a4db94011d3	815	hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
sahilmgandhi	18:6a4db94011d3	816	hdsi->Instance->LVCIDR \|= CmdCfg->VirtualChannelID;
sahilmgandhi	18:6a4db94011d3	817
sahilmgandhi	18:6a4db94011d3	818	/* Configure the polarity of control signals */
sahilmgandhi	18:6a4db94011d3	819	hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP \| DSI_LPCR_VSP \| DSI_LPCR_HSP);
sahilmgandhi	18:6a4db94011d3	820	hdsi->Instance->LPCR \|= (CmdCfg->DEPolarity \| CmdCfg->VSPolarity \| CmdCfg->HSPolarity);
sahilmgandhi	18:6a4db94011d3	821
sahilmgandhi	18:6a4db94011d3	822	/* Select the color coding for the host */
sahilmgandhi	18:6a4db94011d3	823	hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
sahilmgandhi	18:6a4db94011d3	824	hdsi->Instance->LCOLCR \|= CmdCfg->ColorCoding;
sahilmgandhi	18:6a4db94011d3	825
sahilmgandhi	18:6a4db94011d3	826	/* Select the color coding for the wrapper */
sahilmgandhi	18:6a4db94011d3	827	hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
sahilmgandhi	18:6a4db94011d3	828	hdsi->Instance->WCFGR \|= ((CmdCfg->ColorCoding)<<1U);
sahilmgandhi	18:6a4db94011d3	829
sahilmgandhi	18:6a4db94011d3	830	/* Configure the maximum allowed size for write memory command */
sahilmgandhi	18:6a4db94011d3	831	hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
sahilmgandhi	18:6a4db94011d3	832	hdsi->Instance->LCCR \|= CmdCfg->CommandSize;
sahilmgandhi	18:6a4db94011d3	833
sahilmgandhi	18:6a4db94011d3	834	/* Configure the tearing effect source and polarity and select the refresh mode */
sahilmgandhi	18:6a4db94011d3	835	hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC \| DSI_WCFGR_TEPOL \| DSI_WCFGR_AR \| DSI_WCFGR_VSPOL);
sahilmgandhi	18:6a4db94011d3	836	hdsi->Instance->WCFGR \|= (CmdCfg->TearingEffectSource \| CmdCfg->TearingEffectPolarity \| CmdCfg->AutomaticRefresh \| CmdCfg->VSyncPol);
sahilmgandhi	18:6a4db94011d3	837
sahilmgandhi	18:6a4db94011d3	838	/* Configure the tearing effect acknowledge request */
sahilmgandhi	18:6a4db94011d3	839	hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
sahilmgandhi	18:6a4db94011d3	840	hdsi->Instance->CMCR \|= CmdCfg->TEAcknowledgeRequest;
sahilmgandhi	18:6a4db94011d3	841
sahilmgandhi	18:6a4db94011d3	842	/* Enable the Tearing Effect interrupt */
sahilmgandhi	18:6a4db94011d3	843	__HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
sahilmgandhi	18:6a4db94011d3	844
sahilmgandhi	18:6a4db94011d3	845	/* Enable the End of Refresh interrupt */
sahilmgandhi	18:6a4db94011d3	846	__HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
sahilmgandhi	18:6a4db94011d3	847
sahilmgandhi	18:6a4db94011d3	848	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	849	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	850
sahilmgandhi	18:6a4db94011d3	851	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	852	}
sahilmgandhi	18:6a4db94011d3	853
sahilmgandhi	18:6a4db94011d3	854	/**
sahilmgandhi	18:6a4db94011d3	855	* @brief Configure command transmission mode: High-speed or Low-power
sahilmgandhi	18:6a4db94011d3	856	* and enable/disable acknowledge request after packet transmission
sahilmgandhi	18:6a4db94011d3	857	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	858	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	859	* @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	860	* the DSI command transmission mode configuration parameters
sahilmgandhi	18:6a4db94011d3	861	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	862	*/
sahilmgandhi	18:6a4db94011d3	863	HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef hdsi, DSI_LPCmdTypeDef LPCmd)
sahilmgandhi	18:6a4db94011d3	864	{
sahilmgandhi	18:6a4db94011d3	865	/* Process locked */
sahilmgandhi	18:6a4db94011d3	866	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	867
sahilmgandhi	18:6a4db94011d3	868	assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
sahilmgandhi	18:6a4db94011d3	869	assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
sahilmgandhi	18:6a4db94011d3	870	assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
sahilmgandhi	18:6a4db94011d3	871	assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
sahilmgandhi	18:6a4db94011d3	872	assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
sahilmgandhi	18:6a4db94011d3	873	assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
sahilmgandhi	18:6a4db94011d3	874	assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
sahilmgandhi	18:6a4db94011d3	875	assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
sahilmgandhi	18:6a4db94011d3	876	assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
sahilmgandhi	18:6a4db94011d3	877	assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
sahilmgandhi	18:6a4db94011d3	878	assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
sahilmgandhi	18:6a4db94011d3	879	assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
sahilmgandhi	18:6a4db94011d3	880	assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
sahilmgandhi	18:6a4db94011d3	881
sahilmgandhi	18:6a4db94011d3	882	/* Select High-speed or Low-power for command transmission */
sahilmgandhi	18:6a4db94011d3	883	hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX \|\
sahilmgandhi	18:6a4db94011d3	884	DSI_CMCR_GSW1TX \|\
sahilmgandhi	18:6a4db94011d3	885	DSI_CMCR_GSW2TX \|\
sahilmgandhi	18:6a4db94011d3	886	DSI_CMCR_GSR0TX \|\
sahilmgandhi	18:6a4db94011d3	887	DSI_CMCR_GSR1TX \|\
sahilmgandhi	18:6a4db94011d3	888	DSI_CMCR_GSR2TX \|\
sahilmgandhi	18:6a4db94011d3	889	DSI_CMCR_GLWTX \|\
sahilmgandhi	18:6a4db94011d3	890	DSI_CMCR_DSW0TX \|\
sahilmgandhi	18:6a4db94011d3	891	DSI_CMCR_DSW1TX \|\
sahilmgandhi	18:6a4db94011d3	892	DSI_CMCR_DSR0TX \|\
sahilmgandhi	18:6a4db94011d3	893	DSI_CMCR_DLWTX \|\
sahilmgandhi	18:6a4db94011d3	894	DSI_CMCR_MRDPS);
sahilmgandhi	18:6a4db94011d3	895	hdsi->Instance->CMCR \|= (LPCmd->LPGenShortWriteNoP \|\
sahilmgandhi	18:6a4db94011d3	896	LPCmd->LPGenShortWriteOneP \|\
sahilmgandhi	18:6a4db94011d3	897	LPCmd->LPGenShortWriteTwoP \|\
sahilmgandhi	18:6a4db94011d3	898	LPCmd->LPGenShortReadNoP \|\
sahilmgandhi	18:6a4db94011d3	899	LPCmd->LPGenShortReadOneP \|\
sahilmgandhi	18:6a4db94011d3	900	LPCmd->LPGenShortReadTwoP \|\
sahilmgandhi	18:6a4db94011d3	901	LPCmd->LPGenLongWrite \|\
sahilmgandhi	18:6a4db94011d3	902	LPCmd->LPDcsShortWriteNoP \|\
sahilmgandhi	18:6a4db94011d3	903	LPCmd->LPDcsShortWriteOneP \|\
sahilmgandhi	18:6a4db94011d3	904	LPCmd->LPDcsShortReadNoP \|\
sahilmgandhi	18:6a4db94011d3	905	LPCmd->LPDcsLongWrite \|\
sahilmgandhi	18:6a4db94011d3	906	LPCmd->LPMaxReadPacket);
sahilmgandhi	18:6a4db94011d3	907
sahilmgandhi	18:6a4db94011d3	908	/* Configure the acknowledge request after each packet transmission */
sahilmgandhi	18:6a4db94011d3	909	hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
sahilmgandhi	18:6a4db94011d3	910	hdsi->Instance->CMCR \|= LPCmd->AcknowledgeRequest;
sahilmgandhi	18:6a4db94011d3	911
sahilmgandhi	18:6a4db94011d3	912	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	913	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	914
sahilmgandhi	18:6a4db94011d3	915	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	916	}
sahilmgandhi	18:6a4db94011d3	917
sahilmgandhi	18:6a4db94011d3	918	/**
sahilmgandhi	18:6a4db94011d3	919	* @brief Configure the flow control parameters
sahilmgandhi	18:6a4db94011d3	920	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	921	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	922	* @param FlowControl: flow control feature(s) to be enabled.
sahilmgandhi	18:6a4db94011d3	923	* This parameter can be any combination of @ref DSI_FlowControl.
sahilmgandhi	18:6a4db94011d3	924	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	925	*/
sahilmgandhi	18:6a4db94011d3	926	HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
sahilmgandhi	18:6a4db94011d3	927	{
sahilmgandhi	18:6a4db94011d3	928	/* Process locked */
sahilmgandhi	18:6a4db94011d3	929	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	930
sahilmgandhi	18:6a4db94011d3	931	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	932	assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
sahilmgandhi	18:6a4db94011d3	933
sahilmgandhi	18:6a4db94011d3	934	/* Set the DSI Host Protocol Configuration Register */
sahilmgandhi	18:6a4db94011d3	935	hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
sahilmgandhi	18:6a4db94011d3	936	hdsi->Instance->PCR \|= FlowControl;
sahilmgandhi	18:6a4db94011d3	937
sahilmgandhi	18:6a4db94011d3	938	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	939	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	940
sahilmgandhi	18:6a4db94011d3	941	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	942	}
sahilmgandhi	18:6a4db94011d3	943
sahilmgandhi	18:6a4db94011d3	944	/**
sahilmgandhi	18:6a4db94011d3	945	* @brief Configure the DSI PHY timer parameters
sahilmgandhi	18:6a4db94011d3	946	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	947	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	948	* @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	949	* the DSI PHY timing parameters
sahilmgandhi	18:6a4db94011d3	950	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	951	*/
sahilmgandhi	18:6a4db94011d3	952	HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef hdsi, DSI_PHY_TimerTypeDef PhyTimers)
sahilmgandhi	18:6a4db94011d3	953	{
sahilmgandhi	18:6a4db94011d3	954	uint32_t maxTime;
sahilmgandhi	18:6a4db94011d3	955	/* Process locked */
sahilmgandhi	18:6a4db94011d3	956	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	957
sahilmgandhi	18:6a4db94011d3	958	maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
sahilmgandhi	18:6a4db94011d3	959
sahilmgandhi	18:6a4db94011d3	960	/* Clock lane timer configuration */
sahilmgandhi	18:6a4db94011d3	961
sahilmgandhi	18:6a4db94011d3	962	/* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
sahilmgandhi	18:6a4db94011d3	963	High-Speed transmission.
sahilmgandhi	18:6a4db94011d3	964	To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
sahilmgandhi	18:6a4db94011d3	965	to Low-Power and from Low-Power to High-Speed.
sahilmgandhi	18:6a4db94011d3	966	This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
sahilmgandhi	18:6a4db94011d3	967	But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
sahilmgandhi	18:6a4db94011d3	968
sahilmgandhi	18:6a4db94011d3	969	Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
sahilmgandhi	18:6a4db94011d3	970	*/
sahilmgandhi	18:6a4db94011d3	971	hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME \| DSI_CLTCR_HS2LP_TIME);
sahilmgandhi	18:6a4db94011d3	972	hdsi->Instance->CLTCR \|= (maxTime \| ((maxTime)<<16U));
sahilmgandhi	18:6a4db94011d3	973
sahilmgandhi	18:6a4db94011d3	974	/* Data lane timer configuration */
sahilmgandhi	18:6a4db94011d3	975	hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME \| DSI_DLTCR_LP2HS_TIME \| DSI_DLTCR_HS2LP_TIME);
sahilmgandhi	18:6a4db94011d3	976	hdsi->Instance->DLTCR \|= (PhyTimers->DataLaneMaxReadTime \| ((PhyTimers->DataLaneLP2HSTime)<<16U) \| ((PhyTimers->DataLaneHS2LPTime)<<24U));
sahilmgandhi	18:6a4db94011d3	977
sahilmgandhi	18:6a4db94011d3	978	/* Configure the wait period to request HS transmission after a stop state */
sahilmgandhi	18:6a4db94011d3	979	hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
sahilmgandhi	18:6a4db94011d3	980	hdsi->Instance->PCONFR \|= ((PhyTimers->StopWaitTime)<<8U);
sahilmgandhi	18:6a4db94011d3	981
sahilmgandhi	18:6a4db94011d3	982	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	983	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	984
sahilmgandhi	18:6a4db94011d3	985	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	986	}
sahilmgandhi	18:6a4db94011d3	987
sahilmgandhi	18:6a4db94011d3	988	/**
sahilmgandhi	18:6a4db94011d3	989	* @brief Configure the DSI HOST timeout parameters
sahilmgandhi	18:6a4db94011d3	990	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	991	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	992	* @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	993	* the DSI host timeout parameters
sahilmgandhi	18:6a4db94011d3	994	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	995	*/
sahilmgandhi	18:6a4db94011d3	996	HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef hdsi, DSI_HOST_TimeoutTypeDef HostTimeouts)
sahilmgandhi	18:6a4db94011d3	997	{
sahilmgandhi	18:6a4db94011d3	998	/* Process locked */
sahilmgandhi	18:6a4db94011d3	999	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1000
sahilmgandhi	18:6a4db94011d3	1001	/* Set the timeout clock division factor */
sahilmgandhi	18:6a4db94011d3	1002	hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
sahilmgandhi	18:6a4db94011d3	1003	hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8U);
sahilmgandhi	18:6a4db94011d3	1004
sahilmgandhi	18:6a4db94011d3	1005	/* High-speed transmission timeout */
sahilmgandhi	18:6a4db94011d3	1006	hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
sahilmgandhi	18:6a4db94011d3	1007	hdsi->Instance->TCCR[0U] \|= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U);
sahilmgandhi	18:6a4db94011d3	1008
sahilmgandhi	18:6a4db94011d3	1009	/* Low-power reception timeout */
sahilmgandhi	18:6a4db94011d3	1010	hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
sahilmgandhi	18:6a4db94011d3	1011	hdsi->Instance->TCCR[0U] \|= HostTimeouts->LowPowerReceptionTimeout;
sahilmgandhi	18:6a4db94011d3	1012
sahilmgandhi	18:6a4db94011d3	1013	/* High-speed read timeout */
sahilmgandhi	18:6a4db94011d3	1014	hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
sahilmgandhi	18:6a4db94011d3	1015	hdsi->Instance->TCCR[1U] \|= HostTimeouts->HighSpeedReadTimeout;
sahilmgandhi	18:6a4db94011d3	1016
sahilmgandhi	18:6a4db94011d3	1017	/* Low-power read timeout */
sahilmgandhi	18:6a4db94011d3	1018	hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
sahilmgandhi	18:6a4db94011d3	1019	hdsi->Instance->TCCR[2U] \|= HostTimeouts->LowPowerReadTimeout;
sahilmgandhi	18:6a4db94011d3	1020
sahilmgandhi	18:6a4db94011d3	1021	/* High-speed write timeout */
sahilmgandhi	18:6a4db94011d3	1022	hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
sahilmgandhi	18:6a4db94011d3	1023	hdsi->Instance->TCCR[3U] \|= HostTimeouts->HighSpeedWriteTimeout;
sahilmgandhi	18:6a4db94011d3	1024
sahilmgandhi	18:6a4db94011d3	1025	/* High-speed write presp mode */
sahilmgandhi	18:6a4db94011d3	1026	hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
sahilmgandhi	18:6a4db94011d3	1027	hdsi->Instance->TCCR[3U] \|= HostTimeouts->HighSpeedWritePrespMode;
sahilmgandhi	18:6a4db94011d3	1028
sahilmgandhi	18:6a4db94011d3	1029	/* Low-speed write timeout */
sahilmgandhi	18:6a4db94011d3	1030	hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
sahilmgandhi	18:6a4db94011d3	1031	hdsi->Instance->TCCR[4U] \|= HostTimeouts->LowPowerWriteTimeout;
sahilmgandhi	18:6a4db94011d3	1032
sahilmgandhi	18:6a4db94011d3	1033	/* BTA timeout */
sahilmgandhi	18:6a4db94011d3	1034	hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
sahilmgandhi	18:6a4db94011d3	1035	hdsi->Instance->TCCR[5U] \|= HostTimeouts->BTATimeout;
sahilmgandhi	18:6a4db94011d3	1036
sahilmgandhi	18:6a4db94011d3	1037	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1038	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1039
sahilmgandhi	18:6a4db94011d3	1040	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1041	}
sahilmgandhi	18:6a4db94011d3	1042
sahilmgandhi	18:6a4db94011d3	1043	/**
sahilmgandhi	18:6a4db94011d3	1044	* @brief Start the DSI module
sahilmgandhi	18:6a4db94011d3	1045	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1046	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1047	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1048	*/
sahilmgandhi	18:6a4db94011d3	1049	HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	1050	{
sahilmgandhi	18:6a4db94011d3	1051	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1052	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1053
sahilmgandhi	18:6a4db94011d3	1054	/* Enable the DSI host */
sahilmgandhi	18:6a4db94011d3	1055	__HAL_DSI_ENABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	1056
sahilmgandhi	18:6a4db94011d3	1057	/* Enable the DSI wrapper */
sahilmgandhi	18:6a4db94011d3	1058	__HAL_DSI_WRAPPER_ENABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	1059
sahilmgandhi	18:6a4db94011d3	1060	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1061	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1062
sahilmgandhi	18:6a4db94011d3	1063	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1064	}
sahilmgandhi	18:6a4db94011d3	1065
sahilmgandhi	18:6a4db94011d3	1066	/**
sahilmgandhi	18:6a4db94011d3	1067	* @brief Stop the DSI module
sahilmgandhi	18:6a4db94011d3	1068	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1069	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1070	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1071	*/
sahilmgandhi	18:6a4db94011d3	1072	HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	1073	{
sahilmgandhi	18:6a4db94011d3	1074	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1075	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1076
sahilmgandhi	18:6a4db94011d3	1077	/* Disable the DSI host */
sahilmgandhi	18:6a4db94011d3	1078	__HAL_DSI_DISABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	1079
sahilmgandhi	18:6a4db94011d3	1080	/* Disable the DSI wrapper */
sahilmgandhi	18:6a4db94011d3	1081	__HAL_DSI_WRAPPER_DISABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	1082
sahilmgandhi	18:6a4db94011d3	1083	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1084	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1085
sahilmgandhi	18:6a4db94011d3	1086	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1087	}
sahilmgandhi	18:6a4db94011d3	1088
sahilmgandhi	18:6a4db94011d3	1089	/**
sahilmgandhi	18:6a4db94011d3	1090	* @brief Refresh the display in command mode
sahilmgandhi	18:6a4db94011d3	1091	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1092	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1093	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1094	*/
sahilmgandhi	18:6a4db94011d3	1095	HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	1096	{
sahilmgandhi	18:6a4db94011d3	1097	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1098	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1099
sahilmgandhi	18:6a4db94011d3	1100	/* Update the display */
sahilmgandhi	18:6a4db94011d3	1101	hdsi->Instance->WCR \|= DSI_WCR_LTDCEN;
sahilmgandhi	18:6a4db94011d3	1102
sahilmgandhi	18:6a4db94011d3	1103	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1104	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1105
sahilmgandhi	18:6a4db94011d3	1106	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1107	}
sahilmgandhi	18:6a4db94011d3	1108
sahilmgandhi	18:6a4db94011d3	1109	/**
sahilmgandhi	18:6a4db94011d3	1110	* @brief Controls the display color mode in Video mode
sahilmgandhi	18:6a4db94011d3	1111	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1112	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1113	* @param ColorMode: Color mode (full or 8-colors).
sahilmgandhi	18:6a4db94011d3	1114	* This parameter can be any value of @ref DSI_Color_Mode
sahilmgandhi	18:6a4db94011d3	1115	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1116	*/
sahilmgandhi	18:6a4db94011d3	1117	HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
sahilmgandhi	18:6a4db94011d3	1118	{
sahilmgandhi	18:6a4db94011d3	1119	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1120	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1121
sahilmgandhi	18:6a4db94011d3	1122	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1123	assert_param(IS_DSI_COLOR_MODE(ColorMode));
sahilmgandhi	18:6a4db94011d3	1124
sahilmgandhi	18:6a4db94011d3	1125	/* Update the display color mode */
sahilmgandhi	18:6a4db94011d3	1126	hdsi->Instance->WCR &= ~DSI_WCR_COLM;
sahilmgandhi	18:6a4db94011d3	1127	hdsi->Instance->WCR \|= ColorMode;
sahilmgandhi	18:6a4db94011d3	1128
sahilmgandhi	18:6a4db94011d3	1129	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1130	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1131
sahilmgandhi	18:6a4db94011d3	1132	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1133	}
sahilmgandhi	18:6a4db94011d3	1134
sahilmgandhi	18:6a4db94011d3	1135	/**
sahilmgandhi	18:6a4db94011d3	1136	* @brief Control the display shutdown in Video mode
sahilmgandhi	18:6a4db94011d3	1137	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1138	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1139	* @param Shutdown: Shut-down (Display-ON or Display-OFF).
sahilmgandhi	18:6a4db94011d3	1140	* This parameter can be any value of @ref DSI_ShutDown
sahilmgandhi	18:6a4db94011d3	1141	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1142	*/
sahilmgandhi	18:6a4db94011d3	1143	HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
sahilmgandhi	18:6a4db94011d3	1144	{
sahilmgandhi	18:6a4db94011d3	1145	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1146	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1147
sahilmgandhi	18:6a4db94011d3	1148	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1149	assert_param(IS_DSI_SHUT_DOWN(Shutdown));
sahilmgandhi	18:6a4db94011d3	1150
sahilmgandhi	18:6a4db94011d3	1151	/* Update the display Shutdown */
sahilmgandhi	18:6a4db94011d3	1152	hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
sahilmgandhi	18:6a4db94011d3	1153	hdsi->Instance->WCR \|= Shutdown;
sahilmgandhi	18:6a4db94011d3	1154
sahilmgandhi	18:6a4db94011d3	1155	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1156	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1157
sahilmgandhi	18:6a4db94011d3	1158	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1159	}
sahilmgandhi	18:6a4db94011d3	1160
sahilmgandhi	18:6a4db94011d3	1161	/**
sahilmgandhi	18:6a4db94011d3	1162	* @brief DCS or Generic short write command
sahilmgandhi	18:6a4db94011d3	1163	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1164	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1165	* @param ChannelID: Virtual channel ID.
sahilmgandhi	18:6a4db94011d3	1166	* @param Mode: DSI short packet data type.
sahilmgandhi	18:6a4db94011d3	1167	* This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
sahilmgandhi	18:6a4db94011d3	1168	* @param Param1: DSC command or first generic parameter.
sahilmgandhi	18:6a4db94011d3	1169	* This parameter can be any value of @ref DSI_DCS_Command or a
sahilmgandhi	18:6a4db94011d3	1170	* generic command code.
sahilmgandhi	18:6a4db94011d3	1171	* @param Param2: DSC parameter or second generic parameter.
sahilmgandhi	18:6a4db94011d3	1172	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1173	*/
sahilmgandhi	18:6a4db94011d3	1174	HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
sahilmgandhi	18:6a4db94011d3	1175	uint32_t ChannelID,
sahilmgandhi	18:6a4db94011d3	1176	uint32_t Mode,
sahilmgandhi	18:6a4db94011d3	1177	uint32_t Param1,
sahilmgandhi	18:6a4db94011d3	1178	uint32_t Param2)
sahilmgandhi	18:6a4db94011d3	1179	{
sahilmgandhi	18:6a4db94011d3	1180	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1181
sahilmgandhi	18:6a4db94011d3	1182	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1183	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1184
sahilmgandhi	18:6a4db94011d3	1185	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1186	assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
sahilmgandhi	18:6a4db94011d3	1187
sahilmgandhi	18:6a4db94011d3	1188	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1189	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1190
sahilmgandhi	18:6a4db94011d3	1191	/* Wait for Command FIFO Empty */
sahilmgandhi	18:6a4db94011d3	1192	while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
sahilmgandhi	18:6a4db94011d3	1193	{
sahilmgandhi	18:6a4db94011d3	1194	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1195	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1196	{
sahilmgandhi	18:6a4db94011d3	1197	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1198	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1199
sahilmgandhi	18:6a4db94011d3	1200	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1201	}
sahilmgandhi	18:6a4db94011d3	1202	}
sahilmgandhi	18:6a4db94011d3	1203
sahilmgandhi	18:6a4db94011d3	1204	/* Configure the packet to send a short DCS command with 0 or 1 parameter */
sahilmgandhi	18:6a4db94011d3	1205	DSI_ConfigPacketHeader(hdsi->Instance,
sahilmgandhi	18:6a4db94011d3	1206	ChannelID,
sahilmgandhi	18:6a4db94011d3	1207	Mode,
sahilmgandhi	18:6a4db94011d3	1208	Param1,
sahilmgandhi	18:6a4db94011d3	1209	Param2);
sahilmgandhi	18:6a4db94011d3	1210
sahilmgandhi	18:6a4db94011d3	1211	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1212	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1213
sahilmgandhi	18:6a4db94011d3	1214	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1215	}
sahilmgandhi	18:6a4db94011d3	1216
sahilmgandhi	18:6a4db94011d3	1217	/**
sahilmgandhi	18:6a4db94011d3	1218	* @brief DCS or Generic long write command
sahilmgandhi	18:6a4db94011d3	1219	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1220	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1221	* @param ChannelID: Virtual channel ID.
sahilmgandhi	18:6a4db94011d3	1222	* @param Mode: DSI long packet data type.
sahilmgandhi	18:6a4db94011d3	1223	* This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
sahilmgandhi	18:6a4db94011d3	1224	* @param NbParams: Number of parameters.
sahilmgandhi	18:6a4db94011d3	1225	* @param Param1: DSC command or first generic parameter.
sahilmgandhi	18:6a4db94011d3	1226	* This parameter can be any value of @ref DSI_DCS_Command or a
sahilmgandhi	18:6a4db94011d3	1227	* generic command code
sahilmgandhi	18:6a4db94011d3	1228	* @param ParametersTable: Pointer to parameter values table.
sahilmgandhi	18:6a4db94011d3	1229	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1230	*/
sahilmgandhi	18:6a4db94011d3	1231	HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
sahilmgandhi	18:6a4db94011d3	1232	uint32_t ChannelID,
sahilmgandhi	18:6a4db94011d3	1233	uint32_t Mode,
sahilmgandhi	18:6a4db94011d3	1234	uint32_t NbParams,
sahilmgandhi	18:6a4db94011d3	1235	uint32_t Param1,
sahilmgandhi	18:6a4db94011d3	1236	uint8_t* ParametersTable)
sahilmgandhi	18:6a4db94011d3	1237	{
sahilmgandhi	18:6a4db94011d3	1238	uint32_t uicounter = 0U;
sahilmgandhi	18:6a4db94011d3	1239	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1240
sahilmgandhi	18:6a4db94011d3	1241	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1242	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1243
sahilmgandhi	18:6a4db94011d3	1244	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1245	assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
sahilmgandhi	18:6a4db94011d3	1246
sahilmgandhi	18:6a4db94011d3	1247	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1248	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1249
sahilmgandhi	18:6a4db94011d3	1250	/* Wait for Command FIFO Empty */
sahilmgandhi	18:6a4db94011d3	1251	while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
sahilmgandhi	18:6a4db94011d3	1252	{
sahilmgandhi	18:6a4db94011d3	1253	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1254	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1255	{
sahilmgandhi	18:6a4db94011d3	1256	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1257	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1258
sahilmgandhi	18:6a4db94011d3	1259	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1260	}
sahilmgandhi	18:6a4db94011d3	1261	}
sahilmgandhi	18:6a4db94011d3	1262
sahilmgandhi	18:6a4db94011d3	1263	/* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/
sahilmgandhi	18:6a4db94011d3	1264	while(uicounter < NbParams)
sahilmgandhi	18:6a4db94011d3	1265	{
sahilmgandhi	18:6a4db94011d3	1266	if(uicounter == 0x00U)
sahilmgandhi	18:6a4db94011d3	1267	{
sahilmgandhi	18:6a4db94011d3	1268	hdsi->Instance->GPDR=(Param1 \| \
sahilmgandhi	18:6a4db94011d3	1269	((uint32_t)(*(ParametersTable + uicounter)) << 8U) \| \
sahilmgandhi	18:6a4db94011d3	1270	((uint32_t)(*(ParametersTable + uicounter+1U))<<16U) \| \
sahilmgandhi	18:6a4db94011d3	1271	((uint32_t)(*(ParametersTable + uicounter+2U))<<24U));
sahilmgandhi	18:6a4db94011d3	1272	uicounter+=3U;
sahilmgandhi	18:6a4db94011d3	1273	}
sahilmgandhi	18:6a4db94011d3	1274	else
sahilmgandhi	18:6a4db94011d3	1275	{
sahilmgandhi	18:6a4db94011d3	1276	hdsi->Instance->GPDR=((uint32_t)(*(ParametersTable + uicounter)) \| \
sahilmgandhi	18:6a4db94011d3	1277	((uint32_t)(*(ParametersTable + uicounter+1U)) << 8U) \| \
sahilmgandhi	18:6a4db94011d3	1278	((uint32_t)(*(ParametersTable + uicounter+2U)) << 16U) \| \
sahilmgandhi	18:6a4db94011d3	1279	((uint32_t)(*(ParametersTable + uicounter+3U)) << 24U));
sahilmgandhi	18:6a4db94011d3	1280	uicounter+=4U;
sahilmgandhi	18:6a4db94011d3	1281	}
sahilmgandhi	18:6a4db94011d3	1282	}
sahilmgandhi	18:6a4db94011d3	1283
sahilmgandhi	18:6a4db94011d3	1284	/* Configure the packet to send a long DCS command */
sahilmgandhi	18:6a4db94011d3	1285	DSI_ConfigPacketHeader(hdsi->Instance,
sahilmgandhi	18:6a4db94011d3	1286	ChannelID,
sahilmgandhi	18:6a4db94011d3	1287	Mode,
sahilmgandhi	18:6a4db94011d3	1288	((NbParams+1U)&0x00FFU),
sahilmgandhi	18:6a4db94011d3	1289	(((NbParams+1U)&0xFF00U)>>8U));
sahilmgandhi	18:6a4db94011d3	1290
sahilmgandhi	18:6a4db94011d3	1291	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1292	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1293
sahilmgandhi	18:6a4db94011d3	1294	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1295	}
sahilmgandhi	18:6a4db94011d3	1296
sahilmgandhi	18:6a4db94011d3	1297	/**
sahilmgandhi	18:6a4db94011d3	1298	* @brief Read command (DCS or generic)
sahilmgandhi	18:6a4db94011d3	1299	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1300	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1301	* @param ChannelNbr: Virtual channel ID
sahilmgandhi	18:6a4db94011d3	1302	* @param Array: pointer to a buffer to store the payload of a read back operation.
sahilmgandhi	18:6a4db94011d3	1303	* @param Size: Data size to be read (in byte).
sahilmgandhi	18:6a4db94011d3	1304	* @param Mode: DSI read packet data type.
sahilmgandhi	18:6a4db94011d3	1305	* This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
sahilmgandhi	18:6a4db94011d3	1306	* @param DCSCmd: DCS get/read command.
sahilmgandhi	18:6a4db94011d3	1307	* @param ParametersTable: Pointer to parameter values table.
sahilmgandhi	18:6a4db94011d3	1308	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1309	*/
sahilmgandhi	18:6a4db94011d3	1310	HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
sahilmgandhi	18:6a4db94011d3	1311	uint32_t ChannelNbr,
sahilmgandhi	18:6a4db94011d3	1312	uint8_t* Array,
sahilmgandhi	18:6a4db94011d3	1313	uint32_t Size,
sahilmgandhi	18:6a4db94011d3	1314	uint32_t Mode,
sahilmgandhi	18:6a4db94011d3	1315	uint32_t DCSCmd,
sahilmgandhi	18:6a4db94011d3	1316	uint8_t* ParametersTable)
sahilmgandhi	18:6a4db94011d3	1317	{
sahilmgandhi	18:6a4db94011d3	1318	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1319
sahilmgandhi	18:6a4db94011d3	1320	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1321	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1322
sahilmgandhi	18:6a4db94011d3	1323	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1324	assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
sahilmgandhi	18:6a4db94011d3	1325
sahilmgandhi	18:6a4db94011d3	1326	if(Size > 2U)
sahilmgandhi	18:6a4db94011d3	1327	{
sahilmgandhi	18:6a4db94011d3	1328	/* set max return packet size */
sahilmgandhi	18:6a4db94011d3	1329	HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFFU), (((Size)>>8U)&0xFFU));
sahilmgandhi	18:6a4db94011d3	1330	}
sahilmgandhi	18:6a4db94011d3	1331
sahilmgandhi	18:6a4db94011d3	1332	/* Configure the packet to read command */
sahilmgandhi	18:6a4db94011d3	1333	if (Mode == DSI_DCS_SHORT_PKT_READ)
sahilmgandhi	18:6a4db94011d3	1334	{
sahilmgandhi	18:6a4db94011d3	1335	DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
sahilmgandhi	18:6a4db94011d3	1336	}
sahilmgandhi	18:6a4db94011d3	1337	else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
sahilmgandhi	18:6a4db94011d3	1338	{
sahilmgandhi	18:6a4db94011d3	1339	DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
sahilmgandhi	18:6a4db94011d3	1340	}
sahilmgandhi	18:6a4db94011d3	1341	else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
sahilmgandhi	18:6a4db94011d3	1342	{
sahilmgandhi	18:6a4db94011d3	1343	DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
sahilmgandhi	18:6a4db94011d3	1344	}
sahilmgandhi	18:6a4db94011d3	1345	else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
sahilmgandhi	18:6a4db94011d3	1346	{
sahilmgandhi	18:6a4db94011d3	1347	DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
sahilmgandhi	18:6a4db94011d3	1348	}
sahilmgandhi	18:6a4db94011d3	1349	else
sahilmgandhi	18:6a4db94011d3	1350	{
sahilmgandhi	18:6a4db94011d3	1351	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1352	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1353
sahilmgandhi	18:6a4db94011d3	1354	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1355	}
sahilmgandhi	18:6a4db94011d3	1356
sahilmgandhi	18:6a4db94011d3	1357	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1358	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1359
sahilmgandhi	18:6a4db94011d3	1360	/* Check that the payload read FIFO is not empty */
sahilmgandhi	18:6a4db94011d3	1361	while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
sahilmgandhi	18:6a4db94011d3	1362	{
sahilmgandhi	18:6a4db94011d3	1363	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1364	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1365	{
sahilmgandhi	18:6a4db94011d3	1366	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1367	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1368
sahilmgandhi	18:6a4db94011d3	1369	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1370	}
sahilmgandhi	18:6a4db94011d3	1371	}
sahilmgandhi	18:6a4db94011d3	1372
sahilmgandhi	18:6a4db94011d3	1373	/* Get the first byte */
sahilmgandhi	18:6a4db94011d3	1374	((uint32_t )Array) = (hdsi->Instance->GPDR);
sahilmgandhi	18:6a4db94011d3	1375	if (Size > 4U)
sahilmgandhi	18:6a4db94011d3	1376	{
sahilmgandhi	18:6a4db94011d3	1377	Size -= 4U;
sahilmgandhi	18:6a4db94011d3	1378	Array += 4U;
sahilmgandhi	18:6a4db94011d3	1379	}
sahilmgandhi	18:6a4db94011d3	1380	else
sahilmgandhi	18:6a4db94011d3	1381	{
sahilmgandhi	18:6a4db94011d3	1382	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1383	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1384
sahilmgandhi	18:6a4db94011d3	1385	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1386	}
sahilmgandhi	18:6a4db94011d3	1387
sahilmgandhi	18:6a4db94011d3	1388	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1389	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1390
sahilmgandhi	18:6a4db94011d3	1391	/* Get the remaining bytes if any */
sahilmgandhi	18:6a4db94011d3	1392	while(((int)(Size)) > 0U)
sahilmgandhi	18:6a4db94011d3	1393	{
sahilmgandhi	18:6a4db94011d3	1394	if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
sahilmgandhi	18:6a4db94011d3	1395	{
sahilmgandhi	18:6a4db94011d3	1396	((uint32_t )Array) = (hdsi->Instance->GPDR);
sahilmgandhi	18:6a4db94011d3	1397	Size -= 4U;
sahilmgandhi	18:6a4db94011d3	1398	Array += 4U;
sahilmgandhi	18:6a4db94011d3	1399	}
sahilmgandhi	18:6a4db94011d3	1400
sahilmgandhi	18:6a4db94011d3	1401	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1402	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1403	{
sahilmgandhi	18:6a4db94011d3	1404	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1405	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1406
sahilmgandhi	18:6a4db94011d3	1407	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1408	}
sahilmgandhi	18:6a4db94011d3	1409	}
sahilmgandhi	18:6a4db94011d3	1410
sahilmgandhi	18:6a4db94011d3	1411	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1412	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1413
sahilmgandhi	18:6a4db94011d3	1414	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1415	}
sahilmgandhi	18:6a4db94011d3	1416
sahilmgandhi	18:6a4db94011d3	1417	/**
sahilmgandhi	18:6a4db94011d3	1418	* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
sahilmgandhi	18:6a4db94011d3	1419	* (only data lanes are in ULPM)
sahilmgandhi	18:6a4db94011d3	1420	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1421	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1422	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1423	*/
sahilmgandhi	18:6a4db94011d3	1424	HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	1425	{
sahilmgandhi	18:6a4db94011d3	1426	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1427
sahilmgandhi	18:6a4db94011d3	1428	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1429	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1430
sahilmgandhi	18:6a4db94011d3	1431	/* ULPS Request on Data Lanes */
sahilmgandhi	18:6a4db94011d3	1432	hdsi->Instance->PUCR \|= DSI_PUCR_URDL;
sahilmgandhi	18:6a4db94011d3	1433
sahilmgandhi	18:6a4db94011d3	1434	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1435	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1436
sahilmgandhi	18:6a4db94011d3	1437	/* Wait until the D-PHY active lanes enter into ULPM */
sahilmgandhi	18:6a4db94011d3	1438	if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
sahilmgandhi	18:6a4db94011d3	1439	{
sahilmgandhi	18:6a4db94011d3	1440	while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
sahilmgandhi	18:6a4db94011d3	1441	{
sahilmgandhi	18:6a4db94011d3	1442	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1443	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1444	{
sahilmgandhi	18:6a4db94011d3	1445	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1446	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1447
sahilmgandhi	18:6a4db94011d3	1448	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1449	}
sahilmgandhi	18:6a4db94011d3	1450	}
sahilmgandhi	18:6a4db94011d3	1451	}
sahilmgandhi	18:6a4db94011d3	1452	else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
sahilmgandhi	18:6a4db94011d3	1453	{
sahilmgandhi	18:6a4db94011d3	1454	while((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UAN1)) != RESET)
sahilmgandhi	18:6a4db94011d3	1455	{
sahilmgandhi	18:6a4db94011d3	1456	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1457	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1458	{
sahilmgandhi	18:6a4db94011d3	1459	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1460	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1461
sahilmgandhi	18:6a4db94011d3	1462	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1463	}
sahilmgandhi	18:6a4db94011d3	1464	}
sahilmgandhi	18:6a4db94011d3	1465	}
sahilmgandhi	18:6a4db94011d3	1466
sahilmgandhi	18:6a4db94011d3	1467	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1468	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1469
sahilmgandhi	18:6a4db94011d3	1470	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1471	}
sahilmgandhi	18:6a4db94011d3	1472
sahilmgandhi	18:6a4db94011d3	1473	/**
sahilmgandhi	18:6a4db94011d3	1474	* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
sahilmgandhi	18:6a4db94011d3	1475	* (only data lanes are in ULPM)
sahilmgandhi	18:6a4db94011d3	1476	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1477	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1478	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1479	*/
sahilmgandhi	18:6a4db94011d3	1480	HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	1481	{
sahilmgandhi	18:6a4db94011d3	1482	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1483
sahilmgandhi	18:6a4db94011d3	1484	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1485	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1486
sahilmgandhi	18:6a4db94011d3	1487	/* Exit ULPS on Data Lanes */
sahilmgandhi	18:6a4db94011d3	1488	hdsi->Instance->PUCR \|= DSI_PUCR_UEDL;
sahilmgandhi	18:6a4db94011d3	1489
sahilmgandhi	18:6a4db94011d3	1490	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1491	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1492
sahilmgandhi	18:6a4db94011d3	1493	/* Wait until all active lanes exit ULPM */
sahilmgandhi	18:6a4db94011d3	1494	if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
sahilmgandhi	18:6a4db94011d3	1495	{
sahilmgandhi	18:6a4db94011d3	1496	while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
sahilmgandhi	18:6a4db94011d3	1497	{
sahilmgandhi	18:6a4db94011d3	1498	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1499	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1500	{
sahilmgandhi	18:6a4db94011d3	1501	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1502	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1503
sahilmgandhi	18:6a4db94011d3	1504	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1505	}
sahilmgandhi	18:6a4db94011d3	1506	}
sahilmgandhi	18:6a4db94011d3	1507	}
sahilmgandhi	18:6a4db94011d3	1508	else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
sahilmgandhi	18:6a4db94011d3	1509	{
sahilmgandhi	18:6a4db94011d3	1510	while((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UAN1)) != (DSI_PSR_UAN0 \| DSI_PSR_UAN1))
sahilmgandhi	18:6a4db94011d3	1511	{
sahilmgandhi	18:6a4db94011d3	1512	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1513	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1514	{
sahilmgandhi	18:6a4db94011d3	1515	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1516	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1517
sahilmgandhi	18:6a4db94011d3	1518	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1519	}
sahilmgandhi	18:6a4db94011d3	1520	}
sahilmgandhi	18:6a4db94011d3	1521	}
sahilmgandhi	18:6a4db94011d3	1522
sahilmgandhi	18:6a4db94011d3	1523	/* De-assert the ULPM requests and the ULPM exit bits */
sahilmgandhi	18:6a4db94011d3	1524	hdsi->Instance->PUCR = 0U;
sahilmgandhi	18:6a4db94011d3	1525
sahilmgandhi	18:6a4db94011d3	1526	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1527	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1528
sahilmgandhi	18:6a4db94011d3	1529	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1530	}
sahilmgandhi	18:6a4db94011d3	1531
sahilmgandhi	18:6a4db94011d3	1532	/**
sahilmgandhi	18:6a4db94011d3	1533	* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
sahilmgandhi	18:6a4db94011d3	1534	* (both data and clock lanes are in ULPM)
sahilmgandhi	18:6a4db94011d3	1535	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1536	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1537	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1538	*/
sahilmgandhi	18:6a4db94011d3	1539	HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	1540	{
sahilmgandhi	18:6a4db94011d3	1541	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1542
sahilmgandhi	18:6a4db94011d3	1543	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1544	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1545
sahilmgandhi	18:6a4db94011d3	1546	/* Clock lane configuration: no more HS request */
sahilmgandhi	18:6a4db94011d3	1547	hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
sahilmgandhi	18:6a4db94011d3	1548
sahilmgandhi	18:6a4db94011d3	1549	/* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
sahilmgandhi	18:6a4db94011d3	1550	__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
sahilmgandhi	18:6a4db94011d3	1551
sahilmgandhi	18:6a4db94011d3	1552	/* ULPS Request on Clock and Data Lanes */
sahilmgandhi	18:6a4db94011d3	1553	hdsi->Instance->PUCR \|= (DSI_PUCR_URCL \| DSI_PUCR_URDL);
sahilmgandhi	18:6a4db94011d3	1554
sahilmgandhi	18:6a4db94011d3	1555	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1556	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1557
sahilmgandhi	18:6a4db94011d3	1558	/* Wait until all active lanes exit ULPM */
sahilmgandhi	18:6a4db94011d3	1559	if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
sahilmgandhi	18:6a4db94011d3	1560	{
sahilmgandhi	18:6a4db94011d3	1561	while((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UANC)) != RESET)
sahilmgandhi	18:6a4db94011d3	1562	{
sahilmgandhi	18:6a4db94011d3	1563	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1564	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1565	{
sahilmgandhi	18:6a4db94011d3	1566	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1567	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1568
sahilmgandhi	18:6a4db94011d3	1569	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1570	}
sahilmgandhi	18:6a4db94011d3	1571	}
sahilmgandhi	18:6a4db94011d3	1572	}
sahilmgandhi	18:6a4db94011d3	1573	else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
sahilmgandhi	18:6a4db94011d3	1574	{
sahilmgandhi	18:6a4db94011d3	1575	while((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UAN1 \| DSI_PSR_UANC)) != RESET)
sahilmgandhi	18:6a4db94011d3	1576	{
sahilmgandhi	18:6a4db94011d3	1577	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1578	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1579	{
sahilmgandhi	18:6a4db94011d3	1580	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1581	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1582
sahilmgandhi	18:6a4db94011d3	1583	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1584	}
sahilmgandhi	18:6a4db94011d3	1585	}
sahilmgandhi	18:6a4db94011d3	1586	}
sahilmgandhi	18:6a4db94011d3	1587
sahilmgandhi	18:6a4db94011d3	1588	/* Turn off the DSI PLL */
sahilmgandhi	18:6a4db94011d3	1589	__HAL_DSI_PLL_DISABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	1590
sahilmgandhi	18:6a4db94011d3	1591	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1592	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1593
sahilmgandhi	18:6a4db94011d3	1594	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1595	}
sahilmgandhi	18:6a4db94011d3	1596
sahilmgandhi	18:6a4db94011d3	1597	/**
sahilmgandhi	18:6a4db94011d3	1598	* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
sahilmgandhi	18:6a4db94011d3	1599	* (both data and clock lanes are in ULPM)
sahilmgandhi	18:6a4db94011d3	1600	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1601	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1602	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1603	*/
sahilmgandhi	18:6a4db94011d3	1604	HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	1605	{
sahilmgandhi	18:6a4db94011d3	1606	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1607
sahilmgandhi	18:6a4db94011d3	1608	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1609	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1610
sahilmgandhi	18:6a4db94011d3	1611	/* Turn on the DSI PLL */
sahilmgandhi	18:6a4db94011d3	1612	__HAL_DSI_PLL_ENABLE(hdsi);
sahilmgandhi	18:6a4db94011d3	1613
sahilmgandhi	18:6a4db94011d3	1614	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1615	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1616
sahilmgandhi	18:6a4db94011d3	1617	/* Wait for the lock of the PLL */
sahilmgandhi	18:6a4db94011d3	1618	while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
sahilmgandhi	18:6a4db94011d3	1619	{
sahilmgandhi	18:6a4db94011d3	1620	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1621	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1622	{
sahilmgandhi	18:6a4db94011d3	1623	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1624	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1625
sahilmgandhi	18:6a4db94011d3	1626	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1627	}
sahilmgandhi	18:6a4db94011d3	1628	}
sahilmgandhi	18:6a4db94011d3	1629
sahilmgandhi	18:6a4db94011d3	1630	/* Exit ULPS on Clock and Data Lanes */
sahilmgandhi	18:6a4db94011d3	1631	hdsi->Instance->PUCR \|= (DSI_PUCR_UECL \| DSI_PUCR_UEDL);
sahilmgandhi	18:6a4db94011d3	1632
sahilmgandhi	18:6a4db94011d3	1633	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1634	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1635
sahilmgandhi	18:6a4db94011d3	1636	/* Wait until all active lanes exit ULPM */
sahilmgandhi	18:6a4db94011d3	1637	if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
sahilmgandhi	18:6a4db94011d3	1638	{
sahilmgandhi	18:6a4db94011d3	1639	while((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UANC)) != (DSI_PSR_UAN0 \| DSI_PSR_UANC))
sahilmgandhi	18:6a4db94011d3	1640	{
sahilmgandhi	18:6a4db94011d3	1641	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1642	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1643	{
sahilmgandhi	18:6a4db94011d3	1644	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1645	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1646
sahilmgandhi	18:6a4db94011d3	1647	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1648	}
sahilmgandhi	18:6a4db94011d3	1649	}
sahilmgandhi	18:6a4db94011d3	1650	}
sahilmgandhi	18:6a4db94011d3	1651	else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
sahilmgandhi	18:6a4db94011d3	1652	{
sahilmgandhi	18:6a4db94011d3	1653	while((hdsi->Instance->PSR & (DSI_PSR_UAN0 \| DSI_PSR_UAN1 \| DSI_PSR_UANC)) != (DSI_PSR_UAN0 \| DSI_PSR_UAN1 \| DSI_PSR_UANC))
sahilmgandhi	18:6a4db94011d3	1654	{
sahilmgandhi	18:6a4db94011d3	1655	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1656	if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1657	{
sahilmgandhi	18:6a4db94011d3	1658	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1659	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1660
sahilmgandhi	18:6a4db94011d3	1661	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1662	}
sahilmgandhi	18:6a4db94011d3	1663	}
sahilmgandhi	18:6a4db94011d3	1664	}
sahilmgandhi	18:6a4db94011d3	1665
sahilmgandhi	18:6a4db94011d3	1666	/* De-assert the ULPM requests and the ULPM exit bits */
sahilmgandhi	18:6a4db94011d3	1667	hdsi->Instance->PUCR = 0U;
sahilmgandhi	18:6a4db94011d3	1668
sahilmgandhi	18:6a4db94011d3	1669	/* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
sahilmgandhi	18:6a4db94011d3	1670	__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
sahilmgandhi	18:6a4db94011d3	1671
sahilmgandhi	18:6a4db94011d3	1672	/* Restore clock lane configuration to HS */
sahilmgandhi	18:6a4db94011d3	1673	hdsi->Instance->CLCR \|= DSI_CLCR_DPCC;
sahilmgandhi	18:6a4db94011d3	1674
sahilmgandhi	18:6a4db94011d3	1675	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1676	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1677
sahilmgandhi	18:6a4db94011d3	1678	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1679	}
sahilmgandhi	18:6a4db94011d3	1680
sahilmgandhi	18:6a4db94011d3	1681	/**
sahilmgandhi	18:6a4db94011d3	1682	* @brief Start test pattern generation
sahilmgandhi	18:6a4db94011d3	1683	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1684	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1685	* @param Mode: Pattern generator mode
sahilmgandhi	18:6a4db94011d3	1686	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1687	* 0 : Color bars (horizontal or vertical)
sahilmgandhi	18:6a4db94011d3	1688	* 1 : BER pattern (vertical only)
sahilmgandhi	18:6a4db94011d3	1689	* @param Orientation: Pattern generator orientation
sahilmgandhi	18:6a4db94011d3	1690	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1691	* 0 : Vertical color bars
sahilmgandhi	18:6a4db94011d3	1692	* 1 : Horizontal color bars
sahilmgandhi	18:6a4db94011d3	1693	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1694	*/
sahilmgandhi	18:6a4db94011d3	1695	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
sahilmgandhi	18:6a4db94011d3	1696	{
sahilmgandhi	18:6a4db94011d3	1697	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1698	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1699
sahilmgandhi	18:6a4db94011d3	1700	/* Configure pattern generator mode and orientation */
sahilmgandhi	18:6a4db94011d3	1701	hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM \| DSI_VMCR_PGO);
sahilmgandhi	18:6a4db94011d3	1702	hdsi->Instance->VMCR \|= ((Mode<<20U) \| (Orientation<<24U));
sahilmgandhi	18:6a4db94011d3	1703
sahilmgandhi	18:6a4db94011d3	1704	/* Enable pattern generator by setting PGE bit */
sahilmgandhi	18:6a4db94011d3	1705	hdsi->Instance->VMCR \|= DSI_VMCR_PGE;
sahilmgandhi	18:6a4db94011d3	1706
sahilmgandhi	18:6a4db94011d3	1707	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1708	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1709
sahilmgandhi	18:6a4db94011d3	1710	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1711	}
sahilmgandhi	18:6a4db94011d3	1712
sahilmgandhi	18:6a4db94011d3	1713	/**
sahilmgandhi	18:6a4db94011d3	1714	* @brief Stop test pattern generation
sahilmgandhi	18:6a4db94011d3	1715	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1716	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1717	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1718	*/
sahilmgandhi	18:6a4db94011d3	1719	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	1720	{
sahilmgandhi	18:6a4db94011d3	1721	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1722	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1723
sahilmgandhi	18:6a4db94011d3	1724	/* Disable pattern generator by clearing PGE bit */
sahilmgandhi	18:6a4db94011d3	1725	hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
sahilmgandhi	18:6a4db94011d3	1726
sahilmgandhi	18:6a4db94011d3	1727	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1728	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1729
sahilmgandhi	18:6a4db94011d3	1730	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1731	}
sahilmgandhi	18:6a4db94011d3	1732
sahilmgandhi	18:6a4db94011d3	1733	/**
sahilmgandhi	18:6a4db94011d3	1734	* @brief Set Slew-Rate And Delay Tuning
sahilmgandhi	18:6a4db94011d3	1735	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1736	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1737	* @param CommDelay: Communication delay to be adjusted.
sahilmgandhi	18:6a4db94011d3	1738	* This parameter can be any value of @ref DSI_Communication_Delay
sahilmgandhi	18:6a4db94011d3	1739	* @param Lane: select between clock or data lanes.
sahilmgandhi	18:6a4db94011d3	1740	* This parameter can be any value of @ref DSI_Lane_Group
sahilmgandhi	18:6a4db94011d3	1741	* @param Value: Custom value of the slew-rate or delay
sahilmgandhi	18:6a4db94011d3	1742	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1743	*/
sahilmgandhi	18:6a4db94011d3	1744	HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
sahilmgandhi	18:6a4db94011d3	1745	{
sahilmgandhi	18:6a4db94011d3	1746	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1747	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1748
sahilmgandhi	18:6a4db94011d3	1749	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	1750	assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
sahilmgandhi	18:6a4db94011d3	1751	assert_param(IS_DSI_LANE_GROUP(Lane));
sahilmgandhi	18:6a4db94011d3	1752
sahilmgandhi	18:6a4db94011d3	1753	switch(CommDelay)
sahilmgandhi	18:6a4db94011d3	1754	{
sahilmgandhi	18:6a4db94011d3	1755	case DSI_SLEW_RATE_HSTX:
sahilmgandhi	18:6a4db94011d3	1756	if(Lane == DSI_CLOCK_LANE)
sahilmgandhi	18:6a4db94011d3	1757	{
sahilmgandhi	18:6a4db94011d3	1758	/* High-Speed Transmission Slew Rate Control on Clock Lane */
sahilmgandhi	18:6a4db94011d3	1759	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
sahilmgandhi	18:6a4db94011d3	1760	hdsi->Instance->WPCR[1U] \|= Value<<16U;
sahilmgandhi	18:6a4db94011d3	1761	}
sahilmgandhi	18:6a4db94011d3	1762	else if(Lane == DSI_DATA_LANES)
sahilmgandhi	18:6a4db94011d3	1763	{
sahilmgandhi	18:6a4db94011d3	1764	/* High-Speed Transmission Slew Rate Control on Data Lanes */
sahilmgandhi	18:6a4db94011d3	1765	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
sahilmgandhi	18:6a4db94011d3	1766	hdsi->Instance->WPCR[1U] \|= Value<<18U;
sahilmgandhi	18:6a4db94011d3	1767	}
sahilmgandhi	18:6a4db94011d3	1768	break;
sahilmgandhi	18:6a4db94011d3	1769	case DSI_SLEW_RATE_LPTX:
sahilmgandhi	18:6a4db94011d3	1770	if(Lane == DSI_CLOCK_LANE)
sahilmgandhi	18:6a4db94011d3	1771	{
sahilmgandhi	18:6a4db94011d3	1772	/* Low-Power transmission Slew Rate Compensation on Clock Lane */
sahilmgandhi	18:6a4db94011d3	1773	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
sahilmgandhi	18:6a4db94011d3	1774	hdsi->Instance->WPCR[1U] \|= Value<<6U;
sahilmgandhi	18:6a4db94011d3	1775	}
sahilmgandhi	18:6a4db94011d3	1776	else if(Lane == DSI_DATA_LANES)
sahilmgandhi	18:6a4db94011d3	1777	{
sahilmgandhi	18:6a4db94011d3	1778	/* Low-Power transmission Slew Rate Compensation on Data Lanes */
sahilmgandhi	18:6a4db94011d3	1779	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
sahilmgandhi	18:6a4db94011d3	1780	hdsi->Instance->WPCR[1U] \|= Value<<8U;
sahilmgandhi	18:6a4db94011d3	1781	}
sahilmgandhi	18:6a4db94011d3	1782	break;
sahilmgandhi	18:6a4db94011d3	1783	case DSI_HS_DELAY:
sahilmgandhi	18:6a4db94011d3	1784	if(Lane == DSI_CLOCK_LANE)
sahilmgandhi	18:6a4db94011d3	1785	{
sahilmgandhi	18:6a4db94011d3	1786	/* High-Speed Transmission Delay on Clock Lane */
sahilmgandhi	18:6a4db94011d3	1787	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
sahilmgandhi	18:6a4db94011d3	1788	hdsi->Instance->WPCR[1U] \|= Value;
sahilmgandhi	18:6a4db94011d3	1789	}
sahilmgandhi	18:6a4db94011d3	1790	else if(Lane == DSI_DATA_LANES)
sahilmgandhi	18:6a4db94011d3	1791	{
sahilmgandhi	18:6a4db94011d3	1792	/* High-Speed Transmission Delay on Data Lanes */
sahilmgandhi	18:6a4db94011d3	1793	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
sahilmgandhi	18:6a4db94011d3	1794	hdsi->Instance->WPCR[1U] \|= Value<<2U;
sahilmgandhi	18:6a4db94011d3	1795	}
sahilmgandhi	18:6a4db94011d3	1796	break;
sahilmgandhi	18:6a4db94011d3	1797	default:
sahilmgandhi	18:6a4db94011d3	1798	break;
sahilmgandhi	18:6a4db94011d3	1799	}
sahilmgandhi	18:6a4db94011d3	1800
sahilmgandhi	18:6a4db94011d3	1801	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1802	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1803
sahilmgandhi	18:6a4db94011d3	1804	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1805	}
sahilmgandhi	18:6a4db94011d3	1806
sahilmgandhi	18:6a4db94011d3	1807	/**
sahilmgandhi	18:6a4db94011d3	1808	* @brief Low-Power Reception Filter Tuning
sahilmgandhi	18:6a4db94011d3	1809	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1810	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1811	* @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
sahilmgandhi	18:6a4db94011d3	1812	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1813	*/
sahilmgandhi	18:6a4db94011d3	1814	HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
sahilmgandhi	18:6a4db94011d3	1815	{
sahilmgandhi	18:6a4db94011d3	1816	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1817	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1818
sahilmgandhi	18:6a4db94011d3	1819	/* Low-Power RX low-pass Filtering Tuning */
sahilmgandhi	18:6a4db94011d3	1820	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
sahilmgandhi	18:6a4db94011d3	1821	hdsi->Instance->WPCR[1U] \|= Frequency<<25U;
sahilmgandhi	18:6a4db94011d3	1822
sahilmgandhi	18:6a4db94011d3	1823	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1824	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1825
sahilmgandhi	18:6a4db94011d3	1826	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1827	}
sahilmgandhi	18:6a4db94011d3	1828
sahilmgandhi	18:6a4db94011d3	1829	/**
sahilmgandhi	18:6a4db94011d3	1830	* @brief Activate an additional current path on all lanes to meet the SDDTx parameter
sahilmgandhi	18:6a4db94011d3	1831	* defined in the MIPI D-PHY specification
sahilmgandhi	18:6a4db94011d3	1832	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1833	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1834	* @param State: ENABLE or DISABLE
sahilmgandhi	18:6a4db94011d3	1835	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1836	*/
sahilmgandhi	18:6a4db94011d3	1837	HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
sahilmgandhi	18:6a4db94011d3	1838	{
sahilmgandhi	18:6a4db94011d3	1839	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1840	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1841
sahilmgandhi	18:6a4db94011d3	1842	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	1843	assert_param(IS_FUNCTIONAL_STATE(State));
sahilmgandhi	18:6a4db94011d3	1844
sahilmgandhi	18:6a4db94011d3	1845	/* Activate/Disactivate additional current path on all lanes */
sahilmgandhi	18:6a4db94011d3	1846	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
sahilmgandhi	18:6a4db94011d3	1847	hdsi->Instance->WPCR[1U] \|= ((uint32_t)State << 12U);
sahilmgandhi	18:6a4db94011d3	1848
sahilmgandhi	18:6a4db94011d3	1849	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1850	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1851
sahilmgandhi	18:6a4db94011d3	1852	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1853	}
sahilmgandhi	18:6a4db94011d3	1854
sahilmgandhi	18:6a4db94011d3	1855	/**
sahilmgandhi	18:6a4db94011d3	1856	* @brief Custom lane pins configuration
sahilmgandhi	18:6a4db94011d3	1857	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1858	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1859	* @param CustomLane: Function to be applyed on selected lane.
sahilmgandhi	18:6a4db94011d3	1860	* This parameter can be any value of @ref DSI_CustomLane
sahilmgandhi	18:6a4db94011d3	1861	* @param Lane: select between clock or data lane 0 or data lane 1.
sahilmgandhi	18:6a4db94011d3	1862	* This parameter can be any value of @ref DSI_Lane_Select
sahilmgandhi	18:6a4db94011d3	1863	* @param State: ENABLE or DISABLE
sahilmgandhi	18:6a4db94011d3	1864	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1865	*/
sahilmgandhi	18:6a4db94011d3	1866	HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
sahilmgandhi	18:6a4db94011d3	1867	{
sahilmgandhi	18:6a4db94011d3	1868	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1869	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1870
sahilmgandhi	18:6a4db94011d3	1871	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	1872	assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
sahilmgandhi	18:6a4db94011d3	1873	assert_param(IS_DSI_LANE(Lane));
sahilmgandhi	18:6a4db94011d3	1874	assert_param(IS_FUNCTIONAL_STATE(State));
sahilmgandhi	18:6a4db94011d3	1875
sahilmgandhi	18:6a4db94011d3	1876	switch(CustomLane)
sahilmgandhi	18:6a4db94011d3	1877	{
sahilmgandhi	18:6a4db94011d3	1878	case DSI_SWAP_LANE_PINS:
sahilmgandhi	18:6a4db94011d3	1879	if(Lane == DSI_CLOCK_LANE)
sahilmgandhi	18:6a4db94011d3	1880	{
sahilmgandhi	18:6a4db94011d3	1881	/* Swap pins on clock lane */
sahilmgandhi	18:6a4db94011d3	1882	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
sahilmgandhi	18:6a4db94011d3	1883	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 6U);
sahilmgandhi	18:6a4db94011d3	1884	}
sahilmgandhi	18:6a4db94011d3	1885	else if(Lane == DSI_DATA_LANE0)
sahilmgandhi	18:6a4db94011d3	1886	{
sahilmgandhi	18:6a4db94011d3	1887	/* Swap pins on data lane 0 */
sahilmgandhi	18:6a4db94011d3	1888	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
sahilmgandhi	18:6a4db94011d3	1889	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 7U);
sahilmgandhi	18:6a4db94011d3	1890	}
sahilmgandhi	18:6a4db94011d3	1891	else if(Lane == DSI_DATA_LANE1)
sahilmgandhi	18:6a4db94011d3	1892	{
sahilmgandhi	18:6a4db94011d3	1893	/* Swap pins on data lane 1 */
sahilmgandhi	18:6a4db94011d3	1894	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
sahilmgandhi	18:6a4db94011d3	1895	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 8U);
sahilmgandhi	18:6a4db94011d3	1896	}
sahilmgandhi	18:6a4db94011d3	1897	break;
sahilmgandhi	18:6a4db94011d3	1898	case DSI_INVERT_HS_SIGNAL:
sahilmgandhi	18:6a4db94011d3	1899	if(Lane == DSI_CLOCK_LANE)
sahilmgandhi	18:6a4db94011d3	1900	{
sahilmgandhi	18:6a4db94011d3	1901	/* Invert HS signal on clock lane */
sahilmgandhi	18:6a4db94011d3	1902	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
sahilmgandhi	18:6a4db94011d3	1903	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 9U);
sahilmgandhi	18:6a4db94011d3	1904	}
sahilmgandhi	18:6a4db94011d3	1905	else if(Lane == DSI_DATA_LANE0)
sahilmgandhi	18:6a4db94011d3	1906	{
sahilmgandhi	18:6a4db94011d3	1907	/* Invert HS signal on data lane 0 */
sahilmgandhi	18:6a4db94011d3	1908	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
sahilmgandhi	18:6a4db94011d3	1909	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 10U);
sahilmgandhi	18:6a4db94011d3	1910	}
sahilmgandhi	18:6a4db94011d3	1911	else if(Lane == DSI_DATA_LANE1)
sahilmgandhi	18:6a4db94011d3	1912	{
sahilmgandhi	18:6a4db94011d3	1913	/* Invert HS signal on data lane 1 */
sahilmgandhi	18:6a4db94011d3	1914	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
sahilmgandhi	18:6a4db94011d3	1915	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 11U);
sahilmgandhi	18:6a4db94011d3	1916	}
sahilmgandhi	18:6a4db94011d3	1917	break;
sahilmgandhi	18:6a4db94011d3	1918	default:
sahilmgandhi	18:6a4db94011d3	1919	break;
sahilmgandhi	18:6a4db94011d3	1920	}
sahilmgandhi	18:6a4db94011d3	1921
sahilmgandhi	18:6a4db94011d3	1922	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1923	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1924
sahilmgandhi	18:6a4db94011d3	1925	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1926	}
sahilmgandhi	18:6a4db94011d3	1927
sahilmgandhi	18:6a4db94011d3	1928	/**
sahilmgandhi	18:6a4db94011d3	1929	* @brief Set custom timing for the PHY
sahilmgandhi	18:6a4db94011d3	1930	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1931	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	1932	* @param Timing: PHY timing to be adjusted.
sahilmgandhi	18:6a4db94011d3	1933	* This parameter can be any value of @ref DSI_PHY_Timing
sahilmgandhi	18:6a4db94011d3	1934	* @param State: ENABLE or DISABLE
sahilmgandhi	18:6a4db94011d3	1935	* @param Value: Custom value of the timing
sahilmgandhi	18:6a4db94011d3	1936	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1937	*/
sahilmgandhi	18:6a4db94011d3	1938	HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
sahilmgandhi	18:6a4db94011d3	1939	{
sahilmgandhi	18:6a4db94011d3	1940	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1941	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	1942
sahilmgandhi	18:6a4db94011d3	1943	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	1944	assert_param(IS_DSI_PHY_TIMING(Timing));
sahilmgandhi	18:6a4db94011d3	1945	assert_param(IS_FUNCTIONAL_STATE(State));
sahilmgandhi	18:6a4db94011d3	1946
sahilmgandhi	18:6a4db94011d3	1947	switch(Timing)
sahilmgandhi	18:6a4db94011d3	1948	{
sahilmgandhi	18:6a4db94011d3	1949	case DSI_TCLK_POST:
sahilmgandhi	18:6a4db94011d3	1950	/* Enable/Disable custom timing setting */
sahilmgandhi	18:6a4db94011d3	1951	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
sahilmgandhi	18:6a4db94011d3	1952	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 27U);
sahilmgandhi	18:6a4db94011d3	1953
sahilmgandhi	18:6a4db94011d3	1954	if(State)
sahilmgandhi	18:6a4db94011d3	1955	{
sahilmgandhi	18:6a4db94011d3	1956	/* Set custom value */
sahilmgandhi	18:6a4db94011d3	1957	hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
sahilmgandhi	18:6a4db94011d3	1958	hdsi->Instance->WPCR[4U] \|= Value & DSI_WPCR4_TCLKPOST;
sahilmgandhi	18:6a4db94011d3	1959	}
sahilmgandhi	18:6a4db94011d3	1960
sahilmgandhi	18:6a4db94011d3	1961	break;
sahilmgandhi	18:6a4db94011d3	1962	case DSI_TLPX_CLK:
sahilmgandhi	18:6a4db94011d3	1963	/* Enable/Disable custom timing setting */
sahilmgandhi	18:6a4db94011d3	1964	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
sahilmgandhi	18:6a4db94011d3	1965	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 26U);
sahilmgandhi	18:6a4db94011d3	1966
sahilmgandhi	18:6a4db94011d3	1967	if(State)
sahilmgandhi	18:6a4db94011d3	1968	{
sahilmgandhi	18:6a4db94011d3	1969	/* Set custom value */
sahilmgandhi	18:6a4db94011d3	1970	hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
sahilmgandhi	18:6a4db94011d3	1971	hdsi->Instance->WPCR[3U] \|= (Value << 24U) & DSI_WPCR3_TLPXC;
sahilmgandhi	18:6a4db94011d3	1972	}
sahilmgandhi	18:6a4db94011d3	1973
sahilmgandhi	18:6a4db94011d3	1974	break;
sahilmgandhi	18:6a4db94011d3	1975	case DSI_THS_EXIT:
sahilmgandhi	18:6a4db94011d3	1976	/* Enable/Disable custom timing setting */
sahilmgandhi	18:6a4db94011d3	1977	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
sahilmgandhi	18:6a4db94011d3	1978	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 25U);
sahilmgandhi	18:6a4db94011d3	1979
sahilmgandhi	18:6a4db94011d3	1980	if(State)
sahilmgandhi	18:6a4db94011d3	1981	{
sahilmgandhi	18:6a4db94011d3	1982	/* Set custom value */
sahilmgandhi	18:6a4db94011d3	1983	hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
sahilmgandhi	18:6a4db94011d3	1984	hdsi->Instance->WPCR[3U] \|= (Value << 16U) & DSI_WPCR3_THSEXIT;
sahilmgandhi	18:6a4db94011d3	1985	}
sahilmgandhi	18:6a4db94011d3	1986
sahilmgandhi	18:6a4db94011d3	1987	break;
sahilmgandhi	18:6a4db94011d3	1988	case DSI_TLPX_DATA:
sahilmgandhi	18:6a4db94011d3	1989	/* Enable/Disable custom timing setting */
sahilmgandhi	18:6a4db94011d3	1990	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
sahilmgandhi	18:6a4db94011d3	1991	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 24U);
sahilmgandhi	18:6a4db94011d3	1992
sahilmgandhi	18:6a4db94011d3	1993	if(State)
sahilmgandhi	18:6a4db94011d3	1994	{
sahilmgandhi	18:6a4db94011d3	1995	/* Set custom value */
sahilmgandhi	18:6a4db94011d3	1996	hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
sahilmgandhi	18:6a4db94011d3	1997	hdsi->Instance->WPCR[3U] \|= (Value << 8U) & DSI_WPCR3_TLPXD;
sahilmgandhi	18:6a4db94011d3	1998	}
sahilmgandhi	18:6a4db94011d3	1999
sahilmgandhi	18:6a4db94011d3	2000	break;
sahilmgandhi	18:6a4db94011d3	2001	case DSI_THS_ZERO:
sahilmgandhi	18:6a4db94011d3	2002	/* Enable/Disable custom timing setting */
sahilmgandhi	18:6a4db94011d3	2003	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
sahilmgandhi	18:6a4db94011d3	2004	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 23U);
sahilmgandhi	18:6a4db94011d3	2005
sahilmgandhi	18:6a4db94011d3	2006	if(State)
sahilmgandhi	18:6a4db94011d3	2007	{
sahilmgandhi	18:6a4db94011d3	2008	/* Set custom value */
sahilmgandhi	18:6a4db94011d3	2009	hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
sahilmgandhi	18:6a4db94011d3	2010	hdsi->Instance->WPCR[3U] \|= Value & DSI_WPCR3_THSZERO;
sahilmgandhi	18:6a4db94011d3	2011	}
sahilmgandhi	18:6a4db94011d3	2012
sahilmgandhi	18:6a4db94011d3	2013	break;
sahilmgandhi	18:6a4db94011d3	2014	case DSI_THS_TRAIL:
sahilmgandhi	18:6a4db94011d3	2015	/* Enable/Disable custom timing setting */
sahilmgandhi	18:6a4db94011d3	2016	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
sahilmgandhi	18:6a4db94011d3	2017	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 22U);
sahilmgandhi	18:6a4db94011d3	2018
sahilmgandhi	18:6a4db94011d3	2019	if(State)
sahilmgandhi	18:6a4db94011d3	2020	{
sahilmgandhi	18:6a4db94011d3	2021	/* Set custom value */
sahilmgandhi	18:6a4db94011d3	2022	hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
sahilmgandhi	18:6a4db94011d3	2023	hdsi->Instance->WPCR[2U] \|= (Value << 24U) & DSI_WPCR2_THSTRAIL;
sahilmgandhi	18:6a4db94011d3	2024	}
sahilmgandhi	18:6a4db94011d3	2025
sahilmgandhi	18:6a4db94011d3	2026	break;
sahilmgandhi	18:6a4db94011d3	2027	case DSI_THS_PREPARE:
sahilmgandhi	18:6a4db94011d3	2028	/* Enable/Disable custom timing setting */
sahilmgandhi	18:6a4db94011d3	2029	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
sahilmgandhi	18:6a4db94011d3	2030	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 21U);
sahilmgandhi	18:6a4db94011d3	2031
sahilmgandhi	18:6a4db94011d3	2032	if(State)
sahilmgandhi	18:6a4db94011d3	2033	{
sahilmgandhi	18:6a4db94011d3	2034	/* Set custom value */
sahilmgandhi	18:6a4db94011d3	2035	hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
sahilmgandhi	18:6a4db94011d3	2036	hdsi->Instance->WPCR[2U] \|= (Value << 16U) & DSI_WPCR2_THSPREP;
sahilmgandhi	18:6a4db94011d3	2037	}
sahilmgandhi	18:6a4db94011d3	2038
sahilmgandhi	18:6a4db94011d3	2039	break;
sahilmgandhi	18:6a4db94011d3	2040	case DSI_TCLK_ZERO:
sahilmgandhi	18:6a4db94011d3	2041	/* Enable/Disable custom timing setting */
sahilmgandhi	18:6a4db94011d3	2042	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
sahilmgandhi	18:6a4db94011d3	2043	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 20U);
sahilmgandhi	18:6a4db94011d3	2044
sahilmgandhi	18:6a4db94011d3	2045	if(State)
sahilmgandhi	18:6a4db94011d3	2046	{
sahilmgandhi	18:6a4db94011d3	2047	/* Set custom value */
sahilmgandhi	18:6a4db94011d3	2048	hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
sahilmgandhi	18:6a4db94011d3	2049	hdsi->Instance->WPCR[2U] \|= (Value << 8U) & DSI_WPCR2_TCLKZERO;
sahilmgandhi	18:6a4db94011d3	2050	}
sahilmgandhi	18:6a4db94011d3	2051
sahilmgandhi	18:6a4db94011d3	2052	break;
sahilmgandhi	18:6a4db94011d3	2053	case DSI_TCLK_PREPARE:
sahilmgandhi	18:6a4db94011d3	2054	/* Enable/Disable custom timing setting */
sahilmgandhi	18:6a4db94011d3	2055	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
sahilmgandhi	18:6a4db94011d3	2056	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 19U);
sahilmgandhi	18:6a4db94011d3	2057
sahilmgandhi	18:6a4db94011d3	2058	if(State)
sahilmgandhi	18:6a4db94011d3	2059	{
sahilmgandhi	18:6a4db94011d3	2060	/* Set custom value */
sahilmgandhi	18:6a4db94011d3	2061	hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
sahilmgandhi	18:6a4db94011d3	2062	hdsi->Instance->WPCR[2U] \|= Value & DSI_WPCR2_TCLKPREP;
sahilmgandhi	18:6a4db94011d3	2063	}
sahilmgandhi	18:6a4db94011d3	2064
sahilmgandhi	18:6a4db94011d3	2065	break;
sahilmgandhi	18:6a4db94011d3	2066	default:
sahilmgandhi	18:6a4db94011d3	2067	break;
sahilmgandhi	18:6a4db94011d3	2068	}
sahilmgandhi	18:6a4db94011d3	2069
sahilmgandhi	18:6a4db94011d3	2070	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	2071	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2072
sahilmgandhi	18:6a4db94011d3	2073	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2074	}
sahilmgandhi	18:6a4db94011d3	2075
sahilmgandhi	18:6a4db94011d3	2076	/**
sahilmgandhi	18:6a4db94011d3	2077	* @brief Force the Clock/Data Lane in TX Stop Mode
sahilmgandhi	18:6a4db94011d3	2078	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2079	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	2080	* @param Lane: select between clock or data lanes.
sahilmgandhi	18:6a4db94011d3	2081	* This parameter can be any value of @ref DSI_Lane_Group
sahilmgandhi	18:6a4db94011d3	2082	* @param State: ENABLE or DISABLE
sahilmgandhi	18:6a4db94011d3	2083	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2084	*/
sahilmgandhi	18:6a4db94011d3	2085	HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
sahilmgandhi	18:6a4db94011d3	2086	{
sahilmgandhi	18:6a4db94011d3	2087	/* Process locked */
sahilmgandhi	18:6a4db94011d3	2088	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2089
sahilmgandhi	18:6a4db94011d3	2090	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	2091	assert_param(IS_DSI_LANE_GROUP(Lane));
sahilmgandhi	18:6a4db94011d3	2092	assert_param(IS_FUNCTIONAL_STATE(State));
sahilmgandhi	18:6a4db94011d3	2093
sahilmgandhi	18:6a4db94011d3	2094	if(Lane == DSI_CLOCK_LANE)
sahilmgandhi	18:6a4db94011d3	2095	{
sahilmgandhi	18:6a4db94011d3	2096	/* Force/Unforce the Clock Lane in TX Stop Mode */
sahilmgandhi	18:6a4db94011d3	2097	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
sahilmgandhi	18:6a4db94011d3	2098	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 12U);
sahilmgandhi	18:6a4db94011d3	2099	}
sahilmgandhi	18:6a4db94011d3	2100	else if(Lane == DSI_DATA_LANES)
sahilmgandhi	18:6a4db94011d3	2101	{
sahilmgandhi	18:6a4db94011d3	2102	/* Force/Unforce the Data Lanes in TX Stop Mode */
sahilmgandhi	18:6a4db94011d3	2103	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
sahilmgandhi	18:6a4db94011d3	2104	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 13U);
sahilmgandhi	18:6a4db94011d3	2105	}
sahilmgandhi	18:6a4db94011d3	2106
sahilmgandhi	18:6a4db94011d3	2107	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	2108	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2109
sahilmgandhi	18:6a4db94011d3	2110	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2111	}
sahilmgandhi	18:6a4db94011d3	2112
sahilmgandhi	18:6a4db94011d3	2113	/**
sahilmgandhi	18:6a4db94011d3	2114	* @brief Forces LP Receiver in Low-Power Mode
sahilmgandhi	18:6a4db94011d3	2115	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2116	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	2117	* @param State: ENABLE or DISABLE
sahilmgandhi	18:6a4db94011d3	2118	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2119	*/
sahilmgandhi	18:6a4db94011d3	2120	HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
sahilmgandhi	18:6a4db94011d3	2121	{
sahilmgandhi	18:6a4db94011d3	2122	/* Process locked */
sahilmgandhi	18:6a4db94011d3	2123	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2124
sahilmgandhi	18:6a4db94011d3	2125	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	2126	assert_param(IS_FUNCTIONAL_STATE(State));
sahilmgandhi	18:6a4db94011d3	2127
sahilmgandhi	18:6a4db94011d3	2128	/* Force/Unforce LP Receiver in Low-Power Mode */
sahilmgandhi	18:6a4db94011d3	2129	hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
sahilmgandhi	18:6a4db94011d3	2130	hdsi->Instance->WPCR[1U] \|= ((uint32_t)State << 22U);
sahilmgandhi	18:6a4db94011d3	2131
sahilmgandhi	18:6a4db94011d3	2132	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	2133	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2134
sahilmgandhi	18:6a4db94011d3	2135	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2136	}
sahilmgandhi	18:6a4db94011d3	2137
sahilmgandhi	18:6a4db94011d3	2138	/**
sahilmgandhi	18:6a4db94011d3	2139	* @brief Force Data Lanes in RX Mode after a BTA
sahilmgandhi	18:6a4db94011d3	2140	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2141	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	2142	* @param State: ENABLE or DISABLE
sahilmgandhi	18:6a4db94011d3	2143	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2144	*/
sahilmgandhi	18:6a4db94011d3	2145	HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
sahilmgandhi	18:6a4db94011d3	2146	{
sahilmgandhi	18:6a4db94011d3	2147	/* Process locked */
sahilmgandhi	18:6a4db94011d3	2148	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2149
sahilmgandhi	18:6a4db94011d3	2150	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	2151	assert_param(IS_FUNCTIONAL_STATE(State));
sahilmgandhi	18:6a4db94011d3	2152
sahilmgandhi	18:6a4db94011d3	2153	/* Force Data Lanes in RX Mode */
sahilmgandhi	18:6a4db94011d3	2154	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
sahilmgandhi	18:6a4db94011d3	2155	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 16U);
sahilmgandhi	18:6a4db94011d3	2156
sahilmgandhi	18:6a4db94011d3	2157	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	2158	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2159
sahilmgandhi	18:6a4db94011d3	2160	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2161	}
sahilmgandhi	18:6a4db94011d3	2162
sahilmgandhi	18:6a4db94011d3	2163	/**
sahilmgandhi	18:6a4db94011d3	2164	* @brief Enable a pull-down on the lanes to prevent from floating states when unused
sahilmgandhi	18:6a4db94011d3	2165	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2166	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	2167	* @param State: ENABLE or DISABLE
sahilmgandhi	18:6a4db94011d3	2168	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2169	*/
sahilmgandhi	18:6a4db94011d3	2170	HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
sahilmgandhi	18:6a4db94011d3	2171	{
sahilmgandhi	18:6a4db94011d3	2172	/* Process locked */
sahilmgandhi	18:6a4db94011d3	2173	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2174
sahilmgandhi	18:6a4db94011d3	2175	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	2176	assert_param(IS_FUNCTIONAL_STATE(State));
sahilmgandhi	18:6a4db94011d3	2177
sahilmgandhi	18:6a4db94011d3	2178	/* Enable/Disable pull-down on lanes */
sahilmgandhi	18:6a4db94011d3	2179	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
sahilmgandhi	18:6a4db94011d3	2180	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 18U);
sahilmgandhi	18:6a4db94011d3	2181
sahilmgandhi	18:6a4db94011d3	2182	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	2183	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2184
sahilmgandhi	18:6a4db94011d3	2185	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2186	}
sahilmgandhi	18:6a4db94011d3	2187
sahilmgandhi	18:6a4db94011d3	2188	/**
sahilmgandhi	18:6a4db94011d3	2189	* @brief Switch off the contention detection on data lanes
sahilmgandhi	18:6a4db94011d3	2190	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2191	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	2192	* @param State: ENABLE or DISABLE
sahilmgandhi	18:6a4db94011d3	2193	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2194	*/
sahilmgandhi	18:6a4db94011d3	2195	HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
sahilmgandhi	18:6a4db94011d3	2196	{
sahilmgandhi	18:6a4db94011d3	2197	/* Process locked */
sahilmgandhi	18:6a4db94011d3	2198	__HAL_LOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2199
sahilmgandhi	18:6a4db94011d3	2200	/* Check function parameters */
sahilmgandhi	18:6a4db94011d3	2201	assert_param(IS_FUNCTIONAL_STATE(State));
sahilmgandhi	18:6a4db94011d3	2202
sahilmgandhi	18:6a4db94011d3	2203	/* Contention Detection on Data Lanes OFF */
sahilmgandhi	18:6a4db94011d3	2204	hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
sahilmgandhi	18:6a4db94011d3	2205	hdsi->Instance->WPCR[0U] \|= ((uint32_t)State << 14U);
sahilmgandhi	18:6a4db94011d3	2206
sahilmgandhi	18:6a4db94011d3	2207	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	2208	__HAL_UNLOCK(hdsi);
sahilmgandhi	18:6a4db94011d3	2209
sahilmgandhi	18:6a4db94011d3	2210	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2211	}
sahilmgandhi	18:6a4db94011d3	2212
sahilmgandhi	18:6a4db94011d3	2213	/**
sahilmgandhi	18:6a4db94011d3	2214	* @}
sahilmgandhi	18:6a4db94011d3	2215	*/
sahilmgandhi	18:6a4db94011d3	2216
sahilmgandhi	18:6a4db94011d3	2217	/** @defgroup DSI_Group4 Peripheral State and Errors functions
sahilmgandhi	18:6a4db94011d3	2218	* @brief Peripheral State and Errors functions
sahilmgandhi	18:6a4db94011d3	2219	*
sahilmgandhi	18:6a4db94011d3	2220	@verbatim
sahilmgandhi	18:6a4db94011d3	2221	===============================================================================
sahilmgandhi	18:6a4db94011d3	2222	##### Peripheral State and Errors functions #####
sahilmgandhi	18:6a4db94011d3	2223	===============================================================================
sahilmgandhi	18:6a4db94011d3	2224	[..]
sahilmgandhi	18:6a4db94011d3	2225	This subsection provides functions allowing to
sahilmgandhi	18:6a4db94011d3	2226	(+) Check the DSI state.
sahilmgandhi	18:6a4db94011d3	2227	(+) Get error code.
sahilmgandhi	18:6a4db94011d3	2228
sahilmgandhi	18:6a4db94011d3	2229	@endverbatim
sahilmgandhi	18:6a4db94011d3	2230	* @{
sahilmgandhi	18:6a4db94011d3	2231	*/
sahilmgandhi	18:6a4db94011d3	2232
sahilmgandhi	18:6a4db94011d3	2233	/**
sahilmgandhi	18:6a4db94011d3	2234	* @brief Return the DSI state
sahilmgandhi	18:6a4db94011d3	2235	* @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2236	* the configuration information for the DSI.
sahilmgandhi	18:6a4db94011d3	2237	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	2238	*/
sahilmgandhi	18:6a4db94011d3	2239	HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
sahilmgandhi	18:6a4db94011d3	2240	{
sahilmgandhi	18:6a4db94011d3	2241	return hdsi->State;
sahilmgandhi	18:6a4db94011d3	2242	}
sahilmgandhi	18:6a4db94011d3	2243
sahilmgandhi	18:6a4db94011d3	2244	/**
sahilmgandhi	18:6a4db94011d3	2245	* @}
sahilmgandhi	18:6a4db94011d3	2246	*/
sahilmgandhi	18:6a4db94011d3	2247
sahilmgandhi	18:6a4db94011d3	2248	/**
sahilmgandhi	18:6a4db94011d3	2249	* @}
sahilmgandhi	18:6a4db94011d3	2250	*/
sahilmgandhi	18:6a4db94011d3	2251	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	2252	#endif /* HAL_DSI_MODULE_ENABLED */
sahilmgandhi	18:6a4db94011d3	2253	/**
sahilmgandhi	18:6a4db94011d3	2254	* @}
sahilmgandhi	18:6a4db94011d3	2255	*/
sahilmgandhi	18:6a4db94011d3	2256
sahilmgandhi	18:6a4db94011d3	2257	/**
sahilmgandhi	18:6a4db94011d3	2258	* @}
sahilmgandhi	18:6a4db94011d3	2259	*/
sahilmgandhi	18:6a4db94011d3	2260
sahilmgandhi	18:6a4db94011d3	2261	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c@46:b156ef445742, 2017-06-03 (annotated)

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