MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_dma2d.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of DMA2D HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F4xx_HAL_DMA2D_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F4xx_HAL_DMA2D_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 47 defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 48 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 49 #include "stm32f4xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 52 * @{
sahilmgandhi 18:6a4db94011d3 53 */
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 /** @addtogroup DMA2D DMA2D
sahilmgandhi 18:6a4db94011d3 56 * @brief DMA2D HAL module driver
sahilmgandhi 18:6a4db94011d3 57 * @{
sahilmgandhi 18:6a4db94011d3 58 */
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 61 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
sahilmgandhi 18:6a4db94011d3 62 * @{
sahilmgandhi 18:6a4db94011d3 63 */
sahilmgandhi 18:6a4db94011d3 64 #define MAX_DMA2D_LAYER 2U
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 /**
sahilmgandhi 18:6a4db94011d3 67 * @brief DMA2D color Structure definition
sahilmgandhi 18:6a4db94011d3 68 */
sahilmgandhi 18:6a4db94011d3 69 typedef struct
sahilmgandhi 18:6a4db94011d3 70 {
sahilmgandhi 18:6a4db94011d3 71 uint32_t Blue; /*!< Configures the blue value.
sahilmgandhi 18:6a4db94011d3 72 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 uint32_t Green; /*!< Configures the green value.
sahilmgandhi 18:6a4db94011d3 75 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 uint32_t Red; /*!< Configures the red value.
sahilmgandhi 18:6a4db94011d3 78 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
sahilmgandhi 18:6a4db94011d3 79 } DMA2D_ColorTypeDef;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /**
sahilmgandhi 18:6a4db94011d3 82 * @brief DMA2D CLUT Structure definition
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84 typedef struct
sahilmgandhi 18:6a4db94011d3 85 {
sahilmgandhi 18:6a4db94011d3 86 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
sahilmgandhi 18:6a4db94011d3 89 This parameter can be one value of @ref DMA2D_CLUT_CM. */
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 uint32_t Size; /*!< Configures the DMA2D CLUT size.
sahilmgandhi 18:6a4db94011d3 92 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
sahilmgandhi 18:6a4db94011d3 93 } DMA2D_CLUTCfgTypeDef;
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /**
sahilmgandhi 18:6a4db94011d3 96 * @brief DMA2D Init structure definition
sahilmgandhi 18:6a4db94011d3 97 */
sahilmgandhi 18:6a4db94011d3 98 typedef struct
sahilmgandhi 18:6a4db94011d3 99 {
sahilmgandhi 18:6a4db94011d3 100 uint32_t Mode; /*!< Configures the DMA2D transfer mode.
sahilmgandhi 18:6a4db94011d3 101 This parameter can be one value of @ref DMA2D_Mode. */
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 uint32_t ColorMode; /*!< Configures the color format of the output image.
sahilmgandhi 18:6a4db94011d3 104 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 uint32_t OutputOffset; /*!< Specifies the Offset value.
sahilmgandhi 18:6a4db94011d3 107 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 } DMA2D_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /**
sahilmgandhi 18:6a4db94011d3 112 * @brief DMA2D Layer structure definition
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114 typedef struct
sahilmgandhi 18:6a4db94011d3 115 {
sahilmgandhi 18:6a4db94011d3 116 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
sahilmgandhi 18:6a4db94011d3 117 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
sahilmgandhi 18:6a4db94011d3 120 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
sahilmgandhi 18:6a4db94011d3 123 This parameter can be one value of @ref DMA2D_Alpha_Mode. */
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
sahilmgandhi 18:6a4db94011d3 126 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
sahilmgandhi 18:6a4db94011d3 127 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
sahilmgandhi 18:6a4db94011d3 128 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
sahilmgandhi 18:6a4db94011d3 129 - InputAlpha[24:31] is the alpha value ALPHA[0:7]
sahilmgandhi 18:6a4db94011d3 130 - InputAlpha[16:23] is the red value RED[0:7]
sahilmgandhi 18:6a4db94011d3 131 - InputAlpha[8:15] is the green value GREEN[0:7]
sahilmgandhi 18:6a4db94011d3 132 - InputAlpha[0:7] is the blue value BLUE[0:7]. */
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 } DMA2D_LayerCfgTypeDef;
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 /**
sahilmgandhi 18:6a4db94011d3 137 * @brief HAL DMA2D State structures definition
sahilmgandhi 18:6a4db94011d3 138 */
sahilmgandhi 18:6a4db94011d3 139 typedef enum
sahilmgandhi 18:6a4db94011d3 140 {
sahilmgandhi 18:6a4db94011d3 141 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
sahilmgandhi 18:6a4db94011d3 142 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
sahilmgandhi 18:6a4db94011d3 143 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
sahilmgandhi 18:6a4db94011d3 144 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
sahilmgandhi 18:6a4db94011d3 145 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
sahilmgandhi 18:6a4db94011d3 146 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
sahilmgandhi 18:6a4db94011d3 147 }HAL_DMA2D_StateTypeDef;
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 /**
sahilmgandhi 18:6a4db94011d3 150 * @brief DMA2D handle Structure definition
sahilmgandhi 18:6a4db94011d3 151 */
sahilmgandhi 18:6a4db94011d3 152 typedef struct __DMA2D_HandleTypeDef
sahilmgandhi 18:6a4db94011d3 153 {
sahilmgandhi 18:6a4db94011d3 154 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 HAL_LockTypeDef Lock; /*!< DMA2D lock. */
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 __IO uint32_t ErrorCode; /*!< DMA2D error code. */
sahilmgandhi 18:6a4db94011d3 169 } DMA2D_HandleTypeDef;
sahilmgandhi 18:6a4db94011d3 170 /**
sahilmgandhi 18:6a4db94011d3 171 * @}
sahilmgandhi 18:6a4db94011d3 172 */
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 175 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
sahilmgandhi 18:6a4db94011d3 176 * @{
sahilmgandhi 18:6a4db94011d3 177 */
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /** @defgroup DMA2D_Error_Code DMA2D Error Code
sahilmgandhi 18:6a4db94011d3 180 * @{
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182 #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
sahilmgandhi 18:6a4db94011d3 183 #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
sahilmgandhi 18:6a4db94011d3 184 #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */
sahilmgandhi 18:6a4db94011d3 185 #define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */
sahilmgandhi 18:6a4db94011d3 186 #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
sahilmgandhi 18:6a4db94011d3 187 /**
sahilmgandhi 18:6a4db94011d3 188 * @}
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 /** @defgroup DMA2D_Mode DMA2D Mode
sahilmgandhi 18:6a4db94011d3 192 * @{
sahilmgandhi 18:6a4db94011d3 193 */
sahilmgandhi 18:6a4db94011d3 194 #define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */
sahilmgandhi 18:6a4db94011d3 195 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
sahilmgandhi 18:6a4db94011d3 196 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
sahilmgandhi 18:6a4db94011d3 197 #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
sahilmgandhi 18:6a4db94011d3 198 /**
sahilmgandhi 18:6a4db94011d3 199 * @}
sahilmgandhi 18:6a4db94011d3 200 */
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
sahilmgandhi 18:6a4db94011d3 203 * @{
sahilmgandhi 18:6a4db94011d3 204 */
sahilmgandhi 18:6a4db94011d3 205 #define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */
sahilmgandhi 18:6a4db94011d3 206 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
sahilmgandhi 18:6a4db94011d3 207 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
sahilmgandhi 18:6a4db94011d3 208 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
sahilmgandhi 18:6a4db94011d3 209 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
sahilmgandhi 18:6a4db94011d3 210 /**
sahilmgandhi 18:6a4db94011d3 211 * @}
sahilmgandhi 18:6a4db94011d3 212 */
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
sahilmgandhi 18:6a4db94011d3 215 * @{
sahilmgandhi 18:6a4db94011d3 216 */
sahilmgandhi 18:6a4db94011d3 217 #define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */
sahilmgandhi 18:6a4db94011d3 218 #define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */
sahilmgandhi 18:6a4db94011d3 219 #define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */
sahilmgandhi 18:6a4db94011d3 220 #define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */
sahilmgandhi 18:6a4db94011d3 221 #define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */
sahilmgandhi 18:6a4db94011d3 222 #define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */
sahilmgandhi 18:6a4db94011d3 223 #define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */
sahilmgandhi 18:6a4db94011d3 224 #define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */
sahilmgandhi 18:6a4db94011d3 225 #define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */
sahilmgandhi 18:6a4db94011d3 226 #define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */
sahilmgandhi 18:6a4db94011d3 227 #define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */
sahilmgandhi 18:6a4db94011d3 228 /**
sahilmgandhi 18:6a4db94011d3 229 * @}
sahilmgandhi 18:6a4db94011d3 230 */
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
sahilmgandhi 18:6a4db94011d3 233 * @{
sahilmgandhi 18:6a4db94011d3 234 */
sahilmgandhi 18:6a4db94011d3 235 #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
sahilmgandhi 18:6a4db94011d3 236 #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */
sahilmgandhi 18:6a4db94011d3 237 #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value
sahilmgandhi 18:6a4db94011d3 238 with original alpha channel value */
sahilmgandhi 18:6a4db94011d3 239 /**
sahilmgandhi 18:6a4db94011d3 240 * @}
sahilmgandhi 18:6a4db94011d3 241 */
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
sahilmgandhi 18:6a4db94011d3 244 * @{
sahilmgandhi 18:6a4db94011d3 245 */
sahilmgandhi 18:6a4db94011d3 246 #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */
sahilmgandhi 18:6a4db94011d3 247 #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */
sahilmgandhi 18:6a4db94011d3 248 /**
sahilmgandhi 18:6a4db94011d3 249 * @}
sahilmgandhi 18:6a4db94011d3 250 */
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
sahilmgandhi 18:6a4db94011d3 253 * @{
sahilmgandhi 18:6a4db94011d3 254 */
sahilmgandhi 18:6a4db94011d3 255 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
sahilmgandhi 18:6a4db94011d3 256 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
sahilmgandhi 18:6a4db94011d3 257 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
sahilmgandhi 18:6a4db94011d3 258 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
sahilmgandhi 18:6a4db94011d3 259 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
sahilmgandhi 18:6a4db94011d3 260 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
sahilmgandhi 18:6a4db94011d3 261 /**
sahilmgandhi 18:6a4db94011d3 262 * @}
sahilmgandhi 18:6a4db94011d3 263 */
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /** @defgroup DMA2D_Flags DMA2D Flags
sahilmgandhi 18:6a4db94011d3 266 * @{
sahilmgandhi 18:6a4db94011d3 267 */
sahilmgandhi 18:6a4db94011d3 268 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 269 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 270 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 271 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 272 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 273 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 274 /**
sahilmgandhi 18:6a4db94011d3 275 * @}
sahilmgandhi 18:6a4db94011d3 276 */
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 /** @defgroup DMA2D_Aliases DMA2D API Aliases
sahilmgandhi 18:6a4db94011d3 279 * @{
sahilmgandhi 18:6a4db94011d3 280 */
sahilmgandhi 18:6a4db94011d3 281 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
sahilmgandhi 18:6a4db94011d3 282 /**
sahilmgandhi 18:6a4db94011d3 283 * @}
sahilmgandhi 18:6a4db94011d3 284 */
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 /**
sahilmgandhi 18:6a4db94011d3 287 * @}
sahilmgandhi 18:6a4db94011d3 288 */
sahilmgandhi 18:6a4db94011d3 289 /* Exported macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 290 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
sahilmgandhi 18:6a4db94011d3 291 * @{
sahilmgandhi 18:6a4db94011d3 292 */
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 /** @brief Reset DMA2D handle state
sahilmgandhi 18:6a4db94011d3 295 * @param __HANDLE__: specifies the DMA2D handle.
sahilmgandhi 18:6a4db94011d3 296 * @retval None
sahilmgandhi 18:6a4db94011d3 297 */
sahilmgandhi 18:6a4db94011d3 298 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 /**
sahilmgandhi 18:6a4db94011d3 301 * @brief Enable the DMA2D.
sahilmgandhi 18:6a4db94011d3 302 * @param __HANDLE__: DMA2D handle
sahilmgandhi 18:6a4db94011d3 303 * @retval None.
sahilmgandhi 18:6a4db94011d3 304 */
sahilmgandhi 18:6a4db94011d3 305 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Interrupt & Flag management */
sahilmgandhi 18:6a4db94011d3 308 /**
sahilmgandhi 18:6a4db94011d3 309 * @brief Get the DMA2D pending flags.
sahilmgandhi 18:6a4db94011d3 310 * @param __HANDLE__: DMA2D handle
sahilmgandhi 18:6a4db94011d3 311 * @param __FLAG__: flag to check.
sahilmgandhi 18:6a4db94011d3 312 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 313 * @arg DMA2D_FLAG_CE: Configuration error flag
sahilmgandhi 18:6a4db94011d3 314 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
sahilmgandhi 18:6a4db94011d3 315 * @arg DMA2D_FLAG_CAE: CLUT access error flag
sahilmgandhi 18:6a4db94011d3 316 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
sahilmgandhi 18:6a4db94011d3 317 * @arg DMA2D_FLAG_TC: Transfer complete flag
sahilmgandhi 18:6a4db94011d3 318 * @arg DMA2D_FLAG_TE: Transfer error flag
sahilmgandhi 18:6a4db94011d3 319 * @retval The state of FLAG.
sahilmgandhi 18:6a4db94011d3 320 */
sahilmgandhi 18:6a4db94011d3 321 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 /**
sahilmgandhi 18:6a4db94011d3 324 * @brief Clear the DMA2D pending flags.
sahilmgandhi 18:6a4db94011d3 325 * @param __HANDLE__: DMA2D handle
sahilmgandhi 18:6a4db94011d3 326 * @param __FLAG__: specifies the flag to clear.
sahilmgandhi 18:6a4db94011d3 327 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 328 * @arg DMA2D_FLAG_CE: Configuration error flag
sahilmgandhi 18:6a4db94011d3 329 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
sahilmgandhi 18:6a4db94011d3 330 * @arg DMA2D_FLAG_CAE: CLUT access error flag
sahilmgandhi 18:6a4db94011d3 331 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
sahilmgandhi 18:6a4db94011d3 332 * @arg DMA2D_FLAG_TC: Transfer complete flag
sahilmgandhi 18:6a4db94011d3 333 * @arg DMA2D_FLAG_TE: Transfer error flag
sahilmgandhi 18:6a4db94011d3 334 * @retval None
sahilmgandhi 18:6a4db94011d3 335 */
sahilmgandhi 18:6a4db94011d3 336 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 /**
sahilmgandhi 18:6a4db94011d3 339 * @brief Enable the specified DMA2D interrupts.
sahilmgandhi 18:6a4db94011d3 340 * @param __HANDLE__: DMA2D handle
sahilmgandhi 18:6a4db94011d3 341 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
sahilmgandhi 18:6a4db94011d3 342 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 343 * @arg DMA2D_IT_CE: Configuration error interrupt mask
sahilmgandhi 18:6a4db94011d3 344 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
sahilmgandhi 18:6a4db94011d3 345 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
sahilmgandhi 18:6a4db94011d3 346 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
sahilmgandhi 18:6a4db94011d3 347 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
sahilmgandhi 18:6a4db94011d3 348 * @arg DMA2D_IT_TE: Transfer error interrupt mask
sahilmgandhi 18:6a4db94011d3 349 * @retval None
sahilmgandhi 18:6a4db94011d3 350 */
sahilmgandhi 18:6a4db94011d3 351 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 /**
sahilmgandhi 18:6a4db94011d3 354 * @brief Disable the specified DMA2D interrupts.
sahilmgandhi 18:6a4db94011d3 355 * @param __HANDLE__: DMA2D handle
sahilmgandhi 18:6a4db94011d3 356 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
sahilmgandhi 18:6a4db94011d3 357 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 358 * @arg DMA2D_IT_CE: Configuration error interrupt mask
sahilmgandhi 18:6a4db94011d3 359 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
sahilmgandhi 18:6a4db94011d3 360 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
sahilmgandhi 18:6a4db94011d3 361 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
sahilmgandhi 18:6a4db94011d3 362 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
sahilmgandhi 18:6a4db94011d3 363 * @arg DMA2D_IT_TE: Transfer error interrupt mask
sahilmgandhi 18:6a4db94011d3 364 * @retval None
sahilmgandhi 18:6a4db94011d3 365 */
sahilmgandhi 18:6a4db94011d3 366 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 /**
sahilmgandhi 18:6a4db94011d3 369 * @brief Check whether the specified DMA2D interrupt source is enabled or not.
sahilmgandhi 18:6a4db94011d3 370 * @param __HANDLE__: DMA2D handle
sahilmgandhi 18:6a4db94011d3 371 * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
sahilmgandhi 18:6a4db94011d3 372 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 373 * @arg DMA2D_IT_CE: Configuration error interrupt mask
sahilmgandhi 18:6a4db94011d3 374 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
sahilmgandhi 18:6a4db94011d3 375 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask
sahilmgandhi 18:6a4db94011d3 376 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
sahilmgandhi 18:6a4db94011d3 377 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
sahilmgandhi 18:6a4db94011d3 378 * @arg DMA2D_IT_TE: Transfer error interrupt mask
sahilmgandhi 18:6a4db94011d3 379 * @retval The state of INTERRUPT source.
sahilmgandhi 18:6a4db94011d3 380 */
sahilmgandhi 18:6a4db94011d3 381 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 382
sahilmgandhi 18:6a4db94011d3 383 /**
sahilmgandhi 18:6a4db94011d3 384 * @}
sahilmgandhi 18:6a4db94011d3 385 */
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 388 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
sahilmgandhi 18:6a4db94011d3 389 * @{
sahilmgandhi 18:6a4db94011d3 390 */
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 393 * @{
sahilmgandhi 18:6a4db94011d3 394 */
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 /* Initialization and de-initialization functions *******************************/
sahilmgandhi 18:6a4db94011d3 397 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 398 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 399 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
sahilmgandhi 18:6a4db94011d3 400 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
sahilmgandhi 18:6a4db94011d3 401
sahilmgandhi 18:6a4db94011d3 402 /**
sahilmgandhi 18:6a4db94011d3 403 * @}
sahilmgandhi 18:6a4db94011d3 404 */
sahilmgandhi 18:6a4db94011d3 405
sahilmgandhi 18:6a4db94011d3 406 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
sahilmgandhi 18:6a4db94011d3 407 * @{
sahilmgandhi 18:6a4db94011d3 408 */
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 /* IO operation functions *******************************************************/
sahilmgandhi 18:6a4db94011d3 411 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
sahilmgandhi 18:6a4db94011d3 412 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
sahilmgandhi 18:6a4db94011d3 413 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
sahilmgandhi 18:6a4db94011d3 414 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
sahilmgandhi 18:6a4db94011d3 415 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 416 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 417 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 418 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
sahilmgandhi 18:6a4db94011d3 419 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
sahilmgandhi 18:6a4db94011d3 420 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
sahilmgandhi 18:6a4db94011d3 421 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
sahilmgandhi 18:6a4db94011d3 422 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
sahilmgandhi 18:6a4db94011d3 423 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
sahilmgandhi 18:6a4db94011d3 424 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 425 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 426 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 427 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 428
sahilmgandhi 18:6a4db94011d3 429 /**
sahilmgandhi 18:6a4db94011d3 430 * @}
sahilmgandhi 18:6a4db94011d3 431 */
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 434 * @{
sahilmgandhi 18:6a4db94011d3 435 */
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /* Peripheral Control functions *************************************************/
sahilmgandhi 18:6a4db94011d3 438 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
sahilmgandhi 18:6a4db94011d3 439 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
sahilmgandhi 18:6a4db94011d3 440 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
sahilmgandhi 18:6a4db94011d3 441 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 442 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 443 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
sahilmgandhi 18:6a4db94011d3 444
sahilmgandhi 18:6a4db94011d3 445 /**
sahilmgandhi 18:6a4db94011d3 446 * @}
sahilmgandhi 18:6a4db94011d3 447 */
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
sahilmgandhi 18:6a4db94011d3 450 * @{
sahilmgandhi 18:6a4db94011d3 451 */
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 /* Peripheral State functions ***************************************************/
sahilmgandhi 18:6a4db94011d3 454 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 455 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 /**
sahilmgandhi 18:6a4db94011d3 458 * @}
sahilmgandhi 18:6a4db94011d3 459 */
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /**
sahilmgandhi 18:6a4db94011d3 462 * @}
sahilmgandhi 18:6a4db94011d3 463 */
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
sahilmgandhi 18:6a4db94011d3 468 * @{
sahilmgandhi 18:6a4db94011d3 469 */
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
sahilmgandhi 18:6a4db94011d3 472 * @{
sahilmgandhi 18:6a4db94011d3 473 */
sahilmgandhi 18:6a4db94011d3 474 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
sahilmgandhi 18:6a4db94011d3 475 /**
sahilmgandhi 18:6a4db94011d3 476 * @}
sahilmgandhi 18:6a4db94011d3 477 */
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 /** @defgroup DMA2D_Color_Value DMA2D Color Value
sahilmgandhi 18:6a4db94011d3 480 * @{
sahilmgandhi 18:6a4db94011d3 481 */
sahilmgandhi 18:6a4db94011d3 482 #define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */
sahilmgandhi 18:6a4db94011d3 483 /**
sahilmgandhi 18:6a4db94011d3 484 * @}
sahilmgandhi 18:6a4db94011d3 485 */
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
sahilmgandhi 18:6a4db94011d3 488 * @{
sahilmgandhi 18:6a4db94011d3 489 */
sahilmgandhi 18:6a4db94011d3 490 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */
sahilmgandhi 18:6a4db94011d3 491 /**
sahilmgandhi 18:6a4db94011d3 492 * @}
sahilmgandhi 18:6a4db94011d3 493 */
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 /** @defgroup DMA2D_Offset DMA2D Offset
sahilmgandhi 18:6a4db94011d3 496 * @{
sahilmgandhi 18:6a4db94011d3 497 */
sahilmgandhi 18:6a4db94011d3 498 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
sahilmgandhi 18:6a4db94011d3 499 /**
sahilmgandhi 18:6a4db94011d3 500 * @}
sahilmgandhi 18:6a4db94011d3 501 */
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 /** @defgroup DMA2D_Size DMA2D Size
sahilmgandhi 18:6a4db94011d3 504 * @{
sahilmgandhi 18:6a4db94011d3 505 */
sahilmgandhi 18:6a4db94011d3 506 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */
sahilmgandhi 18:6a4db94011d3 507 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */
sahilmgandhi 18:6a4db94011d3 508 /**
sahilmgandhi 18:6a4db94011d3 509 * @}
sahilmgandhi 18:6a4db94011d3 510 */
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
sahilmgandhi 18:6a4db94011d3 513 * @{
sahilmgandhi 18:6a4db94011d3 514 */
sahilmgandhi 18:6a4db94011d3 515 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D CLUT size */
sahilmgandhi 18:6a4db94011d3 516 /**
sahilmgandhi 18:6a4db94011d3 517 * @}
sahilmgandhi 18:6a4db94011d3 518 */
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 /**
sahilmgandhi 18:6a4db94011d3 521 * @}
sahilmgandhi 18:6a4db94011d3 522 */
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 525 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
sahilmgandhi 18:6a4db94011d3 526 * @{
sahilmgandhi 18:6a4db94011d3 527 */
sahilmgandhi 18:6a4db94011d3 528 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER)
sahilmgandhi 18:6a4db94011d3 529 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
sahilmgandhi 18:6a4db94011d3 530 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
sahilmgandhi 18:6a4db94011d3 531 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
sahilmgandhi 18:6a4db94011d3 532 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
sahilmgandhi 18:6a4db94011d3 533 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
sahilmgandhi 18:6a4db94011d3 534 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
sahilmgandhi 18:6a4db94011d3 535 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
sahilmgandhi 18:6a4db94011d3 536 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
sahilmgandhi 18:6a4db94011d3 537 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
sahilmgandhi 18:6a4db94011d3 538 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
sahilmgandhi 18:6a4db94011d3 539 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
sahilmgandhi 18:6a4db94011d3 540 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
sahilmgandhi 18:6a4db94011d3 541 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
sahilmgandhi 18:6a4db94011d3 542 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
sahilmgandhi 18:6a4db94011d3 543 ((INPUT_CM) == DMA2D_INPUT_A4))
sahilmgandhi 18:6a4db94011d3 544 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
sahilmgandhi 18:6a4db94011d3 545 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
sahilmgandhi 18:6a4db94011d3 546 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
sahilmgandhi 18:6a4db94011d3 547
sahilmgandhi 18:6a4db94011d3 548 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
sahilmgandhi 18:6a4db94011d3 549 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
sahilmgandhi 18:6a4db94011d3 550 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
sahilmgandhi 18:6a4db94011d3 551 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
sahilmgandhi 18:6a4db94011d3 552 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
sahilmgandhi 18:6a4db94011d3 553 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
sahilmgandhi 18:6a4db94011d3 554 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
sahilmgandhi 18:6a4db94011d3 555 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
sahilmgandhi 18:6a4db94011d3 556 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
sahilmgandhi 18:6a4db94011d3 557 /**
sahilmgandhi 18:6a4db94011d3 558 * @}
sahilmgandhi 18:6a4db94011d3 559 */
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 /**
sahilmgandhi 18:6a4db94011d3 562 * @}
sahilmgandhi 18:6a4db94011d3 563 */
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 /**
sahilmgandhi 18:6a4db94011d3 566 * @}
sahilmgandhi 18:6a4db94011d3 567 */
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 570
sahilmgandhi 18:6a4db94011d3 571 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 572 }
sahilmgandhi 18:6a4db94011d3 573 #endif
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 #endif /* __STM32F4xx_HAL_DMA2D_H */
sahilmgandhi 18:6a4db94011d3 576
sahilmgandhi 18:6a4db94011d3 577 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/