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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f4xx_hal_dma2d.c
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.5.0
sahilmgandhi	18:6a4db94011d3	6	* @date 06-May-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief DMA2D HAL module driver.
sahilmgandhi	18:6a4db94011d3	8	* This file provides firmware functions to manage the following
sahilmgandhi	18:6a4db94011d3	9	* functionalities of the DMA2D peripheral:
sahilmgandhi	18:6a4db94011d3	10	* + Initialization and de-initialization functions
sahilmgandhi	18:6a4db94011d3	11	* + IO operation functions
sahilmgandhi	18:6a4db94011d3	12	* + Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	13	* + Peripheral State and Errors functions
sahilmgandhi	18:6a4db94011d3	14	*
sahilmgandhi	18:6a4db94011d3	15	@verbatim
sahilmgandhi	18:6a4db94011d3	16	==============================================================================
sahilmgandhi	18:6a4db94011d3	17	##### How to use this driver #####
sahilmgandhi	18:6a4db94011d3	18	==============================================================================
sahilmgandhi	18:6a4db94011d3	19	[..]
sahilmgandhi	18:6a4db94011d3	20	(#) Program the required configuration through the following parameters:
sahilmgandhi	18:6a4db94011d3	21	the transfer mode, the output color mode and the output offset using
sahilmgandhi	18:6a4db94011d3	22	HAL_DMA2D_Init() function.
sahilmgandhi	18:6a4db94011d3	23
sahilmgandhi	18:6a4db94011d3	24	(#) Program the required configuration through the following parameters:
sahilmgandhi	18:6a4db94011d3	25	the input color mode, the input color, the input alpha value, the alpha mode,
sahilmgandhi	18:6a4db94011d3	26	and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
sahilmgandhi	18:6a4db94011d3	27	or/and background layer.
sahilmgandhi	18:6a4db94011d3	28
sahilmgandhi	18:6a4db94011d3	29	* Polling mode IO operation *
sahilmgandhi	18:6a4db94011d3	30	=================================
sahilmgandhi	18:6a4db94011d3	31	[..]
sahilmgandhi	18:6a4db94011d3	32	(#) Configure pdata parameter (explained hereafter), destination and data length
sahilmgandhi	18:6a4db94011d3	33	and enable the transfer using HAL_DMA2D_Start().
sahilmgandhi	18:6a4db94011d3	34	(#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
sahilmgandhi	18:6a4db94011d3	35	user can specify the value of timeout according to his end application.
sahilmgandhi	18:6a4db94011d3	36
sahilmgandhi	18:6a4db94011d3	37	* Interrupt mode IO operation *
sahilmgandhi	18:6a4db94011d3	38	===================================
sahilmgandhi	18:6a4db94011d3	39	[..]
sahilmgandhi	18:6a4db94011d3	40	(#) Configure pdata parameter, destination and data length and enable
sahilmgandhi	18:6a4db94011d3	41	the transfer using HAL_DMA2D_Start_IT().
sahilmgandhi	18:6a4db94011d3	42	(#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
sahilmgandhi	18:6a4db94011d3	43	(#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
sahilmgandhi	18:6a4db94011d3	44	add his own function by customization of function pointer XferCpltCallback (member
sahilmgandhi	18:6a4db94011d3	45	of DMA2D handle structure).
sahilmgandhi	18:6a4db94011d3	46	(#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
sahilmgandhi	18:6a4db94011d3	47	XferErrorCallback.
sahilmgandhi	18:6a4db94011d3	48
sahilmgandhi	18:6a4db94011d3	49	-@- In Register-to-Memory transfer mode, pdata parameter is the register
sahilmgandhi	18:6a4db94011d3	50	color, in Memory-to-memory or Memory-to-Memory with pixel format
sahilmgandhi	18:6a4db94011d3	51	conversion pdata is the source address.
sahilmgandhi	18:6a4db94011d3	52
sahilmgandhi	18:6a4db94011d3	53	-@- Configure the foreground source address, the background source address,
sahilmgandhi	18:6a4db94011d3	54	the destination and data length then Enable the transfer using
sahilmgandhi	18:6a4db94011d3	55	HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
sahilmgandhi	18:6a4db94011d3	56	in interrupt mode
sahilmgandhi	18:6a4db94011d3	57
sahilmgandhi	18:6a4db94011d3	58	-@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
sahilmgandhi	18:6a4db94011d3	59	are used if the memory to memory with blending transfer mode is selected.
sahilmgandhi	18:6a4db94011d3	60
sahilmgandhi	18:6a4db94011d3	61	(#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
sahilmgandhi	18:6a4db94011d3	62	mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
sahilmgandhi	18:6a4db94011d3	63
sahilmgandhi	18:6a4db94011d3	64	(#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
sahilmgandhi	18:6a4db94011d3	65
sahilmgandhi	18:6a4db94011d3	66	(#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
sahilmgandhi	18:6a4db94011d3	67	consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
sahilmgandhi	18:6a4db94011d3	68	and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
sahilmgandhi	18:6a4db94011d3	69	HAL_DMA2D_DisableDeadTime().
sahilmgandhi	18:6a4db94011d3	70
sahilmgandhi	18:6a4db94011d3	71	(#) The transfer can be suspended, resumed and aborted using the following
sahilmgandhi	18:6a4db94011d3	72	functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
sahilmgandhi	18:6a4db94011d3	73
sahilmgandhi	18:6a4db94011d3	74	(#) The CLUT loading can be suspended, resumed and aborted using the following
sahilmgandhi	18:6a4db94011d3	75	functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
sahilmgandhi	18:6a4db94011d3	76	HAL_DMA2D_CLUTLoading_Abort().
sahilmgandhi	18:6a4db94011d3	77
sahilmgandhi	18:6a4db94011d3	78	(#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
sahilmgandhi	18:6a4db94011d3	79
sahilmgandhi	18:6a4db94011d3	80	(#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
sahilmgandhi	18:6a4db94011d3	81
sahilmgandhi	18:6a4db94011d3	82	* DMA2D HAL driver macros list *
sahilmgandhi	18:6a4db94011d3	83	=============================================
sahilmgandhi	18:6a4db94011d3	84	[..]
sahilmgandhi	18:6a4db94011d3	85	Below the list of most used macros in DMA2D HAL driver :
sahilmgandhi	18:6a4db94011d3	86
sahilmgandhi	18:6a4db94011d3	87	(+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
sahilmgandhi	18:6a4db94011d3	88	(+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
sahilmgandhi	18:6a4db94011d3	89	(+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
sahilmgandhi	18:6a4db94011d3	90	(+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
sahilmgandhi	18:6a4db94011d3	91	(+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
sahilmgandhi	18:6a4db94011d3	92	(+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
sahilmgandhi	18:6a4db94011d3	93
sahilmgandhi	18:6a4db94011d3	94	[..]
sahilmgandhi	18:6a4db94011d3	95	(@) You can refer to the DMA2D HAL driver header file for more useful macros
sahilmgandhi	18:6a4db94011d3	96
sahilmgandhi	18:6a4db94011d3	97	@endverbatim
sahilmgandhi	18:6a4db94011d3	98	******************************************************************************
sahilmgandhi	18:6a4db94011d3	99	* @attention
sahilmgandhi	18:6a4db94011d3	100	*
sahilmgandhi	18:6a4db94011d3	101	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	102	*
sahilmgandhi	18:6a4db94011d3	103	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	104	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	105	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	106	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	108	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	109	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	111	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	112	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	113	*
sahilmgandhi	18:6a4db94011d3	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	124	*
sahilmgandhi	18:6a4db94011d3	125	******************************************************************************
sahilmgandhi	18:6a4db94011d3	126	*/
sahilmgandhi	18:6a4db94011d3	127
sahilmgandhi	18:6a4db94011d3	128	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	129	#include "stm32f4xx_hal.h"
sahilmgandhi	18:6a4db94011d3	130
sahilmgandhi	18:6a4db94011d3	131	/** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi	18:6a4db94011d3	132	* @{
sahilmgandhi	18:6a4db94011d3	133	*/
sahilmgandhi	18:6a4db94011d3	134
sahilmgandhi	18:6a4db94011d3	135	/** @defgroup DMA2D DMA2D
sahilmgandhi	18:6a4db94011d3	136	* @brief DMA2D HAL module driver
sahilmgandhi	18:6a4db94011d3	137	* @{
sahilmgandhi	18:6a4db94011d3	138	*/
sahilmgandhi	18:6a4db94011d3	139
sahilmgandhi	18:6a4db94011d3	140	#ifdef HAL_DMA2D_MODULE_ENABLED
sahilmgandhi	18:6a4db94011d3	141
sahilmgandhi	18:6a4db94011d3	142	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	143
sahilmgandhi	18:6a4db94011d3	144	/* Private types -------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	145	/* Private define ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	146	/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
sahilmgandhi	18:6a4db94011d3	147	* @{
sahilmgandhi	18:6a4db94011d3	148	*/
sahilmgandhi	18:6a4db94011d3	149
sahilmgandhi	18:6a4db94011d3	150	/** @defgroup DMA2D_TimeOut DMA2D Time Out
sahilmgandhi	18:6a4db94011d3	151	* @{
sahilmgandhi	18:6a4db94011d3	152	*/
sahilmgandhi	18:6a4db94011d3	153	#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000U) /!< 1s /
sahilmgandhi	18:6a4db94011d3	154	#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000U) /!< 1s /
sahilmgandhi	18:6a4db94011d3	155	/**
sahilmgandhi	18:6a4db94011d3	156	* @}
sahilmgandhi	18:6a4db94011d3	157	*/
sahilmgandhi	18:6a4db94011d3	158
sahilmgandhi	18:6a4db94011d3	159	/** @defgroup DMA2D_Shifts DMA2D Shifts
sahilmgandhi	18:6a4db94011d3	160	* @{
sahilmgandhi	18:6a4db94011d3	161	*/
sahilmgandhi	18:6a4db94011d3	162	#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /!< Required left shift to set foreground CLUT size /
sahilmgandhi	18:6a4db94011d3	163	#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /!< Required left shift to set background CLUT size /
sahilmgandhi	18:6a4db94011d3	164
sahilmgandhi	18:6a4db94011d3	165	#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /!< Required left shift to set foreground CLUT color mode /
sahilmgandhi	18:6a4db94011d3	166	#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /!< Required left shift to set background CLUT color mode /
sahilmgandhi	18:6a4db94011d3	167
sahilmgandhi	18:6a4db94011d3	168	#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /!< Required left shift to set deadtime value /
sahilmgandhi	18:6a4db94011d3	169
sahilmgandhi	18:6a4db94011d3	170	#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /!< Required left shift to set foreground alpha mode /
sahilmgandhi	18:6a4db94011d3	171	#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /!< Required left shift to set background alpha mode /
sahilmgandhi	18:6a4db94011d3	172
sahilmgandhi	18:6a4db94011d3	173	#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /!< Required left shift to set foreground alpha value /
sahilmgandhi	18:6a4db94011d3	174	#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /!< Required left shift to set background alpha value /
sahilmgandhi	18:6a4db94011d3	175
sahilmgandhi	18:6a4db94011d3	176	#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /!< Required left shift to set pixels per lines value /
sahilmgandhi	18:6a4db94011d3	177	/**
sahilmgandhi	18:6a4db94011d3	178	* @}
sahilmgandhi	18:6a4db94011d3	179	*/
sahilmgandhi	18:6a4db94011d3	180
sahilmgandhi	18:6a4db94011d3	181	/**
sahilmgandhi	18:6a4db94011d3	182	* @}
sahilmgandhi	18:6a4db94011d3	183	*/
sahilmgandhi	18:6a4db94011d3	184
sahilmgandhi	18:6a4db94011d3	185	/* Private variables ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	186	/* Private constants ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	187	/* Private macro -------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	188	/* Private function prototypes -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	189	/** @addtogroup DMA2D_Private_Functions_Prototypes
sahilmgandhi	18:6a4db94011d3	190	* @{
sahilmgandhi	18:6a4db94011d3	191	*/
sahilmgandhi	18:6a4db94011d3	192	static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
sahilmgandhi	18:6a4db94011d3	193	/**
sahilmgandhi	18:6a4db94011d3	194	* @}
sahilmgandhi	18:6a4db94011d3	195	*/
sahilmgandhi	18:6a4db94011d3	196
sahilmgandhi	18:6a4db94011d3	197	/* Private functions ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	198	/* Exported functions --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	199	/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
sahilmgandhi	18:6a4db94011d3	200	* @{
sahilmgandhi	18:6a4db94011d3	201	*/
sahilmgandhi	18:6a4db94011d3	202
sahilmgandhi	18:6a4db94011d3	203	/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi	18:6a4db94011d3	204	* @brief Initialization and Configuration functions
sahilmgandhi	18:6a4db94011d3	205	*
sahilmgandhi	18:6a4db94011d3	206	@verbatim
sahilmgandhi	18:6a4db94011d3	207	===============================================================================
sahilmgandhi	18:6a4db94011d3	208	##### Initialization and Configuration functions #####
sahilmgandhi	18:6a4db94011d3	209	===============================================================================
sahilmgandhi	18:6a4db94011d3	210	[..] This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	211	(+) Initialize and configure the DMA2D
sahilmgandhi	18:6a4db94011d3	212	(+) De-initialize the DMA2D
sahilmgandhi	18:6a4db94011d3	213
sahilmgandhi	18:6a4db94011d3	214	@endverbatim
sahilmgandhi	18:6a4db94011d3	215	* @{
sahilmgandhi	18:6a4db94011d3	216	*/
sahilmgandhi	18:6a4db94011d3	217
sahilmgandhi	18:6a4db94011d3	218	/**
sahilmgandhi	18:6a4db94011d3	219	* @brief Initialize the DMA2D according to the specified
sahilmgandhi	18:6a4db94011d3	220	* parameters in the DMA2D_InitTypeDef and create the associated handle.
sahilmgandhi	18:6a4db94011d3	221	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	222	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	223	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	224	*/
sahilmgandhi	18:6a4db94011d3	225	HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	226	{
sahilmgandhi	18:6a4db94011d3	227	/* Check the DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	228	if(hdma2d == NULL)
sahilmgandhi	18:6a4db94011d3	229	{
sahilmgandhi	18:6a4db94011d3	230	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	231	}
sahilmgandhi	18:6a4db94011d3	232
sahilmgandhi	18:6a4db94011d3	233	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	234	assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
sahilmgandhi	18:6a4db94011d3	235	assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
sahilmgandhi	18:6a4db94011d3	236	assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
sahilmgandhi	18:6a4db94011d3	237	assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
sahilmgandhi	18:6a4db94011d3	238
sahilmgandhi	18:6a4db94011d3	239	if(hdma2d->State == HAL_DMA2D_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	240	{
sahilmgandhi	18:6a4db94011d3	241	/* Allocate lock resource and initialize it */
sahilmgandhi	18:6a4db94011d3	242	hdma2d->Lock = HAL_UNLOCKED;
sahilmgandhi	18:6a4db94011d3	243	/* Init the low level hardware */
sahilmgandhi	18:6a4db94011d3	244	HAL_DMA2D_MspInit(hdma2d);
sahilmgandhi	18:6a4db94011d3	245	}
sahilmgandhi	18:6a4db94011d3	246
sahilmgandhi	18:6a4db94011d3	247	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	248	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	249
sahilmgandhi	18:6a4db94011d3	250	/* DMA2D CR register configuration -------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	251	MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
sahilmgandhi	18:6a4db94011d3	252
sahilmgandhi	18:6a4db94011d3	253	/* DMA2D OPFCCR register configuration ---------------------------------------*/
sahilmgandhi	18:6a4db94011d3	254	MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
sahilmgandhi	18:6a4db94011d3	255
sahilmgandhi	18:6a4db94011d3	256	/* DMA2D OOR register configuration ------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	257	MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
sahilmgandhi	18:6a4db94011d3	258
sahilmgandhi	18:6a4db94011d3	259	/* Update error code */
sahilmgandhi	18:6a4db94011d3	260	hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	261
sahilmgandhi	18:6a4db94011d3	262	/* Initialize the DMA2D state*/
sahilmgandhi	18:6a4db94011d3	263	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	264
sahilmgandhi	18:6a4db94011d3	265	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	266	}
sahilmgandhi	18:6a4db94011d3	267
sahilmgandhi	18:6a4db94011d3	268	/**
sahilmgandhi	18:6a4db94011d3	269	* @brief Deinitializes the DMA2D peripheral registers to their default reset
sahilmgandhi	18:6a4db94011d3	270	* values.
sahilmgandhi	18:6a4db94011d3	271	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	272	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	273	* @retval None
sahilmgandhi	18:6a4db94011d3	274	*/
sahilmgandhi	18:6a4db94011d3	275
sahilmgandhi	18:6a4db94011d3	276	HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	277	{
sahilmgandhi	18:6a4db94011d3	278	/* Check the DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	279	if(hdma2d == NULL)
sahilmgandhi	18:6a4db94011d3	280	{
sahilmgandhi	18:6a4db94011d3	281	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	282	}
sahilmgandhi	18:6a4db94011d3	283
sahilmgandhi	18:6a4db94011d3	284	/* Before aborting any DMA2D transfer or CLUT loading, check
sahilmgandhi	18:6a4db94011d3	285	first whether or not DMA2D clock is enabled */
sahilmgandhi	18:6a4db94011d3	286	if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
sahilmgandhi	18:6a4db94011d3	287	{
sahilmgandhi	18:6a4db94011d3	288	/* Abort DMA2D transfer if any */
sahilmgandhi	18:6a4db94011d3	289	if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
sahilmgandhi	18:6a4db94011d3	290	{
sahilmgandhi	18:6a4db94011d3	291	if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	292	{
sahilmgandhi	18:6a4db94011d3	293	/* Issue when aborting DMA2D transfer */
sahilmgandhi	18:6a4db94011d3	294	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	295	}
sahilmgandhi	18:6a4db94011d3	296	}
sahilmgandhi	18:6a4db94011d3	297	else
sahilmgandhi	18:6a4db94011d3	298	{
sahilmgandhi	18:6a4db94011d3	299	/* Abort background CLUT loading if any */
sahilmgandhi	18:6a4db94011d3	300	if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
sahilmgandhi	18:6a4db94011d3	301	{
sahilmgandhi	18:6a4db94011d3	302	if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	303	{
sahilmgandhi	18:6a4db94011d3	304	/* Issue when aborting background CLUT loading */
sahilmgandhi	18:6a4db94011d3	305	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	306	}
sahilmgandhi	18:6a4db94011d3	307	}
sahilmgandhi	18:6a4db94011d3	308	else
sahilmgandhi	18:6a4db94011d3	309	{
sahilmgandhi	18:6a4db94011d3	310	/* Abort foreground CLUT loading if any */
sahilmgandhi	18:6a4db94011d3	311	if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
sahilmgandhi	18:6a4db94011d3	312	{
sahilmgandhi	18:6a4db94011d3	313	if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	314	{
sahilmgandhi	18:6a4db94011d3	315	/* Issue when aborting foreground CLUT loading */
sahilmgandhi	18:6a4db94011d3	316	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	317	}
sahilmgandhi	18:6a4db94011d3	318	}
sahilmgandhi	18:6a4db94011d3	319	}
sahilmgandhi	18:6a4db94011d3	320	}
sahilmgandhi	18:6a4db94011d3	321	}
sahilmgandhi	18:6a4db94011d3	322
sahilmgandhi	18:6a4db94011d3	323	/* Carry on with de-initialization of low level hardware */
sahilmgandhi	18:6a4db94011d3	324	HAL_DMA2D_MspDeInit(hdma2d);
sahilmgandhi	18:6a4db94011d3	325
sahilmgandhi	18:6a4db94011d3	326	/* Reset DMA2D control registers*/
sahilmgandhi	18:6a4db94011d3	327	hdma2d->Instance->CR = 0U;
sahilmgandhi	18:6a4db94011d3	328	hdma2d->Instance->FGOR = 0U;
sahilmgandhi	18:6a4db94011d3	329	hdma2d->Instance->BGOR = 0U;
sahilmgandhi	18:6a4db94011d3	330	hdma2d->Instance->FGPFCCR = 0U;
sahilmgandhi	18:6a4db94011d3	331	hdma2d->Instance->BGPFCCR = 0U;
sahilmgandhi	18:6a4db94011d3	332	hdma2d->Instance->OPFCCR = 0U;
sahilmgandhi	18:6a4db94011d3	333
sahilmgandhi	18:6a4db94011d3	334	/* Update error code */
sahilmgandhi	18:6a4db94011d3	335	hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	336
sahilmgandhi	18:6a4db94011d3	337	/* Initialize the DMA2D state*/
sahilmgandhi	18:6a4db94011d3	338	hdma2d->State = HAL_DMA2D_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	339
sahilmgandhi	18:6a4db94011d3	340	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	341	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	342
sahilmgandhi	18:6a4db94011d3	343	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	344	}
sahilmgandhi	18:6a4db94011d3	345
sahilmgandhi	18:6a4db94011d3	346	/**
sahilmgandhi	18:6a4db94011d3	347	* @brief Initializes the DMA2D MSP.
sahilmgandhi	18:6a4db94011d3	348	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	349	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	350	* @retval None
sahilmgandhi	18:6a4db94011d3	351	*/
sahilmgandhi	18:6a4db94011d3	352	__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
sahilmgandhi	18:6a4db94011d3	353	{
sahilmgandhi	18:6a4db94011d3	354	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	355	UNUSED(hdma2d);
sahilmgandhi	18:6a4db94011d3	356
sahilmgandhi	18:6a4db94011d3	357	/* NOTE : This function should not be modified; when the callback is needed,
sahilmgandhi	18:6a4db94011d3	358	the HAL_DMA2D_MspInit can be implemented in the user file.
sahilmgandhi	18:6a4db94011d3	359	*/
sahilmgandhi	18:6a4db94011d3	360	}
sahilmgandhi	18:6a4db94011d3	361
sahilmgandhi	18:6a4db94011d3	362	/**
sahilmgandhi	18:6a4db94011d3	363	* @brief DeInitializes the DMA2D MSP.
sahilmgandhi	18:6a4db94011d3	364	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	365	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	366	* @retval None
sahilmgandhi	18:6a4db94011d3	367	*/
sahilmgandhi	18:6a4db94011d3	368	__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
sahilmgandhi	18:6a4db94011d3	369	{
sahilmgandhi	18:6a4db94011d3	370	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	371	UNUSED(hdma2d);
sahilmgandhi	18:6a4db94011d3	372
sahilmgandhi	18:6a4db94011d3	373	/* NOTE : This function should not be modified; when the callback is needed,
sahilmgandhi	18:6a4db94011d3	374	the HAL_DMA2D_MspDeInit can be implemented in the user file.
sahilmgandhi	18:6a4db94011d3	375	*/
sahilmgandhi	18:6a4db94011d3	376	}
sahilmgandhi	18:6a4db94011d3	377
sahilmgandhi	18:6a4db94011d3	378	/**
sahilmgandhi	18:6a4db94011d3	379	* @}
sahilmgandhi	18:6a4db94011d3	380	*/
sahilmgandhi	18:6a4db94011d3	381
sahilmgandhi	18:6a4db94011d3	382	/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
sahilmgandhi	18:6a4db94011d3	383	* @brief IO operation functions
sahilmgandhi	18:6a4db94011d3	384	*
sahilmgandhi	18:6a4db94011d3	385	@verbatim
sahilmgandhi	18:6a4db94011d3	386	===============================================================================
sahilmgandhi	18:6a4db94011d3	387	##### IO operation functions #####
sahilmgandhi	18:6a4db94011d3	388	===============================================================================
sahilmgandhi	18:6a4db94011d3	389	[..] This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	390	(+) Configure the pdata, destination address and data size then
sahilmgandhi	18:6a4db94011d3	391	start the DMA2D transfer.
sahilmgandhi	18:6a4db94011d3	392	(+) Configure the source for foreground and background, destination address
sahilmgandhi	18:6a4db94011d3	393	and data size then start a MultiBuffer DMA2D transfer.
sahilmgandhi	18:6a4db94011d3	394	(+) Configure the pdata, destination address and data size then
sahilmgandhi	18:6a4db94011d3	395	start the DMA2D transfer with interrupt.
sahilmgandhi	18:6a4db94011d3	396	(+) Configure the source for foreground and background, destination address
sahilmgandhi	18:6a4db94011d3	397	and data size then start a MultiBuffer DMA2D transfer with interrupt.
sahilmgandhi	18:6a4db94011d3	398	(+) Abort DMA2D transfer.
sahilmgandhi	18:6a4db94011d3	399	(+) Suspend DMA2D transfer.
sahilmgandhi	18:6a4db94011d3	400	(+) Resume DMA2D transfer.
sahilmgandhi	18:6a4db94011d3	401	(+) Enable CLUT transfer.
sahilmgandhi	18:6a4db94011d3	402	(+) Configure CLUT loading then start transfer in polling mode.
sahilmgandhi	18:6a4db94011d3	403	(+) Configure CLUT loading then start transfer in interrupt mode.
sahilmgandhi	18:6a4db94011d3	404	(+) Abort DMA2D CLUT loading.
sahilmgandhi	18:6a4db94011d3	405	(+) Suspend DMA2D CLUT loading.
sahilmgandhi	18:6a4db94011d3	406	(+) Resume DMA2D CLUT loading.
sahilmgandhi	18:6a4db94011d3	407	(+) Poll for transfer complete.
sahilmgandhi	18:6a4db94011d3	408	(+) handle DMA2D interrupt request.
sahilmgandhi	18:6a4db94011d3	409	(+) Transfer watermark callback.
sahilmgandhi	18:6a4db94011d3	410	(+) CLUT Transfer Complete callback.
sahilmgandhi	18:6a4db94011d3	411
sahilmgandhi	18:6a4db94011d3	412	@endverbatim
sahilmgandhi	18:6a4db94011d3	413	* @{
sahilmgandhi	18:6a4db94011d3	414	*/
sahilmgandhi	18:6a4db94011d3	415
sahilmgandhi	18:6a4db94011d3	416	/**
sahilmgandhi	18:6a4db94011d3	417	* @brief Start the DMA2D Transfer.
sahilmgandhi	18:6a4db94011d3	418	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	419	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	420	* @param pdata: Configure the source memory Buffer address if
sahilmgandhi	18:6a4db94011d3	421	* Memory-to-Memory or Memory-to-Memory with pixel format
sahilmgandhi	18:6a4db94011d3	422	* conversion mode is selected, or configure
sahilmgandhi	18:6a4db94011d3	423	* the color value if Register-to-Memory mode is selected.
sahilmgandhi	18:6a4db94011d3	424	* @param DstAddress: The destination memory Buffer address.
sahilmgandhi	18:6a4db94011d3	425	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
sahilmgandhi	18:6a4db94011d3	426	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
sahilmgandhi	18:6a4db94011d3	427	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	428	*/
sahilmgandhi	18:6a4db94011d3	429	HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
sahilmgandhi	18:6a4db94011d3	430	{
sahilmgandhi	18:6a4db94011d3	431	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	432	assert_param(IS_DMA2D_LINE(Height));
sahilmgandhi	18:6a4db94011d3	433	assert_param(IS_DMA2D_PIXEL(Width));
sahilmgandhi	18:6a4db94011d3	434
sahilmgandhi	18:6a4db94011d3	435	/* Process locked */
sahilmgandhi	18:6a4db94011d3	436	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	437
sahilmgandhi	18:6a4db94011d3	438	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	439	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	440
sahilmgandhi	18:6a4db94011d3	441	/* Configure the source, destination address and the data size */
sahilmgandhi	18:6a4db94011d3	442	DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
sahilmgandhi	18:6a4db94011d3	443
sahilmgandhi	18:6a4db94011d3	444	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	445	__HAL_DMA2D_ENABLE(hdma2d);
sahilmgandhi	18:6a4db94011d3	446
sahilmgandhi	18:6a4db94011d3	447	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	448	}
sahilmgandhi	18:6a4db94011d3	449
sahilmgandhi	18:6a4db94011d3	450	/**
sahilmgandhi	18:6a4db94011d3	451	* @brief Start the DMA2D Transfer with interrupt enabled.
sahilmgandhi	18:6a4db94011d3	452	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	453	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	454	* @param pdata: Configure the source memory Buffer address if
sahilmgandhi	18:6a4db94011d3	455	* the Memory-to-Memory or Memory-to-Memory with pixel format
sahilmgandhi	18:6a4db94011d3	456	* conversion mode is selected, or configure
sahilmgandhi	18:6a4db94011d3	457	* the color value if Register-to-Memory mode is selected.
sahilmgandhi	18:6a4db94011d3	458	* @param DstAddress: The destination memory Buffer address.
sahilmgandhi	18:6a4db94011d3	459	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
sahilmgandhi	18:6a4db94011d3	460	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
sahilmgandhi	18:6a4db94011d3	461	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	462	*/
sahilmgandhi	18:6a4db94011d3	463	HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
sahilmgandhi	18:6a4db94011d3	464	{
sahilmgandhi	18:6a4db94011d3	465	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	466	assert_param(IS_DMA2D_LINE(Height));
sahilmgandhi	18:6a4db94011d3	467	assert_param(IS_DMA2D_PIXEL(Width));
sahilmgandhi	18:6a4db94011d3	468
sahilmgandhi	18:6a4db94011d3	469	/* Process locked */
sahilmgandhi	18:6a4db94011d3	470	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	471
sahilmgandhi	18:6a4db94011d3	472	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	473	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	474
sahilmgandhi	18:6a4db94011d3	475	/* Configure the source, destination address and the data size */
sahilmgandhi	18:6a4db94011d3	476	DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
sahilmgandhi	18:6a4db94011d3	477
sahilmgandhi	18:6a4db94011d3	478	/* Enable the transfer complete, transfer error and configuration error interrupts */
sahilmgandhi	18:6a4db94011d3	479	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC\|DMA2D_IT_TE\|DMA2D_IT_CE);
sahilmgandhi	18:6a4db94011d3	480
sahilmgandhi	18:6a4db94011d3	481	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	482	__HAL_DMA2D_ENABLE(hdma2d);
sahilmgandhi	18:6a4db94011d3	483
sahilmgandhi	18:6a4db94011d3	484	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	485	}
sahilmgandhi	18:6a4db94011d3	486
sahilmgandhi	18:6a4db94011d3	487	/**
sahilmgandhi	18:6a4db94011d3	488	* @brief Start the multi-source DMA2D Transfer.
sahilmgandhi	18:6a4db94011d3	489	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	490	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	491	* @param SrcAddress1: The source memory Buffer address for the foreground layer.
sahilmgandhi	18:6a4db94011d3	492	* @param SrcAddress2: The source memory Buffer address for the background layer.
sahilmgandhi	18:6a4db94011d3	493	* @param DstAddress: The destination memory Buffer address.
sahilmgandhi	18:6a4db94011d3	494	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
sahilmgandhi	18:6a4db94011d3	495	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
sahilmgandhi	18:6a4db94011d3	496	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	497	*/
sahilmgandhi	18:6a4db94011d3	498	HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
sahilmgandhi	18:6a4db94011d3	499	{
sahilmgandhi	18:6a4db94011d3	500	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	501	assert_param(IS_DMA2D_LINE(Height));
sahilmgandhi	18:6a4db94011d3	502	assert_param(IS_DMA2D_PIXEL(Width));
sahilmgandhi	18:6a4db94011d3	503
sahilmgandhi	18:6a4db94011d3	504	/* Process locked */
sahilmgandhi	18:6a4db94011d3	505	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	506
sahilmgandhi	18:6a4db94011d3	507	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	508	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	509
sahilmgandhi	18:6a4db94011d3	510	/* Configure DMA2D Stream source2 address */
sahilmgandhi	18:6a4db94011d3	511	WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
sahilmgandhi	18:6a4db94011d3	512
sahilmgandhi	18:6a4db94011d3	513	/* Configure the source, destination address and the data size */
sahilmgandhi	18:6a4db94011d3	514	DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
sahilmgandhi	18:6a4db94011d3	515
sahilmgandhi	18:6a4db94011d3	516	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	517	__HAL_DMA2D_ENABLE(hdma2d);
sahilmgandhi	18:6a4db94011d3	518
sahilmgandhi	18:6a4db94011d3	519	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	520	}
sahilmgandhi	18:6a4db94011d3	521
sahilmgandhi	18:6a4db94011d3	522	/**
sahilmgandhi	18:6a4db94011d3	523	* @brief Start the multi-source DMA2D Transfer with interrupt enabled.
sahilmgandhi	18:6a4db94011d3	524	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	525	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	526	* @param SrcAddress1: The source memory Buffer address for the foreground layer.
sahilmgandhi	18:6a4db94011d3	527	* @param SrcAddress2: The source memory Buffer address for the background layer.
sahilmgandhi	18:6a4db94011d3	528	* @param DstAddress: The destination memory Buffer address.
sahilmgandhi	18:6a4db94011d3	529	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
sahilmgandhi	18:6a4db94011d3	530	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
sahilmgandhi	18:6a4db94011d3	531	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	532	*/
sahilmgandhi	18:6a4db94011d3	533	HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
sahilmgandhi	18:6a4db94011d3	534	{
sahilmgandhi	18:6a4db94011d3	535	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	536	assert_param(IS_DMA2D_LINE(Height));
sahilmgandhi	18:6a4db94011d3	537	assert_param(IS_DMA2D_PIXEL(Width));
sahilmgandhi	18:6a4db94011d3	538
sahilmgandhi	18:6a4db94011d3	539	/* Process locked */
sahilmgandhi	18:6a4db94011d3	540	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	541
sahilmgandhi	18:6a4db94011d3	542	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	543	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	544
sahilmgandhi	18:6a4db94011d3	545	/* Configure DMA2D Stream source2 address */
sahilmgandhi	18:6a4db94011d3	546	WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
sahilmgandhi	18:6a4db94011d3	547
sahilmgandhi	18:6a4db94011d3	548	/* Configure the source, destination address and the data size */
sahilmgandhi	18:6a4db94011d3	549	DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
sahilmgandhi	18:6a4db94011d3	550
sahilmgandhi	18:6a4db94011d3	551	/* Enable the transfer complete, transfer error and configuration error interrupts */
sahilmgandhi	18:6a4db94011d3	552	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC\|DMA2D_IT_TE\|DMA2D_IT_CE);
sahilmgandhi	18:6a4db94011d3	553
sahilmgandhi	18:6a4db94011d3	554	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	555	__HAL_DMA2D_ENABLE(hdma2d);
sahilmgandhi	18:6a4db94011d3	556
sahilmgandhi	18:6a4db94011d3	557	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	558	}
sahilmgandhi	18:6a4db94011d3	559
sahilmgandhi	18:6a4db94011d3	560	/**
sahilmgandhi	18:6a4db94011d3	561	* @brief Abort the DMA2D Transfer.
sahilmgandhi	18:6a4db94011d3	562	* @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	563	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	564	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	565	*/
sahilmgandhi	18:6a4db94011d3	566	HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	567	{
sahilmgandhi	18:6a4db94011d3	568	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	569
sahilmgandhi	18:6a4db94011d3	570	/* Abort the DMA2D transfer */
sahilmgandhi	18:6a4db94011d3	571	/* START bit is reset to make sure not to set it again, in the event the HW clears it
sahilmgandhi	18:6a4db94011d3	572	between the register read and the register write by the CPU (writing 0 has no
sahilmgandhi	18:6a4db94011d3	573	effect on START bitvalue). */
sahilmgandhi	18:6a4db94011d3	574	MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT\|DMA2D_CR_START, DMA2D_CR_ABORT);
sahilmgandhi	18:6a4db94011d3	575
sahilmgandhi	18:6a4db94011d3	576	/* Get tick */
sahilmgandhi	18:6a4db94011d3	577	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	578
sahilmgandhi	18:6a4db94011d3	579	/* Check if the DMA2D is effectively disabled */
sahilmgandhi	18:6a4db94011d3	580	while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
sahilmgandhi	18:6a4db94011d3	581	{
sahilmgandhi	18:6a4db94011d3	582	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
sahilmgandhi	18:6a4db94011d3	583	{
sahilmgandhi	18:6a4db94011d3	584	/* Update error code */
sahilmgandhi	18:6a4db94011d3	585	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	586
sahilmgandhi	18:6a4db94011d3	587	/* Change the DMA2D state */
sahilmgandhi	18:6a4db94011d3	588	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	589
sahilmgandhi	18:6a4db94011d3	590	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	591	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	592
sahilmgandhi	18:6a4db94011d3	593	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	594	}
sahilmgandhi	18:6a4db94011d3	595	}
sahilmgandhi	18:6a4db94011d3	596
sahilmgandhi	18:6a4db94011d3	597	/* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
sahilmgandhi	18:6a4db94011d3	598	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC\|DMA2D_IT_TE\|DMA2D_IT_CE);
sahilmgandhi	18:6a4db94011d3	599
sahilmgandhi	18:6a4db94011d3	600	/* Change the DMA2D state*/
sahilmgandhi	18:6a4db94011d3	601	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	602
sahilmgandhi	18:6a4db94011d3	603	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	604	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	605
sahilmgandhi	18:6a4db94011d3	606	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	607	}
sahilmgandhi	18:6a4db94011d3	608
sahilmgandhi	18:6a4db94011d3	609	/**
sahilmgandhi	18:6a4db94011d3	610	* @brief Suspend the DMA2D Transfer.
sahilmgandhi	18:6a4db94011d3	611	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	612	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	613	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	614	*/
sahilmgandhi	18:6a4db94011d3	615	HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	616	{
sahilmgandhi	18:6a4db94011d3	617	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	618
sahilmgandhi	18:6a4db94011d3	619	/* Suspend the DMA2D transfer */
sahilmgandhi	18:6a4db94011d3	620	/* START bit is reset to make sure not to set it again, in the event the HW clears it
sahilmgandhi	18:6a4db94011d3	621	between the register read and the register write by the CPU (writing 0 has no
sahilmgandhi	18:6a4db94011d3	622	effect on START bitvalue). */
sahilmgandhi	18:6a4db94011d3	623	MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP\|DMA2D_CR_START, DMA2D_CR_SUSP);
sahilmgandhi	18:6a4db94011d3	624
sahilmgandhi	18:6a4db94011d3	625	/* Get tick */
sahilmgandhi	18:6a4db94011d3	626	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	627
sahilmgandhi	18:6a4db94011d3	628	/* Check if the DMA2D is effectively suspended */
sahilmgandhi	18:6a4db94011d3	629	while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
sahilmgandhi	18:6a4db94011d3	630	&& ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
sahilmgandhi	18:6a4db94011d3	631	{
sahilmgandhi	18:6a4db94011d3	632	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
sahilmgandhi	18:6a4db94011d3	633	{
sahilmgandhi	18:6a4db94011d3	634	/* Update error code */
sahilmgandhi	18:6a4db94011d3	635	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	636
sahilmgandhi	18:6a4db94011d3	637	/* Change the DMA2D state */
sahilmgandhi	18:6a4db94011d3	638	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	639
sahilmgandhi	18:6a4db94011d3	640	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	641	}
sahilmgandhi	18:6a4db94011d3	642	}
sahilmgandhi	18:6a4db94011d3	643
sahilmgandhi	18:6a4db94011d3	644	/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
sahilmgandhi	18:6a4db94011d3	645	if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
sahilmgandhi	18:6a4db94011d3	646	{
sahilmgandhi	18:6a4db94011d3	647	hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
sahilmgandhi	18:6a4db94011d3	648	}
sahilmgandhi	18:6a4db94011d3	649	else
sahilmgandhi	18:6a4db94011d3	650	{
sahilmgandhi	18:6a4db94011d3	651	/* Make sure SUSP bit is cleared since it is meaningless
sahilmgandhi	18:6a4db94011d3	652	when no tranfer is on-going */
sahilmgandhi	18:6a4db94011d3	653	CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
sahilmgandhi	18:6a4db94011d3	654	}
sahilmgandhi	18:6a4db94011d3	655
sahilmgandhi	18:6a4db94011d3	656	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	657	}
sahilmgandhi	18:6a4db94011d3	658
sahilmgandhi	18:6a4db94011d3	659	/**
sahilmgandhi	18:6a4db94011d3	660	* @brief Resume the DMA2D Transfer.
sahilmgandhi	18:6a4db94011d3	661	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	662	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	663	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	664	*/
sahilmgandhi	18:6a4db94011d3	665	HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	666	{
sahilmgandhi	18:6a4db94011d3	667	/* Check the SUSP and START bits */
sahilmgandhi	18:6a4db94011d3	668	if((hdma2d->Instance->CR & (DMA2D_CR_SUSP \| DMA2D_CR_START)) == (DMA2D_CR_SUSP \| DMA2D_CR_START))
sahilmgandhi	18:6a4db94011d3	669	{
sahilmgandhi	18:6a4db94011d3	670	/* Ongoing transfer is suspended: change the DMA2D state before resuming */
sahilmgandhi	18:6a4db94011d3	671	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	672	}
sahilmgandhi	18:6a4db94011d3	673
sahilmgandhi	18:6a4db94011d3	674	/* Resume the DMA2D transfer */
sahilmgandhi	18:6a4db94011d3	675	/* START bit is reset to make sure not to set it again, in the event the HW clears it
sahilmgandhi	18:6a4db94011d3	676	between the register read and the register write by the CPU (writing 0 has no
sahilmgandhi	18:6a4db94011d3	677	effect on START bitvalue). */
sahilmgandhi	18:6a4db94011d3	678	CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP\|DMA2D_CR_START));
sahilmgandhi	18:6a4db94011d3	679
sahilmgandhi	18:6a4db94011d3	680	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	681	}
sahilmgandhi	18:6a4db94011d3	682
sahilmgandhi	18:6a4db94011d3	683	/**
sahilmgandhi	18:6a4db94011d3	684	* @brief Enable the DMA2D CLUT Transfer.
sahilmgandhi	18:6a4db94011d3	685	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	686	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	687	* @param LayerIdx: DMA2D Layer index.
sahilmgandhi	18:6a4db94011d3	688	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	689	* 0(background) / 1(foreground)
sahilmgandhi	18:6a4db94011d3	690	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	691	*/
sahilmgandhi	18:6a4db94011d3	692	HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
sahilmgandhi	18:6a4db94011d3	693	{
sahilmgandhi	18:6a4db94011d3	694	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	695	assert_param(IS_DMA2D_LAYER(LayerIdx));
sahilmgandhi	18:6a4db94011d3	696
sahilmgandhi	18:6a4db94011d3	697	/* Process locked */
sahilmgandhi	18:6a4db94011d3	698	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	699
sahilmgandhi	18:6a4db94011d3	700	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	701	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	702
sahilmgandhi	18:6a4db94011d3	703	if(LayerIdx == 0U)
sahilmgandhi	18:6a4db94011d3	704	{
sahilmgandhi	18:6a4db94011d3	705	/* Enable the background CLUT loading */
sahilmgandhi	18:6a4db94011d3	706	SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
sahilmgandhi	18:6a4db94011d3	707	}
sahilmgandhi	18:6a4db94011d3	708	else
sahilmgandhi	18:6a4db94011d3	709	{
sahilmgandhi	18:6a4db94011d3	710	/* Enable the foreground CLUT loading */
sahilmgandhi	18:6a4db94011d3	711	SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
sahilmgandhi	18:6a4db94011d3	712	}
sahilmgandhi	18:6a4db94011d3	713
sahilmgandhi	18:6a4db94011d3	714	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	715	}
sahilmgandhi	18:6a4db94011d3	716
sahilmgandhi	18:6a4db94011d3	717	/**
sahilmgandhi	18:6a4db94011d3	718	* @brief Start DMA2D CLUT Loading.
sahilmgandhi	18:6a4db94011d3	719	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	720	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	721	* @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	722	* the configuration information for the color look up table.
sahilmgandhi	18:6a4db94011d3	723	* @param LayerIdx: DMA2D Layer index.
sahilmgandhi	18:6a4db94011d3	724	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	725	* 0(background) / 1(foreground)
sahilmgandhi	18:6a4db94011d3	726	* @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
sahilmgandhi	18:6a4db94011d3	727	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	728	*/
sahilmgandhi	18:6a4db94011d3	729	HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
sahilmgandhi	18:6a4db94011d3	730	{
sahilmgandhi	18:6a4db94011d3	731	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	732	assert_param(IS_DMA2D_LAYER(LayerIdx));
sahilmgandhi	18:6a4db94011d3	733	assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
sahilmgandhi	18:6a4db94011d3	734	assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
sahilmgandhi	18:6a4db94011d3	735
sahilmgandhi	18:6a4db94011d3	736	/* Process locked */
sahilmgandhi	18:6a4db94011d3	737	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	738
sahilmgandhi	18:6a4db94011d3	739	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	740	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	741
sahilmgandhi	18:6a4db94011d3	742	/* Configure the CLUT of the background DMA2D layer */
sahilmgandhi	18:6a4db94011d3	743	if(LayerIdx == 0U)
sahilmgandhi	18:6a4db94011d3	744	{
sahilmgandhi	18:6a4db94011d3	745	/* Write background CLUT memory address */
sahilmgandhi	18:6a4db94011d3	746	WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
sahilmgandhi	18:6a4db94011d3	747
sahilmgandhi	18:6a4db94011d3	748	/* Write background CLUT size and CLUT color mode */
sahilmgandhi	18:6a4db94011d3	749	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS \| DMA2D_BGPFCCR_CCM),
sahilmgandhi	18:6a4db94011d3	750	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
sahilmgandhi	18:6a4db94011d3	751
sahilmgandhi	18:6a4db94011d3	752	/* Enable the CLUT loading for the background */
sahilmgandhi	18:6a4db94011d3	753	SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
sahilmgandhi	18:6a4db94011d3	754	}
sahilmgandhi	18:6a4db94011d3	755	/* Configure the CLUT of the foreground DMA2D layer */
sahilmgandhi	18:6a4db94011d3	756	else
sahilmgandhi	18:6a4db94011d3	757	{
sahilmgandhi	18:6a4db94011d3	758	/* Write foreground CLUT memory address */
sahilmgandhi	18:6a4db94011d3	759	WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
sahilmgandhi	18:6a4db94011d3	760
sahilmgandhi	18:6a4db94011d3	761	/* Write foreground CLUT size and CLUT color mode */
sahilmgandhi	18:6a4db94011d3	762	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS \| DMA2D_FGPFCCR_CCM),
sahilmgandhi	18:6a4db94011d3	763	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
sahilmgandhi	18:6a4db94011d3	764
sahilmgandhi	18:6a4db94011d3	765	/* Enable the CLUT loading for the foreground */
sahilmgandhi	18:6a4db94011d3	766	SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
sahilmgandhi	18:6a4db94011d3	767	}
sahilmgandhi	18:6a4db94011d3	768
sahilmgandhi	18:6a4db94011d3	769	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	770	}
sahilmgandhi	18:6a4db94011d3	771
sahilmgandhi	18:6a4db94011d3	772	/**
sahilmgandhi	18:6a4db94011d3	773	* @brief Start DMA2D CLUT Loading with interrupt enabled.
sahilmgandhi	18:6a4db94011d3	774	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	775	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	776	* @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	777	* the configuration information for the color look up table.
sahilmgandhi	18:6a4db94011d3	778	* @param LayerIdx: DMA2D Layer index.
sahilmgandhi	18:6a4db94011d3	779	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	780	* 0(background) / 1(foreground)
sahilmgandhi	18:6a4db94011d3	781	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	782	*/
sahilmgandhi	18:6a4db94011d3	783	HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
sahilmgandhi	18:6a4db94011d3	784	{
sahilmgandhi	18:6a4db94011d3	785	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	786	assert_param(IS_DMA2D_LAYER(LayerIdx));
sahilmgandhi	18:6a4db94011d3	787	assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
sahilmgandhi	18:6a4db94011d3	788	assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
sahilmgandhi	18:6a4db94011d3	789
sahilmgandhi	18:6a4db94011d3	790	/* Process locked */
sahilmgandhi	18:6a4db94011d3	791	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	792
sahilmgandhi	18:6a4db94011d3	793	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	794	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	795
sahilmgandhi	18:6a4db94011d3	796	/* Configure the CLUT of the background DMA2D layer */
sahilmgandhi	18:6a4db94011d3	797	if(LayerIdx == 0U)
sahilmgandhi	18:6a4db94011d3	798	{
sahilmgandhi	18:6a4db94011d3	799	/* Write background CLUT memory address */
sahilmgandhi	18:6a4db94011d3	800	WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
sahilmgandhi	18:6a4db94011d3	801
sahilmgandhi	18:6a4db94011d3	802	/* Write background CLUT size and CLUT color mode */
sahilmgandhi	18:6a4db94011d3	803	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS \| DMA2D_BGPFCCR_CCM),
sahilmgandhi	18:6a4db94011d3	804	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
sahilmgandhi	18:6a4db94011d3	805
sahilmgandhi	18:6a4db94011d3	806	/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
sahilmgandhi	18:6a4db94011d3	807	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC \| DMA2D_IT_TE \| DMA2D_IT_CE \|DMA2D_IT_CAE);
sahilmgandhi	18:6a4db94011d3	808
sahilmgandhi	18:6a4db94011d3	809	/* Enable the CLUT loading for the background */
sahilmgandhi	18:6a4db94011d3	810	SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
sahilmgandhi	18:6a4db94011d3	811	}
sahilmgandhi	18:6a4db94011d3	812	/* Configure the CLUT of the foreground DMA2D layer */
sahilmgandhi	18:6a4db94011d3	813	else
sahilmgandhi	18:6a4db94011d3	814	{
sahilmgandhi	18:6a4db94011d3	815	/* Write foreground CLUT memory address */
sahilmgandhi	18:6a4db94011d3	816	WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
sahilmgandhi	18:6a4db94011d3	817
sahilmgandhi	18:6a4db94011d3	818	/* Write foreground CLUT size and CLUT color mode */
sahilmgandhi	18:6a4db94011d3	819	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS \| DMA2D_FGPFCCR_CCM),
sahilmgandhi	18:6a4db94011d3	820	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
sahilmgandhi	18:6a4db94011d3	821
sahilmgandhi	18:6a4db94011d3	822	/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
sahilmgandhi	18:6a4db94011d3	823	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC \| DMA2D_IT_TE \| DMA2D_IT_CE \|DMA2D_IT_CAE);
sahilmgandhi	18:6a4db94011d3	824
sahilmgandhi	18:6a4db94011d3	825	/* Enable the CLUT loading for the foreground */
sahilmgandhi	18:6a4db94011d3	826	SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
sahilmgandhi	18:6a4db94011d3	827	}
sahilmgandhi	18:6a4db94011d3	828
sahilmgandhi	18:6a4db94011d3	829	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	830	}
sahilmgandhi	18:6a4db94011d3	831
sahilmgandhi	18:6a4db94011d3	832	/**
sahilmgandhi	18:6a4db94011d3	833	* @brief Abort the DMA2D CLUT loading.
sahilmgandhi	18:6a4db94011d3	834	* @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	835	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	836	* @param LayerIdx: DMA2D Layer index.
sahilmgandhi	18:6a4db94011d3	837	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	838	* 0(background) / 1(foreground)
sahilmgandhi	18:6a4db94011d3	839	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	840	*/
sahilmgandhi	18:6a4db94011d3	841	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
sahilmgandhi	18:6a4db94011d3	842	{
sahilmgandhi	18:6a4db94011d3	843	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	844	__IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
sahilmgandhi	18:6a4db94011d3	845
sahilmgandhi	18:6a4db94011d3	846	/* Abort the CLUT loading */
sahilmgandhi	18:6a4db94011d3	847	SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
sahilmgandhi	18:6a4db94011d3	848
sahilmgandhi	18:6a4db94011d3	849	/* If foreground CLUT loading is considered, update local variables */
sahilmgandhi	18:6a4db94011d3	850	if(LayerIdx == 1)
sahilmgandhi	18:6a4db94011d3	851	{
sahilmgandhi	18:6a4db94011d3	852	reg = &(hdma2d->Instance->FGPFCCR);
sahilmgandhi	18:6a4db94011d3	853	}
sahilmgandhi	18:6a4db94011d3	854
sahilmgandhi	18:6a4db94011d3	855	/* Get tick */
sahilmgandhi	18:6a4db94011d3	856	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	857
sahilmgandhi	18:6a4db94011d3	858	/* Check if the CLUT loading is aborted */
sahilmgandhi	18:6a4db94011d3	859	while((*reg & DMA2D_BGPFCCR_START) != RESET)
sahilmgandhi	18:6a4db94011d3	860	{
sahilmgandhi	18:6a4db94011d3	861	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
sahilmgandhi	18:6a4db94011d3	862	{
sahilmgandhi	18:6a4db94011d3	863	/* Update error code */
sahilmgandhi	18:6a4db94011d3	864	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	865
sahilmgandhi	18:6a4db94011d3	866	/* Change the DMA2D state */
sahilmgandhi	18:6a4db94011d3	867	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	868
sahilmgandhi	18:6a4db94011d3	869	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	870	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	871
sahilmgandhi	18:6a4db94011d3	872	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	873	}
sahilmgandhi	18:6a4db94011d3	874	}
sahilmgandhi	18:6a4db94011d3	875
sahilmgandhi	18:6a4db94011d3	876	/* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
sahilmgandhi	18:6a4db94011d3	877	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC \| DMA2D_IT_TE \| DMA2D_IT_CE \|DMA2D_IT_CAE);
sahilmgandhi	18:6a4db94011d3	878
sahilmgandhi	18:6a4db94011d3	879	/* Change the DMA2D state*/
sahilmgandhi	18:6a4db94011d3	880	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	881
sahilmgandhi	18:6a4db94011d3	882	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	883	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	884
sahilmgandhi	18:6a4db94011d3	885	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	886	}
sahilmgandhi	18:6a4db94011d3	887
sahilmgandhi	18:6a4db94011d3	888	/**
sahilmgandhi	18:6a4db94011d3	889	* @brief Suspend the DMA2D CLUT loading.
sahilmgandhi	18:6a4db94011d3	890	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	891	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	892	* @param LayerIdx: DMA2D Layer index.
sahilmgandhi	18:6a4db94011d3	893	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	894	* 0(background) / 1(foreground)
sahilmgandhi	18:6a4db94011d3	895	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	896	*/
sahilmgandhi	18:6a4db94011d3	897	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
sahilmgandhi	18:6a4db94011d3	898	{
sahilmgandhi	18:6a4db94011d3	899	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	900	__IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
sahilmgandhi	18:6a4db94011d3	901
sahilmgandhi	18:6a4db94011d3	902	/* Suspend the CLUT loading */
sahilmgandhi	18:6a4db94011d3	903	SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
sahilmgandhi	18:6a4db94011d3	904
sahilmgandhi	18:6a4db94011d3	905	/* If foreground CLUT loading is considered, update local variables */
sahilmgandhi	18:6a4db94011d3	906	if(LayerIdx == 1U)
sahilmgandhi	18:6a4db94011d3	907	{
sahilmgandhi	18:6a4db94011d3	908	reg = &(hdma2d->Instance->FGPFCCR);
sahilmgandhi	18:6a4db94011d3	909	}
sahilmgandhi	18:6a4db94011d3	910
sahilmgandhi	18:6a4db94011d3	911	/* Get tick */
sahilmgandhi	18:6a4db94011d3	912	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	913
sahilmgandhi	18:6a4db94011d3	914	/* Check if the CLUT loading is suspended */
sahilmgandhi	18:6a4db94011d3	915	while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
sahilmgandhi	18:6a4db94011d3	916	&& ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
sahilmgandhi	18:6a4db94011d3	917	{
sahilmgandhi	18:6a4db94011d3	918	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
sahilmgandhi	18:6a4db94011d3	919	{
sahilmgandhi	18:6a4db94011d3	920	/* Update error code */
sahilmgandhi	18:6a4db94011d3	921	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	922
sahilmgandhi	18:6a4db94011d3	923	/* Change the DMA2D state */
sahilmgandhi	18:6a4db94011d3	924	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	925
sahilmgandhi	18:6a4db94011d3	926	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	927	}
sahilmgandhi	18:6a4db94011d3	928	}
sahilmgandhi	18:6a4db94011d3	929
sahilmgandhi	18:6a4db94011d3	930	/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
sahilmgandhi	18:6a4db94011d3	931	if ((*reg & DMA2D_BGPFCCR_START) != RESET)
sahilmgandhi	18:6a4db94011d3	932	{
sahilmgandhi	18:6a4db94011d3	933	hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
sahilmgandhi	18:6a4db94011d3	934	}
sahilmgandhi	18:6a4db94011d3	935	else
sahilmgandhi	18:6a4db94011d3	936	{
sahilmgandhi	18:6a4db94011d3	937	/* Make sure SUSP bit is cleared since it is meaningless
sahilmgandhi	18:6a4db94011d3	938	when no tranfer is on-going */
sahilmgandhi	18:6a4db94011d3	939	CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
sahilmgandhi	18:6a4db94011d3	940	}
sahilmgandhi	18:6a4db94011d3	941
sahilmgandhi	18:6a4db94011d3	942	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	943	}
sahilmgandhi	18:6a4db94011d3	944
sahilmgandhi	18:6a4db94011d3	945	/**
sahilmgandhi	18:6a4db94011d3	946	* @brief Resume the DMA2D CLUT loading.
sahilmgandhi	18:6a4db94011d3	947	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	948	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	949	* @param LayerIdx: DMA2D Layer index.
sahilmgandhi	18:6a4db94011d3	950	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	951	* 0(background) / 1(foreground)
sahilmgandhi	18:6a4db94011d3	952	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	953	*/
sahilmgandhi	18:6a4db94011d3	954	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
sahilmgandhi	18:6a4db94011d3	955	{
sahilmgandhi	18:6a4db94011d3	956	/* Check the SUSP and START bits for background or foreground CLUT loading */
sahilmgandhi	18:6a4db94011d3	957	if(LayerIdx == 0U)
sahilmgandhi	18:6a4db94011d3	958	{
sahilmgandhi	18:6a4db94011d3	959	/* Background CLUT loading suspension check */
sahilmgandhi	18:6a4db94011d3	960	if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
sahilmgandhi	18:6a4db94011d3	961	&& ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
sahilmgandhi	18:6a4db94011d3	962	{
sahilmgandhi	18:6a4db94011d3	963	/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
sahilmgandhi	18:6a4db94011d3	964	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	965	}
sahilmgandhi	18:6a4db94011d3	966	}
sahilmgandhi	18:6a4db94011d3	967	else
sahilmgandhi	18:6a4db94011d3	968	{
sahilmgandhi	18:6a4db94011d3	969	/* Foreground CLUT loading suspension check */
sahilmgandhi	18:6a4db94011d3	970	if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
sahilmgandhi	18:6a4db94011d3	971	&& ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
sahilmgandhi	18:6a4db94011d3	972	{
sahilmgandhi	18:6a4db94011d3	973	/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
sahilmgandhi	18:6a4db94011d3	974	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	975	}
sahilmgandhi	18:6a4db94011d3	976	}
sahilmgandhi	18:6a4db94011d3	977
sahilmgandhi	18:6a4db94011d3	978	/* Resume the CLUT loading */
sahilmgandhi	18:6a4db94011d3	979	CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
sahilmgandhi	18:6a4db94011d3	980
sahilmgandhi	18:6a4db94011d3	981	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	982	}
sahilmgandhi	18:6a4db94011d3	983
sahilmgandhi	18:6a4db94011d3	984	/**
sahilmgandhi	18:6a4db94011d3	985	* @brief Polling for transfer complete or CLUT loading.
sahilmgandhi	18:6a4db94011d3	986	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	987	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	988	* @param Timeout: Timeout duration
sahilmgandhi	18:6a4db94011d3	989	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	990	*/
sahilmgandhi	18:6a4db94011d3	991	HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
sahilmgandhi	18:6a4db94011d3	992	{
sahilmgandhi	18:6a4db94011d3	993	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	994	__IO uint32_t isrflags = 0x0U;
sahilmgandhi	18:6a4db94011d3	995
sahilmgandhi	18:6a4db94011d3	996	/* Polling for DMA2D transfer */
sahilmgandhi	18:6a4db94011d3	997	if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
sahilmgandhi	18:6a4db94011d3	998	{
sahilmgandhi	18:6a4db94011d3	999	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1000	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1001
sahilmgandhi	18:6a4db94011d3	1002	while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
sahilmgandhi	18:6a4db94011d3	1003	{
sahilmgandhi	18:6a4db94011d3	1004	isrflags = READ_REG(hdma2d->Instance->ISR);
sahilmgandhi	18:6a4db94011d3	1005	if ((isrflags & (DMA2D_FLAG_CE\|DMA2D_FLAG_TE)) != RESET)
sahilmgandhi	18:6a4db94011d3	1006	{
sahilmgandhi	18:6a4db94011d3	1007	if ((isrflags & DMA2D_FLAG_CE) != RESET)
sahilmgandhi	18:6a4db94011d3	1008	{
sahilmgandhi	18:6a4db94011d3	1009	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CE;
sahilmgandhi	18:6a4db94011d3	1010	}
sahilmgandhi	18:6a4db94011d3	1011	if ((isrflags & DMA2D_FLAG_TE) != RESET)
sahilmgandhi	18:6a4db94011d3	1012	{
sahilmgandhi	18:6a4db94011d3	1013	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TE;
sahilmgandhi	18:6a4db94011d3	1014	}
sahilmgandhi	18:6a4db94011d3	1015	/* Clear the transfer and configuration error flags */
sahilmgandhi	18:6a4db94011d3	1016	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE \| DMA2D_FLAG_TE);
sahilmgandhi	18:6a4db94011d3	1017
sahilmgandhi	18:6a4db94011d3	1018	/* Change DMA2D state */
sahilmgandhi	18:6a4db94011d3	1019	hdma2d->State = HAL_DMA2D_STATE_ERROR;
sahilmgandhi	18:6a4db94011d3	1020
sahilmgandhi	18:6a4db94011d3	1021	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1022	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1023
sahilmgandhi	18:6a4db94011d3	1024	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1025	}
sahilmgandhi	18:6a4db94011d3	1026	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1027	if(Timeout != HAL_MAX_DELAY)
sahilmgandhi	18:6a4db94011d3	1028	{
sahilmgandhi	18:6a4db94011d3	1029	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi	18:6a4db94011d3	1030	{
sahilmgandhi	18:6a4db94011d3	1031	/* Update error code */
sahilmgandhi	18:6a4db94011d3	1032	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1033
sahilmgandhi	18:6a4db94011d3	1034	/* Change the DMA2D state */
sahilmgandhi	18:6a4db94011d3	1035	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1036
sahilmgandhi	18:6a4db94011d3	1037	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1038	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1039
sahilmgandhi	18:6a4db94011d3	1040	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1041	}
sahilmgandhi	18:6a4db94011d3	1042	}
sahilmgandhi	18:6a4db94011d3	1043	}
sahilmgandhi	18:6a4db94011d3	1044	}
sahilmgandhi	18:6a4db94011d3	1045	/* Polling for CLUT loading (foreground or background) */
sahilmgandhi	18:6a4db94011d3	1046	if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) \|\|
sahilmgandhi	18:6a4db94011d3	1047	((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
sahilmgandhi	18:6a4db94011d3	1048	{
sahilmgandhi	18:6a4db94011d3	1049	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1050	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1051
sahilmgandhi	18:6a4db94011d3	1052	while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
sahilmgandhi	18:6a4db94011d3	1053	{
sahilmgandhi	18:6a4db94011d3	1054	isrflags = READ_REG(hdma2d->Instance->ISR);
sahilmgandhi	18:6a4db94011d3	1055	if ((isrflags & (DMA2D_FLAG_CAE\|DMA2D_FLAG_CE\|DMA2D_FLAG_TE)) != RESET)
sahilmgandhi	18:6a4db94011d3	1056	{
sahilmgandhi	18:6a4db94011d3	1057	if ((isrflags & DMA2D_FLAG_CAE) != RESET)
sahilmgandhi	18:6a4db94011d3	1058	{
sahilmgandhi	18:6a4db94011d3	1059	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CAE;
sahilmgandhi	18:6a4db94011d3	1060	}
sahilmgandhi	18:6a4db94011d3	1061	if ((isrflags & DMA2D_FLAG_CE) != RESET)
sahilmgandhi	18:6a4db94011d3	1062	{
sahilmgandhi	18:6a4db94011d3	1063	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CE;
sahilmgandhi	18:6a4db94011d3	1064	}
sahilmgandhi	18:6a4db94011d3	1065	if ((isrflags & DMA2D_FLAG_TE) != RESET)
sahilmgandhi	18:6a4db94011d3	1066	{
sahilmgandhi	18:6a4db94011d3	1067	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TE;
sahilmgandhi	18:6a4db94011d3	1068	}
sahilmgandhi	18:6a4db94011d3	1069	/* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
sahilmgandhi	18:6a4db94011d3	1070	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE \| DMA2D_FLAG_CE \| DMA2D_FLAG_TE);
sahilmgandhi	18:6a4db94011d3	1071
sahilmgandhi	18:6a4db94011d3	1072	/* Change DMA2D state */
sahilmgandhi	18:6a4db94011d3	1073	hdma2d->State= HAL_DMA2D_STATE_ERROR;
sahilmgandhi	18:6a4db94011d3	1074
sahilmgandhi	18:6a4db94011d3	1075	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1076	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1077
sahilmgandhi	18:6a4db94011d3	1078	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1079	}
sahilmgandhi	18:6a4db94011d3	1080	/* Check for the Timeout */
sahilmgandhi	18:6a4db94011d3	1081	if(Timeout != HAL_MAX_DELAY)
sahilmgandhi	18:6a4db94011d3	1082	{
sahilmgandhi	18:6a4db94011d3	1083	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi	18:6a4db94011d3	1084	{
sahilmgandhi	18:6a4db94011d3	1085	/* Update error code */
sahilmgandhi	18:6a4db94011d3	1086	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1087
sahilmgandhi	18:6a4db94011d3	1088	/* Change the DMA2D state */
sahilmgandhi	18:6a4db94011d3	1089	hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1090
sahilmgandhi	18:6a4db94011d3	1091	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1092	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1093
sahilmgandhi	18:6a4db94011d3	1094	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1095	}
sahilmgandhi	18:6a4db94011d3	1096	}
sahilmgandhi	18:6a4db94011d3	1097	}
sahilmgandhi	18:6a4db94011d3	1098	}
sahilmgandhi	18:6a4db94011d3	1099
sahilmgandhi	18:6a4db94011d3	1100	/* Clear the transfer complete and CLUT loading flags */
sahilmgandhi	18:6a4db94011d3	1101	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC\|DMA2D_FLAG_CTC);
sahilmgandhi	18:6a4db94011d3	1102
sahilmgandhi	18:6a4db94011d3	1103	/* Change DMA2D state */
sahilmgandhi	18:6a4db94011d3	1104	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1105
sahilmgandhi	18:6a4db94011d3	1106	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1107	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1108
sahilmgandhi	18:6a4db94011d3	1109	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1110	}
sahilmgandhi	18:6a4db94011d3	1111	/**
sahilmgandhi	18:6a4db94011d3	1112	* @brief Handle DMA2D interrupt request.
sahilmgandhi	18:6a4db94011d3	1113	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1114	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	1115	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1116	*/
sahilmgandhi	18:6a4db94011d3	1117	void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	1118	{
sahilmgandhi	18:6a4db94011d3	1119	uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
sahilmgandhi	18:6a4db94011d3	1120	uint32_t crflags = READ_REG(hdma2d->Instance->CR);
sahilmgandhi	18:6a4db94011d3	1121
sahilmgandhi	18:6a4db94011d3	1122	/* Transfer Error Interrupt management ***************************************/
sahilmgandhi	18:6a4db94011d3	1123	if ((isrflags & DMA2D_FLAG_TE) != RESET)
sahilmgandhi	18:6a4db94011d3	1124	{
sahilmgandhi	18:6a4db94011d3	1125	if ((crflags & DMA2D_IT_TE) != RESET)
sahilmgandhi	18:6a4db94011d3	1126	{
sahilmgandhi	18:6a4db94011d3	1127	/* Disable the transfer Error interrupt */
sahilmgandhi	18:6a4db94011d3	1128	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
sahilmgandhi	18:6a4db94011d3	1129
sahilmgandhi	18:6a4db94011d3	1130	/* Update error code */
sahilmgandhi	18:6a4db94011d3	1131	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TE;
sahilmgandhi	18:6a4db94011d3	1132
sahilmgandhi	18:6a4db94011d3	1133	/* Clear the transfer error flag */
sahilmgandhi	18:6a4db94011d3	1134	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
sahilmgandhi	18:6a4db94011d3	1135
sahilmgandhi	18:6a4db94011d3	1136	/* Change DMA2D state */
sahilmgandhi	18:6a4db94011d3	1137	hdma2d->State = HAL_DMA2D_STATE_ERROR;
sahilmgandhi	18:6a4db94011d3	1138
sahilmgandhi	18:6a4db94011d3	1139	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1140	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1141
sahilmgandhi	18:6a4db94011d3	1142	if(hdma2d->XferErrorCallback != NULL)
sahilmgandhi	18:6a4db94011d3	1143	{
sahilmgandhi	18:6a4db94011d3	1144	/* Transfer error Callback */
sahilmgandhi	18:6a4db94011d3	1145	hdma2d->XferErrorCallback(hdma2d);
sahilmgandhi	18:6a4db94011d3	1146	}
sahilmgandhi	18:6a4db94011d3	1147	}
sahilmgandhi	18:6a4db94011d3	1148	}
sahilmgandhi	18:6a4db94011d3	1149	/* Configuration Error Interrupt management **********************************/
sahilmgandhi	18:6a4db94011d3	1150	if ((isrflags & DMA2D_FLAG_CE) != RESET)
sahilmgandhi	18:6a4db94011d3	1151	{
sahilmgandhi	18:6a4db94011d3	1152	if ((crflags & DMA2D_IT_CE) != RESET)
sahilmgandhi	18:6a4db94011d3	1153	{
sahilmgandhi	18:6a4db94011d3	1154	/* Disable the Configuration Error interrupt */
sahilmgandhi	18:6a4db94011d3	1155	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
sahilmgandhi	18:6a4db94011d3	1156
sahilmgandhi	18:6a4db94011d3	1157	/* Clear the Configuration error flag */
sahilmgandhi	18:6a4db94011d3	1158	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
sahilmgandhi	18:6a4db94011d3	1159
sahilmgandhi	18:6a4db94011d3	1160	/* Update error code */
sahilmgandhi	18:6a4db94011d3	1161	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CE;
sahilmgandhi	18:6a4db94011d3	1162
sahilmgandhi	18:6a4db94011d3	1163	/* Change DMA2D state */
sahilmgandhi	18:6a4db94011d3	1164	hdma2d->State = HAL_DMA2D_STATE_ERROR;
sahilmgandhi	18:6a4db94011d3	1165
sahilmgandhi	18:6a4db94011d3	1166	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1167	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1168
sahilmgandhi	18:6a4db94011d3	1169	if(hdma2d->XferErrorCallback != NULL)
sahilmgandhi	18:6a4db94011d3	1170	{
sahilmgandhi	18:6a4db94011d3	1171	/* Transfer error Callback */
sahilmgandhi	18:6a4db94011d3	1172	hdma2d->XferErrorCallback(hdma2d);
sahilmgandhi	18:6a4db94011d3	1173	}
sahilmgandhi	18:6a4db94011d3	1174	}
sahilmgandhi	18:6a4db94011d3	1175	}
sahilmgandhi	18:6a4db94011d3	1176	/* CLUT access Error Interrupt management ***********************************/
sahilmgandhi	18:6a4db94011d3	1177	if ((isrflags & DMA2D_FLAG_CAE) != RESET)
sahilmgandhi	18:6a4db94011d3	1178	{
sahilmgandhi	18:6a4db94011d3	1179	if ((crflags & DMA2D_IT_CAE) != RESET)
sahilmgandhi	18:6a4db94011d3	1180	{
sahilmgandhi	18:6a4db94011d3	1181	/* Disable the CLUT access error interrupt */
sahilmgandhi	18:6a4db94011d3	1182	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
sahilmgandhi	18:6a4db94011d3	1183
sahilmgandhi	18:6a4db94011d3	1184	/* Clear the CLUT access error flag */
sahilmgandhi	18:6a4db94011d3	1185	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
sahilmgandhi	18:6a4db94011d3	1186
sahilmgandhi	18:6a4db94011d3	1187	/* Update error code */
sahilmgandhi	18:6a4db94011d3	1188	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CAE;
sahilmgandhi	18:6a4db94011d3	1189
sahilmgandhi	18:6a4db94011d3	1190	/* Change DMA2D state */
sahilmgandhi	18:6a4db94011d3	1191	hdma2d->State = HAL_DMA2D_STATE_ERROR;
sahilmgandhi	18:6a4db94011d3	1192
sahilmgandhi	18:6a4db94011d3	1193	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1194	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1195
sahilmgandhi	18:6a4db94011d3	1196	if(hdma2d->XferErrorCallback != NULL)
sahilmgandhi	18:6a4db94011d3	1197	{
sahilmgandhi	18:6a4db94011d3	1198	/* Transfer error Callback */
sahilmgandhi	18:6a4db94011d3	1199	hdma2d->XferErrorCallback(hdma2d);
sahilmgandhi	18:6a4db94011d3	1200	}
sahilmgandhi	18:6a4db94011d3	1201	}
sahilmgandhi	18:6a4db94011d3	1202	}
sahilmgandhi	18:6a4db94011d3	1203	/* Transfer watermark Interrupt management **********************************/
sahilmgandhi	18:6a4db94011d3	1204	if ((isrflags & DMA2D_FLAG_TW) != RESET)
sahilmgandhi	18:6a4db94011d3	1205	{
sahilmgandhi	18:6a4db94011d3	1206	if ((crflags & DMA2D_IT_TW) != RESET)
sahilmgandhi	18:6a4db94011d3	1207	{
sahilmgandhi	18:6a4db94011d3	1208	/* Disable the transfer watermark interrupt */
sahilmgandhi	18:6a4db94011d3	1209	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
sahilmgandhi	18:6a4db94011d3	1210
sahilmgandhi	18:6a4db94011d3	1211	/* Clear the transfer watermark flag */
sahilmgandhi	18:6a4db94011d3	1212	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
sahilmgandhi	18:6a4db94011d3	1213
sahilmgandhi	18:6a4db94011d3	1214	/* Transfer watermark Callback */
sahilmgandhi	18:6a4db94011d3	1215	HAL_DMA2D_LineEventCallback(hdma2d);
sahilmgandhi	18:6a4db94011d3	1216	}
sahilmgandhi	18:6a4db94011d3	1217	}
sahilmgandhi	18:6a4db94011d3	1218	/* Transfer Complete Interrupt management ************************************/
sahilmgandhi	18:6a4db94011d3	1219	if ((isrflags & DMA2D_FLAG_TC) != RESET)
sahilmgandhi	18:6a4db94011d3	1220	{
sahilmgandhi	18:6a4db94011d3	1221	if ((crflags & DMA2D_IT_TC) != RESET)
sahilmgandhi	18:6a4db94011d3	1222	{
sahilmgandhi	18:6a4db94011d3	1223	/* Disable the transfer complete interrupt */
sahilmgandhi	18:6a4db94011d3	1224	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
sahilmgandhi	18:6a4db94011d3	1225
sahilmgandhi	18:6a4db94011d3	1226	/* Clear the transfer complete flag */
sahilmgandhi	18:6a4db94011d3	1227	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
sahilmgandhi	18:6a4db94011d3	1228
sahilmgandhi	18:6a4db94011d3	1229	/* Update error code */
sahilmgandhi	18:6a4db94011d3	1230	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	1231
sahilmgandhi	18:6a4db94011d3	1232	/* Change DMA2D state */
sahilmgandhi	18:6a4db94011d3	1233	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1234
sahilmgandhi	18:6a4db94011d3	1235	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1236	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1237
sahilmgandhi	18:6a4db94011d3	1238	if(hdma2d->XferCpltCallback != NULL)
sahilmgandhi	18:6a4db94011d3	1239	{
sahilmgandhi	18:6a4db94011d3	1240	/* Transfer complete Callback */
sahilmgandhi	18:6a4db94011d3	1241	hdma2d->XferCpltCallback(hdma2d);
sahilmgandhi	18:6a4db94011d3	1242	}
sahilmgandhi	18:6a4db94011d3	1243	}
sahilmgandhi	18:6a4db94011d3	1244	}
sahilmgandhi	18:6a4db94011d3	1245	/* CLUT Transfer Complete Interrupt management ******************************/
sahilmgandhi	18:6a4db94011d3	1246	if ((isrflags & DMA2D_FLAG_CTC) != RESET)
sahilmgandhi	18:6a4db94011d3	1247	{
sahilmgandhi	18:6a4db94011d3	1248	if ((crflags & DMA2D_IT_CTC) != RESET)
sahilmgandhi	18:6a4db94011d3	1249	{
sahilmgandhi	18:6a4db94011d3	1250	/* Disable the CLUT transfer complete interrupt */
sahilmgandhi	18:6a4db94011d3	1251	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
sahilmgandhi	18:6a4db94011d3	1252
sahilmgandhi	18:6a4db94011d3	1253	/* Clear the CLUT transfer complete flag */
sahilmgandhi	18:6a4db94011d3	1254	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
sahilmgandhi	18:6a4db94011d3	1255
sahilmgandhi	18:6a4db94011d3	1256	/* Update error code */
sahilmgandhi	18:6a4db94011d3	1257	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	1258
sahilmgandhi	18:6a4db94011d3	1259	/* Change DMA2D state */
sahilmgandhi	18:6a4db94011d3	1260	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1261
sahilmgandhi	18:6a4db94011d3	1262	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1263	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1264
sahilmgandhi	18:6a4db94011d3	1265	/* CLUT Transfer complete Callback */
sahilmgandhi	18:6a4db94011d3	1266	HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
sahilmgandhi	18:6a4db94011d3	1267	}
sahilmgandhi	18:6a4db94011d3	1268	}
sahilmgandhi	18:6a4db94011d3	1269	}
sahilmgandhi	18:6a4db94011d3	1270
sahilmgandhi	18:6a4db94011d3	1271	/**
sahilmgandhi	18:6a4db94011d3	1272	* @brief Transfer watermark callback.
sahilmgandhi	18:6a4db94011d3	1273	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1274	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	1275	* @retval None
sahilmgandhi	18:6a4db94011d3	1276	*/
sahilmgandhi	18:6a4db94011d3	1277	__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	1278	{
sahilmgandhi	18:6a4db94011d3	1279	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1280	UNUSED(hdma2d);
sahilmgandhi	18:6a4db94011d3	1281
sahilmgandhi	18:6a4db94011d3	1282	/* NOTE : This function should not be modified; when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1283	the HAL_DMA2D_LineEventCallback can be implemented in the user file.
sahilmgandhi	18:6a4db94011d3	1284	*/
sahilmgandhi	18:6a4db94011d3	1285	}
sahilmgandhi	18:6a4db94011d3	1286
sahilmgandhi	18:6a4db94011d3	1287	/**
sahilmgandhi	18:6a4db94011d3	1288	* @brief CLUT Transfer Complete callback.
sahilmgandhi	18:6a4db94011d3	1289	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1290	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	1291	* @retval None
sahilmgandhi	18:6a4db94011d3	1292	*/
sahilmgandhi	18:6a4db94011d3	1293	__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	1294	{
sahilmgandhi	18:6a4db94011d3	1295	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1296	UNUSED(hdma2d);
sahilmgandhi	18:6a4db94011d3	1297
sahilmgandhi	18:6a4db94011d3	1298	/* NOTE : This function should not be modified; when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1299	the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
sahilmgandhi	18:6a4db94011d3	1300	*/
sahilmgandhi	18:6a4db94011d3	1301	}
sahilmgandhi	18:6a4db94011d3	1302
sahilmgandhi	18:6a4db94011d3	1303	/**
sahilmgandhi	18:6a4db94011d3	1304	* @}
sahilmgandhi	18:6a4db94011d3	1305	*/
sahilmgandhi	18:6a4db94011d3	1306
sahilmgandhi	18:6a4db94011d3	1307	/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	1308	* @brief Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	1309	*
sahilmgandhi	18:6a4db94011d3	1310	@verbatim
sahilmgandhi	18:6a4db94011d3	1311	===============================================================================
sahilmgandhi	18:6a4db94011d3	1312	##### Peripheral Control functions #####
sahilmgandhi	18:6a4db94011d3	1313	===============================================================================
sahilmgandhi	18:6a4db94011d3	1314	[..] This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	1315	(+) Configure the DMA2D foreground or background layer parameters.
sahilmgandhi	18:6a4db94011d3	1316	(+) Configure the DMA2D CLUT transfer.
sahilmgandhi	18:6a4db94011d3	1317	(+) Configure the line watermark
sahilmgandhi	18:6a4db94011d3	1318	(+) Configure the dead time value.
sahilmgandhi	18:6a4db94011d3	1319	(+) Enable or disable the dead time value functionality.
sahilmgandhi	18:6a4db94011d3	1320
sahilmgandhi	18:6a4db94011d3	1321	@endverbatim
sahilmgandhi	18:6a4db94011d3	1322	* @{
sahilmgandhi	18:6a4db94011d3	1323	*/
sahilmgandhi	18:6a4db94011d3	1324
sahilmgandhi	18:6a4db94011d3	1325	/**
sahilmgandhi	18:6a4db94011d3	1326	* @brief Configure the DMA2D Layer according to the specified
sahilmgandhi	18:6a4db94011d3	1327	* parameters in the DMA2D_InitTypeDef and create the associated handle.
sahilmgandhi	18:6a4db94011d3	1328	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1329	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	1330	* @param LayerIdx: DMA2D Layer index.
sahilmgandhi	18:6a4db94011d3	1331	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1332	* 0(background) / 1(foreground)
sahilmgandhi	18:6a4db94011d3	1333	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1334	*/
sahilmgandhi	18:6a4db94011d3	1335	HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
sahilmgandhi	18:6a4db94011d3	1336	{
sahilmgandhi	18:6a4db94011d3	1337	DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
sahilmgandhi	18:6a4db94011d3	1338	uint32_t regValue = 0U;
sahilmgandhi	18:6a4db94011d3	1339
sahilmgandhi	18:6a4db94011d3	1340	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1341	assert_param(IS_DMA2D_LAYER(LayerIdx));
sahilmgandhi	18:6a4db94011d3	1342	assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
sahilmgandhi	18:6a4db94011d3	1343	if(hdma2d->Init.Mode != DMA2D_R2M)
sahilmgandhi	18:6a4db94011d3	1344	{
sahilmgandhi	18:6a4db94011d3	1345	assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
sahilmgandhi	18:6a4db94011d3	1346	if(hdma2d->Init.Mode != DMA2D_M2M)
sahilmgandhi	18:6a4db94011d3	1347	{
sahilmgandhi	18:6a4db94011d3	1348	assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
sahilmgandhi	18:6a4db94011d3	1349	}
sahilmgandhi	18:6a4db94011d3	1350	}
sahilmgandhi	18:6a4db94011d3	1351
sahilmgandhi	18:6a4db94011d3	1352	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1353	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1354
sahilmgandhi	18:6a4db94011d3	1355	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	1356	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1357
sahilmgandhi	18:6a4db94011d3	1358	/* DMA2D BGPFCR register configuration -----------------------------------*/
sahilmgandhi	18:6a4db94011d3	1359	/* Prepare the value to be written to the BGPFCCR register */
sahilmgandhi	18:6a4db94011d3	1360
sahilmgandhi	18:6a4db94011d3	1361	if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) \|\| (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
sahilmgandhi	18:6a4db94011d3	1362	{
sahilmgandhi	18:6a4db94011d3	1363	regValue = pLayerCfg->InputColorMode \| (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) \| (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
sahilmgandhi	18:6a4db94011d3	1364	}
sahilmgandhi	18:6a4db94011d3	1365	else
sahilmgandhi	18:6a4db94011d3	1366	{
sahilmgandhi	18:6a4db94011d3	1367	regValue = pLayerCfg->InputColorMode \| (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) \| (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
sahilmgandhi	18:6a4db94011d3	1368	}
sahilmgandhi	18:6a4db94011d3	1369
sahilmgandhi	18:6a4db94011d3	1370	/* Configure the background DMA2D layer */
sahilmgandhi	18:6a4db94011d3	1371	if(LayerIdx == 0)
sahilmgandhi	18:6a4db94011d3	1372	{
sahilmgandhi	18:6a4db94011d3	1373	/* Write DMA2D BGPFCCR register */
sahilmgandhi	18:6a4db94011d3	1374	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM \| DMA2D_BGPFCCR_AM \| DMA2D_BGPFCCR_ALPHA), regValue);
sahilmgandhi	18:6a4db94011d3	1375
sahilmgandhi	18:6a4db94011d3	1376	/* DMA2D BGOR register configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1377	WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
sahilmgandhi	18:6a4db94011d3	1378
sahilmgandhi	18:6a4db94011d3	1379	/* DMA2D BGCOLR register configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1380	if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) \|\| (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
sahilmgandhi	18:6a4db94011d3	1381	{
sahilmgandhi	18:6a4db94011d3	1382	WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE\|DMA2D_BGCOLR_GREEN\|DMA2D_BGCOLR_RED));
sahilmgandhi	18:6a4db94011d3	1383	}
sahilmgandhi	18:6a4db94011d3	1384	}
sahilmgandhi	18:6a4db94011d3	1385	/* Configure the foreground DMA2D layer */
sahilmgandhi	18:6a4db94011d3	1386	else
sahilmgandhi	18:6a4db94011d3	1387	{
sahilmgandhi	18:6a4db94011d3	1388	/* Write DMA2D FGPFCCR register */
sahilmgandhi	18:6a4db94011d3	1389	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM \| DMA2D_BGPFCCR_AM \| DMA2D_BGPFCCR_ALPHA), regValue);
sahilmgandhi	18:6a4db94011d3	1390
sahilmgandhi	18:6a4db94011d3	1391	/* DMA2D FGOR register configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1392	WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
sahilmgandhi	18:6a4db94011d3	1393
sahilmgandhi	18:6a4db94011d3	1394	/* DMA2D FGCOLR register configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1395	if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) \|\| (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
sahilmgandhi	18:6a4db94011d3	1396	{
sahilmgandhi	18:6a4db94011d3	1397	WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE\|DMA2D_FGCOLR_GREEN\|DMA2D_FGCOLR_RED));
sahilmgandhi	18:6a4db94011d3	1398	}
sahilmgandhi	18:6a4db94011d3	1399	}
sahilmgandhi	18:6a4db94011d3	1400	/* Initialize the DMA2D state*/
sahilmgandhi	18:6a4db94011d3	1401	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1402
sahilmgandhi	18:6a4db94011d3	1403	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1404	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1405
sahilmgandhi	18:6a4db94011d3	1406	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1407	}
sahilmgandhi	18:6a4db94011d3	1408
sahilmgandhi	18:6a4db94011d3	1409	/**
sahilmgandhi	18:6a4db94011d3	1410	* @brief Configure the DMA2D CLUT Transfer.
sahilmgandhi	18:6a4db94011d3	1411	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1412	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	1413	* @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1414	* the configuration information for the color look up table.
sahilmgandhi	18:6a4db94011d3	1415	* @param LayerIdx: DMA2D Layer index.
sahilmgandhi	18:6a4db94011d3	1416	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1417	* 0(background) / 1(foreground)
sahilmgandhi	18:6a4db94011d3	1418	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1419	*/
sahilmgandhi	18:6a4db94011d3	1420	HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
sahilmgandhi	18:6a4db94011d3	1421	{
sahilmgandhi	18:6a4db94011d3	1422	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1423	assert_param(IS_DMA2D_LAYER(LayerIdx));
sahilmgandhi	18:6a4db94011d3	1424	assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
sahilmgandhi	18:6a4db94011d3	1425	assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
sahilmgandhi	18:6a4db94011d3	1426
sahilmgandhi	18:6a4db94011d3	1427	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1428	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1429
sahilmgandhi	18:6a4db94011d3	1430	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	1431	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1432
sahilmgandhi	18:6a4db94011d3	1433	/* Configure the CLUT of the background DMA2D layer */
sahilmgandhi	18:6a4db94011d3	1434	if(LayerIdx == 0U)
sahilmgandhi	18:6a4db94011d3	1435	{
sahilmgandhi	18:6a4db94011d3	1436	/* Write background CLUT memory address */
sahilmgandhi	18:6a4db94011d3	1437	WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
sahilmgandhi	18:6a4db94011d3	1438
sahilmgandhi	18:6a4db94011d3	1439	/* Write background CLUT size and CLUT color mode */
sahilmgandhi	18:6a4db94011d3	1440	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS \| DMA2D_BGPFCCR_CCM),
sahilmgandhi	18:6a4db94011d3	1441	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
sahilmgandhi	18:6a4db94011d3	1442	}
sahilmgandhi	18:6a4db94011d3	1443	/* Configure the CLUT of the foreground DMA2D layer */
sahilmgandhi	18:6a4db94011d3	1444	else
sahilmgandhi	18:6a4db94011d3	1445	{
sahilmgandhi	18:6a4db94011d3	1446	/* Write foreground CLUT memory address */
sahilmgandhi	18:6a4db94011d3	1447	WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
sahilmgandhi	18:6a4db94011d3	1448
sahilmgandhi	18:6a4db94011d3	1449	/* Write foreground CLUT size and CLUT color mode */
sahilmgandhi	18:6a4db94011d3	1450	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS \| DMA2D_FGPFCCR_CCM),
sahilmgandhi	18:6a4db94011d3	1451	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
sahilmgandhi	18:6a4db94011d3	1452	}
sahilmgandhi	18:6a4db94011d3	1453
sahilmgandhi	18:6a4db94011d3	1454	/* Set the DMA2D state to Ready */
sahilmgandhi	18:6a4db94011d3	1455	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1456
sahilmgandhi	18:6a4db94011d3	1457	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1458	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1459
sahilmgandhi	18:6a4db94011d3	1460	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1461	}
sahilmgandhi	18:6a4db94011d3	1462
sahilmgandhi	18:6a4db94011d3	1463	/**
sahilmgandhi	18:6a4db94011d3	1464	* @brief Configure the line watermark.
sahilmgandhi	18:6a4db94011d3	1465	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1466	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	1467	* @param Line: Line Watermark configuration (maximum 16-bit long value expected).
sahilmgandhi	18:6a4db94011d3	1468	* @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
sahilmgandhi	18:6a4db94011d3	1469	* @note The transfer watermark interrupt is disabled once it has occurred.
sahilmgandhi	18:6a4db94011d3	1470	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1471	*/
sahilmgandhi	18:6a4db94011d3	1472
sahilmgandhi	18:6a4db94011d3	1473	HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
sahilmgandhi	18:6a4db94011d3	1474	{
sahilmgandhi	18:6a4db94011d3	1475	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1476	assert_param(IS_DMA2D_LINEWATERMARK(Line));
sahilmgandhi	18:6a4db94011d3	1477
sahilmgandhi	18:6a4db94011d3	1478	if (Line > DMA2D_LWR_LW)
sahilmgandhi	18:6a4db94011d3	1479	{
sahilmgandhi	18:6a4db94011d3	1480	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1481	}
sahilmgandhi	18:6a4db94011d3	1482	else
sahilmgandhi	18:6a4db94011d3	1483	{
sahilmgandhi	18:6a4db94011d3	1484	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1485	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1486
sahilmgandhi	18:6a4db94011d3	1487	/* Change DMA2D peripheral state */
sahilmgandhi	18:6a4db94011d3	1488	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1489
sahilmgandhi	18:6a4db94011d3	1490	/* Sets the Line watermark configuration */
sahilmgandhi	18:6a4db94011d3	1491	WRITE_REG(hdma2d->Instance->LWR, Line);
sahilmgandhi	18:6a4db94011d3	1492
sahilmgandhi	18:6a4db94011d3	1493	/* Enable the Line interrupt */
sahilmgandhi	18:6a4db94011d3	1494	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
sahilmgandhi	18:6a4db94011d3	1495
sahilmgandhi	18:6a4db94011d3	1496	/* Initialize the DMA2D state */
sahilmgandhi	18:6a4db94011d3	1497	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1498
sahilmgandhi	18:6a4db94011d3	1499	/* Process unlocked */
sahilmgandhi	18:6a4db94011d3	1500	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1501
sahilmgandhi	18:6a4db94011d3	1502	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1503	}
sahilmgandhi	18:6a4db94011d3	1504	}
sahilmgandhi	18:6a4db94011d3	1505
sahilmgandhi	18:6a4db94011d3	1506	/**
sahilmgandhi	18:6a4db94011d3	1507	* @brief Enable DMA2D dead time feature.
sahilmgandhi	18:6a4db94011d3	1508	* @param hdma2d: DMA2D handle.
sahilmgandhi	18:6a4db94011d3	1509	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1510	*/
sahilmgandhi	18:6a4db94011d3	1511	HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	1512	{
sahilmgandhi	18:6a4db94011d3	1513	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	1514	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1515
sahilmgandhi	18:6a4db94011d3	1516	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1517
sahilmgandhi	18:6a4db94011d3	1518	/* Set DMA2D_AMTCR EN bit */
sahilmgandhi	18:6a4db94011d3	1519	SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
sahilmgandhi	18:6a4db94011d3	1520
sahilmgandhi	18:6a4db94011d3	1521	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1522
sahilmgandhi	18:6a4db94011d3	1523	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1524	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1525
sahilmgandhi	18:6a4db94011d3	1526	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1527	}
sahilmgandhi	18:6a4db94011d3	1528
sahilmgandhi	18:6a4db94011d3	1529	/**
sahilmgandhi	18:6a4db94011d3	1530	* @brief Disable DMA2D dead time feature.
sahilmgandhi	18:6a4db94011d3	1531	* @param hdma2d: DMA2D handle.
sahilmgandhi	18:6a4db94011d3	1532	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1533	*/
sahilmgandhi	18:6a4db94011d3	1534	HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	1535	{
sahilmgandhi	18:6a4db94011d3	1536	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	1537	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1538
sahilmgandhi	18:6a4db94011d3	1539	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1540
sahilmgandhi	18:6a4db94011d3	1541	/* Clear DMA2D_AMTCR EN bit */
sahilmgandhi	18:6a4db94011d3	1542	CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
sahilmgandhi	18:6a4db94011d3	1543
sahilmgandhi	18:6a4db94011d3	1544	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1545
sahilmgandhi	18:6a4db94011d3	1546	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1547	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1548
sahilmgandhi	18:6a4db94011d3	1549	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1550	}
sahilmgandhi	18:6a4db94011d3	1551
sahilmgandhi	18:6a4db94011d3	1552	/**
sahilmgandhi	18:6a4db94011d3	1553	* @brief Configure dead time.
sahilmgandhi	18:6a4db94011d3	1554	* @note The dead time value represents the guaranteed minimum number of cycles between
sahilmgandhi	18:6a4db94011d3	1555	* two consecutive transactions on the AHB bus.
sahilmgandhi	18:6a4db94011d3	1556	* @param hdma2d: DMA2D handle.
sahilmgandhi	18:6a4db94011d3	1557	* @param DeadTime: dead time value.
sahilmgandhi	18:6a4db94011d3	1558	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1559	*/
sahilmgandhi	18:6a4db94011d3	1560	HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
sahilmgandhi	18:6a4db94011d3	1561	{
sahilmgandhi	18:6a4db94011d3	1562	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	1563	__HAL_LOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1564
sahilmgandhi	18:6a4db94011d3	1565	hdma2d->State = HAL_DMA2D_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1566
sahilmgandhi	18:6a4db94011d3	1567	/* Set DMA2D_AMTCR DT field */
sahilmgandhi	18:6a4db94011d3	1568	MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
sahilmgandhi	18:6a4db94011d3	1569
sahilmgandhi	18:6a4db94011d3	1570	hdma2d->State = HAL_DMA2D_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1571
sahilmgandhi	18:6a4db94011d3	1572	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1573	__HAL_UNLOCK(hdma2d);
sahilmgandhi	18:6a4db94011d3	1574
sahilmgandhi	18:6a4db94011d3	1575	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1576	}
sahilmgandhi	18:6a4db94011d3	1577
sahilmgandhi	18:6a4db94011d3	1578	/**
sahilmgandhi	18:6a4db94011d3	1579	* @}
sahilmgandhi	18:6a4db94011d3	1580	*/
sahilmgandhi	18:6a4db94011d3	1581
sahilmgandhi	18:6a4db94011d3	1582	/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
sahilmgandhi	18:6a4db94011d3	1583	* @brief Peripheral State functions
sahilmgandhi	18:6a4db94011d3	1584	*
sahilmgandhi	18:6a4db94011d3	1585	@verbatim
sahilmgandhi	18:6a4db94011d3	1586	===============================================================================
sahilmgandhi	18:6a4db94011d3	1587	##### Peripheral State and Errors functions #####
sahilmgandhi	18:6a4db94011d3	1588	===============================================================================
sahilmgandhi	18:6a4db94011d3	1589	[..]
sahilmgandhi	18:6a4db94011d3	1590	This subsection provides functions allowing to :
sahilmgandhi	18:6a4db94011d3	1591	(+) Get the DMA2D state
sahilmgandhi	18:6a4db94011d3	1592	(+) Get the DMA2D error code
sahilmgandhi	18:6a4db94011d3	1593
sahilmgandhi	18:6a4db94011d3	1594	@endverbatim
sahilmgandhi	18:6a4db94011d3	1595	* @{
sahilmgandhi	18:6a4db94011d3	1596	*/
sahilmgandhi	18:6a4db94011d3	1597
sahilmgandhi	18:6a4db94011d3	1598	/**
sahilmgandhi	18:6a4db94011d3	1599	* @brief Return the DMA2D state
sahilmgandhi	18:6a4db94011d3	1600	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1601	* the configuration information for the DMA2D.
sahilmgandhi	18:6a4db94011d3	1602	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	1603	*/
sahilmgandhi	18:6a4db94011d3	1604	HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	1605	{
sahilmgandhi	18:6a4db94011d3	1606	return hdma2d->State;
sahilmgandhi	18:6a4db94011d3	1607	}
sahilmgandhi	18:6a4db94011d3	1608
sahilmgandhi	18:6a4db94011d3	1609	/**
sahilmgandhi	18:6a4db94011d3	1610	* @brief Return the DMA2D error code
sahilmgandhi	18:6a4db94011d3	1611	* @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1612	* the configuration information for DMA2D.
sahilmgandhi	18:6a4db94011d3	1613	* @retval DMA2D Error Code
sahilmgandhi	18:6a4db94011d3	1614	*/
sahilmgandhi	18:6a4db94011d3	1615	uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
sahilmgandhi	18:6a4db94011d3	1616	{
sahilmgandhi	18:6a4db94011d3	1617	return hdma2d->ErrorCode;
sahilmgandhi	18:6a4db94011d3	1618	}
sahilmgandhi	18:6a4db94011d3	1619
sahilmgandhi	18:6a4db94011d3	1620	/**
sahilmgandhi	18:6a4db94011d3	1621	* @}
sahilmgandhi	18:6a4db94011d3	1622	*/
sahilmgandhi	18:6a4db94011d3	1623
sahilmgandhi	18:6a4db94011d3	1624	/**
sahilmgandhi	18:6a4db94011d3	1625	* @}
sahilmgandhi	18:6a4db94011d3	1626	*/
sahilmgandhi	18:6a4db94011d3	1627
sahilmgandhi	18:6a4db94011d3	1628	/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
sahilmgandhi	18:6a4db94011d3	1629	* @{
sahilmgandhi	18:6a4db94011d3	1630	*/
sahilmgandhi	18:6a4db94011d3	1631
sahilmgandhi	18:6a4db94011d3	1632	/**
sahilmgandhi	18:6a4db94011d3	1633	* @brief Set the DMA2D transfer parameters.
sahilmgandhi	18:6a4db94011d3	1634	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1635	* the configuration information for the specified DMA2D.
sahilmgandhi	18:6a4db94011d3	1636	* @param pdata: The source memory Buffer address
sahilmgandhi	18:6a4db94011d3	1637	* @param DstAddress: The destination memory Buffer address
sahilmgandhi	18:6a4db94011d3	1638	* @param Width: The width of data to be transferred from source to destination.
sahilmgandhi	18:6a4db94011d3	1639	* @param Height: The height of data to be transferred from source to destination.
sahilmgandhi	18:6a4db94011d3	1640	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1641	*/
sahilmgandhi	18:6a4db94011d3	1642	static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
sahilmgandhi	18:6a4db94011d3	1643	{
sahilmgandhi	18:6a4db94011d3	1644	uint32_t tmp = 0U;
sahilmgandhi	18:6a4db94011d3	1645	uint32_t tmp1 = 0U;
sahilmgandhi	18:6a4db94011d3	1646	uint32_t tmp2 = 0U;
sahilmgandhi	18:6a4db94011d3	1647	uint32_t tmp3 = 0U;
sahilmgandhi	18:6a4db94011d3	1648	uint32_t tmp4 = 0U;
sahilmgandhi	18:6a4db94011d3	1649
sahilmgandhi	18:6a4db94011d3	1650	/* Configure DMA2D data size */
sahilmgandhi	18:6a4db94011d3	1651	MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL\|DMA2D_NLR_PL), (Height\| (Width << DMA2D_POSITION_NLR_PL)));
sahilmgandhi	18:6a4db94011d3	1652
sahilmgandhi	18:6a4db94011d3	1653	/* Configure DMA2D destination address */
sahilmgandhi	18:6a4db94011d3	1654	WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
sahilmgandhi	18:6a4db94011d3	1655
sahilmgandhi	18:6a4db94011d3	1656	/* Register to memory DMA2D mode selected */
sahilmgandhi	18:6a4db94011d3	1657	if (hdma2d->Init.Mode == DMA2D_R2M)
sahilmgandhi	18:6a4db94011d3	1658	{
sahilmgandhi	18:6a4db94011d3	1659	tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
sahilmgandhi	18:6a4db94011d3	1660	tmp2 = pdata & DMA2D_OCOLR_RED_1;
sahilmgandhi	18:6a4db94011d3	1661	tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
sahilmgandhi	18:6a4db94011d3	1662	tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
sahilmgandhi	18:6a4db94011d3	1663
sahilmgandhi	18:6a4db94011d3	1664	/* Prepare the value to be written to the OCOLR register according to the color mode */
sahilmgandhi	18:6a4db94011d3	1665	if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
sahilmgandhi	18:6a4db94011d3	1666	{
sahilmgandhi	18:6a4db94011d3	1667	tmp = (tmp3 \| tmp2 \| tmp1\| tmp4);
sahilmgandhi	18:6a4db94011d3	1668	}
sahilmgandhi	18:6a4db94011d3	1669	else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
sahilmgandhi	18:6a4db94011d3	1670	{
sahilmgandhi	18:6a4db94011d3	1671	tmp = (tmp3 \| tmp2 \| tmp4);
sahilmgandhi	18:6a4db94011d3	1672	}
sahilmgandhi	18:6a4db94011d3	1673	else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
sahilmgandhi	18:6a4db94011d3	1674	{
sahilmgandhi	18:6a4db94011d3	1675	tmp2 = (tmp2 >> 19U);
sahilmgandhi	18:6a4db94011d3	1676	tmp3 = (tmp3 >> 10U);
sahilmgandhi	18:6a4db94011d3	1677	tmp4 = (tmp4 >> 3U);
sahilmgandhi	18:6a4db94011d3	1678	tmp = ((tmp3 << 5U) \| (tmp2 << 11U) \| tmp4);
sahilmgandhi	18:6a4db94011d3	1679	}
sahilmgandhi	18:6a4db94011d3	1680	else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
sahilmgandhi	18:6a4db94011d3	1681	{
sahilmgandhi	18:6a4db94011d3	1682	tmp1 = (tmp1 >> 31U);
sahilmgandhi	18:6a4db94011d3	1683	tmp2 = (tmp2 >> 19U);
sahilmgandhi	18:6a4db94011d3	1684	tmp3 = (tmp3 >> 11U);
sahilmgandhi	18:6a4db94011d3	1685	tmp4 = (tmp4 >> 3U);
sahilmgandhi	18:6a4db94011d3	1686	tmp = ((tmp3 << 5U) \| (tmp2 << 10U) \| (tmp1 << 15U) \| tmp4);
sahilmgandhi	18:6a4db94011d3	1687	}
sahilmgandhi	18:6a4db94011d3	1688	else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
sahilmgandhi	18:6a4db94011d3	1689	{
sahilmgandhi	18:6a4db94011d3	1690	tmp1 = (tmp1 >> 28U);
sahilmgandhi	18:6a4db94011d3	1691	tmp2 = (tmp2 >> 20U);
sahilmgandhi	18:6a4db94011d3	1692	tmp3 = (tmp3 >> 12U);
sahilmgandhi	18:6a4db94011d3	1693	tmp4 = (tmp4 >> 4U);
sahilmgandhi	18:6a4db94011d3	1694	tmp = ((tmp3 << 4U) \| (tmp2 << 8U) \| (tmp1 << 12U) \| tmp4);
sahilmgandhi	18:6a4db94011d3	1695	}
sahilmgandhi	18:6a4db94011d3	1696	/* Write to DMA2D OCOLR register */
sahilmgandhi	18:6a4db94011d3	1697	WRITE_REG(hdma2d->Instance->OCOLR, tmp);
sahilmgandhi	18:6a4db94011d3	1698	}
sahilmgandhi	18:6a4db94011d3	1699	else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
sahilmgandhi	18:6a4db94011d3	1700	{
sahilmgandhi	18:6a4db94011d3	1701	/* Configure DMA2D source address */
sahilmgandhi	18:6a4db94011d3	1702	WRITE_REG(hdma2d->Instance->FGMAR, pdata);
sahilmgandhi	18:6a4db94011d3	1703	}
sahilmgandhi	18:6a4db94011d3	1704	}
sahilmgandhi	18:6a4db94011d3	1705
sahilmgandhi	18:6a4db94011d3	1706	/**
sahilmgandhi	18:6a4db94011d3	1707	* @}
sahilmgandhi	18:6a4db94011d3	1708	*/
sahilmgandhi	18:6a4db94011d3	1709	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1710	#endif /* HAL_DMA2D_MODULE_ENABLED */
sahilmgandhi	18:6a4db94011d3	1711	/**
sahilmgandhi	18:6a4db94011d3	1712	* @}
sahilmgandhi	18:6a4db94011d3	1713	*/
sahilmgandhi	18:6a4db94011d3	1714
sahilmgandhi	18:6a4db94011d3	1715	/**
sahilmgandhi	18:6a4db94011d3	1716	* @}
sahilmgandhi	18:6a4db94011d3	1717	*/
sahilmgandhi	18:6a4db94011d3	1718
sahilmgandhi	18:6a4db94011d3	1719	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c@46:b156ef445742, 2017-06-03 (annotated)

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