MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_dma.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of DMA HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F4xx_HAL_DMA_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F4xx_HAL_DMA_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32f4xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** @addtogroup DMA
sahilmgandhi 18:6a4db94011d3 54 * @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /** @defgroup DMA_Exported_Types DMA Exported Types
sahilmgandhi 18:6a4db94011d3 60 * @brief DMA Exported Types
sahilmgandhi 18:6a4db94011d3 61 * @{
sahilmgandhi 18:6a4db94011d3 62 */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /**
sahilmgandhi 18:6a4db94011d3 65 * @brief DMA Configuration Structure definition
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67 typedef struct
sahilmgandhi 18:6a4db94011d3 68 {
sahilmgandhi 18:6a4db94011d3 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
sahilmgandhi 18:6a4db94011d3 70 This parameter can be a value of @ref DMA_Channel_selection */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
sahilmgandhi 18:6a4db94011d3 73 from memory to memory or from peripheral to memory.
sahilmgandhi 18:6a4db94011d3 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
sahilmgandhi 18:6a4db94011d3 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
sahilmgandhi 18:6a4db94011d3 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
sahilmgandhi 18:6a4db94011d3 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
sahilmgandhi 18:6a4db94011d3 86 This parameter can be a value of @ref DMA_Memory_data_size */
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
sahilmgandhi 18:6a4db94011d3 89 This parameter can be a value of @ref DMA_mode
sahilmgandhi 18:6a4db94011d3 90 @note The circular buffer mode cannot be used if the memory-to-memory
sahilmgandhi 18:6a4db94011d3 91 data transfer is configured on the selected Stream */
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
sahilmgandhi 18:6a4db94011d3 94 This parameter can be a value of @ref DMA_Priority_level */
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
sahilmgandhi 18:6a4db94011d3 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
sahilmgandhi 18:6a4db94011d3 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
sahilmgandhi 18:6a4db94011d3 99 memory-to-memory data transfer is configured on the selected stream */
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
sahilmgandhi 18:6a4db94011d3 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
sahilmgandhi 18:6a4db94011d3 105 It specifies the amount of data to be transferred in a single non interruptible
sahilmgandhi 18:6a4db94011d3 106 transaction.
sahilmgandhi 18:6a4db94011d3 107 This parameter can be a value of @ref DMA_Memory_burst
sahilmgandhi 18:6a4db94011d3 108 @note The burst mode is possible only if the address Increment mode is enabled. */
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
sahilmgandhi 18:6a4db94011d3 111 It specifies the amount of data to be transferred in a single non interruptible
sahilmgandhi 18:6a4db94011d3 112 transaction.
sahilmgandhi 18:6a4db94011d3 113 This parameter can be a value of @ref DMA_Peripheral_burst
sahilmgandhi 18:6a4db94011d3 114 @note The burst mode is possible only if the address Increment mode is enabled. */
sahilmgandhi 18:6a4db94011d3 115 }DMA_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /**
sahilmgandhi 18:6a4db94011d3 119 * @brief HAL DMA State structures definition
sahilmgandhi 18:6a4db94011d3 120 */
sahilmgandhi 18:6a4db94011d3 121 typedef enum
sahilmgandhi 18:6a4db94011d3 122 {
sahilmgandhi 18:6a4db94011d3 123 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
sahilmgandhi 18:6a4db94011d3 124 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
sahilmgandhi 18:6a4db94011d3 125 HAL_DMA_STATE_READY_MEM0 = 0x11U, /*!< DMA Mem0 process success */ // FIX
sahilmgandhi 18:6a4db94011d3 126 HAL_DMA_STATE_READY_MEM1 = 0x21U, /*!< DMA Mem1 process success */ // FIX
sahilmgandhi 18:6a4db94011d3 127 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31U, /*!< DMA Mem0 Half process success */ // FIX
sahilmgandhi 18:6a4db94011d3 128 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41U, /*!< DMA Mem1 Half process success */ // FIX
sahilmgandhi 18:6a4db94011d3 129 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
sahilmgandhi 18:6a4db94011d3 130 HAL_DMA_STATE_BUSY_MEM0 = 0x12U, /*!< DMA Mem0 process is ongoing */ // FIX
sahilmgandhi 18:6a4db94011d3 131 HAL_DMA_STATE_BUSY_MEM1 = 0x22U, /*!< DMA Mem1 process is ongoing */ // FIX
sahilmgandhi 18:6a4db94011d3 132 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
sahilmgandhi 18:6a4db94011d3 133 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
sahilmgandhi 18:6a4db94011d3 134 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
sahilmgandhi 18:6a4db94011d3 135 }HAL_DMA_StateTypeDef;
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 /**
sahilmgandhi 18:6a4db94011d3 138 * @brief HAL DMA Error Code structure definition
sahilmgandhi 18:6a4db94011d3 139 */
sahilmgandhi 18:6a4db94011d3 140 typedef enum
sahilmgandhi 18:6a4db94011d3 141 {
sahilmgandhi 18:6a4db94011d3 142 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
sahilmgandhi 18:6a4db94011d3 143 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
sahilmgandhi 18:6a4db94011d3 144 }HAL_DMA_LevelCompleteTypeDef;
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /**
sahilmgandhi 18:6a4db94011d3 147 * @brief HAL DMA Error Code structure definition
sahilmgandhi 18:6a4db94011d3 148 */
sahilmgandhi 18:6a4db94011d3 149 typedef enum
sahilmgandhi 18:6a4db94011d3 150 {
sahilmgandhi 18:6a4db94011d3 151 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
sahilmgandhi 18:6a4db94011d3 152 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
sahilmgandhi 18:6a4db94011d3 153 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
sahilmgandhi 18:6a4db94011d3 154 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
sahilmgandhi 18:6a4db94011d3 155 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
sahilmgandhi 18:6a4db94011d3 156 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
sahilmgandhi 18:6a4db94011d3 157 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
sahilmgandhi 18:6a4db94011d3 158 }HAL_DMA_CallbackIDTypeDef;
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /**
sahilmgandhi 18:6a4db94011d3 161 * @brief DMA handle Structure definition
sahilmgandhi 18:6a4db94011d3 162 */
sahilmgandhi 18:6a4db94011d3 163 typedef struct __DMA_HandleTypeDef
sahilmgandhi 18:6a4db94011d3 164 {
sahilmgandhi 18:6a4db94011d3 165 DMA_Stream_TypeDef *Instance; /*!< Register base address */
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 DMA_InitTypeDef Init; /*!< DMA communication parameters */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 HAL_LockTypeDef Lock; /*!< DMA locking object */
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 void *Parent; /*!< Parent object state */
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 __IO uint32_t ErrorCode; /*!< DMA Error code */
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 uint32_t StreamIndex; /*!< DMA Stream Index */
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 }DMA_HandleTypeDef;
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 /**
sahilmgandhi 18:6a4db94011d3 196 * @}
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 /** @defgroup DMA_Exported_Constants DMA Exported Constants
sahilmgandhi 18:6a4db94011d3 202 * @brief DMA Exported constants
sahilmgandhi 18:6a4db94011d3 203 * @{
sahilmgandhi 18:6a4db94011d3 204 */
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 /** @defgroup DMA_Error_Code DMA Error Code
sahilmgandhi 18:6a4db94011d3 207 * @brief DMA Error Code
sahilmgandhi 18:6a4db94011d3 208 * @{
sahilmgandhi 18:6a4db94011d3 209 */
sahilmgandhi 18:6a4db94011d3 210 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
sahilmgandhi 18:6a4db94011d3 211 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
sahilmgandhi 18:6a4db94011d3 212 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
sahilmgandhi 18:6a4db94011d3 213 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
sahilmgandhi 18:6a4db94011d3 214 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
sahilmgandhi 18:6a4db94011d3 215 #define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
sahilmgandhi 18:6a4db94011d3 216 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
sahilmgandhi 18:6a4db94011d3 217 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
sahilmgandhi 18:6a4db94011d3 218 /**
sahilmgandhi 18:6a4db94011d3 219 * @}
sahilmgandhi 18:6a4db94011d3 220 */
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 /** @defgroup DMA_Channel_selection DMA Channel selection
sahilmgandhi 18:6a4db94011d3 223 * @brief DMA channel selection
sahilmgandhi 18:6a4db94011d3 224 * @{
sahilmgandhi 18:6a4db94011d3 225 */
sahilmgandhi 18:6a4db94011d3 226 #define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
sahilmgandhi 18:6a4db94011d3 227 #define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
sahilmgandhi 18:6a4db94011d3 228 #define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
sahilmgandhi 18:6a4db94011d3 229 #define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
sahilmgandhi 18:6a4db94011d3 230 #define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
sahilmgandhi 18:6a4db94011d3 231 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
sahilmgandhi 18:6a4db94011d3 232 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
sahilmgandhi 18:6a4db94011d3 233 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
sahilmgandhi 18:6a4db94011d3 234 /**
sahilmgandhi 18:6a4db94011d3 235 * @}
sahilmgandhi 18:6a4db94011d3 236 */
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
sahilmgandhi 18:6a4db94011d3 239 * @brief DMA data transfer direction
sahilmgandhi 18:6a4db94011d3 240 * @{
sahilmgandhi 18:6a4db94011d3 241 */
sahilmgandhi 18:6a4db94011d3 242 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
sahilmgandhi 18:6a4db94011d3 243 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
sahilmgandhi 18:6a4db94011d3 244 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
sahilmgandhi 18:6a4db94011d3 245 /**
sahilmgandhi 18:6a4db94011d3 246 * @}
sahilmgandhi 18:6a4db94011d3 247 */
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
sahilmgandhi 18:6a4db94011d3 250 * @brief DMA peripheral incremented mode
sahilmgandhi 18:6a4db94011d3 251 * @{
sahilmgandhi 18:6a4db94011d3 252 */
sahilmgandhi 18:6a4db94011d3 253 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
sahilmgandhi 18:6a4db94011d3 254 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
sahilmgandhi 18:6a4db94011d3 255 /**
sahilmgandhi 18:6a4db94011d3 256 * @}
sahilmgandhi 18:6a4db94011d3 257 */
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
sahilmgandhi 18:6a4db94011d3 260 * @brief DMA memory incremented mode
sahilmgandhi 18:6a4db94011d3 261 * @{
sahilmgandhi 18:6a4db94011d3 262 */
sahilmgandhi 18:6a4db94011d3 263 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
sahilmgandhi 18:6a4db94011d3 264 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
sahilmgandhi 18:6a4db94011d3 265 /**
sahilmgandhi 18:6a4db94011d3 266 * @}
sahilmgandhi 18:6a4db94011d3 267 */
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
sahilmgandhi 18:6a4db94011d3 270 * @brief DMA peripheral data size
sahilmgandhi 18:6a4db94011d3 271 * @{
sahilmgandhi 18:6a4db94011d3 272 */
sahilmgandhi 18:6a4db94011d3 273 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
sahilmgandhi 18:6a4db94011d3 274 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
sahilmgandhi 18:6a4db94011d3 275 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
sahilmgandhi 18:6a4db94011d3 276 /**
sahilmgandhi 18:6a4db94011d3 277 * @}
sahilmgandhi 18:6a4db94011d3 278 */
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 /** @defgroup DMA_Memory_data_size DMA Memory data size
sahilmgandhi 18:6a4db94011d3 281 * @brief DMA memory data size
sahilmgandhi 18:6a4db94011d3 282 * @{
sahilmgandhi 18:6a4db94011d3 283 */
sahilmgandhi 18:6a4db94011d3 284 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
sahilmgandhi 18:6a4db94011d3 285 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
sahilmgandhi 18:6a4db94011d3 286 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
sahilmgandhi 18:6a4db94011d3 287 /**
sahilmgandhi 18:6a4db94011d3 288 * @}
sahilmgandhi 18:6a4db94011d3 289 */
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /** @defgroup DMA_mode DMA mode
sahilmgandhi 18:6a4db94011d3 292 * @brief DMA mode
sahilmgandhi 18:6a4db94011d3 293 * @{
sahilmgandhi 18:6a4db94011d3 294 */
sahilmgandhi 18:6a4db94011d3 295 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
sahilmgandhi 18:6a4db94011d3 296 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
sahilmgandhi 18:6a4db94011d3 297 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
sahilmgandhi 18:6a4db94011d3 298 /**
sahilmgandhi 18:6a4db94011d3 299 * @}
sahilmgandhi 18:6a4db94011d3 300 */
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 /** @defgroup DMA_Priority_level DMA Priority level
sahilmgandhi 18:6a4db94011d3 303 * @brief DMA priority levels
sahilmgandhi 18:6a4db94011d3 304 * @{
sahilmgandhi 18:6a4db94011d3 305 */
sahilmgandhi 18:6a4db94011d3 306 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
sahilmgandhi 18:6a4db94011d3 307 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
sahilmgandhi 18:6a4db94011d3 308 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
sahilmgandhi 18:6a4db94011d3 309 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
sahilmgandhi 18:6a4db94011d3 310 /**
sahilmgandhi 18:6a4db94011d3 311 * @}
sahilmgandhi 18:6a4db94011d3 312 */
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
sahilmgandhi 18:6a4db94011d3 315 * @brief DMA FIFO direct mode
sahilmgandhi 18:6a4db94011d3 316 * @{
sahilmgandhi 18:6a4db94011d3 317 */
sahilmgandhi 18:6a4db94011d3 318 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
sahilmgandhi 18:6a4db94011d3 319 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
sahilmgandhi 18:6a4db94011d3 320 /**
sahilmgandhi 18:6a4db94011d3 321 * @}
sahilmgandhi 18:6a4db94011d3 322 */
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
sahilmgandhi 18:6a4db94011d3 325 * @brief DMA FIFO level
sahilmgandhi 18:6a4db94011d3 326 * @{
sahilmgandhi 18:6a4db94011d3 327 */
sahilmgandhi 18:6a4db94011d3 328 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
sahilmgandhi 18:6a4db94011d3 329 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
sahilmgandhi 18:6a4db94011d3 330 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
sahilmgandhi 18:6a4db94011d3 331 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
sahilmgandhi 18:6a4db94011d3 332 /**
sahilmgandhi 18:6a4db94011d3 333 * @}
sahilmgandhi 18:6a4db94011d3 334 */
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 /** @defgroup DMA_Memory_burst DMA Memory burst
sahilmgandhi 18:6a4db94011d3 337 * @brief DMA memory burst
sahilmgandhi 18:6a4db94011d3 338 * @{
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 341 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
sahilmgandhi 18:6a4db94011d3 342 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
sahilmgandhi 18:6a4db94011d3 343 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
sahilmgandhi 18:6a4db94011d3 344 /**
sahilmgandhi 18:6a4db94011d3 345 * @}
sahilmgandhi 18:6a4db94011d3 346 */
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
sahilmgandhi 18:6a4db94011d3 349 * @brief DMA peripheral burst
sahilmgandhi 18:6a4db94011d3 350 * @{
sahilmgandhi 18:6a4db94011d3 351 */
sahilmgandhi 18:6a4db94011d3 352 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 353 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
sahilmgandhi 18:6a4db94011d3 354 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
sahilmgandhi 18:6a4db94011d3 355 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
sahilmgandhi 18:6a4db94011d3 356 /**
sahilmgandhi 18:6a4db94011d3 357 * @}
sahilmgandhi 18:6a4db94011d3 358 */
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
sahilmgandhi 18:6a4db94011d3 361 * @brief DMA interrupts definition
sahilmgandhi 18:6a4db94011d3 362 * @{
sahilmgandhi 18:6a4db94011d3 363 */
sahilmgandhi 18:6a4db94011d3 364 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
sahilmgandhi 18:6a4db94011d3 365 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
sahilmgandhi 18:6a4db94011d3 366 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
sahilmgandhi 18:6a4db94011d3 367 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
sahilmgandhi 18:6a4db94011d3 368 #define DMA_IT_FE ((uint32_t)0x00000080U)
sahilmgandhi 18:6a4db94011d3 369 /**
sahilmgandhi 18:6a4db94011d3 370 * @}
sahilmgandhi 18:6a4db94011d3 371 */
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /** @defgroup DMA_flag_definitions DMA flag definitions
sahilmgandhi 18:6a4db94011d3 374 * @brief DMA flag definitions
sahilmgandhi 18:6a4db94011d3 375 * @{
sahilmgandhi 18:6a4db94011d3 376 */
sahilmgandhi 18:6a4db94011d3 377 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
sahilmgandhi 18:6a4db94011d3 378 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
sahilmgandhi 18:6a4db94011d3 379 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
sahilmgandhi 18:6a4db94011d3 380 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
sahilmgandhi 18:6a4db94011d3 381 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
sahilmgandhi 18:6a4db94011d3 382 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
sahilmgandhi 18:6a4db94011d3 383 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
sahilmgandhi 18:6a4db94011d3 384 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
sahilmgandhi 18:6a4db94011d3 385 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
sahilmgandhi 18:6a4db94011d3 386 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
sahilmgandhi 18:6a4db94011d3 387 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
sahilmgandhi 18:6a4db94011d3 388 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
sahilmgandhi 18:6a4db94011d3 389 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
sahilmgandhi 18:6a4db94011d3 390 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
sahilmgandhi 18:6a4db94011d3 391 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
sahilmgandhi 18:6a4db94011d3 392 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
sahilmgandhi 18:6a4db94011d3 393 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
sahilmgandhi 18:6a4db94011d3 394 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
sahilmgandhi 18:6a4db94011d3 395 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
sahilmgandhi 18:6a4db94011d3 396 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
sahilmgandhi 18:6a4db94011d3 397 /**
sahilmgandhi 18:6a4db94011d3 398 * @}
sahilmgandhi 18:6a4db94011d3 399 */
sahilmgandhi 18:6a4db94011d3 400
sahilmgandhi 18:6a4db94011d3 401 /**
sahilmgandhi 18:6a4db94011d3 402 * @}
sahilmgandhi 18:6a4db94011d3 403 */
sahilmgandhi 18:6a4db94011d3 404
sahilmgandhi 18:6a4db94011d3 405 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /** @brief Reset DMA handle state
sahilmgandhi 18:6a4db94011d3 408 * @param __HANDLE__: specifies the DMA handle.
sahilmgandhi 18:6a4db94011d3 409 * @retval None
sahilmgandhi 18:6a4db94011d3 410 */
sahilmgandhi 18:6a4db94011d3 411 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 /**
sahilmgandhi 18:6a4db94011d3 414 * @brief Return the current DMA Stream FIFO filled level.
sahilmgandhi 18:6a4db94011d3 415 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 416 * @retval The FIFO filling state.
sahilmgandhi 18:6a4db94011d3 417 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
sahilmgandhi 18:6a4db94011d3 418 * and not empty.
sahilmgandhi 18:6a4db94011d3 419 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
sahilmgandhi 18:6a4db94011d3 420 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
sahilmgandhi 18:6a4db94011d3 421 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
sahilmgandhi 18:6a4db94011d3 422 * - DMA_FIFOStatus_Empty: when FIFO is empty
sahilmgandhi 18:6a4db94011d3 423 * - DMA_FIFOStatus_Full: when FIFO is full
sahilmgandhi 18:6a4db94011d3 424 */
sahilmgandhi 18:6a4db94011d3 425 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 /**
sahilmgandhi 18:6a4db94011d3 428 * @brief Enable the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 429 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 430 * @retval None
sahilmgandhi 18:6a4db94011d3 431 */
sahilmgandhi 18:6a4db94011d3 432 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 /**
sahilmgandhi 18:6a4db94011d3 435 * @brief Disable the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 436 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 437 * @retval None
sahilmgandhi 18:6a4db94011d3 438 */
sahilmgandhi 18:6a4db94011d3 439 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441 /* Interrupt & Flag management */
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 /**
sahilmgandhi 18:6a4db94011d3 444 * @brief Return the current DMA Stream transfer complete flag.
sahilmgandhi 18:6a4db94011d3 445 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 446 * @retval The specified transfer complete flag index.
sahilmgandhi 18:6a4db94011d3 447 */
sahilmgandhi 18:6a4db94011d3 448 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
sahilmgandhi 18:6a4db94011d3 449 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
sahilmgandhi 18:6a4db94011d3 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
sahilmgandhi 18:6a4db94011d3 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
sahilmgandhi 18:6a4db94011d3 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
sahilmgandhi 18:6a4db94011d3 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
sahilmgandhi 18:6a4db94011d3 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
sahilmgandhi 18:6a4db94011d3 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
sahilmgandhi 18:6a4db94011d3 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
sahilmgandhi 18:6a4db94011d3 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
sahilmgandhi 18:6a4db94011d3 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
sahilmgandhi 18:6a4db94011d3 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
sahilmgandhi 18:6a4db94011d3 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
sahilmgandhi 18:6a4db94011d3 461 DMA_FLAG_TCIF3_7)
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 /**
sahilmgandhi 18:6a4db94011d3 464 * @brief Return the current DMA Stream half transfer complete flag.
sahilmgandhi 18:6a4db94011d3 465 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 466 * @retval The specified half transfer complete flag index.
sahilmgandhi 18:6a4db94011d3 467 */
sahilmgandhi 18:6a4db94011d3 468 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
sahilmgandhi 18:6a4db94011d3 469 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
sahilmgandhi 18:6a4db94011d3 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
sahilmgandhi 18:6a4db94011d3 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
sahilmgandhi 18:6a4db94011d3 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
sahilmgandhi 18:6a4db94011d3 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
sahilmgandhi 18:6a4db94011d3 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
sahilmgandhi 18:6a4db94011d3 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
sahilmgandhi 18:6a4db94011d3 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
sahilmgandhi 18:6a4db94011d3 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
sahilmgandhi 18:6a4db94011d3 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
sahilmgandhi 18:6a4db94011d3 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
sahilmgandhi 18:6a4db94011d3 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
sahilmgandhi 18:6a4db94011d3 481 DMA_FLAG_HTIF3_7)
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 /**
sahilmgandhi 18:6a4db94011d3 484 * @brief Return the current DMA Stream transfer error flag.
sahilmgandhi 18:6a4db94011d3 485 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 486 * @retval The specified transfer error flag index.
sahilmgandhi 18:6a4db94011d3 487 */
sahilmgandhi 18:6a4db94011d3 488 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
sahilmgandhi 18:6a4db94011d3 489 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 501 DMA_FLAG_TEIF3_7)
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 /**
sahilmgandhi 18:6a4db94011d3 504 * @brief Return the current DMA Stream FIFO error flag.
sahilmgandhi 18:6a4db94011d3 505 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 506 * @retval The specified FIFO error flag index.
sahilmgandhi 18:6a4db94011d3 507 */
sahilmgandhi 18:6a4db94011d3 508 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
sahilmgandhi 18:6a4db94011d3 509 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 521 DMA_FLAG_FEIF3_7)
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 /**
sahilmgandhi 18:6a4db94011d3 524 * @brief Return the current DMA Stream direct mode error flag.
sahilmgandhi 18:6a4db94011d3 525 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 526 * @retval The specified direct mode error flag index.
sahilmgandhi 18:6a4db94011d3 527 */
sahilmgandhi 18:6a4db94011d3 528 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
sahilmgandhi 18:6a4db94011d3 529 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
sahilmgandhi 18:6a4db94011d3 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
sahilmgandhi 18:6a4db94011d3 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
sahilmgandhi 18:6a4db94011d3 541 DMA_FLAG_DMEIF3_7)
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 /**
sahilmgandhi 18:6a4db94011d3 544 * @brief Get the DMA Stream pending flags.
sahilmgandhi 18:6a4db94011d3 545 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 546 * @param __FLAG__: Get the specified flag.
sahilmgandhi 18:6a4db94011d3 547 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 548 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
sahilmgandhi 18:6a4db94011d3 549 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
sahilmgandhi 18:6a4db94011d3 550 * @arg DMA_FLAG_TEIFx: Transfer error flag.
sahilmgandhi 18:6a4db94011d3 551 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
sahilmgandhi 18:6a4db94011d3 552 * @arg DMA_FLAG_FEIFx: FIFO error flag.
sahilmgandhi 18:6a4db94011d3 553 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
sahilmgandhi 18:6a4db94011d3 554 * @retval The state of FLAG (SET or RESET).
sahilmgandhi 18:6a4db94011d3 555 */
sahilmgandhi 18:6a4db94011d3 556 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
sahilmgandhi 18:6a4db94011d3 557 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
sahilmgandhi 18:6a4db94011d3 558 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
sahilmgandhi 18:6a4db94011d3 559 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 /**
sahilmgandhi 18:6a4db94011d3 562 * @brief Clear the DMA Stream pending flags.
sahilmgandhi 18:6a4db94011d3 563 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 564 * @param __FLAG__: specifies the flag to clear.
sahilmgandhi 18:6a4db94011d3 565 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 566 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
sahilmgandhi 18:6a4db94011d3 567 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
sahilmgandhi 18:6a4db94011d3 568 * @arg DMA_FLAG_TEIFx: Transfer error flag.
sahilmgandhi 18:6a4db94011d3 569 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
sahilmgandhi 18:6a4db94011d3 570 * @arg DMA_FLAG_FEIFx: FIFO error flag.
sahilmgandhi 18:6a4db94011d3 571 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
sahilmgandhi 18:6a4db94011d3 572 * @retval None
sahilmgandhi 18:6a4db94011d3 573 */
sahilmgandhi 18:6a4db94011d3 574 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
sahilmgandhi 18:6a4db94011d3 575 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
sahilmgandhi 18:6a4db94011d3 576 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
sahilmgandhi 18:6a4db94011d3 577 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
sahilmgandhi 18:6a4db94011d3 578
sahilmgandhi 18:6a4db94011d3 579 /**
sahilmgandhi 18:6a4db94011d3 580 * @brief Enable the specified DMA Stream interrupts.
sahilmgandhi 18:6a4db94011d3 581 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 582 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
sahilmgandhi 18:6a4db94011d3 583 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 584 * @arg DMA_IT_TC: Transfer complete interrupt mask.
sahilmgandhi 18:6a4db94011d3 585 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
sahilmgandhi 18:6a4db94011d3 586 * @arg DMA_IT_TE: Transfer error interrupt mask.
sahilmgandhi 18:6a4db94011d3 587 * @arg DMA_IT_FE: FIFO error interrupt mask.
sahilmgandhi 18:6a4db94011d3 588 * @arg DMA_IT_DME: Direct mode error interrupt.
sahilmgandhi 18:6a4db94011d3 589 * @retval None
sahilmgandhi 18:6a4db94011d3 590 */
sahilmgandhi 18:6a4db94011d3 591 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
sahilmgandhi 18:6a4db94011d3 592 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 /**
sahilmgandhi 18:6a4db94011d3 595 * @brief Disable the specified DMA Stream interrupts.
sahilmgandhi 18:6a4db94011d3 596 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 597 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
sahilmgandhi 18:6a4db94011d3 598 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 599 * @arg DMA_IT_TC: Transfer complete interrupt mask.
sahilmgandhi 18:6a4db94011d3 600 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
sahilmgandhi 18:6a4db94011d3 601 * @arg DMA_IT_TE: Transfer error interrupt mask.
sahilmgandhi 18:6a4db94011d3 602 * @arg DMA_IT_FE: FIFO error interrupt mask.
sahilmgandhi 18:6a4db94011d3 603 * @arg DMA_IT_DME: Direct mode error interrupt.
sahilmgandhi 18:6a4db94011d3 604 * @retval None
sahilmgandhi 18:6a4db94011d3 605 */
sahilmgandhi 18:6a4db94011d3 606 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
sahilmgandhi 18:6a4db94011d3 607 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
sahilmgandhi 18:6a4db94011d3 608
sahilmgandhi 18:6a4db94011d3 609 /**
sahilmgandhi 18:6a4db94011d3 610 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
sahilmgandhi 18:6a4db94011d3 611 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 612 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
sahilmgandhi 18:6a4db94011d3 613 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 614 * @arg DMA_IT_TC: Transfer complete interrupt mask.
sahilmgandhi 18:6a4db94011d3 615 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
sahilmgandhi 18:6a4db94011d3 616 * @arg DMA_IT_TE: Transfer error interrupt mask.
sahilmgandhi 18:6a4db94011d3 617 * @arg DMA_IT_FE: FIFO error interrupt mask.
sahilmgandhi 18:6a4db94011d3 618 * @arg DMA_IT_DME: Direct mode error interrupt.
sahilmgandhi 18:6a4db94011d3 619 * @retval The state of DMA_IT.
sahilmgandhi 18:6a4db94011d3 620 */
sahilmgandhi 18:6a4db94011d3 621 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
sahilmgandhi 18:6a4db94011d3 622 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
sahilmgandhi 18:6a4db94011d3 623 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
sahilmgandhi 18:6a4db94011d3 624
sahilmgandhi 18:6a4db94011d3 625 /**
sahilmgandhi 18:6a4db94011d3 626 * @brief Writes the number of data units to be transferred on the DMA Stream.
sahilmgandhi 18:6a4db94011d3 627 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 628 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
sahilmgandhi 18:6a4db94011d3 629 * Number of data items depends only on the Peripheral data format.
sahilmgandhi 18:6a4db94011d3 630 *
sahilmgandhi 18:6a4db94011d3 631 * @note If Peripheral data format is Bytes: number of data units is equal
sahilmgandhi 18:6a4db94011d3 632 * to total number of bytes to be transferred.
sahilmgandhi 18:6a4db94011d3 633 *
sahilmgandhi 18:6a4db94011d3 634 * @note If Peripheral data format is Half-Word: number of data units is
sahilmgandhi 18:6a4db94011d3 635 * equal to total number of bytes to be transferred / 2.
sahilmgandhi 18:6a4db94011d3 636 *
sahilmgandhi 18:6a4db94011d3 637 * @note If Peripheral data format is Word: number of data units is equal
sahilmgandhi 18:6a4db94011d3 638 * to total number of bytes to be transferred / 4.
sahilmgandhi 18:6a4db94011d3 639 *
sahilmgandhi 18:6a4db94011d3 640 * @retval The number of remaining data units in the current DMAy Streamx transfer.
sahilmgandhi 18:6a4db94011d3 641 */
sahilmgandhi 18:6a4db94011d3 642 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
sahilmgandhi 18:6a4db94011d3 643
sahilmgandhi 18:6a4db94011d3 644 /**
sahilmgandhi 18:6a4db94011d3 645 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
sahilmgandhi 18:6a4db94011d3 646 * @param __HANDLE__: DMA handle
sahilmgandhi 18:6a4db94011d3 647 *
sahilmgandhi 18:6a4db94011d3 648 * @retval The number of remaining data units in the current DMA Stream transfer.
sahilmgandhi 18:6a4db94011d3 649 */
sahilmgandhi 18:6a4db94011d3 650 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652
sahilmgandhi 18:6a4db94011d3 653 /* Include DMA HAL Extension module */
sahilmgandhi 18:6a4db94011d3 654 #include "stm32f4xx_hal_dma_ex.h"
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 /** @defgroup DMA_Exported_Functions DMA Exported Functions
sahilmgandhi 18:6a4db94011d3 659 * @brief DMA Exported functions
sahilmgandhi 18:6a4db94011d3 660 * @{
sahilmgandhi 18:6a4db94011d3 661 */
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 664 * @brief Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 665 * @{
sahilmgandhi 18:6a4db94011d3 666 */
sahilmgandhi 18:6a4db94011d3 667 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 668 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 669 /**
sahilmgandhi 18:6a4db94011d3 670 * @}
sahilmgandhi 18:6a4db94011d3 671 */
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
sahilmgandhi 18:6a4db94011d3 674 * @brief I/O operation functions
sahilmgandhi 18:6a4db94011d3 675 * @{
sahilmgandhi 18:6a4db94011d3 676 */
sahilmgandhi 18:6a4db94011d3 677 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
sahilmgandhi 18:6a4db94011d3 678 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
sahilmgandhi 18:6a4db94011d3 679 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 680 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 681 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 682 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 683 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 684 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
sahilmgandhi 18:6a4db94011d3 685 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
sahilmgandhi 18:6a4db94011d3 686
sahilmgandhi 18:6a4db94011d3 687 /**
sahilmgandhi 18:6a4db94011d3 688 * @}
sahilmgandhi 18:6a4db94011d3 689 */
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
sahilmgandhi 18:6a4db94011d3 692 * @brief Peripheral State functions
sahilmgandhi 18:6a4db94011d3 693 * @{
sahilmgandhi 18:6a4db94011d3 694 */
sahilmgandhi 18:6a4db94011d3 695 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 696 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 697 /**
sahilmgandhi 18:6a4db94011d3 698 * @}
sahilmgandhi 18:6a4db94011d3 699 */
sahilmgandhi 18:6a4db94011d3 700 /**
sahilmgandhi 18:6a4db94011d3 701 * @}
sahilmgandhi 18:6a4db94011d3 702 */
sahilmgandhi 18:6a4db94011d3 703 /* Private Constants -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 704 /** @defgroup DMA_Private_Constants DMA Private Constants
sahilmgandhi 18:6a4db94011d3 705 * @brief DMA private defines and constants
sahilmgandhi 18:6a4db94011d3 706 * @{
sahilmgandhi 18:6a4db94011d3 707 */
sahilmgandhi 18:6a4db94011d3 708 /**
sahilmgandhi 18:6a4db94011d3 709 * @}
sahilmgandhi 18:6a4db94011d3 710 */
sahilmgandhi 18:6a4db94011d3 711
sahilmgandhi 18:6a4db94011d3 712 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 713 /** @defgroup DMA_Private_Macros DMA Private Macros
sahilmgandhi 18:6a4db94011d3 714 * @brief DMA private macros
sahilmgandhi 18:6a4db94011d3 715 * @{
sahilmgandhi 18:6a4db94011d3 716 */
sahilmgandhi 18:6a4db94011d3 717 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
sahilmgandhi 18:6a4db94011d3 718 ((CHANNEL) == DMA_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 719 ((CHANNEL) == DMA_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 720 ((CHANNEL) == DMA_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 721 ((CHANNEL) == DMA_CHANNEL_4) || \
sahilmgandhi 18:6a4db94011d3 722 ((CHANNEL) == DMA_CHANNEL_5) || \
sahilmgandhi 18:6a4db94011d3 723 ((CHANNEL) == DMA_CHANNEL_6) || \
sahilmgandhi 18:6a4db94011d3 724 ((CHANNEL) == DMA_CHANNEL_7))
sahilmgandhi 18:6a4db94011d3 725
sahilmgandhi 18:6a4db94011d3 726 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
sahilmgandhi 18:6a4db94011d3 727 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
sahilmgandhi 18:6a4db94011d3 728 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
sahilmgandhi 18:6a4db94011d3 729
sahilmgandhi 18:6a4db94011d3 730 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
sahilmgandhi 18:6a4db94011d3 733 ((STATE) == DMA_PINC_DISABLE))
sahilmgandhi 18:6a4db94011d3 734
sahilmgandhi 18:6a4db94011d3 735 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
sahilmgandhi 18:6a4db94011d3 736 ((STATE) == DMA_MINC_DISABLE))
sahilmgandhi 18:6a4db94011d3 737
sahilmgandhi 18:6a4db94011d3 738 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
sahilmgandhi 18:6a4db94011d3 739 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
sahilmgandhi 18:6a4db94011d3 740 ((SIZE) == DMA_PDATAALIGN_WORD))
sahilmgandhi 18:6a4db94011d3 741
sahilmgandhi 18:6a4db94011d3 742 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
sahilmgandhi 18:6a4db94011d3 743 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
sahilmgandhi 18:6a4db94011d3 744 ((SIZE) == DMA_MDATAALIGN_WORD ))
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
sahilmgandhi 18:6a4db94011d3 747 ((MODE) == DMA_CIRCULAR) || \
sahilmgandhi 18:6a4db94011d3 748 ((MODE) == DMA_PFCTRL))
sahilmgandhi 18:6a4db94011d3 749
sahilmgandhi 18:6a4db94011d3 750 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
sahilmgandhi 18:6a4db94011d3 751 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
sahilmgandhi 18:6a4db94011d3 752 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
sahilmgandhi 18:6a4db94011d3 753 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
sahilmgandhi 18:6a4db94011d3 756 ((STATE) == DMA_FIFOMODE_ENABLE))
sahilmgandhi 18:6a4db94011d3 757
sahilmgandhi 18:6a4db94011d3 758 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
sahilmgandhi 18:6a4db94011d3 759 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
sahilmgandhi 18:6a4db94011d3 760 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
sahilmgandhi 18:6a4db94011d3 761 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
sahilmgandhi 18:6a4db94011d3 764 ((BURST) == DMA_MBURST_INC4) || \
sahilmgandhi 18:6a4db94011d3 765 ((BURST) == DMA_MBURST_INC8) || \
sahilmgandhi 18:6a4db94011d3 766 ((BURST) == DMA_MBURST_INC16))
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
sahilmgandhi 18:6a4db94011d3 769 ((BURST) == DMA_PBURST_INC4) || \
sahilmgandhi 18:6a4db94011d3 770 ((BURST) == DMA_PBURST_INC8) || \
sahilmgandhi 18:6a4db94011d3 771 ((BURST) == DMA_PBURST_INC16))
sahilmgandhi 18:6a4db94011d3 772 /**
sahilmgandhi 18:6a4db94011d3 773 * @}
sahilmgandhi 18:6a4db94011d3 774 */
sahilmgandhi 18:6a4db94011d3 775
sahilmgandhi 18:6a4db94011d3 776 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 777 /** @defgroup DMA_Private_Functions DMA Private Functions
sahilmgandhi 18:6a4db94011d3 778 * @brief DMA private functions
sahilmgandhi 18:6a4db94011d3 779 * @{
sahilmgandhi 18:6a4db94011d3 780 */
sahilmgandhi 18:6a4db94011d3 781 /**
sahilmgandhi 18:6a4db94011d3 782 * @}
sahilmgandhi 18:6a4db94011d3 783 */
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 /**
sahilmgandhi 18:6a4db94011d3 786 * @}
sahilmgandhi 18:6a4db94011d3 787 */
sahilmgandhi 18:6a4db94011d3 788
sahilmgandhi 18:6a4db94011d3 789 /**
sahilmgandhi 18:6a4db94011d3 790 * @}
sahilmgandhi 18:6a4db94011d3 791 */
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 794 }
sahilmgandhi 18:6a4db94011d3 795 #endif
sahilmgandhi 18:6a4db94011d3 796
sahilmgandhi 18:6a4db94011d3 797 #endif /* __STM32F4xx_HAL_DMA_H */
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/