MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_dma.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief DMA HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 10 * functionalities of the Direct Memory Access (DMA) peripheral:
sahilmgandhi 18:6a4db94011d3 11 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 12 * + IO operation functions
sahilmgandhi 18:6a4db94011d3 13 * + Peripheral State and errors functions
sahilmgandhi 18:6a4db94011d3 14 @verbatim
sahilmgandhi 18:6a4db94011d3 15 ==============================================================================
sahilmgandhi 18:6a4db94011d3 16 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 17 ==============================================================================
sahilmgandhi 18:6a4db94011d3 18 [..]
sahilmgandhi 18:6a4db94011d3 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
sahilmgandhi 18:6a4db94011d3 20 (except for internal SRAM/FLASH memories: no initialization is
sahilmgandhi 18:6a4db94011d3 21 necessary) please refer to Reference manual for connection between peripherals
sahilmgandhi 18:6a4db94011d3 22 and DMA requests .
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 (#) For a given Stream, program the required configuration through the following parameters:
sahilmgandhi 18:6a4db94011d3 25 Transfer Direction, Source and Destination data formats,
sahilmgandhi 18:6a4db94011d3 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
sahilmgandhi 18:6a4db94011d3 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
sahilmgandhi 18:6a4db94011d3 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 *** Polling mode IO operation ***
sahilmgandhi 18:6a4db94011d3 31 =================================
sahilmgandhi 18:6a4db94011d3 32 [..]
sahilmgandhi 18:6a4db94011d3 33 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
sahilmgandhi 18:6a4db94011d3 34 address and destination address and the Length of data to be transferred
sahilmgandhi 18:6a4db94011d3 35 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
sahilmgandhi 18:6a4db94011d3 36 case a fixed Timeout can be configured by User depending from his application.
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 *** Interrupt mode IO operation ***
sahilmgandhi 18:6a4db94011d3 39 ===================================
sahilmgandhi 18:6a4db94011d3 40 [..]
sahilmgandhi 18:6a4db94011d3 41 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
sahilmgandhi 18:6a4db94011d3 42 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
sahilmgandhi 18:6a4db94011d3 43 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
sahilmgandhi 18:6a4db94011d3 44 Source address and destination address and the Length of data to be transferred. In this
sahilmgandhi 18:6a4db94011d3 45 case the DMA interrupt is configured
sahilmgandhi 18:6a4db94011d3 46 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
sahilmgandhi 18:6a4db94011d3 47 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
sahilmgandhi 18:6a4db94011d3 48 add his own function by customization of function pointer XferCpltCallback and
sahilmgandhi 18:6a4db94011d3 49 XferErrorCallback (i.e a member of DMA handle structure).
sahilmgandhi 18:6a4db94011d3 50 [..]
sahilmgandhi 18:6a4db94011d3 51 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
sahilmgandhi 18:6a4db94011d3 52 detection.
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 (#) Use HAL_DMA_Abort() function to abort the current transfer
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
sahilmgandhi 18:6a4db94011d3 59 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
sahilmgandhi 18:6a4db94011d3 60 Half-Word data size for the peripheral to access its data register and set Word data size
sahilmgandhi 18:6a4db94011d3 61 for the Memory to gain in access time. Each two half words will be packed and written in
sahilmgandhi 18:6a4db94011d3 62 a single access to a Word in the Memory).
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
sahilmgandhi 18:6a4db94011d3 65 and Destination. In this case the Peripheral Data Size will be applied to both Source
sahilmgandhi 18:6a4db94011d3 66 and Destination.
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 *** DMA HAL driver macros list ***
sahilmgandhi 18:6a4db94011d3 69 =============================================
sahilmgandhi 18:6a4db94011d3 70 [..]
sahilmgandhi 18:6a4db94011d3 71 Below the list of most used macros in DMA HAL driver.
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 74 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 75 (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
sahilmgandhi 18:6a4db94011d3 76 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
sahilmgandhi 18:6a4db94011d3 77 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
sahilmgandhi 18:6a4db94011d3 78 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 [..]
sahilmgandhi 18:6a4db94011d3 81 (@) You can refer to the DMA HAL driver header file for more useful macros
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 @endverbatim
sahilmgandhi 18:6a4db94011d3 84 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 85 * @attention
sahilmgandhi 18:6a4db94011d3 86 *
sahilmgandhi 18:6a4db94011d3 87 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 88 *
sahilmgandhi 18:6a4db94011d3 89 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 90 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 91 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 92 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 93 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 94 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 95 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 96 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 97 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 98 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 99 *
sahilmgandhi 18:6a4db94011d3 100 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 101 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 102 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 103 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 104 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 105 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 106 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 107 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 108 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 109 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 110 *
sahilmgandhi 18:6a4db94011d3 111 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 112 */
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 115 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 118 * @{
sahilmgandhi 18:6a4db94011d3 119 */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /** @defgroup DMA DMA
sahilmgandhi 18:6a4db94011d3 122 * @brief DMA HAL module driver
sahilmgandhi 18:6a4db94011d3 123 * @{
sahilmgandhi 18:6a4db94011d3 124 */
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 #ifdef HAL_DMA_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 129 typedef struct
sahilmgandhi 18:6a4db94011d3 130 {
sahilmgandhi 18:6a4db94011d3 131 __IO uint32_t ISR; /*!< DMA interrupt status register */
sahilmgandhi 18:6a4db94011d3 132 __IO uint32_t Reserved0;
sahilmgandhi 18:6a4db94011d3 133 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
sahilmgandhi 18:6a4db94011d3 134 } DMA_Base_Registers;
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 137 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 138 /** @addtogroup DMA_Private_Constants
sahilmgandhi 18:6a4db94011d3 139 * @{
sahilmgandhi 18:6a4db94011d3 140 */
sahilmgandhi 18:6a4db94011d3 141 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */
sahilmgandhi 18:6a4db94011d3 142 /**
sahilmgandhi 18:6a4db94011d3 143 * @}
sahilmgandhi 18:6a4db94011d3 144 */
sahilmgandhi 18:6a4db94011d3 145 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 146 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 147 /** @addtogroup DMA_Private_Functions
sahilmgandhi 18:6a4db94011d3 148 * @{
sahilmgandhi 18:6a4db94011d3 149 */
sahilmgandhi 18:6a4db94011d3 150 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
sahilmgandhi 18:6a4db94011d3 151 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 152 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /**
sahilmgandhi 18:6a4db94011d3 155 * @}
sahilmgandhi 18:6a4db94011d3 156 */
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 159 /** @addtogroup DMA_Exported_Functions
sahilmgandhi 18:6a4db94011d3 160 * @{
sahilmgandhi 18:6a4db94011d3 161 */
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 /** @addtogroup DMA_Exported_Functions_Group1
sahilmgandhi 18:6a4db94011d3 164 *
sahilmgandhi 18:6a4db94011d3 165 @verbatim
sahilmgandhi 18:6a4db94011d3 166 ===============================================================================
sahilmgandhi 18:6a4db94011d3 167 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 168 ===============================================================================
sahilmgandhi 18:6a4db94011d3 169 [..]
sahilmgandhi 18:6a4db94011d3 170 This section provides functions allowing to initialize the DMA Stream source
sahilmgandhi 18:6a4db94011d3 171 and destination addresses, incrementation and data sizes, transfer direction,
sahilmgandhi 18:6a4db94011d3 172 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
sahilmgandhi 18:6a4db94011d3 173 [..]
sahilmgandhi 18:6a4db94011d3 174 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
sahilmgandhi 18:6a4db94011d3 175 reference manual.
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 @endverbatim
sahilmgandhi 18:6a4db94011d3 178 * @{
sahilmgandhi 18:6a4db94011d3 179 */
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 /**
sahilmgandhi 18:6a4db94011d3 182 * @brief Initializes the DMA according to the specified
sahilmgandhi 18:6a4db94011d3 183 * parameters in the DMA_InitTypeDef and create the associated handle.
sahilmgandhi 18:6a4db94011d3 184 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 185 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 186 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 187 */
sahilmgandhi 18:6a4db94011d3 188 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 189 {
sahilmgandhi 18:6a4db94011d3 190 uint32_t tmp = 0U;
sahilmgandhi 18:6a4db94011d3 191 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 192 DMA_Base_Registers *regs;
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 /* Check the DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 195 if(hdma == NULL)
sahilmgandhi 18:6a4db94011d3 196 {
sahilmgandhi 18:6a4db94011d3 197 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 198 }
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 201 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
sahilmgandhi 18:6a4db94011d3 202 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
sahilmgandhi 18:6a4db94011d3 203 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
sahilmgandhi 18:6a4db94011d3 204 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
sahilmgandhi 18:6a4db94011d3 205 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
sahilmgandhi 18:6a4db94011d3 206 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
sahilmgandhi 18:6a4db94011d3 207 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
sahilmgandhi 18:6a4db94011d3 208 assert_param(IS_DMA_MODE(hdma->Init.Mode));
sahilmgandhi 18:6a4db94011d3 209 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
sahilmgandhi 18:6a4db94011d3 210 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
sahilmgandhi 18:6a4db94011d3 211 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
sahilmgandhi 18:6a4db94011d3 212 when FIFO mode is enabled */
sahilmgandhi 18:6a4db94011d3 213 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
sahilmgandhi 18:6a4db94011d3 214 {
sahilmgandhi 18:6a4db94011d3 215 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
sahilmgandhi 18:6a4db94011d3 216 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
sahilmgandhi 18:6a4db94011d3 217 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
sahilmgandhi 18:6a4db94011d3 218 }
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 /* Allocate lock resource */
sahilmgandhi 18:6a4db94011d3 221 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 224 hdma->State = HAL_DMA_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /* Disable the peripheral */
sahilmgandhi 18:6a4db94011d3 227 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 /* Check if the DMA Stream is effectively disabled */
sahilmgandhi 18:6a4db94011d3 230 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
sahilmgandhi 18:6a4db94011d3 231 {
sahilmgandhi 18:6a4db94011d3 232 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 233 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
sahilmgandhi 18:6a4db94011d3 234 {
sahilmgandhi 18:6a4db94011d3 235 /* Update error code */
sahilmgandhi 18:6a4db94011d3 236 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 239 hdma->State = HAL_DMA_STATE_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 242 }
sahilmgandhi 18:6a4db94011d3 243 }
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 /* Get the CR register value */
sahilmgandhi 18:6a4db94011d3 246 tmp = hdma->Instance->CR;
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
sahilmgandhi 18:6a4db94011d3 249 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
sahilmgandhi 18:6a4db94011d3 250 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
sahilmgandhi 18:6a4db94011d3 251 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
sahilmgandhi 18:6a4db94011d3 252 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /* Prepare the DMA Stream configuration */
sahilmgandhi 18:6a4db94011d3 255 tmp |= hdma->Init.Channel | hdma->Init.Direction |
sahilmgandhi 18:6a4db94011d3 256 hdma->Init.PeriphInc | hdma->Init.MemInc |
sahilmgandhi 18:6a4db94011d3 257 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
sahilmgandhi 18:6a4db94011d3 258 hdma->Init.Mode | hdma->Init.Priority;
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
sahilmgandhi 18:6a4db94011d3 261 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 262 {
sahilmgandhi 18:6a4db94011d3 263 /* Get memory burst and peripheral burst */
sahilmgandhi 18:6a4db94011d3 264 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
sahilmgandhi 18:6a4db94011d3 265 }
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 /* Write to DMA Stream CR register */
sahilmgandhi 18:6a4db94011d3 268 hdma->Instance->CR = tmp;
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 /* Get the FCR register value */
sahilmgandhi 18:6a4db94011d3 271 tmp = hdma->Instance->FCR;
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 /* Clear Direct mode and FIFO threshold bits */
sahilmgandhi 18:6a4db94011d3 274 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 /* Prepare the DMA Stream FIFO configuration */
sahilmgandhi 18:6a4db94011d3 277 tmp |= hdma->Init.FIFOMode;
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 /* the FIFO threshold is not used when the FIFO mode is disabled */
sahilmgandhi 18:6a4db94011d3 280 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 281 {
sahilmgandhi 18:6a4db94011d3 282 /* Get the FIFO threshold */
sahilmgandhi 18:6a4db94011d3 283 tmp |= hdma->Init.FIFOThreshold;
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 if(DMA_CheckFifoParam(hdma) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 286 {
sahilmgandhi 18:6a4db94011d3 287 /* Update error code */
sahilmgandhi 18:6a4db94011d3 288 hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 291 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295 }
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 /* Write to DMA Stream FCR */
sahilmgandhi 18:6a4db94011d3 298 hdma->Instance->FCR = tmp;
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
sahilmgandhi 18:6a4db94011d3 301 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
sahilmgandhi 18:6a4db94011d3 302 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 /* Clear all interrupt flags */
sahilmgandhi 18:6a4db94011d3 305 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Initialize the error code */
sahilmgandhi 18:6a4db94011d3 308 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 /* Initialize the DMA state */
sahilmgandhi 18:6a4db94011d3 311 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 314 }
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 /**
sahilmgandhi 18:6a4db94011d3 317 * @brief DeInitializes the DMA peripheral
sahilmgandhi 18:6a4db94011d3 318 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 319 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 320 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 321 */
sahilmgandhi 18:6a4db94011d3 322 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 323 {
sahilmgandhi 18:6a4db94011d3 324 DMA_Base_Registers *regs;
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 /* Check the DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 327 if(hdma == NULL)
sahilmgandhi 18:6a4db94011d3 328 {
sahilmgandhi 18:6a4db94011d3 329 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 330 }
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 /* Check the DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 333 if(hdma->State == HAL_DMA_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 334 {
sahilmgandhi 18:6a4db94011d3 335 /* Return error status */
sahilmgandhi 18:6a4db94011d3 336 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 337 }
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 /* Disable the selected DMA Streamx */
sahilmgandhi 18:6a4db94011d3 340 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /* Reset DMA Streamx control register */
sahilmgandhi 18:6a4db94011d3 343 hdma->Instance->CR = 0U;
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 /* Reset DMA Streamx number of data to transfer register */
sahilmgandhi 18:6a4db94011d3 346 hdma->Instance->NDTR = 0U;
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 /* Reset DMA Streamx peripheral address register */
sahilmgandhi 18:6a4db94011d3 349 hdma->Instance->PAR = 0U;
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 /* Reset DMA Streamx memory 0 address register */
sahilmgandhi 18:6a4db94011d3 352 hdma->Instance->M0AR = 0U;
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 /* Reset DMA Streamx memory 1 address register */
sahilmgandhi 18:6a4db94011d3 355 hdma->Instance->M1AR = 0U;
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 /* Reset DMA Streamx FIFO control register */
sahilmgandhi 18:6a4db94011d3 358 hdma->Instance->FCR = (uint32_t)0x00000021U;
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 /* Get DMA steam Base Address */
sahilmgandhi 18:6a4db94011d3 361 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 /* Clear all interrupt flags at correct offset within the register */
sahilmgandhi 18:6a4db94011d3 364 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /* Initialize the error code */
sahilmgandhi 18:6a4db94011d3 367 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 /* Initialize the DMA state */
sahilmgandhi 18:6a4db94011d3 370 hdma->State = HAL_DMA_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 373 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 376 }
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 /**
sahilmgandhi 18:6a4db94011d3 379 * @}
sahilmgandhi 18:6a4db94011d3 380 */
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 /** @addtogroup DMA_Exported_Functions_Group2
sahilmgandhi 18:6a4db94011d3 383 *
sahilmgandhi 18:6a4db94011d3 384 @verbatim
sahilmgandhi 18:6a4db94011d3 385 ===============================================================================
sahilmgandhi 18:6a4db94011d3 386 ##### IO operation functions #####
sahilmgandhi 18:6a4db94011d3 387 ===============================================================================
sahilmgandhi 18:6a4db94011d3 388 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 389 (+) Configure the source, destination address and data length and Start DMA transfer
sahilmgandhi 18:6a4db94011d3 390 (+) Configure the source, destination address and data length and
sahilmgandhi 18:6a4db94011d3 391 Start DMA transfer with interrupt
sahilmgandhi 18:6a4db94011d3 392 (+) Abort DMA transfer
sahilmgandhi 18:6a4db94011d3 393 (+) Poll for transfer complete
sahilmgandhi 18:6a4db94011d3 394 (+) Handle DMA interrupt request
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 @endverbatim
sahilmgandhi 18:6a4db94011d3 397 * @{
sahilmgandhi 18:6a4db94011d3 398 */
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 /**
sahilmgandhi 18:6a4db94011d3 401 * @brief Starts the DMA Transfer.
sahilmgandhi 18:6a4db94011d3 402 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 403 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 404 * @param SrcAddress: The source memory Buffer address
sahilmgandhi 18:6a4db94011d3 405 * @param DstAddress: The destination memory Buffer address
sahilmgandhi 18:6a4db94011d3 406 * @param DataLength: The length of data to be transferred from source to destination
sahilmgandhi 18:6a4db94011d3 407 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 408 */
sahilmgandhi 18:6a4db94011d3 409 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
sahilmgandhi 18:6a4db94011d3 410 {
sahilmgandhi 18:6a4db94011d3 411 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 414 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 /* Process locked */
sahilmgandhi 18:6a4db94011d3 417 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 420 {
sahilmgandhi 18:6a4db94011d3 421 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 422 hdma->State = HAL_DMA_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 /* Initialize the error code */
sahilmgandhi 18:6a4db94011d3 425 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 /* Configure the source, destination address and the data length */
sahilmgandhi 18:6a4db94011d3 428 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 /* Enable the Peripheral */
sahilmgandhi 18:6a4db94011d3 431 __HAL_DMA_ENABLE(hdma);
sahilmgandhi 18:6a4db94011d3 432 }
sahilmgandhi 18:6a4db94011d3 433 else
sahilmgandhi 18:6a4db94011d3 434 {
sahilmgandhi 18:6a4db94011d3 435 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 436 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 /* Return error status */
sahilmgandhi 18:6a4db94011d3 439 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 440 }
sahilmgandhi 18:6a4db94011d3 441 return status;
sahilmgandhi 18:6a4db94011d3 442 }
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 /**
sahilmgandhi 18:6a4db94011d3 445 * @brief Starts the DMA Transfer with interrupt enabled.
sahilmgandhi 18:6a4db94011d3 446 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 447 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 448 * @param SrcAddress: The source memory Buffer address
sahilmgandhi 18:6a4db94011d3 449 * @param DstAddress: The destination memory Buffer address
sahilmgandhi 18:6a4db94011d3 450 * @param DataLength: The length of data to be transferred from source to destination
sahilmgandhi 18:6a4db94011d3 451 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 452 */
sahilmgandhi 18:6a4db94011d3 453 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
sahilmgandhi 18:6a4db94011d3 454 {
sahilmgandhi 18:6a4db94011d3 455 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 /* calculate DMA base and stream number */
sahilmgandhi 18:6a4db94011d3 458 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 461 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 /* Process locked */
sahilmgandhi 18:6a4db94011d3 464 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 467 {
sahilmgandhi 18:6a4db94011d3 468 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 469 hdma->State = HAL_DMA_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 /* Initialize the error code */
sahilmgandhi 18:6a4db94011d3 472 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 /* Configure the source, destination address and the data length */
sahilmgandhi 18:6a4db94011d3 475 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /* Clear all interrupt flags at correct offset within the register */
sahilmgandhi 18:6a4db94011d3 478 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /* Enable Common interrupts*/
sahilmgandhi 18:6a4db94011d3 481 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
sahilmgandhi 18:6a4db94011d3 482 hdma->Instance->FCR |= DMA_IT_FE;
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 if(hdma->XferHalfCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 485 {
sahilmgandhi 18:6a4db94011d3 486 hdma->Instance->CR |= DMA_IT_HT;
sahilmgandhi 18:6a4db94011d3 487 }
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 /* Enable the Peripheral */
sahilmgandhi 18:6a4db94011d3 490 __HAL_DMA_ENABLE(hdma);
sahilmgandhi 18:6a4db94011d3 491 }
sahilmgandhi 18:6a4db94011d3 492 else
sahilmgandhi 18:6a4db94011d3 493 {
sahilmgandhi 18:6a4db94011d3 494 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 495 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 /* Return error status */
sahilmgandhi 18:6a4db94011d3 498 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 499 }
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 return status;
sahilmgandhi 18:6a4db94011d3 502 }
sahilmgandhi 18:6a4db94011d3 503
sahilmgandhi 18:6a4db94011d3 504 /**
sahilmgandhi 18:6a4db94011d3 505 * @brief Aborts the DMA Transfer.
sahilmgandhi 18:6a4db94011d3 506 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 507 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 508 *
sahilmgandhi 18:6a4db94011d3 509 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
sahilmgandhi 18:6a4db94011d3 510 * effectively disabled is added. If a Stream is disabled
sahilmgandhi 18:6a4db94011d3 511 * while a data transfer is ongoing, the current data will be transferred
sahilmgandhi 18:6a4db94011d3 512 * and the Stream will be effectively disabled only after the transfer of
sahilmgandhi 18:6a4db94011d3 513 * this single data is finished.
sahilmgandhi 18:6a4db94011d3 514 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 515 */
sahilmgandhi 18:6a4db94011d3 516 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 517 {
sahilmgandhi 18:6a4db94011d3 518 /* calculate DMA base and stream number */
sahilmgandhi 18:6a4db94011d3 519 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 520
sahilmgandhi 18:6a4db94011d3 521 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 if(hdma->State != HAL_DMA_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 524 {
sahilmgandhi 18:6a4db94011d3 525 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 528 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 531 }
sahilmgandhi 18:6a4db94011d3 532 else
sahilmgandhi 18:6a4db94011d3 533 {
sahilmgandhi 18:6a4db94011d3 534 /* Disable all the transfer interrupts */
sahilmgandhi 18:6a4db94011d3 535 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
sahilmgandhi 18:6a4db94011d3 536 hdma->Instance->FCR &= ~(DMA_IT_FE);
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 hdma->Instance->CR &= ~(DMA_IT_HT);
sahilmgandhi 18:6a4db94011d3 541 }
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 /* Disable the stream */
sahilmgandhi 18:6a4db94011d3 544 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 /* Check if the DMA Stream is effectively disabled */
sahilmgandhi 18:6a4db94011d3 547 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
sahilmgandhi 18:6a4db94011d3 548 {
sahilmgandhi 18:6a4db94011d3 549 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 550 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
sahilmgandhi 18:6a4db94011d3 551 {
sahilmgandhi 18:6a4db94011d3 552 /* Update error code */
sahilmgandhi 18:6a4db94011d3 553 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 554
sahilmgandhi 18:6a4db94011d3 555 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 556 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 559 hdma->State = HAL_DMA_STATE_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 562 }
sahilmgandhi 18:6a4db94011d3 563 }
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 /* Clear all interrupt flags at correct offset within the register */
sahilmgandhi 18:6a4db94011d3 566 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 569 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 570
sahilmgandhi 18:6a4db94011d3 571 /* Change the DMA state*/
sahilmgandhi 18:6a4db94011d3 572 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 573 }
sahilmgandhi 18:6a4db94011d3 574 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 575 }
sahilmgandhi 18:6a4db94011d3 576
sahilmgandhi 18:6a4db94011d3 577 /**
sahilmgandhi 18:6a4db94011d3 578 * @brief Aborts the DMA Transfer in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 579 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 580 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 581 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 582 */
sahilmgandhi 18:6a4db94011d3 583 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 584 {
sahilmgandhi 18:6a4db94011d3 585 if(hdma->State != HAL_DMA_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 586 {
sahilmgandhi 18:6a4db94011d3 587 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
sahilmgandhi 18:6a4db94011d3 588 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 589 }
sahilmgandhi 18:6a4db94011d3 590 else
sahilmgandhi 18:6a4db94011d3 591 {
sahilmgandhi 18:6a4db94011d3 592 /* Set Abort State */
sahilmgandhi 18:6a4db94011d3 593 hdma->State = HAL_DMA_STATE_ABORT;
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 /* Disable the stream */
sahilmgandhi 18:6a4db94011d3 596 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 597 }
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 600 }
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 /**
sahilmgandhi 18:6a4db94011d3 603 * @brief Polling for transfer complete.
sahilmgandhi 18:6a4db94011d3 604 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 605 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 606 * @param CompleteLevel: Specifies the DMA level complete.
sahilmgandhi 18:6a4db94011d3 607 * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
sahilmgandhi 18:6a4db94011d3 608 * This model could be used for debug purpose.
sahilmgandhi 18:6a4db94011d3 609 * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
sahilmgandhi 18:6a4db94011d3 610 * @param Timeout: Timeout duration.
sahilmgandhi 18:6a4db94011d3 611 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 612 */
sahilmgandhi 18:6a4db94011d3 613 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 614 {
sahilmgandhi 18:6a4db94011d3 615 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 616 uint32_t temp;
sahilmgandhi 18:6a4db94011d3 617 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 618 uint32_t tmpisr;
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 /* calculate DMA base and stream number */
sahilmgandhi 18:6a4db94011d3 621 DMA_Base_Registers *regs;
sahilmgandhi 18:6a4db94011d3 622
sahilmgandhi 18:6a4db94011d3 623 /* Polling mode not supported in circular mode and double buffering mode */
sahilmgandhi 18:6a4db94011d3 624 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
sahilmgandhi 18:6a4db94011d3 625 {
sahilmgandhi 18:6a4db94011d3 626 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
sahilmgandhi 18:6a4db94011d3 627 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 628 }
sahilmgandhi 18:6a4db94011d3 629
sahilmgandhi 18:6a4db94011d3 630 /* Get the level transfer complete flag */
sahilmgandhi 18:6a4db94011d3 631 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
sahilmgandhi 18:6a4db94011d3 632 {
sahilmgandhi 18:6a4db94011d3 633 /* Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 634 temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 635 }
sahilmgandhi 18:6a4db94011d3 636 else
sahilmgandhi 18:6a4db94011d3 637 {
sahilmgandhi 18:6a4db94011d3 638 /* Half Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 639 temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 640 }
sahilmgandhi 18:6a4db94011d3 641
sahilmgandhi 18:6a4db94011d3 642 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 643 tmpisr = regs->ISR;
sahilmgandhi 18:6a4db94011d3 644
sahilmgandhi 18:6a4db94011d3 645 while((tmpisr & temp) == RESET )
sahilmgandhi 18:6a4db94011d3 646 {
sahilmgandhi 18:6a4db94011d3 647 /* Check for the Timeout (Not applicable in circular mode)*/
sahilmgandhi 18:6a4db94011d3 648 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 649 {
sahilmgandhi 18:6a4db94011d3 650 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 651 {
sahilmgandhi 18:6a4db94011d3 652 /* Update error code */
sahilmgandhi 18:6a4db94011d3 653 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 656 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 659 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 662 }
sahilmgandhi 18:6a4db94011d3 663 }
sahilmgandhi 18:6a4db94011d3 664
sahilmgandhi 18:6a4db94011d3 665 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 666 {
sahilmgandhi 18:6a4db94011d3 667 /* Update error code */
sahilmgandhi 18:6a4db94011d3 668 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 /* Clear the transfer error flag */
sahilmgandhi 18:6a4db94011d3 671 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 672 }
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 675 {
sahilmgandhi 18:6a4db94011d3 676 /* Update error code */
sahilmgandhi 18:6a4db94011d3 677 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
sahilmgandhi 18:6a4db94011d3 678
sahilmgandhi 18:6a4db94011d3 679 /* Clear the FIFO error flag */
sahilmgandhi 18:6a4db94011d3 680 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 681 }
sahilmgandhi 18:6a4db94011d3 682
sahilmgandhi 18:6a4db94011d3 683 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 684 {
sahilmgandhi 18:6a4db94011d3 685 /* Update error code */
sahilmgandhi 18:6a4db94011d3 686 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
sahilmgandhi 18:6a4db94011d3 687
sahilmgandhi 18:6a4db94011d3 688 /* Clear the Direct Mode error flag */
sahilmgandhi 18:6a4db94011d3 689 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 690 }
sahilmgandhi 18:6a4db94011d3 691 tmpisr = regs->ISR;
sahilmgandhi 18:6a4db94011d3 692 }
sahilmgandhi 18:6a4db94011d3 693
sahilmgandhi 18:6a4db94011d3 694 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 695 {
sahilmgandhi 18:6a4db94011d3 696 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
sahilmgandhi 18:6a4db94011d3 697 {
sahilmgandhi 18:6a4db94011d3 698 HAL_DMA_Abort(hdma);
sahilmgandhi 18:6a4db94011d3 699
sahilmgandhi 18:6a4db94011d3 700 /* Clear the half transfer and transfer complete flags */
sahilmgandhi 18:6a4db94011d3 701 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 704 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 705
sahilmgandhi 18:6a4db94011d3 706 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 707 hdma->State= HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 708
sahilmgandhi 18:6a4db94011d3 709 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 710 }
sahilmgandhi 18:6a4db94011d3 711
sahilmgandhi 18:6a4db94011d3 712 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 713 }
sahilmgandhi 18:6a4db94011d3 714
sahilmgandhi 18:6a4db94011d3 715 /* Get the level transfer complete flag */
sahilmgandhi 18:6a4db94011d3 716 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
sahilmgandhi 18:6a4db94011d3 717 {
sahilmgandhi 18:6a4db94011d3 718 /* Clear the half transfer and transfer complete flags */
sahilmgandhi 18:6a4db94011d3 719 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 720
sahilmgandhi 18:6a4db94011d3 721 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 722 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 723
sahilmgandhi 18:6a4db94011d3 724 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 725 }
sahilmgandhi 18:6a4db94011d3 726 else
sahilmgandhi 18:6a4db94011d3 727 {
sahilmgandhi 18:6a4db94011d3 728 /* Clear the half transfer and transfer complete flags */
sahilmgandhi 18:6a4db94011d3 729 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 730 }
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 return status;
sahilmgandhi 18:6a4db94011d3 733 }
sahilmgandhi 18:6a4db94011d3 734
sahilmgandhi 18:6a4db94011d3 735 /**
sahilmgandhi 18:6a4db94011d3 736 * @brief Handles DMA interrupt request.
sahilmgandhi 18:6a4db94011d3 737 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 738 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 739 * @retval None
sahilmgandhi 18:6a4db94011d3 740 */
sahilmgandhi 18:6a4db94011d3 741 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 742 {
sahilmgandhi 18:6a4db94011d3 743 uint32_t tmpisr;
sahilmgandhi 18:6a4db94011d3 744 __IO uint32_t count = 0;
sahilmgandhi 18:6a4db94011d3 745 uint32_t timeout = SystemCoreClock / 9600;
sahilmgandhi 18:6a4db94011d3 746
sahilmgandhi 18:6a4db94011d3 747 /* calculate DMA base and stream number */
sahilmgandhi 18:6a4db94011d3 748 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 749
sahilmgandhi 18:6a4db94011d3 750 tmpisr = regs->ISR;
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752 /* Transfer Error Interrupt management ***************************************/
sahilmgandhi 18:6a4db94011d3 753 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 754 {
sahilmgandhi 18:6a4db94011d3 755 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
sahilmgandhi 18:6a4db94011d3 756 {
sahilmgandhi 18:6a4db94011d3 757 /* Disable the transfer error interrupt */
sahilmgandhi 18:6a4db94011d3 758 hdma->Instance->CR &= ~(DMA_IT_TE);
sahilmgandhi 18:6a4db94011d3 759
sahilmgandhi 18:6a4db94011d3 760 /* Clear the transfer error flag */
sahilmgandhi 18:6a4db94011d3 761 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 /* Update error code */
sahilmgandhi 18:6a4db94011d3 764 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
sahilmgandhi 18:6a4db94011d3 765
sahilmgandhi 18:6a4db94011d3 766 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 767 hdma->State = HAL_DMA_STATE_ERROR; // FIX
sahilmgandhi 18:6a4db94011d3 768 }
sahilmgandhi 18:6a4db94011d3 769 }
sahilmgandhi 18:6a4db94011d3 770 /* FIFO Error Interrupt management ******************************************/
sahilmgandhi 18:6a4db94011d3 771 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 772 {
sahilmgandhi 18:6a4db94011d3 773 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
sahilmgandhi 18:6a4db94011d3 774 {
sahilmgandhi 18:6a4db94011d3 775 /* Clear the FIFO error flag */
sahilmgandhi 18:6a4db94011d3 776 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 777
sahilmgandhi 18:6a4db94011d3 778 /* Update error code */
sahilmgandhi 18:6a4db94011d3 779 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
sahilmgandhi 18:6a4db94011d3 780
sahilmgandhi 18:6a4db94011d3 781 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 782 hdma->State = HAL_DMA_STATE_ERROR; // FIX
sahilmgandhi 18:6a4db94011d3 783 }
sahilmgandhi 18:6a4db94011d3 784 }
sahilmgandhi 18:6a4db94011d3 785 /* Direct Mode Error Interrupt management ***********************************/
sahilmgandhi 18:6a4db94011d3 786 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 787 {
sahilmgandhi 18:6a4db94011d3 788 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
sahilmgandhi 18:6a4db94011d3 789 {
sahilmgandhi 18:6a4db94011d3 790 /* Clear the direct mode error flag */
sahilmgandhi 18:6a4db94011d3 791 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793 /* Update error code */
sahilmgandhi 18:6a4db94011d3 794 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 797 hdma->State = HAL_DMA_STATE_ERROR; // FIX
sahilmgandhi 18:6a4db94011d3 798 }
sahilmgandhi 18:6a4db94011d3 799 }
sahilmgandhi 18:6a4db94011d3 800 /* Half Transfer Complete Interrupt management ******************************/
sahilmgandhi 18:6a4db94011d3 801 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 802 {
sahilmgandhi 18:6a4db94011d3 803 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
sahilmgandhi 18:6a4db94011d3 804 {
sahilmgandhi 18:6a4db94011d3 805 /* Clear the half transfer complete flag */
sahilmgandhi 18:6a4db94011d3 806 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 807
sahilmgandhi 18:6a4db94011d3 808 /* Multi_Buffering mode enabled */
sahilmgandhi 18:6a4db94011d3 809 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
sahilmgandhi 18:6a4db94011d3 810 {
sahilmgandhi 18:6a4db94011d3 811 /* Current memory buffer used is Memory 0 */
sahilmgandhi 18:6a4db94011d3 812 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
sahilmgandhi 18:6a4db94011d3 813 {
sahilmgandhi 18:6a4db94011d3 814 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 815 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; // FIX
sahilmgandhi 18:6a4db94011d3 816
sahilmgandhi 18:6a4db94011d3 817 if(hdma->XferHalfCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 818 {
sahilmgandhi 18:6a4db94011d3 819 /* Half transfer callback */
sahilmgandhi 18:6a4db94011d3 820 hdma->XferHalfCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 821 }
sahilmgandhi 18:6a4db94011d3 822 }
sahilmgandhi 18:6a4db94011d3 823 /* Current memory buffer used is Memory 1 */
sahilmgandhi 18:6a4db94011d3 824 else
sahilmgandhi 18:6a4db94011d3 825 {
sahilmgandhi 18:6a4db94011d3 826 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 827 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; // FIX
sahilmgandhi 18:6a4db94011d3 828
sahilmgandhi 18:6a4db94011d3 829 if(hdma->XferM1HalfCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 830 {
sahilmgandhi 18:6a4db94011d3 831 /* Half transfer callback */
sahilmgandhi 18:6a4db94011d3 832 hdma->XferM1HalfCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 833 }
sahilmgandhi 18:6a4db94011d3 834 }
sahilmgandhi 18:6a4db94011d3 835 }
sahilmgandhi 18:6a4db94011d3 836 else
sahilmgandhi 18:6a4db94011d3 837 {
sahilmgandhi 18:6a4db94011d3 838 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
sahilmgandhi 18:6a4db94011d3 839 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
sahilmgandhi 18:6a4db94011d3 840 {
sahilmgandhi 18:6a4db94011d3 841 /* Disable the half transfer interrupt */
sahilmgandhi 18:6a4db94011d3 842 hdma->Instance->CR &= ~(DMA_IT_HT);
sahilmgandhi 18:6a4db94011d3 843 }
sahilmgandhi 18:6a4db94011d3 844
sahilmgandhi 18:6a4db94011d3 845 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 846 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; // FIX
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 if(hdma->XferHalfCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 849 {
sahilmgandhi 18:6a4db94011d3 850 /* Half transfer callback */
sahilmgandhi 18:6a4db94011d3 851 hdma->XferHalfCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 852 }
sahilmgandhi 18:6a4db94011d3 853 }
sahilmgandhi 18:6a4db94011d3 854 }
sahilmgandhi 18:6a4db94011d3 855 }
sahilmgandhi 18:6a4db94011d3 856 /* Transfer Complete Interrupt management ***********************************/
sahilmgandhi 18:6a4db94011d3 857 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 858 {
sahilmgandhi 18:6a4db94011d3 859 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
sahilmgandhi 18:6a4db94011d3 860 {
sahilmgandhi 18:6a4db94011d3 861 /* Clear the transfer complete flag */
sahilmgandhi 18:6a4db94011d3 862 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 if(HAL_DMA_STATE_ABORT == hdma->State)
sahilmgandhi 18:6a4db94011d3 865 {
sahilmgandhi 18:6a4db94011d3 866 /* Disable all the transfer interrupts */
sahilmgandhi 18:6a4db94011d3 867 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
sahilmgandhi 18:6a4db94011d3 868 hdma->Instance->FCR &= ~(DMA_IT_FE);
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
sahilmgandhi 18:6a4db94011d3 871 {
sahilmgandhi 18:6a4db94011d3 872 hdma->Instance->CR &= ~(DMA_IT_HT);
sahilmgandhi 18:6a4db94011d3 873 }
sahilmgandhi 18:6a4db94011d3 874
sahilmgandhi 18:6a4db94011d3 875 /* Clear all interrupt flags at correct offset within the register */
sahilmgandhi 18:6a4db94011d3 876 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 877
sahilmgandhi 18:6a4db94011d3 878 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 879 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 880
sahilmgandhi 18:6a4db94011d3 881 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 882 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 if(hdma->XferAbortCallback != NULL)
sahilmgandhi 18:6a4db94011d3 885 {
sahilmgandhi 18:6a4db94011d3 886 hdma->XferAbortCallback(hdma);
sahilmgandhi 18:6a4db94011d3 887 }
sahilmgandhi 18:6a4db94011d3 888 return;
sahilmgandhi 18:6a4db94011d3 889 }
sahilmgandhi 18:6a4db94011d3 890
sahilmgandhi 18:6a4db94011d3 891 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
sahilmgandhi 18:6a4db94011d3 892 {
sahilmgandhi 18:6a4db94011d3 893 /* Current memory buffer used is Memory 0 */
sahilmgandhi 18:6a4db94011d3 894 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
sahilmgandhi 18:6a4db94011d3 895 {
sahilmgandhi 18:6a4db94011d3 896 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 897 hdma->State = HAL_DMA_STATE_READY_MEM1; // FIX
sahilmgandhi 18:6a4db94011d3 898
sahilmgandhi 18:6a4db94011d3 899 if(hdma->XferM1CpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 900 {
sahilmgandhi 18:6a4db94011d3 901 /* Transfer complete Callback for memory1 */
sahilmgandhi 18:6a4db94011d3 902 hdma->XferM1CpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 903 }
sahilmgandhi 18:6a4db94011d3 904 }
sahilmgandhi 18:6a4db94011d3 905 /* Current memory buffer used is Memory 1 */
sahilmgandhi 18:6a4db94011d3 906 else
sahilmgandhi 18:6a4db94011d3 907 {
sahilmgandhi 18:6a4db94011d3 908 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 909 hdma->State = HAL_DMA_STATE_READY_MEM0; // FIX
sahilmgandhi 18:6a4db94011d3 910
sahilmgandhi 18:6a4db94011d3 911 if(hdma->XferCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 912 {
sahilmgandhi 18:6a4db94011d3 913 /* Transfer complete Callback for memory0 */
sahilmgandhi 18:6a4db94011d3 914 hdma->XferCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916 }
sahilmgandhi 18:6a4db94011d3 917 }
sahilmgandhi 18:6a4db94011d3 918 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
sahilmgandhi 18:6a4db94011d3 919 else
sahilmgandhi 18:6a4db94011d3 920 {
sahilmgandhi 18:6a4db94011d3 921 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 922 hdma->State = HAL_DMA_STATE_READY_MEM0; // FIX
sahilmgandhi 18:6a4db94011d3 923
sahilmgandhi 18:6a4db94011d3 924 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
sahilmgandhi 18:6a4db94011d3 925 {
sahilmgandhi 18:6a4db94011d3 926 /* Disable the transfer complete interrupt */
sahilmgandhi 18:6a4db94011d3 927 hdma->Instance->CR &= ~(DMA_IT_TC);
sahilmgandhi 18:6a4db94011d3 928
sahilmgandhi 18:6a4db94011d3 929 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 930 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 931
sahilmgandhi 18:6a4db94011d3 932 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 933 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 934 }
sahilmgandhi 18:6a4db94011d3 935
sahilmgandhi 18:6a4db94011d3 936 if(hdma->XferCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 937 {
sahilmgandhi 18:6a4db94011d3 938 /* Transfer complete callback */
sahilmgandhi 18:6a4db94011d3 939 hdma->XferCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 940 }
sahilmgandhi 18:6a4db94011d3 941 }
sahilmgandhi 18:6a4db94011d3 942 }
sahilmgandhi 18:6a4db94011d3 943 }
sahilmgandhi 18:6a4db94011d3 944
sahilmgandhi 18:6a4db94011d3 945 /* manage error case */
sahilmgandhi 18:6a4db94011d3 946 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 947 {
sahilmgandhi 18:6a4db94011d3 948 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
sahilmgandhi 18:6a4db94011d3 949 {
sahilmgandhi 18:6a4db94011d3 950 hdma->State = HAL_DMA_STATE_ABORT;
sahilmgandhi 18:6a4db94011d3 951
sahilmgandhi 18:6a4db94011d3 952 /* Disable the stream */
sahilmgandhi 18:6a4db94011d3 953 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 do
sahilmgandhi 18:6a4db94011d3 956 {
sahilmgandhi 18:6a4db94011d3 957 if (++count > timeout)
sahilmgandhi 18:6a4db94011d3 958 {
sahilmgandhi 18:6a4db94011d3 959 break;
sahilmgandhi 18:6a4db94011d3 960 }
sahilmgandhi 18:6a4db94011d3 961 }
sahilmgandhi 18:6a4db94011d3 962 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
sahilmgandhi 18:6a4db94011d3 963
sahilmgandhi 18:6a4db94011d3 964 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 965 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 966
sahilmgandhi 18:6a4db94011d3 967 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 968 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 969 }
sahilmgandhi 18:6a4db94011d3 970
sahilmgandhi 18:6a4db94011d3 971 if(hdma->XferErrorCallback != NULL)
sahilmgandhi 18:6a4db94011d3 972 {
sahilmgandhi 18:6a4db94011d3 973 /* Transfer error callback */
sahilmgandhi 18:6a4db94011d3 974 hdma->XferErrorCallback(hdma);
sahilmgandhi 18:6a4db94011d3 975 }
sahilmgandhi 18:6a4db94011d3 976 }
sahilmgandhi 18:6a4db94011d3 977 }
sahilmgandhi 18:6a4db94011d3 978
sahilmgandhi 18:6a4db94011d3 979 /**
sahilmgandhi 18:6a4db94011d3 980 * @brief Register callbacks
sahilmgandhi 18:6a4db94011d3 981 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 982 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 983 * @param CallbackID: User Callback identifer
sahilmgandhi 18:6a4db94011d3 984 * a DMA_HandleTypeDef structure as parameter.
sahilmgandhi 18:6a4db94011d3 985 * @param pCallback: pointer to private callbacsk function which has pointer to
sahilmgandhi 18:6a4db94011d3 986 * a DMA_HandleTypeDef structure as parameter.
sahilmgandhi 18:6a4db94011d3 987 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 988 */
sahilmgandhi 18:6a4db94011d3 989 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
sahilmgandhi 18:6a4db94011d3 990 {
sahilmgandhi 18:6a4db94011d3 991
sahilmgandhi 18:6a4db94011d3 992 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 993
sahilmgandhi 18:6a4db94011d3 994 /* Process locked */
sahilmgandhi 18:6a4db94011d3 995 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 996
sahilmgandhi 18:6a4db94011d3 997 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 998 {
sahilmgandhi 18:6a4db94011d3 999 switch (CallbackID)
sahilmgandhi 18:6a4db94011d3 1000 {
sahilmgandhi 18:6a4db94011d3 1001 case HAL_DMA_XFER_CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1002 hdma->XferCpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 1003 break;
sahilmgandhi 18:6a4db94011d3 1004
sahilmgandhi 18:6a4db94011d3 1005 case HAL_DMA_XFER_HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1006 hdma->XferHalfCpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 1007 break;
sahilmgandhi 18:6a4db94011d3 1008
sahilmgandhi 18:6a4db94011d3 1009 case HAL_DMA_XFER_M1CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1010 hdma->XferM1CpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 1011 break;
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1014 hdma->XferM1HalfCpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 1015 break;
sahilmgandhi 18:6a4db94011d3 1016
sahilmgandhi 18:6a4db94011d3 1017 case HAL_DMA_XFER_ERROR_CB_ID:
sahilmgandhi 18:6a4db94011d3 1018 hdma->XferErrorCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 1019 break;
sahilmgandhi 18:6a4db94011d3 1020
sahilmgandhi 18:6a4db94011d3 1021 case HAL_DMA_XFER_ABORT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1022 hdma->XferAbortCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 1023 break;
sahilmgandhi 18:6a4db94011d3 1024
sahilmgandhi 18:6a4db94011d3 1025 default:
sahilmgandhi 18:6a4db94011d3 1026 break;
sahilmgandhi 18:6a4db94011d3 1027 }
sahilmgandhi 18:6a4db94011d3 1028 }
sahilmgandhi 18:6a4db94011d3 1029 else
sahilmgandhi 18:6a4db94011d3 1030 {
sahilmgandhi 18:6a4db94011d3 1031 /* Return error status */
sahilmgandhi 18:6a4db94011d3 1032 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1033 }
sahilmgandhi 18:6a4db94011d3 1034
sahilmgandhi 18:6a4db94011d3 1035 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 1036 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 1037
sahilmgandhi 18:6a4db94011d3 1038 return status;
sahilmgandhi 18:6a4db94011d3 1039 }
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041 /**
sahilmgandhi 18:6a4db94011d3 1042 * @brief UnRegister callbacks
sahilmgandhi 18:6a4db94011d3 1043 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1044 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1045 * @param CallbackID: User Callback identifer
sahilmgandhi 18:6a4db94011d3 1046 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
sahilmgandhi 18:6a4db94011d3 1047 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1048 */
sahilmgandhi 18:6a4db94011d3 1049 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
sahilmgandhi 18:6a4db94011d3 1050 {
sahilmgandhi 18:6a4db94011d3 1051 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1052
sahilmgandhi 18:6a4db94011d3 1053 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1054 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 1055
sahilmgandhi 18:6a4db94011d3 1056 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 1057 {
sahilmgandhi 18:6a4db94011d3 1058 switch (CallbackID)
sahilmgandhi 18:6a4db94011d3 1059 {
sahilmgandhi 18:6a4db94011d3 1060 case HAL_DMA_XFER_CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1061 hdma->XferCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1062 break;
sahilmgandhi 18:6a4db94011d3 1063
sahilmgandhi 18:6a4db94011d3 1064 case HAL_DMA_XFER_HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1065 hdma->XferHalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1066 break;
sahilmgandhi 18:6a4db94011d3 1067
sahilmgandhi 18:6a4db94011d3 1068 case HAL_DMA_XFER_M1CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1069 hdma->XferM1CpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1070 break;
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1073 hdma->XferM1HalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1074 break;
sahilmgandhi 18:6a4db94011d3 1075
sahilmgandhi 18:6a4db94011d3 1076 case HAL_DMA_XFER_ERROR_CB_ID:
sahilmgandhi 18:6a4db94011d3 1077 hdma->XferErrorCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1078 break;
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 case HAL_DMA_XFER_ABORT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1081 hdma->XferAbortCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1082 break;
sahilmgandhi 18:6a4db94011d3 1083
sahilmgandhi 18:6a4db94011d3 1084 case HAL_DMA_XFER_ALL_CB_ID:
sahilmgandhi 18:6a4db94011d3 1085 hdma->XferCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1086 hdma->XferHalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1087 hdma->XferM1CpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1088 hdma->XferM1HalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1089 hdma->XferErrorCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1090 hdma->XferAbortCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1091 break;
sahilmgandhi 18:6a4db94011d3 1092
sahilmgandhi 18:6a4db94011d3 1093 default:
sahilmgandhi 18:6a4db94011d3 1094 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1095 break;
sahilmgandhi 18:6a4db94011d3 1096 }
sahilmgandhi 18:6a4db94011d3 1097 }
sahilmgandhi 18:6a4db94011d3 1098 else
sahilmgandhi 18:6a4db94011d3 1099 {
sahilmgandhi 18:6a4db94011d3 1100 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1101 }
sahilmgandhi 18:6a4db94011d3 1102
sahilmgandhi 18:6a4db94011d3 1103 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 1104 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 1105
sahilmgandhi 18:6a4db94011d3 1106 return status;
sahilmgandhi 18:6a4db94011d3 1107 }
sahilmgandhi 18:6a4db94011d3 1108
sahilmgandhi 18:6a4db94011d3 1109 /**
sahilmgandhi 18:6a4db94011d3 1110 * @}
sahilmgandhi 18:6a4db94011d3 1111 */
sahilmgandhi 18:6a4db94011d3 1112
sahilmgandhi 18:6a4db94011d3 1113 /** @addtogroup DMA_Exported_Functions_Group3
sahilmgandhi 18:6a4db94011d3 1114 *
sahilmgandhi 18:6a4db94011d3 1115 @verbatim
sahilmgandhi 18:6a4db94011d3 1116 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1117 ##### State and Errors functions #####
sahilmgandhi 18:6a4db94011d3 1118 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1119 [..]
sahilmgandhi 18:6a4db94011d3 1120 This subsection provides functions allowing to
sahilmgandhi 18:6a4db94011d3 1121 (+) Check the DMA state
sahilmgandhi 18:6a4db94011d3 1122 (+) Get error code
sahilmgandhi 18:6a4db94011d3 1123
sahilmgandhi 18:6a4db94011d3 1124 @endverbatim
sahilmgandhi 18:6a4db94011d3 1125 * @{
sahilmgandhi 18:6a4db94011d3 1126 */
sahilmgandhi 18:6a4db94011d3 1127
sahilmgandhi 18:6a4db94011d3 1128 /**
sahilmgandhi 18:6a4db94011d3 1129 * @brief Returns the DMA state.
sahilmgandhi 18:6a4db94011d3 1130 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1131 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1132 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1133 */
sahilmgandhi 18:6a4db94011d3 1134 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1135 {
sahilmgandhi 18:6a4db94011d3 1136 return hdma->State;
sahilmgandhi 18:6a4db94011d3 1137 }
sahilmgandhi 18:6a4db94011d3 1138
sahilmgandhi 18:6a4db94011d3 1139 /**
sahilmgandhi 18:6a4db94011d3 1140 * @brief Return the DMA error code
sahilmgandhi 18:6a4db94011d3 1141 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1142 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1143 * @retval DMA Error Code
sahilmgandhi 18:6a4db94011d3 1144 */
sahilmgandhi 18:6a4db94011d3 1145 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1146 {
sahilmgandhi 18:6a4db94011d3 1147 return hdma->ErrorCode;
sahilmgandhi 18:6a4db94011d3 1148 }
sahilmgandhi 18:6a4db94011d3 1149
sahilmgandhi 18:6a4db94011d3 1150 /**
sahilmgandhi 18:6a4db94011d3 1151 * @}
sahilmgandhi 18:6a4db94011d3 1152 */
sahilmgandhi 18:6a4db94011d3 1153
sahilmgandhi 18:6a4db94011d3 1154 /**
sahilmgandhi 18:6a4db94011d3 1155 * @}
sahilmgandhi 18:6a4db94011d3 1156 */
sahilmgandhi 18:6a4db94011d3 1157
sahilmgandhi 18:6a4db94011d3 1158 /** @addtogroup DMA_Private_Functions
sahilmgandhi 18:6a4db94011d3 1159 * @{
sahilmgandhi 18:6a4db94011d3 1160 */
sahilmgandhi 18:6a4db94011d3 1161
sahilmgandhi 18:6a4db94011d3 1162 /**
sahilmgandhi 18:6a4db94011d3 1163 * @brief Sets the DMA Transfer parameter.
sahilmgandhi 18:6a4db94011d3 1164 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1165 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1166 * @param SrcAddress: The source memory Buffer address
sahilmgandhi 18:6a4db94011d3 1167 * @param DstAddress: The destination memory Buffer address
sahilmgandhi 18:6a4db94011d3 1168 * @param DataLength: The length of data to be transferred from source to destination
sahilmgandhi 18:6a4db94011d3 1169 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1170 */
sahilmgandhi 18:6a4db94011d3 1171 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
sahilmgandhi 18:6a4db94011d3 1172 {
sahilmgandhi 18:6a4db94011d3 1173 /* Clear DBM bit */
sahilmgandhi 18:6a4db94011d3 1174 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
sahilmgandhi 18:6a4db94011d3 1175
sahilmgandhi 18:6a4db94011d3 1176 /* Configure DMA Stream data length */
sahilmgandhi 18:6a4db94011d3 1177 hdma->Instance->NDTR = DataLength;
sahilmgandhi 18:6a4db94011d3 1178
sahilmgandhi 18:6a4db94011d3 1179 /* Peripheral to Memory */
sahilmgandhi 18:6a4db94011d3 1180 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
sahilmgandhi 18:6a4db94011d3 1181 {
sahilmgandhi 18:6a4db94011d3 1182 /* Configure DMA Stream destination address */
sahilmgandhi 18:6a4db94011d3 1183 hdma->Instance->PAR = DstAddress;
sahilmgandhi 18:6a4db94011d3 1184
sahilmgandhi 18:6a4db94011d3 1185 /* Configure DMA Stream source address */
sahilmgandhi 18:6a4db94011d3 1186 hdma->Instance->M0AR = SrcAddress;
sahilmgandhi 18:6a4db94011d3 1187 }
sahilmgandhi 18:6a4db94011d3 1188 /* Memory to Peripheral */
sahilmgandhi 18:6a4db94011d3 1189 else
sahilmgandhi 18:6a4db94011d3 1190 {
sahilmgandhi 18:6a4db94011d3 1191 /* Configure DMA Stream source address */
sahilmgandhi 18:6a4db94011d3 1192 hdma->Instance->PAR = SrcAddress;
sahilmgandhi 18:6a4db94011d3 1193
sahilmgandhi 18:6a4db94011d3 1194 /* Configure DMA Stream destination address */
sahilmgandhi 18:6a4db94011d3 1195 hdma->Instance->M0AR = DstAddress;
sahilmgandhi 18:6a4db94011d3 1196 }
sahilmgandhi 18:6a4db94011d3 1197 }
sahilmgandhi 18:6a4db94011d3 1198
sahilmgandhi 18:6a4db94011d3 1199 /**
sahilmgandhi 18:6a4db94011d3 1200 * @brief Returns the DMA Stream base address depending on stream number
sahilmgandhi 18:6a4db94011d3 1201 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1202 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1203 * @retval Stream base address
sahilmgandhi 18:6a4db94011d3 1204 */
sahilmgandhi 18:6a4db94011d3 1205 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1206 {
sahilmgandhi 18:6a4db94011d3 1207 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
sahilmgandhi 18:6a4db94011d3 1208
sahilmgandhi 18:6a4db94011d3 1209 /* lookup table for necessary bitshift of flags within status registers */
sahilmgandhi 18:6a4db94011d3 1210 static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
sahilmgandhi 18:6a4db94011d3 1211 hdma->StreamIndex = flagBitshiftOffset[stream_number];
sahilmgandhi 18:6a4db94011d3 1212
sahilmgandhi 18:6a4db94011d3 1213 if (stream_number > 3U)
sahilmgandhi 18:6a4db94011d3 1214 {
sahilmgandhi 18:6a4db94011d3 1215 /* return pointer to HISR and HIFCR */
sahilmgandhi 18:6a4db94011d3 1216 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
sahilmgandhi 18:6a4db94011d3 1217 }
sahilmgandhi 18:6a4db94011d3 1218 else
sahilmgandhi 18:6a4db94011d3 1219 {
sahilmgandhi 18:6a4db94011d3 1220 /* return pointer to LISR and LIFCR */
sahilmgandhi 18:6a4db94011d3 1221 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
sahilmgandhi 18:6a4db94011d3 1222 }
sahilmgandhi 18:6a4db94011d3 1223
sahilmgandhi 18:6a4db94011d3 1224 return hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 1225 }
sahilmgandhi 18:6a4db94011d3 1226
sahilmgandhi 18:6a4db94011d3 1227 /**
sahilmgandhi 18:6a4db94011d3 1228 * @brief Checks compatibility between FIFO threshold level and size of the memory burst
sahilmgandhi 18:6a4db94011d3 1229 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1230 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1231 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1232 */
sahilmgandhi 18:6a4db94011d3 1233 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1234 {
sahilmgandhi 18:6a4db94011d3 1235 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1236 uint32_t tmp = hdma->Init.FIFOThreshold;
sahilmgandhi 18:6a4db94011d3 1237
sahilmgandhi 18:6a4db94011d3 1238 /* Memory Data size equal to Byte */
sahilmgandhi 18:6a4db94011d3 1239 if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
sahilmgandhi 18:6a4db94011d3 1240 {
sahilmgandhi 18:6a4db94011d3 1241 switch (tmp)
sahilmgandhi 18:6a4db94011d3 1242 {
sahilmgandhi 18:6a4db94011d3 1243 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
sahilmgandhi 18:6a4db94011d3 1244 if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
sahilmgandhi 18:6a4db94011d3 1245 {
sahilmgandhi 18:6a4db94011d3 1246 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1247 }
sahilmgandhi 18:6a4db94011d3 1248 break;
sahilmgandhi 18:6a4db94011d3 1249 case DMA_FIFO_THRESHOLD_HALFFULL:
sahilmgandhi 18:6a4db94011d3 1250 if(hdma->Init.MemBurst == DMA_MBURST_INC16)
sahilmgandhi 18:6a4db94011d3 1251 {
sahilmgandhi 18:6a4db94011d3 1252 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1253 }
sahilmgandhi 18:6a4db94011d3 1254 break;
sahilmgandhi 18:6a4db94011d3 1255 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
sahilmgandhi 18:6a4db94011d3 1256 if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
sahilmgandhi 18:6a4db94011d3 1257 {
sahilmgandhi 18:6a4db94011d3 1258 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1259 }
sahilmgandhi 18:6a4db94011d3 1260 break;
sahilmgandhi 18:6a4db94011d3 1261 case DMA_FIFO_THRESHOLD_FULL:
sahilmgandhi 18:6a4db94011d3 1262 break;
sahilmgandhi 18:6a4db94011d3 1263 default:
sahilmgandhi 18:6a4db94011d3 1264 break;
sahilmgandhi 18:6a4db94011d3 1265 }
sahilmgandhi 18:6a4db94011d3 1266 }
sahilmgandhi 18:6a4db94011d3 1267
sahilmgandhi 18:6a4db94011d3 1268 /* Memory Data size equal to Half-Word */
sahilmgandhi 18:6a4db94011d3 1269 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
sahilmgandhi 18:6a4db94011d3 1270 {
sahilmgandhi 18:6a4db94011d3 1271 switch (tmp)
sahilmgandhi 18:6a4db94011d3 1272 {
sahilmgandhi 18:6a4db94011d3 1273 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
sahilmgandhi 18:6a4db94011d3 1274 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1275 break;
sahilmgandhi 18:6a4db94011d3 1276 case DMA_FIFO_THRESHOLD_HALFFULL:
sahilmgandhi 18:6a4db94011d3 1277 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
sahilmgandhi 18:6a4db94011d3 1278 {
sahilmgandhi 18:6a4db94011d3 1279 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1280 }
sahilmgandhi 18:6a4db94011d3 1281 break;
sahilmgandhi 18:6a4db94011d3 1282 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
sahilmgandhi 18:6a4db94011d3 1283 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1284 break;
sahilmgandhi 18:6a4db94011d3 1285 case DMA_FIFO_THRESHOLD_FULL:
sahilmgandhi 18:6a4db94011d3 1286 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
sahilmgandhi 18:6a4db94011d3 1287 {
sahilmgandhi 18:6a4db94011d3 1288 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1289 }
sahilmgandhi 18:6a4db94011d3 1290 break;
sahilmgandhi 18:6a4db94011d3 1291 default:
sahilmgandhi 18:6a4db94011d3 1292 break;
sahilmgandhi 18:6a4db94011d3 1293 }
sahilmgandhi 18:6a4db94011d3 1294 }
sahilmgandhi 18:6a4db94011d3 1295
sahilmgandhi 18:6a4db94011d3 1296 /* Memory Data size equal to Word */
sahilmgandhi 18:6a4db94011d3 1297 else
sahilmgandhi 18:6a4db94011d3 1298 {
sahilmgandhi 18:6a4db94011d3 1299 switch (tmp)
sahilmgandhi 18:6a4db94011d3 1300 {
sahilmgandhi 18:6a4db94011d3 1301 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
sahilmgandhi 18:6a4db94011d3 1302 case DMA_FIFO_THRESHOLD_HALFFULL:
sahilmgandhi 18:6a4db94011d3 1303 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
sahilmgandhi 18:6a4db94011d3 1304 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1305 break;
sahilmgandhi 18:6a4db94011d3 1306 case DMA_FIFO_THRESHOLD_FULL:
sahilmgandhi 18:6a4db94011d3 1307 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
sahilmgandhi 18:6a4db94011d3 1308 {
sahilmgandhi 18:6a4db94011d3 1309 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1310 }
sahilmgandhi 18:6a4db94011d3 1311 break;
sahilmgandhi 18:6a4db94011d3 1312 default:
sahilmgandhi 18:6a4db94011d3 1313 break;
sahilmgandhi 18:6a4db94011d3 1314 }
sahilmgandhi 18:6a4db94011d3 1315 }
sahilmgandhi 18:6a4db94011d3 1316
sahilmgandhi 18:6a4db94011d3 1317 return status;
sahilmgandhi 18:6a4db94011d3 1318 }
sahilmgandhi 18:6a4db94011d3 1319
sahilmgandhi 18:6a4db94011d3 1320 /**
sahilmgandhi 18:6a4db94011d3 1321 * @}
sahilmgandhi 18:6a4db94011d3 1322 */
sahilmgandhi 18:6a4db94011d3 1323
sahilmgandhi 18:6a4db94011d3 1324 #endif /* HAL_DMA_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1325 /**
sahilmgandhi 18:6a4db94011d3 1326 * @}
sahilmgandhi 18:6a4db94011d3 1327 */
sahilmgandhi 18:6a4db94011d3 1328
sahilmgandhi 18:6a4db94011d3 1329 /**
sahilmgandhi 18:6a4db94011d3 1330 * @}
sahilmgandhi 18:6a4db94011d3 1331 */
sahilmgandhi 18:6a4db94011d3 1332
sahilmgandhi 18:6a4db94011d3 1333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/