MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_def.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief This file contains HAL common defines, enumeration, macros and
sahilmgandhi 18:6a4db94011d3 8 * structures definitions.
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * @attention
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 15 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 16 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 17 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 19 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 20 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 22 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 23 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 *
sahilmgandhi 18:6a4db94011d3 36 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 37 */
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 40 #ifndef __STM32F4xx_HAL_DEF
sahilmgandhi 18:6a4db94011d3 41 #define __STM32F4xx_HAL_DEF
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 44 extern "C" {
sahilmgandhi 18:6a4db94011d3 45 #endif
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 48 #include "stm32f4xx.h"
sahilmgandhi 18:6a4db94011d3 49 #include "stm32_hal_legacy.h"
sahilmgandhi 18:6a4db94011d3 50 #include <stdio.h>
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 /**
sahilmgandhi 18:6a4db94011d3 55 * @brief HAL Status structures definition
sahilmgandhi 18:6a4db94011d3 56 */
sahilmgandhi 18:6a4db94011d3 57 typedef enum
sahilmgandhi 18:6a4db94011d3 58 {
sahilmgandhi 18:6a4db94011d3 59 HAL_OK = 0x00U,
sahilmgandhi 18:6a4db94011d3 60 HAL_ERROR = 0x01U,
sahilmgandhi 18:6a4db94011d3 61 HAL_BUSY = 0x02U,
sahilmgandhi 18:6a4db94011d3 62 HAL_TIMEOUT = 0x03U
sahilmgandhi 18:6a4db94011d3 63 } HAL_StatusTypeDef;
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /**
sahilmgandhi 18:6a4db94011d3 66 * @brief HAL Lock structures definition
sahilmgandhi 18:6a4db94011d3 67 */
sahilmgandhi 18:6a4db94011d3 68 typedef enum
sahilmgandhi 18:6a4db94011d3 69 {
sahilmgandhi 18:6a4db94011d3 70 HAL_UNLOCKED = 0x00U,
sahilmgandhi 18:6a4db94011d3 71 HAL_LOCKED = 0x01U
sahilmgandhi 18:6a4db94011d3 72 } HAL_LockTypeDef;
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 75 #define HAL_MAX_DELAY 0xFFFFFFFFU
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
sahilmgandhi 18:6a4db94011d3 78 #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
sahilmgandhi 18:6a4db94011d3 81 do{ \
sahilmgandhi 18:6a4db94011d3 82 (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
sahilmgandhi 18:6a4db94011d3 83 (__DMA_HANDLE__).Parent = (__HANDLE__); \
sahilmgandhi 18:6a4db94011d3 84 } while(0)
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 #define UNUSED(x) ((void)(x))
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /** @brief Reset the Handle's State field.
sahilmgandhi 18:6a4db94011d3 89 * @param __HANDLE__: specifies the Peripheral Handle.
sahilmgandhi 18:6a4db94011d3 90 * @note This macro can be used for the following purpose:
sahilmgandhi 18:6a4db94011d3 91 * - When the Handle is declared as local variable; before passing it as parameter
sahilmgandhi 18:6a4db94011d3 92 * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
sahilmgandhi 18:6a4db94011d3 93 * to set to 0 the Handle's "State" field.
sahilmgandhi 18:6a4db94011d3 94 * Otherwise, "State" field may have any random value and the first time the function
sahilmgandhi 18:6a4db94011d3 95 * HAL_PPP_Init() is called, the low level hardware initialization will be missed
sahilmgandhi 18:6a4db94011d3 96 * (i.e. HAL_PPP_MspInit() will not be executed).
sahilmgandhi 18:6a4db94011d3 97 * - When there is a need to reconfigure the low level hardware: instead of calling
sahilmgandhi 18:6a4db94011d3 98 * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
sahilmgandhi 18:6a4db94011d3 99 * In this later function, when the Handle's "State" field is set to 0, it will execute the function
sahilmgandhi 18:6a4db94011d3 100 * HAL_PPP_MspInit() which will reconfigure the low level hardware.
sahilmgandhi 18:6a4db94011d3 101 * @retval None
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103 #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 #if (USE_RTOS == 1)
sahilmgandhi 18:6a4db94011d3 106 /* Reserved for future use */
sahilmgandhi 18:6a4db94011d3 107 #error "USE_RTOS should be 0 in the current HAL release"
sahilmgandhi 18:6a4db94011d3 108 #else
sahilmgandhi 18:6a4db94011d3 109 #define __HAL_LOCK(__HANDLE__) \
sahilmgandhi 18:6a4db94011d3 110 do{ \
sahilmgandhi 18:6a4db94011d3 111 if((__HANDLE__)->Lock == HAL_LOCKED) \
sahilmgandhi 18:6a4db94011d3 112 { \
sahilmgandhi 18:6a4db94011d3 113 return HAL_BUSY; \
sahilmgandhi 18:6a4db94011d3 114 } \
sahilmgandhi 18:6a4db94011d3 115 else \
sahilmgandhi 18:6a4db94011d3 116 { \
sahilmgandhi 18:6a4db94011d3 117 (__HANDLE__)->Lock = HAL_LOCKED; \
sahilmgandhi 18:6a4db94011d3 118 } \
sahilmgandhi 18:6a4db94011d3 119 }while (0)
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 #define __HAL_UNLOCK(__HANDLE__) \
sahilmgandhi 18:6a4db94011d3 122 do{ \
sahilmgandhi 18:6a4db94011d3 123 (__HANDLE__)->Lock = HAL_UNLOCKED; \
sahilmgandhi 18:6a4db94011d3 124 }while (0)
sahilmgandhi 18:6a4db94011d3 125 #if defined (__CC_ARM)
sahilmgandhi 18:6a4db94011d3 126 #pragma diag_suppress 3731
sahilmgandhi 18:6a4db94011d3 127 #endif
sahilmgandhi 18:6a4db94011d3 128 static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
sahilmgandhi 18:6a4db94011d3 129 {
sahilmgandhi 18:6a4db94011d3 130 uint32_t newValue;
sahilmgandhi 18:6a4db94011d3 131 do {
sahilmgandhi 18:6a4db94011d3 132 newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 } while (__STREXW(newValue,(volatile unsigned long*) ptr));
sahilmgandhi 18:6a4db94011d3 135 }
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
sahilmgandhi 18:6a4db94011d3 139 {
sahilmgandhi 18:6a4db94011d3 140 uint32_t newValue;
sahilmgandhi 18:6a4db94011d3 141 do {
sahilmgandhi 18:6a4db94011d3 142 newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 } while (__STREXW(newValue,(volatile unsigned long*) ptr));
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 #endif /* USE_RTOS */
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 #if defined ( __GNUC__ ) && !defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 150 #ifndef __weak
sahilmgandhi 18:6a4db94011d3 151 #define __weak __attribute__((weak))
sahilmgandhi 18:6a4db94011d3 152 #endif /* __weak */
sahilmgandhi 18:6a4db94011d3 153 #ifndef __packed
sahilmgandhi 18:6a4db94011d3 154 #define __packed __attribute__((__packed__))
sahilmgandhi 18:6a4db94011d3 155 #endif /* __packed */
sahilmgandhi 18:6a4db94011d3 156 #endif /* __GNUC__ */
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
sahilmgandhi 18:6a4db94011d3 160 #if defined (__GNUC__) /* GNU Compiler */
sahilmgandhi 18:6a4db94011d3 161 #ifndef __ALIGN_END
sahilmgandhi 18:6a4db94011d3 162 #define __ALIGN_END __attribute__ ((aligned (4)))
sahilmgandhi 18:6a4db94011d3 163 #endif /* __ALIGN_END */
sahilmgandhi 18:6a4db94011d3 164 #ifndef __ALIGN_BEGIN
sahilmgandhi 18:6a4db94011d3 165 #define __ALIGN_BEGIN
sahilmgandhi 18:6a4db94011d3 166 #endif /* __ALIGN_BEGIN */
sahilmgandhi 18:6a4db94011d3 167 #else
sahilmgandhi 18:6a4db94011d3 168 #ifndef __ALIGN_END
sahilmgandhi 18:6a4db94011d3 169 #define __ALIGN_END
sahilmgandhi 18:6a4db94011d3 170 #endif /* __ALIGN_END */
sahilmgandhi 18:6a4db94011d3 171 #ifndef __ALIGN_BEGIN
sahilmgandhi 18:6a4db94011d3 172 #if defined (__CC_ARM) /* ARM Compiler */
sahilmgandhi 18:6a4db94011d3 173 #define __ALIGN_BEGIN __align(4)
sahilmgandhi 18:6a4db94011d3 174 #elif defined (__ICCARM__) /* IAR Compiler */
sahilmgandhi 18:6a4db94011d3 175 #define __ALIGN_BEGIN
sahilmgandhi 18:6a4db94011d3 176 #endif /* __CC_ARM */
sahilmgandhi 18:6a4db94011d3 177 #endif /* __ALIGN_BEGIN */
sahilmgandhi 18:6a4db94011d3 178 #endif /* __GNUC__ */
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 /**
sahilmgandhi 18:6a4db94011d3 182 * @brief __RAM_FUNC definition
sahilmgandhi 18:6a4db94011d3 183 */
sahilmgandhi 18:6a4db94011d3 184 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 185 /* ARM Compiler
sahilmgandhi 18:6a4db94011d3 186 ------------
sahilmgandhi 18:6a4db94011d3 187 RAM functions are defined using the toolchain options.
sahilmgandhi 18:6a4db94011d3 188 Functions that are executed in RAM should reside in a separate source module.
sahilmgandhi 18:6a4db94011d3 189 Using the 'Options for File' dialog you can simply change the 'Code / Const'
sahilmgandhi 18:6a4db94011d3 190 area of a module to a memory space in physical RAM.
sahilmgandhi 18:6a4db94011d3 191 Available memory areas are declared in the 'Target' tab of the 'Options for Target'
sahilmgandhi 18:6a4db94011d3 192 dialog.
sahilmgandhi 18:6a4db94011d3 193 */
sahilmgandhi 18:6a4db94011d3 194 #define __RAM_FUNC HAL_StatusTypeDef
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 197 /* ICCARM Compiler
sahilmgandhi 18:6a4db94011d3 198 ---------------
sahilmgandhi 18:6a4db94011d3 199 RAM functions are defined using a specific toolchain keyword "__ramfunc".
sahilmgandhi 18:6a4db94011d3 200 */
sahilmgandhi 18:6a4db94011d3 201 #define __RAM_FUNC __ramfunc HAL_StatusTypeDef
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 #elif defined ( __GNUC__ )
sahilmgandhi 18:6a4db94011d3 204 /* GNU Compiler
sahilmgandhi 18:6a4db94011d3 205 ------------
sahilmgandhi 18:6a4db94011d3 206 RAM functions are defined using a specific toolchain attribute
sahilmgandhi 18:6a4db94011d3 207 "__attribute__((section(".RamFunc")))".
sahilmgandhi 18:6a4db94011d3 208 */
sahilmgandhi 18:6a4db94011d3 209 #define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 #endif
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 /**
sahilmgandhi 18:6a4db94011d3 214 * @brief __NOINLINE definition
sahilmgandhi 18:6a4db94011d3 215 */
sahilmgandhi 18:6a4db94011d3 216 #if defined ( __CC_ARM ) || defined ( __GNUC__ )
sahilmgandhi 18:6a4db94011d3 217 /* ARM & GNUCompiler
sahilmgandhi 18:6a4db94011d3 218 ----------------
sahilmgandhi 18:6a4db94011d3 219 */
sahilmgandhi 18:6a4db94011d3 220 #define __NOINLINE __attribute__ ( (noinline) )
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 223 /* ICCARM Compiler
sahilmgandhi 18:6a4db94011d3 224 ---------------
sahilmgandhi 18:6a4db94011d3 225 */
sahilmgandhi 18:6a4db94011d3 226 #define __NOINLINE _Pragma("optimize = no_inline")
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 #endif
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 231 }
sahilmgandhi 18:6a4db94011d3 232 #endif
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 #endif /* ___STM32F4xx_HAL_DEF */
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/