MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_adc.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 8 * functionalities of the Analog to Digital Convertor (ADC) peripheral:
sahilmgandhi 18:6a4db94011d3 9 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 10 * + IO operation functions
sahilmgandhi 18:6a4db94011d3 11 * + State and errors functions
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 @verbatim
sahilmgandhi 18:6a4db94011d3 14 ==============================================================================
sahilmgandhi 18:6a4db94011d3 15 ##### ADC Peripheral features #####
sahilmgandhi 18:6a4db94011d3 16 ==============================================================================
sahilmgandhi 18:6a4db94011d3 17 [..]
sahilmgandhi 18:6a4db94011d3 18 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
sahilmgandhi 18:6a4db94011d3 19 (#) Interrupt generation at the end of conversion, end of injected conversion,
sahilmgandhi 18:6a4db94011d3 20 and in case of analog watchdog or overrun events
sahilmgandhi 18:6a4db94011d3 21 (#) Single and continuous conversion modes.
sahilmgandhi 18:6a4db94011d3 22 (#) Scan mode for automatic conversion of channel 0 to channel x.
sahilmgandhi 18:6a4db94011d3 23 (#) Data alignment with in-built data coherency.
sahilmgandhi 18:6a4db94011d3 24 (#) Channel-wise programmable sampling time.
sahilmgandhi 18:6a4db94011d3 25 (#) External trigger option with configurable polarity for both regular and
sahilmgandhi 18:6a4db94011d3 26 injected conversion.
sahilmgandhi 18:6a4db94011d3 27 (#) Dual/Triple mode (on devices with 2 ADCs or more).
sahilmgandhi 18:6a4db94011d3 28 (#) Configurable DMA data storage in Dual/Triple ADC mode.
sahilmgandhi 18:6a4db94011d3 29 (#) Configurable delay between conversions in Dual/Triple interleaved mode.
sahilmgandhi 18:6a4db94011d3 30 (#) ADC conversion type (refer to the datasheets).
sahilmgandhi 18:6a4db94011d3 31 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
sahilmgandhi 18:6a4db94011d3 32 slower speed.
sahilmgandhi 18:6a4db94011d3 33 (#) ADC input range: VREF(minus) = VIN = VREF(plus).
sahilmgandhi 18:6a4db94011d3 34 (#) DMA request generation during regular channel conversion.
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 38 ==============================================================================
sahilmgandhi 18:6a4db94011d3 39 [..]
sahilmgandhi 18:6a4db94011d3 40 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
sahilmgandhi 18:6a4db94011d3 41 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
sahilmgandhi 18:6a4db94011d3 42 (##) ADC pins configuration
sahilmgandhi 18:6a4db94011d3 43 (+++) Enable the clock for the ADC GPIOs using the following function:
sahilmgandhi 18:6a4db94011d3 44 __HAL_RCC_GPIOx_CLK_ENABLE()
sahilmgandhi 18:6a4db94011d3 45 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
sahilmgandhi 18:6a4db94011d3 46 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
sahilmgandhi 18:6a4db94011d3 47 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
sahilmgandhi 18:6a4db94011d3 48 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
sahilmgandhi 18:6a4db94011d3 49 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
sahilmgandhi 18:6a4db94011d3 50 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
sahilmgandhi 18:6a4db94011d3 51 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
sahilmgandhi 18:6a4db94011d3 52 (+++) Configure and enable two DMA streams stream for managing data
sahilmgandhi 18:6a4db94011d3 53 transfer from peripheral to memory (output stream)
sahilmgandhi 18:6a4db94011d3 54 (+++) Associate the initialized DMA handle to the CRYP DMA handle
sahilmgandhi 18:6a4db94011d3 55 using __HAL_LINKDMA()
sahilmgandhi 18:6a4db94011d3 56 (+++) Configure the priority and enable the NVIC for the transfer complete
sahilmgandhi 18:6a4db94011d3 57 interrupt on the two DMA Streams. The output stream should have higher
sahilmgandhi 18:6a4db94011d3 58 priority than the input stream.
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 *** Configuration of ADC, groups regular/injected, channels parameters ***
sahilmgandhi 18:6a4db94011d3 61 ==============================================================================
sahilmgandhi 18:6a4db94011d3 62 [..]
sahilmgandhi 18:6a4db94011d3 63 (#) Configure the ADC parameters (resolution, data alignment, ...)
sahilmgandhi 18:6a4db94011d3 64 and regular group parameters (conversion trigger, sequencer, ...)
sahilmgandhi 18:6a4db94011d3 65 using function HAL_ADC_Init().
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 (#) Configure the channels for regular group parameters (channel number,
sahilmgandhi 18:6a4db94011d3 68 channel rank into sequencer, ..., into regular group)
sahilmgandhi 18:6a4db94011d3 69 using function HAL_ADC_ConfigChannel().
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 (#) Optionally, configure the injected group parameters (conversion trigger,
sahilmgandhi 18:6a4db94011d3 72 sequencer, ..., of injected group)
sahilmgandhi 18:6a4db94011d3 73 and the channels for injected group parameters (channel number,
sahilmgandhi 18:6a4db94011d3 74 channel rank into sequencer, ..., into injected group)
sahilmgandhi 18:6a4db94011d3 75 using function HAL_ADCEx_InjectedConfigChannel().
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 (#) Optionally, configure the analog watchdog parameters (channels
sahilmgandhi 18:6a4db94011d3 78 monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 (#) Optionally, for devices with several ADC instances: configure the
sahilmgandhi 18:6a4db94011d3 81 multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 *** Execution of ADC conversions ***
sahilmgandhi 18:6a4db94011d3 84 ==============================================================================
sahilmgandhi 18:6a4db94011d3 85 [..]
sahilmgandhi 18:6a4db94011d3 86 (#) ADC driver can be used among three modes: polling, interruption,
sahilmgandhi 18:6a4db94011d3 87 transfer by DMA.
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 *** Polling mode IO operation ***
sahilmgandhi 18:6a4db94011d3 90 =================================
sahilmgandhi 18:6a4db94011d3 91 [..]
sahilmgandhi 18:6a4db94011d3 92 (+) Start the ADC peripheral using HAL_ADC_Start()
sahilmgandhi 18:6a4db94011d3 93 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
sahilmgandhi 18:6a4db94011d3 94 user can specify the value of timeout according to his end application
sahilmgandhi 18:6a4db94011d3 95 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
sahilmgandhi 18:6a4db94011d3 96 (+) Stop the ADC peripheral using HAL_ADC_Stop()
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 *** Interrupt mode IO operation ***
sahilmgandhi 18:6a4db94011d3 99 ===================================
sahilmgandhi 18:6a4db94011d3 100 [..]
sahilmgandhi 18:6a4db94011d3 101 (+) Start the ADC peripheral using HAL_ADC_Start_IT()
sahilmgandhi 18:6a4db94011d3 102 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
sahilmgandhi 18:6a4db94011d3 103 (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 104 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
sahilmgandhi 18:6a4db94011d3 105 (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 106 add his own code by customization of function pointer HAL_ADC_ErrorCallback
sahilmgandhi 18:6a4db94011d3 107 (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 *** DMA mode IO operation ***
sahilmgandhi 18:6a4db94011d3 110 ==============================
sahilmgandhi 18:6a4db94011d3 111 [..]
sahilmgandhi 18:6a4db94011d3 112 (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
sahilmgandhi 18:6a4db94011d3 113 of data to be transferred at each end of conversion
sahilmgandhi 18:6a4db94011d3 114 (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 115 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
sahilmgandhi 18:6a4db94011d3 116 (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 117 add his own code by customization of function pointer HAL_ADC_ErrorCallback
sahilmgandhi 18:6a4db94011d3 118 (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 *** ADC HAL driver macros list ***
sahilmgandhi 18:6a4db94011d3 121 =============================================
sahilmgandhi 18:6a4db94011d3 122 [..]
sahilmgandhi 18:6a4db94011d3 123 Below the list of most used macros in ADC HAL driver.
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 (+) __HAL_ADC_ENABLE : Enable the ADC peripheral
sahilmgandhi 18:6a4db94011d3 126 (+) __HAL_ADC_DISABLE : Disable the ADC peripheral
sahilmgandhi 18:6a4db94011d3 127 (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
sahilmgandhi 18:6a4db94011d3 128 (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
sahilmgandhi 18:6a4db94011d3 129 (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
sahilmgandhi 18:6a4db94011d3 130 (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
sahilmgandhi 18:6a4db94011d3 131 (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
sahilmgandhi 18:6a4db94011d3 132 (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 [..]
sahilmgandhi 18:6a4db94011d3 135 (@) You can refer to the ADC HAL driver header file for more useful macros
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 *** Deinitialization of ADC ***
sahilmgandhi 18:6a4db94011d3 138 ==============================================================================
sahilmgandhi 18:6a4db94011d3 139 [..]
sahilmgandhi 18:6a4db94011d3 140 (#) Disable the ADC interface
sahilmgandhi 18:6a4db94011d3 141 (++) ADC clock can be hard reset and disabled at RCC top level.
sahilmgandhi 18:6a4db94011d3 142 (++) Hard reset of ADC peripherals
sahilmgandhi 18:6a4db94011d3 143 using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
sahilmgandhi 18:6a4db94011d3 144 (++) ADC clock disable using the equivalent macro/functions as configuration step.
sahilmgandhi 18:6a4db94011d3 145 (+++) Example:
sahilmgandhi 18:6a4db94011d3 146 Into HAL_ADC_MspDeInit() (recommended code location) or with
sahilmgandhi 18:6a4db94011d3 147 other device clock parameters configuration:
sahilmgandhi 18:6a4db94011d3 148 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
sahilmgandhi 18:6a4db94011d3 149 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
sahilmgandhi 18:6a4db94011d3 150 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
sahilmgandhi 18:6a4db94011d3 151 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 (#) ADC pins configuration
sahilmgandhi 18:6a4db94011d3 154 (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 (#) Optionally, in case of usage of ADC with interruptions:
sahilmgandhi 18:6a4db94011d3 157 (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 (#) Optionally, in case of usage of DMA:
sahilmgandhi 18:6a4db94011d3 160 (++) Deinitialize the DMA using function HAL_DMA_DeInit().
sahilmgandhi 18:6a4db94011d3 161 (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 @endverbatim
sahilmgandhi 18:6a4db94011d3 164 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 165 * @attention
sahilmgandhi 18:6a4db94011d3 166 *
sahilmgandhi 18:6a4db94011d3 167 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 168 *
sahilmgandhi 18:6a4db94011d3 169 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 170 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 171 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 172 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 173 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 174 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 175 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 176 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 177 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 178 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 179 *
sahilmgandhi 18:6a4db94011d3 180 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 181 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 182 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 183 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 184 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 185 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 186 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 187 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 188 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 189 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 190 *
sahilmgandhi 18:6a4db94011d3 191 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 192 */
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 195 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 198 * @{
sahilmgandhi 18:6a4db94011d3 199 */
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 /** @defgroup ADC ADC
sahilmgandhi 18:6a4db94011d3 202 * @brief ADC driver modules
sahilmgandhi 18:6a4db94011d3 203 * @{
sahilmgandhi 18:6a4db94011d3 204 */
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 #ifdef HAL_ADC_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 209 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 210 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 211 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 212 /** @addtogroup ADC_Private_Functions
sahilmgandhi 18:6a4db94011d3 213 * @{
sahilmgandhi 18:6a4db94011d3 214 */
sahilmgandhi 18:6a4db94011d3 215 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 216 static void ADC_Init(ADC_HandleTypeDef* hadc);
sahilmgandhi 18:6a4db94011d3 217 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 218 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 219 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 220 /**
sahilmgandhi 18:6a4db94011d3 221 * @}
sahilmgandhi 18:6a4db94011d3 222 */
sahilmgandhi 18:6a4db94011d3 223 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 224 /** @defgroup ADC_Exported_Functions ADC Exported Functions
sahilmgandhi 18:6a4db94011d3 225 * @{
sahilmgandhi 18:6a4db94011d3 226 */
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 229 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 230 *
sahilmgandhi 18:6a4db94011d3 231 @verbatim
sahilmgandhi 18:6a4db94011d3 232 ===============================================================================
sahilmgandhi 18:6a4db94011d3 233 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 234 ===============================================================================
sahilmgandhi 18:6a4db94011d3 235 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 236 (+) Initialize and configure the ADC.
sahilmgandhi 18:6a4db94011d3 237 (+) De-initialize the ADC.
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 @endverbatim
sahilmgandhi 18:6a4db94011d3 240 * @{
sahilmgandhi 18:6a4db94011d3 241 */
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 /**
sahilmgandhi 18:6a4db94011d3 244 * @brief Initializes the ADCx peripheral according to the specified parameters
sahilmgandhi 18:6a4db94011d3 245 * in the ADC_InitStruct and initializes the ADC MSP.
sahilmgandhi 18:6a4db94011d3 246 *
sahilmgandhi 18:6a4db94011d3 247 * @note This function is used to configure the global features of the ADC (
sahilmgandhi 18:6a4db94011d3 248 * ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
sahilmgandhi 18:6a4db94011d3 249 * the rest of the configuration parameters are specific to the regular
sahilmgandhi 18:6a4db94011d3 250 * channels group (scan mode activation, continuous mode activation,
sahilmgandhi 18:6a4db94011d3 251 * External trigger source and edge, DMA continuous request after the
sahilmgandhi 18:6a4db94011d3 252 * last transfer and End of conversion selection).
sahilmgandhi 18:6a4db94011d3 253 *
sahilmgandhi 18:6a4db94011d3 254 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 255 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 256 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 257 */
sahilmgandhi 18:6a4db94011d3 258 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 259 {
sahilmgandhi 18:6a4db94011d3 260 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /* Check ADC handle */
sahilmgandhi 18:6a4db94011d3 263 if(hadc == NULL)
sahilmgandhi 18:6a4db94011d3 264 {
sahilmgandhi 18:6a4db94011d3 265 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 266 }
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 269 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
sahilmgandhi 18:6a4db94011d3 270 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
sahilmgandhi 18:6a4db94011d3 271 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
sahilmgandhi 18:6a4db94011d3 272 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
sahilmgandhi 18:6a4db94011d3 273 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
sahilmgandhi 18:6a4db94011d3 274 assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
sahilmgandhi 18:6a4db94011d3 275 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
sahilmgandhi 18:6a4db94011d3 276 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
sahilmgandhi 18:6a4db94011d3 277 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
sahilmgandhi 18:6a4db94011d3 278 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
sahilmgandhi 18:6a4db94011d3 279 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
sahilmgandhi 18:6a4db94011d3 282 {
sahilmgandhi 18:6a4db94011d3 283 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
sahilmgandhi 18:6a4db94011d3 284 }
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 if(hadc->State == HAL_ADC_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 287 {
sahilmgandhi 18:6a4db94011d3 288 /* Initialize ADC error code */
sahilmgandhi 18:6a4db94011d3 289 ADC_CLEAR_ERRORCODE(hadc);
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 292 hadc->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 /* Init the low level hardware */
sahilmgandhi 18:6a4db94011d3 295 HAL_ADC_MspInit(hadc);
sahilmgandhi 18:6a4db94011d3 296 }
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 /* Configuration of ADC parameters if previous preliminary actions are */
sahilmgandhi 18:6a4db94011d3 299 /* correctly completed. */
sahilmgandhi 18:6a4db94011d3 300 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
sahilmgandhi 18:6a4db94011d3 301 {
sahilmgandhi 18:6a4db94011d3 302 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 303 ADC_STATE_CLR_SET(hadc->State,
sahilmgandhi 18:6a4db94011d3 304 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
sahilmgandhi 18:6a4db94011d3 305 HAL_ADC_STATE_BUSY_INTERNAL);
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Set ADC parameters */
sahilmgandhi 18:6a4db94011d3 308 ADC_Init(hadc);
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 /* Set ADC error code to none */
sahilmgandhi 18:6a4db94011d3 311 ADC_CLEAR_ERRORCODE(hadc);
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 /* Set the ADC state */
sahilmgandhi 18:6a4db94011d3 314 ADC_STATE_CLR_SET(hadc->State,
sahilmgandhi 18:6a4db94011d3 315 HAL_ADC_STATE_BUSY_INTERNAL,
sahilmgandhi 18:6a4db94011d3 316 HAL_ADC_STATE_READY);
sahilmgandhi 18:6a4db94011d3 317 }
sahilmgandhi 18:6a4db94011d3 318 else
sahilmgandhi 18:6a4db94011d3 319 {
sahilmgandhi 18:6a4db94011d3 320 tmp_hal_status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 321 }
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 324 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 /* Return function status */
sahilmgandhi 18:6a4db94011d3 327 return tmp_hal_status;
sahilmgandhi 18:6a4db94011d3 328 }
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 /**
sahilmgandhi 18:6a4db94011d3 331 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
sahilmgandhi 18:6a4db94011d3 332 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 333 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 334 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 335 */
sahilmgandhi 18:6a4db94011d3 336 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 337 {
sahilmgandhi 18:6a4db94011d3 338 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 /* Check ADC handle */
sahilmgandhi 18:6a4db94011d3 341 if(hadc == NULL)
sahilmgandhi 18:6a4db94011d3 342 {
sahilmgandhi 18:6a4db94011d3 343 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 344 }
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 347 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 350 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 /* Stop potential conversion on going, on regular and injected groups */
sahilmgandhi 18:6a4db94011d3 353 /* Disable ADC peripheral */
sahilmgandhi 18:6a4db94011d3 354 __HAL_ADC_DISABLE(hadc);
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 /* Configuration of ADC parameters if previous preliminary actions are */
sahilmgandhi 18:6a4db94011d3 357 /* correctly completed. */
sahilmgandhi 18:6a4db94011d3 358 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
sahilmgandhi 18:6a4db94011d3 359 {
sahilmgandhi 18:6a4db94011d3 360 /* DeInit the low level hardware */
sahilmgandhi 18:6a4db94011d3 361 HAL_ADC_MspDeInit(hadc);
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 /* Set ADC error code to none */
sahilmgandhi 18:6a4db94011d3 364 ADC_CLEAR_ERRORCODE(hadc);
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 367 hadc->State = HAL_ADC_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 368 }
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 371 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /* Return function status */
sahilmgandhi 18:6a4db94011d3 374 return tmp_hal_status;
sahilmgandhi 18:6a4db94011d3 375 }
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 /**
sahilmgandhi 18:6a4db94011d3 378 * @brief Initializes the ADC MSP.
sahilmgandhi 18:6a4db94011d3 379 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 380 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 381 * @retval None
sahilmgandhi 18:6a4db94011d3 382 */
sahilmgandhi 18:6a4db94011d3 383 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 384 {
sahilmgandhi 18:6a4db94011d3 385 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 386 UNUSED(hadc);
sahilmgandhi 18:6a4db94011d3 387 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 388 the HAL_ADC_MspInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 389 */
sahilmgandhi 18:6a4db94011d3 390 }
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 /**
sahilmgandhi 18:6a4db94011d3 393 * @brief DeInitializes the ADC MSP.
sahilmgandhi 18:6a4db94011d3 394 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 395 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 396 * @retval None
sahilmgandhi 18:6a4db94011d3 397 */
sahilmgandhi 18:6a4db94011d3 398 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 399 {
sahilmgandhi 18:6a4db94011d3 400 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 401 UNUSED(hadc);
sahilmgandhi 18:6a4db94011d3 402 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 403 the HAL_ADC_MspDeInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 404 */
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /**
sahilmgandhi 18:6a4db94011d3 408 * @}
sahilmgandhi 18:6a4db94011d3 409 */
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
sahilmgandhi 18:6a4db94011d3 412 * @brief IO operation functions
sahilmgandhi 18:6a4db94011d3 413 *
sahilmgandhi 18:6a4db94011d3 414 @verbatim
sahilmgandhi 18:6a4db94011d3 415 ===============================================================================
sahilmgandhi 18:6a4db94011d3 416 ##### IO operation functions #####
sahilmgandhi 18:6a4db94011d3 417 ===============================================================================
sahilmgandhi 18:6a4db94011d3 418 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 419 (+) Start conversion of regular channel.
sahilmgandhi 18:6a4db94011d3 420 (+) Stop conversion of regular channel.
sahilmgandhi 18:6a4db94011d3 421 (+) Start conversion of regular channel and enable interrupt.
sahilmgandhi 18:6a4db94011d3 422 (+) Stop conversion of regular channel and disable interrupt.
sahilmgandhi 18:6a4db94011d3 423 (+) Start conversion of regular channel and enable DMA transfer.
sahilmgandhi 18:6a4db94011d3 424 (+) Stop conversion of regular channel and disable DMA transfer.
sahilmgandhi 18:6a4db94011d3 425 (+) Handle ADC interrupt request.
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 @endverbatim
sahilmgandhi 18:6a4db94011d3 428 * @{
sahilmgandhi 18:6a4db94011d3 429 */
sahilmgandhi 18:6a4db94011d3 430
sahilmgandhi 18:6a4db94011d3 431 /**
sahilmgandhi 18:6a4db94011d3 432 * @brief Enables ADC and starts conversion of the regular channels.
sahilmgandhi 18:6a4db94011d3 433 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 434 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 435 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 436 */
sahilmgandhi 18:6a4db94011d3 437 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 438 {
sahilmgandhi 18:6a4db94011d3 439 __IO uint32_t counter = 0U;
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 442 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
sahilmgandhi 18:6a4db94011d3 443 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
sahilmgandhi 18:6a4db94011d3 444
sahilmgandhi 18:6a4db94011d3 445 /* Process locked */
sahilmgandhi 18:6a4db94011d3 446 __HAL_LOCK(hadc);
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /* Enable the ADC peripheral */
sahilmgandhi 18:6a4db94011d3 449 /* Check if ADC peripheral is disabled in order to enable it and wait during
sahilmgandhi 18:6a4db94011d3 450 Tstab time the ADC's stabilization */
sahilmgandhi 18:6a4db94011d3 451 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
sahilmgandhi 18:6a4db94011d3 452 {
sahilmgandhi 18:6a4db94011d3 453 /* Enable the Peripheral */
sahilmgandhi 18:6a4db94011d3 454 __HAL_ADC_ENABLE(hadc);
sahilmgandhi 18:6a4db94011d3 455
sahilmgandhi 18:6a4db94011d3 456 /* Delay for ADC stabilization time */
sahilmgandhi 18:6a4db94011d3 457 /* Compute number of CPU cycles to wait for */
sahilmgandhi 18:6a4db94011d3 458 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
sahilmgandhi 18:6a4db94011d3 459 while(counter != 0U)
sahilmgandhi 18:6a4db94011d3 460 {
sahilmgandhi 18:6a4db94011d3 461 counter--;
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 /* Start conversion if ADC is effectively enabled */
sahilmgandhi 18:6a4db94011d3 466 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
sahilmgandhi 18:6a4db94011d3 467 {
sahilmgandhi 18:6a4db94011d3 468 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 469 /* - Clear state bitfield related to regular group conversion results */
sahilmgandhi 18:6a4db94011d3 470 /* - Set state bitfield related to regular group operation */
sahilmgandhi 18:6a4db94011d3 471 ADC_STATE_CLR_SET(hadc->State,
sahilmgandhi 18:6a4db94011d3 472 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
sahilmgandhi 18:6a4db94011d3 473 HAL_ADC_STATE_REG_BUSY);
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /* If conversions on group regular are also triggering group injected, */
sahilmgandhi 18:6a4db94011d3 476 /* update ADC state. */
sahilmgandhi 18:6a4db94011d3 477 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
sahilmgandhi 18:6a4db94011d3 478 {
sahilmgandhi 18:6a4db94011d3 479 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
sahilmgandhi 18:6a4db94011d3 480 }
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 /* State machine update: Check if an injected conversion is ongoing */
sahilmgandhi 18:6a4db94011d3 483 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
sahilmgandhi 18:6a4db94011d3 484 {
sahilmgandhi 18:6a4db94011d3 485 /* Reset ADC error code fields related to conversions on group regular */
sahilmgandhi 18:6a4db94011d3 486 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
sahilmgandhi 18:6a4db94011d3 487 }
sahilmgandhi 18:6a4db94011d3 488 else
sahilmgandhi 18:6a4db94011d3 489 {
sahilmgandhi 18:6a4db94011d3 490 /* Reset ADC all error code fields */
sahilmgandhi 18:6a4db94011d3 491 ADC_CLEAR_ERRORCODE(hadc);
sahilmgandhi 18:6a4db94011d3 492 }
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 495 /* Unlock before starting ADC conversions: in case of potential */
sahilmgandhi 18:6a4db94011d3 496 /* interruption, to let the process to ADC IRQ Handler. */
sahilmgandhi 18:6a4db94011d3 497 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 /* Clear regular group conversion flag and overrun flag */
sahilmgandhi 18:6a4db94011d3 500 /* (To ensure of no unknown state from potential previous ADC operations) */
sahilmgandhi 18:6a4db94011d3 501 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 /* Check if Multimode enabled */
sahilmgandhi 18:6a4db94011d3 504 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
sahilmgandhi 18:6a4db94011d3 505 {
sahilmgandhi 18:6a4db94011d3 506 /* if no external trigger present enable software conversion of regular channels */
sahilmgandhi 18:6a4db94011d3 507 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
sahilmgandhi 18:6a4db94011d3 508 {
sahilmgandhi 18:6a4db94011d3 509 /* Enable the selected ADC software conversion for regular group */
sahilmgandhi 18:6a4db94011d3 510 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
sahilmgandhi 18:6a4db94011d3 511 }
sahilmgandhi 18:6a4db94011d3 512 }
sahilmgandhi 18:6a4db94011d3 513 else
sahilmgandhi 18:6a4db94011d3 514 {
sahilmgandhi 18:6a4db94011d3 515 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
sahilmgandhi 18:6a4db94011d3 516 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
sahilmgandhi 18:6a4db94011d3 517 {
sahilmgandhi 18:6a4db94011d3 518 /* Enable the selected ADC software conversion for regular group */
sahilmgandhi 18:6a4db94011d3 519 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
sahilmgandhi 18:6a4db94011d3 520 }
sahilmgandhi 18:6a4db94011d3 521 }
sahilmgandhi 18:6a4db94011d3 522 }
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 /* Return function status */
sahilmgandhi 18:6a4db94011d3 525 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 526 }
sahilmgandhi 18:6a4db94011d3 527
sahilmgandhi 18:6a4db94011d3 528 /**
sahilmgandhi 18:6a4db94011d3 529 * @brief Disables ADC and stop conversion of regular channels.
sahilmgandhi 18:6a4db94011d3 530 *
sahilmgandhi 18:6a4db94011d3 531 * @note Caution: This function will stop also injected channels.
sahilmgandhi 18:6a4db94011d3 532 *
sahilmgandhi 18:6a4db94011d3 533 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 534 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 535 *
sahilmgandhi 18:6a4db94011d3 536 * @retval HAL status.
sahilmgandhi 18:6a4db94011d3 537 */
sahilmgandhi 18:6a4db94011d3 538 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 541 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 /* Process locked */
sahilmgandhi 18:6a4db94011d3 544 __HAL_LOCK(hadc);
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 /* Stop potential conversion on going, on regular and injected groups */
sahilmgandhi 18:6a4db94011d3 547 /* Disable ADC peripheral */
sahilmgandhi 18:6a4db94011d3 548 __HAL_ADC_DISABLE(hadc);
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 /* Check if ADC is effectively disabled */
sahilmgandhi 18:6a4db94011d3 551 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
sahilmgandhi 18:6a4db94011d3 552 {
sahilmgandhi 18:6a4db94011d3 553 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 554 ADC_STATE_CLR_SET(hadc->State,
sahilmgandhi 18:6a4db94011d3 555 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
sahilmgandhi 18:6a4db94011d3 556 HAL_ADC_STATE_READY);
sahilmgandhi 18:6a4db94011d3 557 }
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 560 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 /* Return function status */
sahilmgandhi 18:6a4db94011d3 563 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 564 }
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 /**
sahilmgandhi 18:6a4db94011d3 567 * @brief Poll for regular conversion complete
sahilmgandhi 18:6a4db94011d3 568 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
sahilmgandhi 18:6a4db94011d3 569 * conversion) are cleared by this function.
sahilmgandhi 18:6a4db94011d3 570 * @note This function cannot be used in a particular setup: ADC configured
sahilmgandhi 18:6a4db94011d3 571 * in DMA mode and polling for end of each conversion (ADC init
sahilmgandhi 18:6a4db94011d3 572 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
sahilmgandhi 18:6a4db94011d3 573 * In this case, DMA resets the flag EOC and polling cannot be
sahilmgandhi 18:6a4db94011d3 574 * performed on each conversion. Nevertheless, polling can still
sahilmgandhi 18:6a4db94011d3 575 * be performed on the complete sequence.
sahilmgandhi 18:6a4db94011d3 576 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 577 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 578 * @param Timeout: Timeout value in millisecond.
sahilmgandhi 18:6a4db94011d3 579 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 580 */
sahilmgandhi 18:6a4db94011d3 581 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 582 {
sahilmgandhi 18:6a4db94011d3 583 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 584
sahilmgandhi 18:6a4db94011d3 585 /* Verification that ADC configuration is compliant with polling for */
sahilmgandhi 18:6a4db94011d3 586 /* each conversion: */
sahilmgandhi 18:6a4db94011d3 587 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
sahilmgandhi 18:6a4db94011d3 588 /* several ranks and polling for end of each conversion. */
sahilmgandhi 18:6a4db94011d3 589 /* For code simplicity sake, this particular case is generalized to */
sahilmgandhi 18:6a4db94011d3 590 /* ADC configured in DMA mode and polling for end of each conversion. */
sahilmgandhi 18:6a4db94011d3 591 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
sahilmgandhi 18:6a4db94011d3 592 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
sahilmgandhi 18:6a4db94011d3 593 {
sahilmgandhi 18:6a4db94011d3 594 /* Update ADC state machine to error */
sahilmgandhi 18:6a4db94011d3 595 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
sahilmgandhi 18:6a4db94011d3 596
sahilmgandhi 18:6a4db94011d3 597 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 598 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 601 }
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 /* Get tick */
sahilmgandhi 18:6a4db94011d3 604 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 /* Check End of conversion flag */
sahilmgandhi 18:6a4db94011d3 607 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
sahilmgandhi 18:6a4db94011d3 608 {
sahilmgandhi 18:6a4db94011d3 609 /* Check if timeout is disabled (set to infinite wait) */
sahilmgandhi 18:6a4db94011d3 610 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 611 {
sahilmgandhi 18:6a4db94011d3 612 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 613 {
sahilmgandhi 18:6a4db94011d3 614 /* Update ADC state machine to timeout */
sahilmgandhi 18:6a4db94011d3 615 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
sahilmgandhi 18:6a4db94011d3 616
sahilmgandhi 18:6a4db94011d3 617 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 618 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 621 }
sahilmgandhi 18:6a4db94011d3 622 }
sahilmgandhi 18:6a4db94011d3 623 }
sahilmgandhi 18:6a4db94011d3 624
sahilmgandhi 18:6a4db94011d3 625 /* Clear regular group conversion flag */
sahilmgandhi 18:6a4db94011d3 626 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
sahilmgandhi 18:6a4db94011d3 627
sahilmgandhi 18:6a4db94011d3 628 /* Update ADC state machine */
sahilmgandhi 18:6a4db94011d3 629 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
sahilmgandhi 18:6a4db94011d3 630
sahilmgandhi 18:6a4db94011d3 631 /* Determine whether any further conversion upcoming on group regular */
sahilmgandhi 18:6a4db94011d3 632 /* by external trigger, continuous mode or scan sequence on going. */
sahilmgandhi 18:6a4db94011d3 633 /* Note: On STM32F4, there is no independent flag of end of sequence. */
sahilmgandhi 18:6a4db94011d3 634 /* The test of scan sequence on going is done either with scan */
sahilmgandhi 18:6a4db94011d3 635 /* sequence disabled or with end of conversion flag set to */
sahilmgandhi 18:6a4db94011d3 636 /* of end of sequence. */
sahilmgandhi 18:6a4db94011d3 637 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
sahilmgandhi 18:6a4db94011d3 638 (hadc->Init.ContinuousConvMode == DISABLE) &&
sahilmgandhi 18:6a4db94011d3 639 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
sahilmgandhi 18:6a4db94011d3 640 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
sahilmgandhi 18:6a4db94011d3 641 {
sahilmgandhi 18:6a4db94011d3 642 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 643 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
sahilmgandhi 18:6a4db94011d3 644
sahilmgandhi 18:6a4db94011d3 645 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
sahilmgandhi 18:6a4db94011d3 646 {
sahilmgandhi 18:6a4db94011d3 647 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
sahilmgandhi 18:6a4db94011d3 648 }
sahilmgandhi 18:6a4db94011d3 649 }
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651 /* Return ADC state */
sahilmgandhi 18:6a4db94011d3 652 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 653 }
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 /**
sahilmgandhi 18:6a4db94011d3 656 * @brief Poll for conversion event
sahilmgandhi 18:6a4db94011d3 657 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 658 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 659 * @param EventType: the ADC event type.
sahilmgandhi 18:6a4db94011d3 660 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 661 * @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
sahilmgandhi 18:6a4db94011d3 662 * @arg ADC_OVR_EVENT: ADC Overrun event.
sahilmgandhi 18:6a4db94011d3 663 * @param Timeout: Timeout value in millisecond.
sahilmgandhi 18:6a4db94011d3 664 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 665 */
sahilmgandhi 18:6a4db94011d3 666 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 667 {
sahilmgandhi 18:6a4db94011d3 668 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 671 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
sahilmgandhi 18:6a4db94011d3 672 assert_param(IS_ADC_EVENT_TYPE(EventType));
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 /* Get tick */
sahilmgandhi 18:6a4db94011d3 675 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 676
sahilmgandhi 18:6a4db94011d3 677 /* Check selected event flag */
sahilmgandhi 18:6a4db94011d3 678 while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
sahilmgandhi 18:6a4db94011d3 679 {
sahilmgandhi 18:6a4db94011d3 680 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 681 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 682 {
sahilmgandhi 18:6a4db94011d3 683 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 684 {
sahilmgandhi 18:6a4db94011d3 685 /* Update ADC state machine to timeout */
sahilmgandhi 18:6a4db94011d3 686 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
sahilmgandhi 18:6a4db94011d3 687
sahilmgandhi 18:6a4db94011d3 688 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 689 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 692 }
sahilmgandhi 18:6a4db94011d3 693 }
sahilmgandhi 18:6a4db94011d3 694 }
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 /* Analog watchdog (level out of window) event */
sahilmgandhi 18:6a4db94011d3 697 if(EventType == ADC_AWD_EVENT)
sahilmgandhi 18:6a4db94011d3 698 {
sahilmgandhi 18:6a4db94011d3 699 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 700 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
sahilmgandhi 18:6a4db94011d3 701
sahilmgandhi 18:6a4db94011d3 702 /* Clear ADC analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 703 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
sahilmgandhi 18:6a4db94011d3 704 }
sahilmgandhi 18:6a4db94011d3 705 /* Overrun event */
sahilmgandhi 18:6a4db94011d3 706 else
sahilmgandhi 18:6a4db94011d3 707 {
sahilmgandhi 18:6a4db94011d3 708 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 709 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
sahilmgandhi 18:6a4db94011d3 710 /* Set ADC error code to overrun */
sahilmgandhi 18:6a4db94011d3 711 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
sahilmgandhi 18:6a4db94011d3 712
sahilmgandhi 18:6a4db94011d3 713 /* Clear ADC overrun flag */
sahilmgandhi 18:6a4db94011d3 714 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 715 }
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 /* Return ADC state */
sahilmgandhi 18:6a4db94011d3 718 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 719 }
sahilmgandhi 18:6a4db94011d3 720
sahilmgandhi 18:6a4db94011d3 721
sahilmgandhi 18:6a4db94011d3 722 /**
sahilmgandhi 18:6a4db94011d3 723 * @brief Enables the interrupt and starts ADC conversion of regular channels.
sahilmgandhi 18:6a4db94011d3 724 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 725 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 726 * @retval HAL status.
sahilmgandhi 18:6a4db94011d3 727 */
sahilmgandhi 18:6a4db94011d3 728 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 729 {
sahilmgandhi 18:6a4db94011d3 730 __IO uint32_t counter = 0U;
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 733 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
sahilmgandhi 18:6a4db94011d3 734 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
sahilmgandhi 18:6a4db94011d3 735
sahilmgandhi 18:6a4db94011d3 736 /* Process locked */
sahilmgandhi 18:6a4db94011d3 737 __HAL_LOCK(hadc);
sahilmgandhi 18:6a4db94011d3 738
sahilmgandhi 18:6a4db94011d3 739 /* Enable the ADC peripheral */
sahilmgandhi 18:6a4db94011d3 740 /* Check if ADC peripheral is disabled in order to enable it and wait during
sahilmgandhi 18:6a4db94011d3 741 Tstab time the ADC's stabilization */
sahilmgandhi 18:6a4db94011d3 742 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
sahilmgandhi 18:6a4db94011d3 743 {
sahilmgandhi 18:6a4db94011d3 744 /* Enable the Peripheral */
sahilmgandhi 18:6a4db94011d3 745 __HAL_ADC_ENABLE(hadc);
sahilmgandhi 18:6a4db94011d3 746
sahilmgandhi 18:6a4db94011d3 747 /* Delay for ADC stabilization time */
sahilmgandhi 18:6a4db94011d3 748 /* Compute number of CPU cycles to wait for */
sahilmgandhi 18:6a4db94011d3 749 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
sahilmgandhi 18:6a4db94011d3 750 while(counter != 0U)
sahilmgandhi 18:6a4db94011d3 751 {
sahilmgandhi 18:6a4db94011d3 752 counter--;
sahilmgandhi 18:6a4db94011d3 753 }
sahilmgandhi 18:6a4db94011d3 754 }
sahilmgandhi 18:6a4db94011d3 755
sahilmgandhi 18:6a4db94011d3 756 /* Start conversion if ADC is effectively enabled */
sahilmgandhi 18:6a4db94011d3 757 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
sahilmgandhi 18:6a4db94011d3 758 {
sahilmgandhi 18:6a4db94011d3 759 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 760 /* - Clear state bitfield related to regular group conversion results */
sahilmgandhi 18:6a4db94011d3 761 /* - Set state bitfield related to regular group operation */
sahilmgandhi 18:6a4db94011d3 762 ADC_STATE_CLR_SET(hadc->State,
sahilmgandhi 18:6a4db94011d3 763 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
sahilmgandhi 18:6a4db94011d3 764 HAL_ADC_STATE_REG_BUSY);
sahilmgandhi 18:6a4db94011d3 765
sahilmgandhi 18:6a4db94011d3 766 /* If conversions on group regular are also triggering group injected, */
sahilmgandhi 18:6a4db94011d3 767 /* update ADC state. */
sahilmgandhi 18:6a4db94011d3 768 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
sahilmgandhi 18:6a4db94011d3 769 {
sahilmgandhi 18:6a4db94011d3 770 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
sahilmgandhi 18:6a4db94011d3 771 }
sahilmgandhi 18:6a4db94011d3 772
sahilmgandhi 18:6a4db94011d3 773 /* State machine update: Check if an injected conversion is ongoing */
sahilmgandhi 18:6a4db94011d3 774 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
sahilmgandhi 18:6a4db94011d3 775 {
sahilmgandhi 18:6a4db94011d3 776 /* Reset ADC error code fields related to conversions on group regular */
sahilmgandhi 18:6a4db94011d3 777 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
sahilmgandhi 18:6a4db94011d3 778 }
sahilmgandhi 18:6a4db94011d3 779 else
sahilmgandhi 18:6a4db94011d3 780 {
sahilmgandhi 18:6a4db94011d3 781 /* Reset ADC all error code fields */
sahilmgandhi 18:6a4db94011d3 782 ADC_CLEAR_ERRORCODE(hadc);
sahilmgandhi 18:6a4db94011d3 783 }
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 786 /* Unlock before starting ADC conversions: in case of potential */
sahilmgandhi 18:6a4db94011d3 787 /* interruption, to let the process to ADC IRQ Handler. */
sahilmgandhi 18:6a4db94011d3 788 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 789
sahilmgandhi 18:6a4db94011d3 790 /* Clear regular group conversion flag and overrun flag */
sahilmgandhi 18:6a4db94011d3 791 /* (To ensure of no unknown state from potential previous ADC operations) */
sahilmgandhi 18:6a4db94011d3 792 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 793
sahilmgandhi 18:6a4db94011d3 794 /* Enable end of conversion interrupt for regular group */
sahilmgandhi 18:6a4db94011d3 795 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
sahilmgandhi 18:6a4db94011d3 796
sahilmgandhi 18:6a4db94011d3 797 /* Check if Multimode enabled */
sahilmgandhi 18:6a4db94011d3 798 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
sahilmgandhi 18:6a4db94011d3 799 {
sahilmgandhi 18:6a4db94011d3 800 /* if no external trigger present enable software conversion of regular channels */
sahilmgandhi 18:6a4db94011d3 801 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
sahilmgandhi 18:6a4db94011d3 802 {
sahilmgandhi 18:6a4db94011d3 803 /* Enable the selected ADC software conversion for regular group */
sahilmgandhi 18:6a4db94011d3 804 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
sahilmgandhi 18:6a4db94011d3 805 }
sahilmgandhi 18:6a4db94011d3 806 }
sahilmgandhi 18:6a4db94011d3 807 else
sahilmgandhi 18:6a4db94011d3 808 {
sahilmgandhi 18:6a4db94011d3 809 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
sahilmgandhi 18:6a4db94011d3 810 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
sahilmgandhi 18:6a4db94011d3 811 {
sahilmgandhi 18:6a4db94011d3 812 /* Enable the selected ADC software conversion for regular group */
sahilmgandhi 18:6a4db94011d3 813 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
sahilmgandhi 18:6a4db94011d3 814 }
sahilmgandhi 18:6a4db94011d3 815 }
sahilmgandhi 18:6a4db94011d3 816 }
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 /* Return function status */
sahilmgandhi 18:6a4db94011d3 819 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 820 }
sahilmgandhi 18:6a4db94011d3 821
sahilmgandhi 18:6a4db94011d3 822 /**
sahilmgandhi 18:6a4db94011d3 823 * @brief Disables the interrupt and stop ADC conversion of regular channels.
sahilmgandhi 18:6a4db94011d3 824 *
sahilmgandhi 18:6a4db94011d3 825 * @note Caution: This function will stop also injected channels.
sahilmgandhi 18:6a4db94011d3 826 *
sahilmgandhi 18:6a4db94011d3 827 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 828 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 829 * @retval HAL status.
sahilmgandhi 18:6a4db94011d3 830 */
sahilmgandhi 18:6a4db94011d3 831 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 832 {
sahilmgandhi 18:6a4db94011d3 833 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 834 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
sahilmgandhi 18:6a4db94011d3 835
sahilmgandhi 18:6a4db94011d3 836 /* Process locked */
sahilmgandhi 18:6a4db94011d3 837 __HAL_LOCK(hadc);
sahilmgandhi 18:6a4db94011d3 838
sahilmgandhi 18:6a4db94011d3 839 /* Stop potential conversion on going, on regular and injected groups */
sahilmgandhi 18:6a4db94011d3 840 /* Disable ADC peripheral */
sahilmgandhi 18:6a4db94011d3 841 __HAL_ADC_DISABLE(hadc);
sahilmgandhi 18:6a4db94011d3 842
sahilmgandhi 18:6a4db94011d3 843 /* Check if ADC is effectively disabled */
sahilmgandhi 18:6a4db94011d3 844 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
sahilmgandhi 18:6a4db94011d3 845 {
sahilmgandhi 18:6a4db94011d3 846 /* Disable ADC end of conversion interrupt for regular group */
sahilmgandhi 18:6a4db94011d3 847 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
sahilmgandhi 18:6a4db94011d3 848
sahilmgandhi 18:6a4db94011d3 849 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 850 ADC_STATE_CLR_SET(hadc->State,
sahilmgandhi 18:6a4db94011d3 851 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
sahilmgandhi 18:6a4db94011d3 852 HAL_ADC_STATE_READY);
sahilmgandhi 18:6a4db94011d3 853 }
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 856 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 /* Return function status */
sahilmgandhi 18:6a4db94011d3 859 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 860 }
sahilmgandhi 18:6a4db94011d3 861
sahilmgandhi 18:6a4db94011d3 862 /**
sahilmgandhi 18:6a4db94011d3 863 * @brief Handles ADC interrupt request
sahilmgandhi 18:6a4db94011d3 864 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 865 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 866 * @retval None
sahilmgandhi 18:6a4db94011d3 867 */
sahilmgandhi 18:6a4db94011d3 868 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 869 {
sahilmgandhi 18:6a4db94011d3 870 uint32_t tmp1 = 0U, tmp2 = 0U;
sahilmgandhi 18:6a4db94011d3 871
sahilmgandhi 18:6a4db94011d3 872 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 873 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
sahilmgandhi 18:6a4db94011d3 874 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
sahilmgandhi 18:6a4db94011d3 875 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
sahilmgandhi 18:6a4db94011d3 876
sahilmgandhi 18:6a4db94011d3 877 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
sahilmgandhi 18:6a4db94011d3 878 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
sahilmgandhi 18:6a4db94011d3 879 /* Check End of conversion flag for regular channels */
sahilmgandhi 18:6a4db94011d3 880 if(tmp1 && tmp2)
sahilmgandhi 18:6a4db94011d3 881 {
sahilmgandhi 18:6a4db94011d3 882 /* Update state machine on conversion status if not in error state */
sahilmgandhi 18:6a4db94011d3 883 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
sahilmgandhi 18:6a4db94011d3 884 {
sahilmgandhi 18:6a4db94011d3 885 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 886 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
sahilmgandhi 18:6a4db94011d3 887 }
sahilmgandhi 18:6a4db94011d3 888
sahilmgandhi 18:6a4db94011d3 889 /* Determine whether any further conversion upcoming on group regular */
sahilmgandhi 18:6a4db94011d3 890 /* by external trigger, continuous mode or scan sequence on going. */
sahilmgandhi 18:6a4db94011d3 891 /* Note: On STM32F4, there is no independent flag of end of sequence. */
sahilmgandhi 18:6a4db94011d3 892 /* The test of scan sequence on going is done either with scan */
sahilmgandhi 18:6a4db94011d3 893 /* sequence disabled or with end of conversion flag set to */
sahilmgandhi 18:6a4db94011d3 894 /* of end of sequence. */
sahilmgandhi 18:6a4db94011d3 895 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
sahilmgandhi 18:6a4db94011d3 896 (hadc->Init.ContinuousConvMode == DISABLE) &&
sahilmgandhi 18:6a4db94011d3 897 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
sahilmgandhi 18:6a4db94011d3 898 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
sahilmgandhi 18:6a4db94011d3 899 {
sahilmgandhi 18:6a4db94011d3 900 /* Disable ADC end of single conversion interrupt on group regular */
sahilmgandhi 18:6a4db94011d3 901 /* Note: Overrun interrupt was enabled with EOC interrupt in */
sahilmgandhi 18:6a4db94011d3 902 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
sahilmgandhi 18:6a4db94011d3 903 /* by overrun IRQ process below. */
sahilmgandhi 18:6a4db94011d3 904 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
sahilmgandhi 18:6a4db94011d3 905
sahilmgandhi 18:6a4db94011d3 906 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 907 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
sahilmgandhi 18:6a4db94011d3 908
sahilmgandhi 18:6a4db94011d3 909 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
sahilmgandhi 18:6a4db94011d3 910 {
sahilmgandhi 18:6a4db94011d3 911 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
sahilmgandhi 18:6a4db94011d3 912 }
sahilmgandhi 18:6a4db94011d3 913 }
sahilmgandhi 18:6a4db94011d3 914
sahilmgandhi 18:6a4db94011d3 915 /* Conversion complete callback */
sahilmgandhi 18:6a4db94011d3 916 HAL_ADC_ConvCpltCallback(hadc);
sahilmgandhi 18:6a4db94011d3 917
sahilmgandhi 18:6a4db94011d3 918 /* Clear regular group conversion flag */
sahilmgandhi 18:6a4db94011d3 919 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
sahilmgandhi 18:6a4db94011d3 920 }
sahilmgandhi 18:6a4db94011d3 921
sahilmgandhi 18:6a4db94011d3 922 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
sahilmgandhi 18:6a4db94011d3 923 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
sahilmgandhi 18:6a4db94011d3 924 /* Check End of conversion flag for injected channels */
sahilmgandhi 18:6a4db94011d3 925 if(tmp1 && tmp2)
sahilmgandhi 18:6a4db94011d3 926 {
sahilmgandhi 18:6a4db94011d3 927 /* Update state machine on conversion status if not in error state */
sahilmgandhi 18:6a4db94011d3 928 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
sahilmgandhi 18:6a4db94011d3 929 {
sahilmgandhi 18:6a4db94011d3 930 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 931 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
sahilmgandhi 18:6a4db94011d3 932 }
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934 /* Determine whether any further conversion upcoming on group injected */
sahilmgandhi 18:6a4db94011d3 935 /* by external trigger, scan sequence on going or by automatic injected */
sahilmgandhi 18:6a4db94011d3 936 /* conversion from group regular (same conditions as group regular */
sahilmgandhi 18:6a4db94011d3 937 /* interruption disabling above). */
sahilmgandhi 18:6a4db94011d3 938 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
sahilmgandhi 18:6a4db94011d3 939 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
sahilmgandhi 18:6a4db94011d3 940 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
sahilmgandhi 18:6a4db94011d3 941 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
sahilmgandhi 18:6a4db94011d3 942 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
sahilmgandhi 18:6a4db94011d3 943 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
sahilmgandhi 18:6a4db94011d3 944 {
sahilmgandhi 18:6a4db94011d3 945 /* Disable ADC end of single conversion interrupt on group injected */
sahilmgandhi 18:6a4db94011d3 946 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
sahilmgandhi 18:6a4db94011d3 947
sahilmgandhi 18:6a4db94011d3 948 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 949 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
sahilmgandhi 18:6a4db94011d3 950
sahilmgandhi 18:6a4db94011d3 951 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
sahilmgandhi 18:6a4db94011d3 952 {
sahilmgandhi 18:6a4db94011d3 953 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
sahilmgandhi 18:6a4db94011d3 954 }
sahilmgandhi 18:6a4db94011d3 955 }
sahilmgandhi 18:6a4db94011d3 956
sahilmgandhi 18:6a4db94011d3 957 /* Conversion complete callback */
sahilmgandhi 18:6a4db94011d3 958 HAL_ADCEx_InjectedConvCpltCallback(hadc);
sahilmgandhi 18:6a4db94011d3 959
sahilmgandhi 18:6a4db94011d3 960 /* Clear injected group conversion flag */
sahilmgandhi 18:6a4db94011d3 961 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
sahilmgandhi 18:6a4db94011d3 962 }
sahilmgandhi 18:6a4db94011d3 963
sahilmgandhi 18:6a4db94011d3 964 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
sahilmgandhi 18:6a4db94011d3 965 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
sahilmgandhi 18:6a4db94011d3 966 /* Check Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 967 if(tmp1 && tmp2)
sahilmgandhi 18:6a4db94011d3 968 {
sahilmgandhi 18:6a4db94011d3 969 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
sahilmgandhi 18:6a4db94011d3 970 {
sahilmgandhi 18:6a4db94011d3 971 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 972 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
sahilmgandhi 18:6a4db94011d3 973
sahilmgandhi 18:6a4db94011d3 974 /* Level out of window callback */
sahilmgandhi 18:6a4db94011d3 975 HAL_ADC_LevelOutOfWindowCallback(hadc);
sahilmgandhi 18:6a4db94011d3 976
sahilmgandhi 18:6a4db94011d3 977 /* Clear the ADC analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 978 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
sahilmgandhi 18:6a4db94011d3 979 }
sahilmgandhi 18:6a4db94011d3 980 }
sahilmgandhi 18:6a4db94011d3 981
sahilmgandhi 18:6a4db94011d3 982 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 983 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
sahilmgandhi 18:6a4db94011d3 984 /* Check Overrun flag */
sahilmgandhi 18:6a4db94011d3 985 if(tmp1 && tmp2)
sahilmgandhi 18:6a4db94011d3 986 {
sahilmgandhi 18:6a4db94011d3 987 /* Note: On STM32F4, ADC overrun can be set through other parameters */
sahilmgandhi 18:6a4db94011d3 988 /* refer to description of parameter "EOCSelection" for more */
sahilmgandhi 18:6a4db94011d3 989 /* details. */
sahilmgandhi 18:6a4db94011d3 990
sahilmgandhi 18:6a4db94011d3 991 /* Set ADC error code to overrun */
sahilmgandhi 18:6a4db94011d3 992 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
sahilmgandhi 18:6a4db94011d3 993
sahilmgandhi 18:6a4db94011d3 994 /* Clear ADC overrun flag */
sahilmgandhi 18:6a4db94011d3 995 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 996
sahilmgandhi 18:6a4db94011d3 997 /* Error callback */
sahilmgandhi 18:6a4db94011d3 998 HAL_ADC_ErrorCallback(hadc);
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 /* Clear the Overrun flag */
sahilmgandhi 18:6a4db94011d3 1001 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 1002 }
sahilmgandhi 18:6a4db94011d3 1003 }
sahilmgandhi 18:6a4db94011d3 1004
sahilmgandhi 18:6a4db94011d3 1005 /**
sahilmgandhi 18:6a4db94011d3 1006 * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
sahilmgandhi 18:6a4db94011d3 1007 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1008 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1009 * @param pData: The destination Buffer address.
sahilmgandhi 18:6a4db94011d3 1010 * @param Length: The length of data to be transferred from ADC peripheral to memory.
sahilmgandhi 18:6a4db94011d3 1011 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1012 */
sahilmgandhi 18:6a4db94011d3 1013 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
sahilmgandhi 18:6a4db94011d3 1014 {
sahilmgandhi 18:6a4db94011d3 1015 __IO uint32_t counter = 0U;
sahilmgandhi 18:6a4db94011d3 1016
sahilmgandhi 18:6a4db94011d3 1017 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1018 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
sahilmgandhi 18:6a4db94011d3 1019 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
sahilmgandhi 18:6a4db94011d3 1020
sahilmgandhi 18:6a4db94011d3 1021 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1022 __HAL_LOCK(hadc);
sahilmgandhi 18:6a4db94011d3 1023
sahilmgandhi 18:6a4db94011d3 1024 /* Enable the ADC peripheral */
sahilmgandhi 18:6a4db94011d3 1025 /* Check if ADC peripheral is disabled in order to enable it and wait during
sahilmgandhi 18:6a4db94011d3 1026 Tstab time the ADC's stabilization */
sahilmgandhi 18:6a4db94011d3 1027 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
sahilmgandhi 18:6a4db94011d3 1028 {
sahilmgandhi 18:6a4db94011d3 1029 /* Enable the Peripheral */
sahilmgandhi 18:6a4db94011d3 1030 __HAL_ADC_ENABLE(hadc);
sahilmgandhi 18:6a4db94011d3 1031
sahilmgandhi 18:6a4db94011d3 1032 /* Delay for ADC stabilization time */
sahilmgandhi 18:6a4db94011d3 1033 /* Compute number of CPU cycles to wait for */
sahilmgandhi 18:6a4db94011d3 1034 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
sahilmgandhi 18:6a4db94011d3 1035 while(counter != 0U)
sahilmgandhi 18:6a4db94011d3 1036 {
sahilmgandhi 18:6a4db94011d3 1037 counter--;
sahilmgandhi 18:6a4db94011d3 1038 }
sahilmgandhi 18:6a4db94011d3 1039 }
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041 /* Start conversion if ADC is effectively enabled */
sahilmgandhi 18:6a4db94011d3 1042 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
sahilmgandhi 18:6a4db94011d3 1043 {
sahilmgandhi 18:6a4db94011d3 1044 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 1045 /* - Clear state bitfield related to regular group conversion results */
sahilmgandhi 18:6a4db94011d3 1046 /* - Set state bitfield related to regular group operation */
sahilmgandhi 18:6a4db94011d3 1047 ADC_STATE_CLR_SET(hadc->State,
sahilmgandhi 18:6a4db94011d3 1048 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
sahilmgandhi 18:6a4db94011d3 1049 HAL_ADC_STATE_REG_BUSY);
sahilmgandhi 18:6a4db94011d3 1050
sahilmgandhi 18:6a4db94011d3 1051 /* If conversions on group regular are also triggering group injected, */
sahilmgandhi 18:6a4db94011d3 1052 /* update ADC state. */
sahilmgandhi 18:6a4db94011d3 1053 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
sahilmgandhi 18:6a4db94011d3 1054 {
sahilmgandhi 18:6a4db94011d3 1055 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
sahilmgandhi 18:6a4db94011d3 1056 }
sahilmgandhi 18:6a4db94011d3 1057
sahilmgandhi 18:6a4db94011d3 1058 /* State machine update: Check if an injected conversion is ongoing */
sahilmgandhi 18:6a4db94011d3 1059 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
sahilmgandhi 18:6a4db94011d3 1060 {
sahilmgandhi 18:6a4db94011d3 1061 /* Reset ADC error code fields related to conversions on group regular */
sahilmgandhi 18:6a4db94011d3 1062 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
sahilmgandhi 18:6a4db94011d3 1063 }
sahilmgandhi 18:6a4db94011d3 1064 else
sahilmgandhi 18:6a4db94011d3 1065 {
sahilmgandhi 18:6a4db94011d3 1066 /* Reset ADC all error code fields */
sahilmgandhi 18:6a4db94011d3 1067 ADC_CLEAR_ERRORCODE(hadc);
sahilmgandhi 18:6a4db94011d3 1068 }
sahilmgandhi 18:6a4db94011d3 1069
sahilmgandhi 18:6a4db94011d3 1070 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1071 /* Unlock before starting ADC conversions: in case of potential */
sahilmgandhi 18:6a4db94011d3 1072 /* interruption, to let the process to ADC IRQ Handler. */
sahilmgandhi 18:6a4db94011d3 1073 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075 /* Set the DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1076 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 /* Set the DMA half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1079 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
sahilmgandhi 18:6a4db94011d3 1080
sahilmgandhi 18:6a4db94011d3 1081 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 1082 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
sahilmgandhi 18:6a4db94011d3 1083
sahilmgandhi 18:6a4db94011d3 1084
sahilmgandhi 18:6a4db94011d3 1085 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
sahilmgandhi 18:6a4db94011d3 1086 /* start (in case of SW start): */
sahilmgandhi 18:6a4db94011d3 1087
sahilmgandhi 18:6a4db94011d3 1088 /* Clear regular group conversion flag and overrun flag */
sahilmgandhi 18:6a4db94011d3 1089 /* (To ensure of no unknown state from potential previous ADC operations) */
sahilmgandhi 18:6a4db94011d3 1090 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 1091
sahilmgandhi 18:6a4db94011d3 1092 /* Enable ADC overrun interrupt */
sahilmgandhi 18:6a4db94011d3 1093 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
sahilmgandhi 18:6a4db94011d3 1094
sahilmgandhi 18:6a4db94011d3 1095 /* Enable ADC DMA mode */
sahilmgandhi 18:6a4db94011d3 1096 hadc->Instance->CR2 |= ADC_CR2_DMA;
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 /* Start the DMA channel */
sahilmgandhi 18:6a4db94011d3 1099 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
sahilmgandhi 18:6a4db94011d3 1100
sahilmgandhi 18:6a4db94011d3 1101 /* Check if Multimode enabled */
sahilmgandhi 18:6a4db94011d3 1102 if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
sahilmgandhi 18:6a4db94011d3 1103 {
sahilmgandhi 18:6a4db94011d3 1104 /* if no external trigger present enable software conversion of regular channels */
sahilmgandhi 18:6a4db94011d3 1105 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
sahilmgandhi 18:6a4db94011d3 1106 {
sahilmgandhi 18:6a4db94011d3 1107 /* Enable the selected ADC software conversion for regular group */
sahilmgandhi 18:6a4db94011d3 1108 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
sahilmgandhi 18:6a4db94011d3 1109 }
sahilmgandhi 18:6a4db94011d3 1110 }
sahilmgandhi 18:6a4db94011d3 1111 else
sahilmgandhi 18:6a4db94011d3 1112 {
sahilmgandhi 18:6a4db94011d3 1113 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
sahilmgandhi 18:6a4db94011d3 1114 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
sahilmgandhi 18:6a4db94011d3 1115 {
sahilmgandhi 18:6a4db94011d3 1116 /* Enable the selected ADC software conversion for regular group */
sahilmgandhi 18:6a4db94011d3 1117 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
sahilmgandhi 18:6a4db94011d3 1118 }
sahilmgandhi 18:6a4db94011d3 1119 }
sahilmgandhi 18:6a4db94011d3 1120 }
sahilmgandhi 18:6a4db94011d3 1121
sahilmgandhi 18:6a4db94011d3 1122 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1123 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1124 }
sahilmgandhi 18:6a4db94011d3 1125
sahilmgandhi 18:6a4db94011d3 1126 /**
sahilmgandhi 18:6a4db94011d3 1127 * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
sahilmgandhi 18:6a4db94011d3 1128 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1129 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1130 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1131 */
sahilmgandhi 18:6a4db94011d3 1132 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 1133 {
sahilmgandhi 18:6a4db94011d3 1134 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1135
sahilmgandhi 18:6a4db94011d3 1136 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1137 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
sahilmgandhi 18:6a4db94011d3 1138
sahilmgandhi 18:6a4db94011d3 1139 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1140 __HAL_LOCK(hadc);
sahilmgandhi 18:6a4db94011d3 1141
sahilmgandhi 18:6a4db94011d3 1142 /* Stop potential conversion on going, on regular and injected groups */
sahilmgandhi 18:6a4db94011d3 1143 /* Disable ADC peripheral */
sahilmgandhi 18:6a4db94011d3 1144 __HAL_ADC_DISABLE(hadc);
sahilmgandhi 18:6a4db94011d3 1145
sahilmgandhi 18:6a4db94011d3 1146 /* Check if ADC is effectively disabled */
sahilmgandhi 18:6a4db94011d3 1147 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
sahilmgandhi 18:6a4db94011d3 1148 {
sahilmgandhi 18:6a4db94011d3 1149 /* Disable the selected ADC DMA mode */
sahilmgandhi 18:6a4db94011d3 1150 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
sahilmgandhi 18:6a4db94011d3 1151
sahilmgandhi 18:6a4db94011d3 1152 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
sahilmgandhi 18:6a4db94011d3 1153 /* DMA transfer is on going) */
sahilmgandhi 18:6a4db94011d3 1154 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
sahilmgandhi 18:6a4db94011d3 1155
sahilmgandhi 18:6a4db94011d3 1156 /* Disable ADC overrun interrupt */
sahilmgandhi 18:6a4db94011d3 1157 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
sahilmgandhi 18:6a4db94011d3 1158
sahilmgandhi 18:6a4db94011d3 1159 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 1160 ADC_STATE_CLR_SET(hadc->State,
sahilmgandhi 18:6a4db94011d3 1161 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
sahilmgandhi 18:6a4db94011d3 1162 HAL_ADC_STATE_READY);
sahilmgandhi 18:6a4db94011d3 1163 }
sahilmgandhi 18:6a4db94011d3 1164
sahilmgandhi 18:6a4db94011d3 1165 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1166 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 1167
sahilmgandhi 18:6a4db94011d3 1168 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1169 return tmp_hal_status;
sahilmgandhi 18:6a4db94011d3 1170 }
sahilmgandhi 18:6a4db94011d3 1171
sahilmgandhi 18:6a4db94011d3 1172 /**
sahilmgandhi 18:6a4db94011d3 1173 * @brief Gets the converted value from data register of regular channel.
sahilmgandhi 18:6a4db94011d3 1174 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1175 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1176 * @retval Converted value
sahilmgandhi 18:6a4db94011d3 1177 */
sahilmgandhi 18:6a4db94011d3 1178 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 1179 {
sahilmgandhi 18:6a4db94011d3 1180 /* Return the selected ADC converted value */
sahilmgandhi 18:6a4db94011d3 1181 return hadc->Instance->DR;
sahilmgandhi 18:6a4db94011d3 1182 }
sahilmgandhi 18:6a4db94011d3 1183
sahilmgandhi 18:6a4db94011d3 1184 /**
sahilmgandhi 18:6a4db94011d3 1185 * @brief Regular conversion complete callback in non blocking mode
sahilmgandhi 18:6a4db94011d3 1186 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1187 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1188 * @retval None
sahilmgandhi 18:6a4db94011d3 1189 */
sahilmgandhi 18:6a4db94011d3 1190 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 1191 {
sahilmgandhi 18:6a4db94011d3 1192 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1193 UNUSED(hadc);
sahilmgandhi 18:6a4db94011d3 1194 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1195 the HAL_ADC_ConvCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1196 */
sahilmgandhi 18:6a4db94011d3 1197 }
sahilmgandhi 18:6a4db94011d3 1198
sahilmgandhi 18:6a4db94011d3 1199 /**
sahilmgandhi 18:6a4db94011d3 1200 * @brief Regular conversion half DMA transfer callback in non blocking mode
sahilmgandhi 18:6a4db94011d3 1201 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1202 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1203 * @retval None
sahilmgandhi 18:6a4db94011d3 1204 */
sahilmgandhi 18:6a4db94011d3 1205 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 1206 {
sahilmgandhi 18:6a4db94011d3 1207 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1208 UNUSED(hadc);
sahilmgandhi 18:6a4db94011d3 1209 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1210 the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1211 */
sahilmgandhi 18:6a4db94011d3 1212 }
sahilmgandhi 18:6a4db94011d3 1213
sahilmgandhi 18:6a4db94011d3 1214 /**
sahilmgandhi 18:6a4db94011d3 1215 * @brief Analog watchdog callback in non blocking mode
sahilmgandhi 18:6a4db94011d3 1216 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1217 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1218 * @retval None
sahilmgandhi 18:6a4db94011d3 1219 */
sahilmgandhi 18:6a4db94011d3 1220 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 1221 {
sahilmgandhi 18:6a4db94011d3 1222 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1223 UNUSED(hadc);
sahilmgandhi 18:6a4db94011d3 1224 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1225 the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1226 */
sahilmgandhi 18:6a4db94011d3 1227 }
sahilmgandhi 18:6a4db94011d3 1228
sahilmgandhi 18:6a4db94011d3 1229 /**
sahilmgandhi 18:6a4db94011d3 1230 * @brief Error ADC callback.
sahilmgandhi 18:6a4db94011d3 1231 * @note In case of error due to overrun when using ADC with DMA transfer
sahilmgandhi 18:6a4db94011d3 1232 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
sahilmgandhi 18:6a4db94011d3 1233 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
sahilmgandhi 18:6a4db94011d3 1234 * - If needed, restart a new ADC conversion using function
sahilmgandhi 18:6a4db94011d3 1235 * "HAL_ADC_Start_DMA()"
sahilmgandhi 18:6a4db94011d3 1236 * (this function is also clearing overrun flag)
sahilmgandhi 18:6a4db94011d3 1237 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1238 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1239 * @retval None
sahilmgandhi 18:6a4db94011d3 1240 */
sahilmgandhi 18:6a4db94011d3 1241 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
sahilmgandhi 18:6a4db94011d3 1242 {
sahilmgandhi 18:6a4db94011d3 1243 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1244 UNUSED(hadc);
sahilmgandhi 18:6a4db94011d3 1245 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1246 the HAL_ADC_ErrorCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1247 */
sahilmgandhi 18:6a4db94011d3 1248 }
sahilmgandhi 18:6a4db94011d3 1249
sahilmgandhi 18:6a4db94011d3 1250 /**
sahilmgandhi 18:6a4db94011d3 1251 * @}
sahilmgandhi 18:6a4db94011d3 1252 */
sahilmgandhi 18:6a4db94011d3 1253
sahilmgandhi 18:6a4db94011d3 1254 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 1255 * @brief Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 1256 *
sahilmgandhi 18:6a4db94011d3 1257 @verbatim
sahilmgandhi 18:6a4db94011d3 1258 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1259 ##### Peripheral Control functions #####
sahilmgandhi 18:6a4db94011d3 1260 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1261 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 1262 (+) Configure regular channels.
sahilmgandhi 18:6a4db94011d3 1263 (+) Configure injected channels.
sahilmgandhi 18:6a4db94011d3 1264 (+) Configure multimode.
sahilmgandhi 18:6a4db94011d3 1265 (+) Configure the analog watch dog.
sahilmgandhi 18:6a4db94011d3 1266
sahilmgandhi 18:6a4db94011d3 1267 @endverbatim
sahilmgandhi 18:6a4db94011d3 1268 * @{
sahilmgandhi 18:6a4db94011d3 1269 */
sahilmgandhi 18:6a4db94011d3 1270
sahilmgandhi 18:6a4db94011d3 1271 /**
sahilmgandhi 18:6a4db94011d3 1272 * @brief Configures for the selected ADC regular channel its corresponding
sahilmgandhi 18:6a4db94011d3 1273 * rank in the sequencer and its sample time.
sahilmgandhi 18:6a4db94011d3 1274 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1275 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1276 * @param sConfig: ADC configuration structure.
sahilmgandhi 18:6a4db94011d3 1277 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1278 */
sahilmgandhi 18:6a4db94011d3 1279 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
sahilmgandhi 18:6a4db94011d3 1280 {
sahilmgandhi 18:6a4db94011d3 1281 __IO uint32_t counter = 0U;
sahilmgandhi 18:6a4db94011d3 1282
sahilmgandhi 18:6a4db94011d3 1283 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1284 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
sahilmgandhi 18:6a4db94011d3 1285 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
sahilmgandhi 18:6a4db94011d3 1286 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
sahilmgandhi 18:6a4db94011d3 1287
sahilmgandhi 18:6a4db94011d3 1288 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1289 __HAL_LOCK(hadc);
sahilmgandhi 18:6a4db94011d3 1290
sahilmgandhi 18:6a4db94011d3 1291 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
sahilmgandhi 18:6a4db94011d3 1292 if (sConfig->Channel > ADC_CHANNEL_9)
sahilmgandhi 18:6a4db94011d3 1293 {
sahilmgandhi 18:6a4db94011d3 1294 /* Clear the old sample time */
sahilmgandhi 18:6a4db94011d3 1295 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
sahilmgandhi 18:6a4db94011d3 1296
sahilmgandhi 18:6a4db94011d3 1297 /* Set the new sample time */
sahilmgandhi 18:6a4db94011d3 1298 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
sahilmgandhi 18:6a4db94011d3 1299 }
sahilmgandhi 18:6a4db94011d3 1300 else /* ADC_Channel include in ADC_Channel_[0..9] */
sahilmgandhi 18:6a4db94011d3 1301 {
sahilmgandhi 18:6a4db94011d3 1302 /* Clear the old sample time */
sahilmgandhi 18:6a4db94011d3 1303 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
sahilmgandhi 18:6a4db94011d3 1304
sahilmgandhi 18:6a4db94011d3 1305 /* Set the new sample time */
sahilmgandhi 18:6a4db94011d3 1306 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
sahilmgandhi 18:6a4db94011d3 1307 }
sahilmgandhi 18:6a4db94011d3 1308
sahilmgandhi 18:6a4db94011d3 1309 /* For Rank 1 to 6 */
sahilmgandhi 18:6a4db94011d3 1310 if (sConfig->Rank < 7U)
sahilmgandhi 18:6a4db94011d3 1311 {
sahilmgandhi 18:6a4db94011d3 1312 /* Clear the old SQx bits for the selected rank */
sahilmgandhi 18:6a4db94011d3 1313 hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
sahilmgandhi 18:6a4db94011d3 1314
sahilmgandhi 18:6a4db94011d3 1315 /* Set the SQx bits for the selected rank */
sahilmgandhi 18:6a4db94011d3 1316 hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
sahilmgandhi 18:6a4db94011d3 1317 }
sahilmgandhi 18:6a4db94011d3 1318 /* For Rank 7 to 12 */
sahilmgandhi 18:6a4db94011d3 1319 else if (sConfig->Rank < 13U)
sahilmgandhi 18:6a4db94011d3 1320 {
sahilmgandhi 18:6a4db94011d3 1321 /* Clear the old SQx bits for the selected rank */
sahilmgandhi 18:6a4db94011d3 1322 hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
sahilmgandhi 18:6a4db94011d3 1323
sahilmgandhi 18:6a4db94011d3 1324 /* Set the SQx bits for the selected rank */
sahilmgandhi 18:6a4db94011d3 1325 hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
sahilmgandhi 18:6a4db94011d3 1326 }
sahilmgandhi 18:6a4db94011d3 1327 /* For Rank 13 to 16 */
sahilmgandhi 18:6a4db94011d3 1328 else
sahilmgandhi 18:6a4db94011d3 1329 {
sahilmgandhi 18:6a4db94011d3 1330 /* Clear the old SQx bits for the selected rank */
sahilmgandhi 18:6a4db94011d3 1331 hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
sahilmgandhi 18:6a4db94011d3 1332
sahilmgandhi 18:6a4db94011d3 1333 /* Set the SQx bits for the selected rank */
sahilmgandhi 18:6a4db94011d3 1334 hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
sahilmgandhi 18:6a4db94011d3 1335 }
sahilmgandhi 18:6a4db94011d3 1336
sahilmgandhi 18:6a4db94011d3 1337 /* if ADC1 Channel_18 is selected enable VBAT Channel */
sahilmgandhi 18:6a4db94011d3 1338 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
sahilmgandhi 18:6a4db94011d3 1339 {
sahilmgandhi 18:6a4db94011d3 1340 /* Enable the VBAT channel*/
sahilmgandhi 18:6a4db94011d3 1341 ADC->CCR |= ADC_CCR_VBATE;
sahilmgandhi 18:6a4db94011d3 1342 }
sahilmgandhi 18:6a4db94011d3 1343
sahilmgandhi 18:6a4db94011d3 1344 /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
sahilmgandhi 18:6a4db94011d3 1345 if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
sahilmgandhi 18:6a4db94011d3 1346 {
sahilmgandhi 18:6a4db94011d3 1347 /* Enable the TSVREFE channel*/
sahilmgandhi 18:6a4db94011d3 1348 ADC->CCR |= ADC_CCR_TSVREFE;
sahilmgandhi 18:6a4db94011d3 1349
sahilmgandhi 18:6a4db94011d3 1350 if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
sahilmgandhi 18:6a4db94011d3 1351 {
sahilmgandhi 18:6a4db94011d3 1352 /* Delay for temperature sensor stabilization time */
sahilmgandhi 18:6a4db94011d3 1353 /* Compute number of CPU cycles to wait for */
sahilmgandhi 18:6a4db94011d3 1354 counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
sahilmgandhi 18:6a4db94011d3 1355 while(counter != 0U)
sahilmgandhi 18:6a4db94011d3 1356 {
sahilmgandhi 18:6a4db94011d3 1357 counter--;
sahilmgandhi 18:6a4db94011d3 1358 }
sahilmgandhi 18:6a4db94011d3 1359 }
sahilmgandhi 18:6a4db94011d3 1360 }
sahilmgandhi 18:6a4db94011d3 1361
sahilmgandhi 18:6a4db94011d3 1362 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1363 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 1364
sahilmgandhi 18:6a4db94011d3 1365 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1366 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1367 }
sahilmgandhi 18:6a4db94011d3 1368
sahilmgandhi 18:6a4db94011d3 1369 /**
sahilmgandhi 18:6a4db94011d3 1370 * @brief Configures the analog watchdog.
sahilmgandhi 18:6a4db94011d3 1371 * @note Analog watchdog thresholds can be modified while ADC conversion
sahilmgandhi 18:6a4db94011d3 1372 * is on going.
sahilmgandhi 18:6a4db94011d3 1373 * In this case, some constraints must be taken into account:
sahilmgandhi 18:6a4db94011d3 1374 * The programmed threshold values are effective from the next
sahilmgandhi 18:6a4db94011d3 1375 * ADC EOC (end of unitary conversion).
sahilmgandhi 18:6a4db94011d3 1376 * Considering that registers write delay may happen due to
sahilmgandhi 18:6a4db94011d3 1377 * bus activity, this might cause an uncertainty on the
sahilmgandhi 18:6a4db94011d3 1378 * effective timing of the new programmed threshold values.
sahilmgandhi 18:6a4db94011d3 1379 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1380 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1381 * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure
sahilmgandhi 18:6a4db94011d3 1382 * that contains the configuration information of ADC analog watchdog.
sahilmgandhi 18:6a4db94011d3 1383 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1384 */
sahilmgandhi 18:6a4db94011d3 1385 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
sahilmgandhi 18:6a4db94011d3 1386 {
sahilmgandhi 18:6a4db94011d3 1387 #ifdef USE_FULL_ASSERT
sahilmgandhi 18:6a4db94011d3 1388 uint32_t tmp = 0U;
sahilmgandhi 18:6a4db94011d3 1389 #endif /* USE_FULL_ASSERT */
sahilmgandhi 18:6a4db94011d3 1390
sahilmgandhi 18:6a4db94011d3 1391 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1392 assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
sahilmgandhi 18:6a4db94011d3 1393 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
sahilmgandhi 18:6a4db94011d3 1394 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
sahilmgandhi 18:6a4db94011d3 1395
sahilmgandhi 18:6a4db94011d3 1396 #ifdef USE_FULL_ASSERT
sahilmgandhi 18:6a4db94011d3 1397 tmp = ADC_GET_RESOLUTION(hadc);
sahilmgandhi 18:6a4db94011d3 1398 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
sahilmgandhi 18:6a4db94011d3 1399 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
sahilmgandhi 18:6a4db94011d3 1400 #endif /* USE_FULL_ASSERT */
sahilmgandhi 18:6a4db94011d3 1401
sahilmgandhi 18:6a4db94011d3 1402 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1403 __HAL_LOCK(hadc);
sahilmgandhi 18:6a4db94011d3 1404
sahilmgandhi 18:6a4db94011d3 1405 if(AnalogWDGConfig->ITMode == ENABLE)
sahilmgandhi 18:6a4db94011d3 1406 {
sahilmgandhi 18:6a4db94011d3 1407 /* Enable the ADC Analog watchdog interrupt */
sahilmgandhi 18:6a4db94011d3 1408 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
sahilmgandhi 18:6a4db94011d3 1409 }
sahilmgandhi 18:6a4db94011d3 1410 else
sahilmgandhi 18:6a4db94011d3 1411 {
sahilmgandhi 18:6a4db94011d3 1412 /* Disable the ADC Analog watchdog interrupt */
sahilmgandhi 18:6a4db94011d3 1413 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
sahilmgandhi 18:6a4db94011d3 1414 }
sahilmgandhi 18:6a4db94011d3 1415
sahilmgandhi 18:6a4db94011d3 1416 /* Clear AWDEN, JAWDEN and AWDSGL bits */
sahilmgandhi 18:6a4db94011d3 1417 hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);
sahilmgandhi 18:6a4db94011d3 1418
sahilmgandhi 18:6a4db94011d3 1419 /* Set the analog watchdog enable mode */
sahilmgandhi 18:6a4db94011d3 1420 hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;
sahilmgandhi 18:6a4db94011d3 1421
sahilmgandhi 18:6a4db94011d3 1422 /* Set the high threshold */
sahilmgandhi 18:6a4db94011d3 1423 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
sahilmgandhi 18:6a4db94011d3 1424
sahilmgandhi 18:6a4db94011d3 1425 /* Set the low threshold */
sahilmgandhi 18:6a4db94011d3 1426 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
sahilmgandhi 18:6a4db94011d3 1427
sahilmgandhi 18:6a4db94011d3 1428 /* Clear the Analog watchdog channel select bits */
sahilmgandhi 18:6a4db94011d3 1429 hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
sahilmgandhi 18:6a4db94011d3 1430
sahilmgandhi 18:6a4db94011d3 1431 /* Set the Analog watchdog channel */
sahilmgandhi 18:6a4db94011d3 1432 hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
sahilmgandhi 18:6a4db94011d3 1433
sahilmgandhi 18:6a4db94011d3 1434 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1435 __HAL_UNLOCK(hadc);
sahilmgandhi 18:6a4db94011d3 1436
sahilmgandhi 18:6a4db94011d3 1437 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1438 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1439 }
sahilmgandhi 18:6a4db94011d3 1440
sahilmgandhi 18:6a4db94011d3 1441 /**
sahilmgandhi 18:6a4db94011d3 1442 * @}
sahilmgandhi 18:6a4db94011d3 1443 */
sahilmgandhi 18:6a4db94011d3 1444
sahilmgandhi 18:6a4db94011d3 1445 /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1446 * @brief ADC Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1447 *
sahilmgandhi 18:6a4db94011d3 1448 @verbatim
sahilmgandhi 18:6a4db94011d3 1449 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1450 ##### Peripheral State and errors functions #####
sahilmgandhi 18:6a4db94011d3 1451 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1452 [..]
sahilmgandhi 18:6a4db94011d3 1453 This subsection provides functions allowing to
sahilmgandhi 18:6a4db94011d3 1454 (+) Check the ADC state
sahilmgandhi 18:6a4db94011d3 1455 (+) Check the ADC Error
sahilmgandhi 18:6a4db94011d3 1456
sahilmgandhi 18:6a4db94011d3 1457 @endverbatim
sahilmgandhi 18:6a4db94011d3 1458 * @{
sahilmgandhi 18:6a4db94011d3 1459 */
sahilmgandhi 18:6a4db94011d3 1460
sahilmgandhi 18:6a4db94011d3 1461 /**
sahilmgandhi 18:6a4db94011d3 1462 * @brief return the ADC state
sahilmgandhi 18:6a4db94011d3 1463 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1464 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1465 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1466 */
sahilmgandhi 18:6a4db94011d3 1467 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 1468 {
sahilmgandhi 18:6a4db94011d3 1469 /* Return ADC state */
sahilmgandhi 18:6a4db94011d3 1470 return hadc->State;
sahilmgandhi 18:6a4db94011d3 1471 }
sahilmgandhi 18:6a4db94011d3 1472
sahilmgandhi 18:6a4db94011d3 1473 /**
sahilmgandhi 18:6a4db94011d3 1474 * @brief Return the ADC error code
sahilmgandhi 18:6a4db94011d3 1475 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1476 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1477 * @retval ADC Error Code
sahilmgandhi 18:6a4db94011d3 1478 */
sahilmgandhi 18:6a4db94011d3 1479 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
sahilmgandhi 18:6a4db94011d3 1480 {
sahilmgandhi 18:6a4db94011d3 1481 return hadc->ErrorCode;
sahilmgandhi 18:6a4db94011d3 1482 }
sahilmgandhi 18:6a4db94011d3 1483
sahilmgandhi 18:6a4db94011d3 1484 /**
sahilmgandhi 18:6a4db94011d3 1485 * @}
sahilmgandhi 18:6a4db94011d3 1486 */
sahilmgandhi 18:6a4db94011d3 1487
sahilmgandhi 18:6a4db94011d3 1488 /** @addtogroup ADC_Private_Functions
sahilmgandhi 18:6a4db94011d3 1489 * @{
sahilmgandhi 18:6a4db94011d3 1490 */
sahilmgandhi 18:6a4db94011d3 1491
sahilmgandhi 18:6a4db94011d3 1492 /**
sahilmgandhi 18:6a4db94011d3 1493 * @brief Initializes the ADCx peripheral according to the specified parameters
sahilmgandhi 18:6a4db94011d3 1494 * in the ADC_InitStruct without initializing the ADC MSP.
sahilmgandhi 18:6a4db94011d3 1495 * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1496 * the configuration information for the specified ADC.
sahilmgandhi 18:6a4db94011d3 1497 * @retval None
sahilmgandhi 18:6a4db94011d3 1498 */
sahilmgandhi 18:6a4db94011d3 1499 static void ADC_Init(ADC_HandleTypeDef* hadc)
sahilmgandhi 18:6a4db94011d3 1500 {
sahilmgandhi 18:6a4db94011d3 1501 /* Set ADC parameters */
sahilmgandhi 18:6a4db94011d3 1502 /* Set the ADC clock prescaler */
sahilmgandhi 18:6a4db94011d3 1503 ADC->CCR &= ~(ADC_CCR_ADCPRE);
sahilmgandhi 18:6a4db94011d3 1504 ADC->CCR |= hadc->Init.ClockPrescaler;
sahilmgandhi 18:6a4db94011d3 1505
sahilmgandhi 18:6a4db94011d3 1506 /* Set ADC scan mode */
sahilmgandhi 18:6a4db94011d3 1507 hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
sahilmgandhi 18:6a4db94011d3 1508 hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
sahilmgandhi 18:6a4db94011d3 1509
sahilmgandhi 18:6a4db94011d3 1510 /* Set ADC resolution */
sahilmgandhi 18:6a4db94011d3 1511 hadc->Instance->CR1 &= ~(ADC_CR1_RES);
sahilmgandhi 18:6a4db94011d3 1512 hadc->Instance->CR1 |= hadc->Init.Resolution;
sahilmgandhi 18:6a4db94011d3 1513
sahilmgandhi 18:6a4db94011d3 1514 /* Set ADC data alignment */
sahilmgandhi 18:6a4db94011d3 1515 hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
sahilmgandhi 18:6a4db94011d3 1516 hadc->Instance->CR2 |= hadc->Init.DataAlign;
sahilmgandhi 18:6a4db94011d3 1517
sahilmgandhi 18:6a4db94011d3 1518 /* Enable external trigger if trigger selection is different of software */
sahilmgandhi 18:6a4db94011d3 1519 /* start. */
sahilmgandhi 18:6a4db94011d3 1520 /* Note: This configuration keeps the hardware feature of parameter */
sahilmgandhi 18:6a4db94011d3 1521 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
sahilmgandhi 18:6a4db94011d3 1522 /* software start. */
sahilmgandhi 18:6a4db94011d3 1523 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
sahilmgandhi 18:6a4db94011d3 1524 {
sahilmgandhi 18:6a4db94011d3 1525 /* Select external trigger to start conversion */
sahilmgandhi 18:6a4db94011d3 1526 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
sahilmgandhi 18:6a4db94011d3 1527 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
sahilmgandhi 18:6a4db94011d3 1528
sahilmgandhi 18:6a4db94011d3 1529 /* Select external trigger polarity */
sahilmgandhi 18:6a4db94011d3 1530 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
sahilmgandhi 18:6a4db94011d3 1531 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
sahilmgandhi 18:6a4db94011d3 1532 }
sahilmgandhi 18:6a4db94011d3 1533 else
sahilmgandhi 18:6a4db94011d3 1534 {
sahilmgandhi 18:6a4db94011d3 1535 /* Reset the external trigger */
sahilmgandhi 18:6a4db94011d3 1536 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
sahilmgandhi 18:6a4db94011d3 1537 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
sahilmgandhi 18:6a4db94011d3 1538 }
sahilmgandhi 18:6a4db94011d3 1539
sahilmgandhi 18:6a4db94011d3 1540 /* Enable or disable ADC continuous conversion mode */
sahilmgandhi 18:6a4db94011d3 1541 hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
sahilmgandhi 18:6a4db94011d3 1542 hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
sahilmgandhi 18:6a4db94011d3 1543
sahilmgandhi 18:6a4db94011d3 1544 if(hadc->Init.DiscontinuousConvMode != DISABLE)
sahilmgandhi 18:6a4db94011d3 1545 {
sahilmgandhi 18:6a4db94011d3 1546 assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
sahilmgandhi 18:6a4db94011d3 1547
sahilmgandhi 18:6a4db94011d3 1548 /* Enable the selected ADC regular discontinuous mode */
sahilmgandhi 18:6a4db94011d3 1549 hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
sahilmgandhi 18:6a4db94011d3 1550
sahilmgandhi 18:6a4db94011d3 1551 /* Set the number of channels to be converted in discontinuous mode */
sahilmgandhi 18:6a4db94011d3 1552 hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
sahilmgandhi 18:6a4db94011d3 1553 hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
sahilmgandhi 18:6a4db94011d3 1554 }
sahilmgandhi 18:6a4db94011d3 1555 else
sahilmgandhi 18:6a4db94011d3 1556 {
sahilmgandhi 18:6a4db94011d3 1557 /* Disable the selected ADC regular discontinuous mode */
sahilmgandhi 18:6a4db94011d3 1558 hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
sahilmgandhi 18:6a4db94011d3 1559 }
sahilmgandhi 18:6a4db94011d3 1560
sahilmgandhi 18:6a4db94011d3 1561 /* Set ADC number of conversion */
sahilmgandhi 18:6a4db94011d3 1562 hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
sahilmgandhi 18:6a4db94011d3 1563 hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
sahilmgandhi 18:6a4db94011d3 1564
sahilmgandhi 18:6a4db94011d3 1565 /* Enable or disable ADC DMA continuous request */
sahilmgandhi 18:6a4db94011d3 1566 hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
sahilmgandhi 18:6a4db94011d3 1567 hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
sahilmgandhi 18:6a4db94011d3 1568
sahilmgandhi 18:6a4db94011d3 1569 /* Enable or disable ADC end of conversion selection */
sahilmgandhi 18:6a4db94011d3 1570 hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
sahilmgandhi 18:6a4db94011d3 1571 hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
sahilmgandhi 18:6a4db94011d3 1572 }
sahilmgandhi 18:6a4db94011d3 1573
sahilmgandhi 18:6a4db94011d3 1574 /**
sahilmgandhi 18:6a4db94011d3 1575 * @brief DMA transfer complete callback.
sahilmgandhi 18:6a4db94011d3 1576 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1577 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1578 * @retval None
sahilmgandhi 18:6a4db94011d3 1579 */
sahilmgandhi 18:6a4db94011d3 1580 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1581 {
sahilmgandhi 18:6a4db94011d3 1582 /* Retrieve ADC handle corresponding to current DMA handle */
sahilmgandhi 18:6a4db94011d3 1583 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1584
sahilmgandhi 18:6a4db94011d3 1585 /* Update state machine on conversion status if not in error state */
sahilmgandhi 18:6a4db94011d3 1586 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
sahilmgandhi 18:6a4db94011d3 1587 {
sahilmgandhi 18:6a4db94011d3 1588 /* Update ADC state machine */
sahilmgandhi 18:6a4db94011d3 1589 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
sahilmgandhi 18:6a4db94011d3 1590
sahilmgandhi 18:6a4db94011d3 1591 /* Determine whether any further conversion upcoming on group regular */
sahilmgandhi 18:6a4db94011d3 1592 /* by external trigger, continuous mode or scan sequence on going. */
sahilmgandhi 18:6a4db94011d3 1593 /* Note: On STM32F4, there is no independent flag of end of sequence. */
sahilmgandhi 18:6a4db94011d3 1594 /* The test of scan sequence on going is done either with scan */
sahilmgandhi 18:6a4db94011d3 1595 /* sequence disabled or with end of conversion flag set to */
sahilmgandhi 18:6a4db94011d3 1596 /* of end of sequence. */
sahilmgandhi 18:6a4db94011d3 1597 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
sahilmgandhi 18:6a4db94011d3 1598 (hadc->Init.ContinuousConvMode == DISABLE) &&
sahilmgandhi 18:6a4db94011d3 1599 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
sahilmgandhi 18:6a4db94011d3 1600 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
sahilmgandhi 18:6a4db94011d3 1601 {
sahilmgandhi 18:6a4db94011d3 1602 /* Disable ADC end of single conversion interrupt on group regular */
sahilmgandhi 18:6a4db94011d3 1603 /* Note: Overrun interrupt was enabled with EOC interrupt in */
sahilmgandhi 18:6a4db94011d3 1604 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
sahilmgandhi 18:6a4db94011d3 1605 /* by overrun IRQ process below. */
sahilmgandhi 18:6a4db94011d3 1606 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
sahilmgandhi 18:6a4db94011d3 1607
sahilmgandhi 18:6a4db94011d3 1608 /* Set ADC state */
sahilmgandhi 18:6a4db94011d3 1609 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
sahilmgandhi 18:6a4db94011d3 1610
sahilmgandhi 18:6a4db94011d3 1611 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
sahilmgandhi 18:6a4db94011d3 1612 {
sahilmgandhi 18:6a4db94011d3 1613 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
sahilmgandhi 18:6a4db94011d3 1614 }
sahilmgandhi 18:6a4db94011d3 1615 }
sahilmgandhi 18:6a4db94011d3 1616
sahilmgandhi 18:6a4db94011d3 1617 /* Conversion complete callback */
sahilmgandhi 18:6a4db94011d3 1618 HAL_ADC_ConvCpltCallback(hadc);
sahilmgandhi 18:6a4db94011d3 1619 }
sahilmgandhi 18:6a4db94011d3 1620 else
sahilmgandhi 18:6a4db94011d3 1621 {
sahilmgandhi 18:6a4db94011d3 1622 /* Call DMA error callback */
sahilmgandhi 18:6a4db94011d3 1623 hadc->DMA_Handle->XferErrorCallback(hdma);
sahilmgandhi 18:6a4db94011d3 1624 }
sahilmgandhi 18:6a4db94011d3 1625 }
sahilmgandhi 18:6a4db94011d3 1626
sahilmgandhi 18:6a4db94011d3 1627 /**
sahilmgandhi 18:6a4db94011d3 1628 * @brief DMA half transfer complete callback.
sahilmgandhi 18:6a4db94011d3 1629 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1630 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1631 * @retval None
sahilmgandhi 18:6a4db94011d3 1632 */
sahilmgandhi 18:6a4db94011d3 1633 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1634 {
sahilmgandhi 18:6a4db94011d3 1635 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1636 /* Conversion complete callback */
sahilmgandhi 18:6a4db94011d3 1637 HAL_ADC_ConvHalfCpltCallback(hadc);
sahilmgandhi 18:6a4db94011d3 1638 }
sahilmgandhi 18:6a4db94011d3 1639
sahilmgandhi 18:6a4db94011d3 1640 /**
sahilmgandhi 18:6a4db94011d3 1641 * @brief DMA error callback
sahilmgandhi 18:6a4db94011d3 1642 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1643 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1644 * @retval None
sahilmgandhi 18:6a4db94011d3 1645 */
sahilmgandhi 18:6a4db94011d3 1646 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1647 {
sahilmgandhi 18:6a4db94011d3 1648 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1649 hadc->State= HAL_ADC_STATE_ERROR_DMA;
sahilmgandhi 18:6a4db94011d3 1650 /* Set ADC error code to DMA error */
sahilmgandhi 18:6a4db94011d3 1651 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
sahilmgandhi 18:6a4db94011d3 1652 HAL_ADC_ErrorCallback(hadc);
sahilmgandhi 18:6a4db94011d3 1653 }
sahilmgandhi 18:6a4db94011d3 1654
sahilmgandhi 18:6a4db94011d3 1655 /**
sahilmgandhi 18:6a4db94011d3 1656 * @}
sahilmgandhi 18:6a4db94011d3 1657 */
sahilmgandhi 18:6a4db94011d3 1658
sahilmgandhi 18:6a4db94011d3 1659 /**
sahilmgandhi 18:6a4db94011d3 1660 * @}
sahilmgandhi 18:6a4db94011d3 1661 */
sahilmgandhi 18:6a4db94011d3 1662
sahilmgandhi 18:6a4db94011d3 1663 #endif /* HAL_ADC_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1664 /**
sahilmgandhi 18:6a4db94011d3 1665 * @}
sahilmgandhi 18:6a4db94011d3 1666 */
sahilmgandhi 18:6a4db94011d3 1667
sahilmgandhi 18:6a4db94011d3 1668 /**
sahilmgandhi 18:6a4db94011d3 1669 * @}
sahilmgandhi 18:6a4db94011d3 1670 */
sahilmgandhi 18:6a4db94011d3 1671
sahilmgandhi 18:6a4db94011d3 1672 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/