MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/pin_device.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * Copyright (c) 2016, STMicroelectronics
sahilmgandhi 18:6a4db94011d3 4 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 7 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 10 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 12 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 13 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 15 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 16 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 28 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 29 */
sahilmgandhi 18:6a4db94011d3 30 #ifndef MBED_PIN_DEVICE_H
sahilmgandhi 18:6a4db94011d3 31 #define MBED_PIN_DEVICE_H
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 // when LL is available, below include can be used
sahilmgandhi 18:6a4db94011d3 36 // #include "stm32f2xx_ll_gpio.h"
sahilmgandhi 18:6a4db94011d3 37 // until then let's define locally the required functions
sahilmgandhi 18:6a4db94011d3 38 #define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
sahilmgandhi 18:6a4db94011d3 39 #define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
sahilmgandhi 18:6a4db94011d3 40 #define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
sahilmgandhi 18:6a4db94011d3 41 #define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
sahilmgandhi 18:6a4db94011d3 42 #define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
sahilmgandhi 18:6a4db94011d3 43 #define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
sahilmgandhi 18:6a4db94011d3 44 #define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
sahilmgandhi 18:6a4db94011d3 45 #define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
sahilmgandhi 18:6a4db94011d3 46 #define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
sahilmgandhi 18:6a4db94011d3 47 #define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
sahilmgandhi 18:6a4db94011d3 48 #define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
sahilmgandhi 18:6a4db94011d3 49 #define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
sahilmgandhi 18:6a4db94011d3 50 #define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
sahilmgandhi 18:6a4db94011d3 51 #define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
sahilmgandhi 18:6a4db94011d3 52 #define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
sahilmgandhi 18:6a4db94011d3 53 #define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #define LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Select input mode */
sahilmgandhi 18:6a4db94011d3 56 #define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
sahilmgandhi 18:6a4db94011d3 57 #define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
sahilmgandhi 18:6a4db94011d3 58 #define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 #define LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U) /*!< Select push-pull as output type */
sahilmgandhi 18:6a4db94011d3 61 #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 #define LL_GPIO_PULL_NO ((uint32_t)0x00000000U) /*!< Select I/O no pull */
sahilmgandhi 18:6a4db94011d3 64 #define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
sahilmgandhi 18:6a4db94011d3 65 #define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 #define LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Select I/O low output speed */
sahilmgandhi 18:6a4db94011d3 68 #define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
sahilmgandhi 18:6a4db94011d3 69 #define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */
sahilmgandhi 18:6a4db94011d3 70 #define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
sahilmgandhi 18:6a4db94011d3 73 {
sahilmgandhi 18:6a4db94011d3 74 MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
sahilmgandhi 18:6a4db94011d3 75 (Alternate << (POSITION_VAL(Pin) * 4U)));
sahilmgandhi 18:6a4db94011d3 76 }
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
sahilmgandhi 18:6a4db94011d3 79 {
sahilmgandhi 18:6a4db94011d3 80 MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
sahilmgandhi 18:6a4db94011d3 81 (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
sahilmgandhi 18:6a4db94011d3 82 }
sahilmgandhi 18:6a4db94011d3 83 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
sahilmgandhi 18:6a4db94011d3 84 {
sahilmgandhi 18:6a4db94011d3 85 MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
sahilmgandhi 18:6a4db94011d3 86 }
sahilmgandhi 18:6a4db94011d3 87 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
sahilmgandhi 18:6a4db94011d3 88 {
sahilmgandhi 18:6a4db94011d3 89 return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
sahilmgandhi 18:6a4db94011d3 90 }
sahilmgandhi 18:6a4db94011d3 91 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
sahilmgandhi 18:6a4db94011d3 92 {
sahilmgandhi 18:6a4db94011d3 93 MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
sahilmgandhi 18:6a4db94011d3 94 }
sahilmgandhi 18:6a4db94011d3 95 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
sahilmgandhi 18:6a4db94011d3 96 {
sahilmgandhi 18:6a4db94011d3 97 MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
sahilmgandhi 18:6a4db94011d3 98 }
sahilmgandhi 18:6a4db94011d3 99 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
sahilmgandhi 18:6a4db94011d3 100 {
sahilmgandhi 18:6a4db94011d3 101 MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
sahilmgandhi 18:6a4db94011d3 102 (Speed << (POSITION_VAL(Pin) * 2U)));
sahilmgandhi 18:6a4db94011d3 103 }
sahilmgandhi 18:6a4db94011d3 104 // Above lines shall be defined in LL when available
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 extern const uint32_t ll_pin_defines[16];
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /* Family specific implementations */
sahilmgandhi 18:6a4db94011d3 109 static inline void stm_pin_DisconnectDebug(PinName pin)
sahilmgandhi 18:6a4db94011d3 110 {
sahilmgandhi 18:6a4db94011d3 111 /* empty for now */
sahilmgandhi 18:6a4db94011d3 112 }
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
sahilmgandhi 18:6a4db94011d3 115 {
sahilmgandhi 18:6a4db94011d3 116 switch (pull_config) {
sahilmgandhi 18:6a4db94011d3 117 case GPIO_PULLUP:
sahilmgandhi 18:6a4db94011d3 118 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP);
sahilmgandhi 18:6a4db94011d3 119 break;
sahilmgandhi 18:6a4db94011d3 120 case GPIO_PULLDOWN:
sahilmgandhi 18:6a4db94011d3 121 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN);
sahilmgandhi 18:6a4db94011d3 122 break;
sahilmgandhi 18:6a4db94011d3 123 default:
sahilmgandhi 18:6a4db94011d3 124 LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_NO);
sahilmgandhi 18:6a4db94011d3 125 break;
sahilmgandhi 18:6a4db94011d3 126 }
sahilmgandhi 18:6a4db94011d3 127 }
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
sahilmgandhi 18:6a4db94011d3 130 {
sahilmgandhi 18:6a4db94011d3 131 uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 if (STM_PIN(pin) > 7)
sahilmgandhi 18:6a4db94011d3 134 LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
sahilmgandhi 18:6a4db94011d3 135 else
sahilmgandhi 18:6a4db94011d3 136 LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
sahilmgandhi 18:6a4db94011d3 137 }
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 #endif