MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc_ex.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f2xx_hal_rcc_ex.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.1.3
sahilmgandhi 18:6a4db94011d3 6 * @date 29-June-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of RCC HAL Extension module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F2xx_HAL_RCC_EX_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F2xx_HAL_RCC_EX_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32f2xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** @addtogroup RCCEx
sahilmgandhi 18:6a4db94011d3 54 * @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
sahilmgandhi 18:6a4db94011d3 59 * @{
sahilmgandhi 18:6a4db94011d3 60 */
sahilmgandhi 18:6a4db94011d3 61 /**
sahilmgandhi 18:6a4db94011d3 62 * @brief PLLI2S Clock structure definition
sahilmgandhi 18:6a4db94011d3 63 */
sahilmgandhi 18:6a4db94011d3 64 typedef struct
sahilmgandhi 18:6a4db94011d3 65 {
sahilmgandhi 18:6a4db94011d3 66 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
sahilmgandhi 18:6a4db94011d3 67 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
sahilmgandhi 18:6a4db94011d3 68 This parameter will be used only when PLLI2S is selected as Clock Source I2S */
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
sahilmgandhi 18:6a4db94011d3 71 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi 18:6a4db94011d3 72 This parameter will be used only when PLLI2S is selected as Clock Source I2S */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 }RCC_PLLI2SInitTypeDef;
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 /**
sahilmgandhi 18:6a4db94011d3 77 * @brief RCC extended clocks structure definition
sahilmgandhi 18:6a4db94011d3 78 */
sahilmgandhi 18:6a4db94011d3 79 typedef struct
sahilmgandhi 18:6a4db94011d3 80 {
sahilmgandhi 18:6a4db94011d3 81 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
sahilmgandhi 18:6a4db94011d3 82 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
sahilmgandhi 18:6a4db94011d3 85 This parameter will be used only when PLLI2S is selected as Clock Source I2S */
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
sahilmgandhi 18:6a4db94011d3 88 This parameter can be a value of @ref RCC_RTC_Clock_Source */
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
sahilmgandhi 18:6a4db94011d3 91 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 }RCC_PeriphCLKInitTypeDef;
sahilmgandhi 18:6a4db94011d3 94 /**
sahilmgandhi 18:6a4db94011d3 95 * @}
sahilmgandhi 18:6a4db94011d3 96 */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 99 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
sahilmgandhi 18:6a4db94011d3 100 * @{
sahilmgandhi 18:6a4db94011d3 101 */
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
sahilmgandhi 18:6a4db94011d3 104 * @{
sahilmgandhi 18:6a4db94011d3 105 */
sahilmgandhi 18:6a4db94011d3 106 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
sahilmgandhi 18:6a4db94011d3 107 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
sahilmgandhi 18:6a4db94011d3 108 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
sahilmgandhi 18:6a4db94011d3 109 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000008)
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /**
sahilmgandhi 18:6a4db94011d3 112 * @}
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
sahilmgandhi 18:6a4db94011d3 116 * @{
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
sahilmgandhi 18:6a4db94011d3 119 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
sahilmgandhi 18:6a4db94011d3 120 /**
sahilmgandhi 18:6a4db94011d3 121 * @}
sahilmgandhi 18:6a4db94011d3 122 */
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 /**
sahilmgandhi 18:6a4db94011d3 125 * @}
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 129 /** @defgroup RCCEx_Exported_Macros RCC Exported Macros
sahilmgandhi 18:6a4db94011d3 130 * @{
sahilmgandhi 18:6a4db94011d3 131 */
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
sahilmgandhi 18:6a4db94011d3 134 * @brief Enables or disables the AHB1 peripheral clock.
sahilmgandhi 18:6a4db94011d3 135 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 136 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 137 * using it.
sahilmgandhi 18:6a4db94011d3 138 * @{
sahilmgandhi 18:6a4db94011d3 139 */
sahilmgandhi 18:6a4db94011d3 140 #if defined(STM32F207xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 141 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 142 __IO uint32_t tmpreg = 0x00; \
sahilmgandhi 18:6a4db94011d3 143 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
sahilmgandhi 18:6a4db94011d3 144 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 145 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
sahilmgandhi 18:6a4db94011d3 146 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 147 } while(0)
sahilmgandhi 18:6a4db94011d3 148 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 149 __IO uint32_t tmpreg = 0x00; \
sahilmgandhi 18:6a4db94011d3 150 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
sahilmgandhi 18:6a4db94011d3 151 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 152 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
sahilmgandhi 18:6a4db94011d3 153 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 154 } while(0)
sahilmgandhi 18:6a4db94011d3 155 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 156 __IO uint32_t tmpreg = 0x00; \
sahilmgandhi 18:6a4db94011d3 157 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
sahilmgandhi 18:6a4db94011d3 158 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 159 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
sahilmgandhi 18:6a4db94011d3 160 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 161 } while(0)
sahilmgandhi 18:6a4db94011d3 162 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 163 __IO uint32_t tmpreg = 0x00; \
sahilmgandhi 18:6a4db94011d3 164 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
sahilmgandhi 18:6a4db94011d3 165 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 166 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
sahilmgandhi 18:6a4db94011d3 167 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 168 } while(0)
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
sahilmgandhi 18:6a4db94011d3 171 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
sahilmgandhi 18:6a4db94011d3 172 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
sahilmgandhi 18:6a4db94011d3 173 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
sahilmgandhi 18:6a4db94011d3 176 * @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi 18:6a4db94011d3 177 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 178 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 179 * using it.
sahilmgandhi 18:6a4db94011d3 180 * @{
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET)
sahilmgandhi 18:6a4db94011d3 183 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET)
sahilmgandhi 18:6a4db94011d3 184 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET)
sahilmgandhi 18:6a4db94011d3 185 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET)
sahilmgandhi 18:6a4db94011d3 186 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
sahilmgandhi 18:6a4db94011d3 187 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
sahilmgandhi 18:6a4db94011d3 188 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
sahilmgandhi 18:6a4db94011d3 189 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET)
sahilmgandhi 18:6a4db94011d3 190 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET)
sahilmgandhi 18:6a4db94011d3 191 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET)
sahilmgandhi 18:6a4db94011d3 192 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET)
sahilmgandhi 18:6a4db94011d3 193 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
sahilmgandhi 18:6a4db94011d3 194 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
sahilmgandhi 18:6a4db94011d3 195 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
sahilmgandhi 18:6a4db94011d3 196 /**
sahilmgandhi 18:6a4db94011d3 197 * @}
sahilmgandhi 18:6a4db94011d3 198 */
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /**
sahilmgandhi 18:6a4db94011d3 201 * @brief Enable ETHERNET clock.
sahilmgandhi 18:6a4db94011d3 202 */
sahilmgandhi 18:6a4db94011d3 203 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 204 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
sahilmgandhi 18:6a4db94011d3 205 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
sahilmgandhi 18:6a4db94011d3 206 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
sahilmgandhi 18:6a4db94011d3 207 } while(0)
sahilmgandhi 18:6a4db94011d3 208 /**
sahilmgandhi 18:6a4db94011d3 209 * @brief Disable ETHERNET clock.
sahilmgandhi 18:6a4db94011d3 210 */
sahilmgandhi 18:6a4db94011d3 211 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
sahilmgandhi 18:6a4db94011d3 212 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
sahilmgandhi 18:6a4db94011d3 213 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
sahilmgandhi 18:6a4db94011d3 214 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
sahilmgandhi 18:6a4db94011d3 215 } while(0)
sahilmgandhi 18:6a4db94011d3 216 #endif /* STM32F207xx || STM32F217xx */
sahilmgandhi 18:6a4db94011d3 217 /**
sahilmgandhi 18:6a4db94011d3 218 * @}
sahilmgandhi 18:6a4db94011d3 219 */
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
sahilmgandhi 18:6a4db94011d3 222 * @brief Enable or disable the AHB2 peripheral clock.
sahilmgandhi 18:6a4db94011d3 223 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 224 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 225 * using it.
sahilmgandhi 18:6a4db94011d3 226 * @{
sahilmgandhi 18:6a4db94011d3 227 */
sahilmgandhi 18:6a4db94011d3 228 #if defined(STM32F207xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 229 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 230 __IO uint32_t tmpreg = 0x00; \
sahilmgandhi 18:6a4db94011d3 231 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
sahilmgandhi 18:6a4db94011d3 232 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 233 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
sahilmgandhi 18:6a4db94011d3 234 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 235 } while(0)
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
sahilmgandhi 18:6a4db94011d3 238 #endif /* STM32F207xx || STM32F217xx */
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 #if defined(STM32F215xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 241 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 242 __IO uint32_t tmpreg = 0x00; \
sahilmgandhi 18:6a4db94011d3 243 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
sahilmgandhi 18:6a4db94011d3 244 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 245 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
sahilmgandhi 18:6a4db94011d3 246 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 247 } while(0)
sahilmgandhi 18:6a4db94011d3 248 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 249 __IO uint32_t tmpreg = 0x00; \
sahilmgandhi 18:6a4db94011d3 250 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
sahilmgandhi 18:6a4db94011d3 251 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 252 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
sahilmgandhi 18:6a4db94011d3 253 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 254 } while(0)
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
sahilmgandhi 18:6a4db94011d3 257 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
sahilmgandhi 18:6a4db94011d3 258 #endif /* STM32F215xx || STM32F217xx */
sahilmgandhi 18:6a4db94011d3 259 /**
sahilmgandhi 18:6a4db94011d3 260 * @}
sahilmgandhi 18:6a4db94011d3 261 */
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
sahilmgandhi 18:6a4db94011d3 264 * @brief Get the enable or disable status of the AHB2 peripheral clock.
sahilmgandhi 18:6a4db94011d3 265 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 266 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 267 * using it.
sahilmgandhi 18:6a4db94011d3 268 * @{
sahilmgandhi 18:6a4db94011d3 269 */
sahilmgandhi 18:6a4db94011d3 270 #if defined(STM32F207xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 271 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET)
sahilmgandhi 18:6a4db94011d3 272 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET)
sahilmgandhi 18:6a4db94011d3 273 #endif /* defined(STM32F207xx) || defined(STM32F217xx) */
sahilmgandhi 18:6a4db94011d3 274 #if defined(STM32F215xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 275 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET)
sahilmgandhi 18:6a4db94011d3 276 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET)
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET)
sahilmgandhi 18:6a4db94011d3 279 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET)
sahilmgandhi 18:6a4db94011d3 280 #endif /* defined(STM32F215xx) || defined(STM32F217xx) */
sahilmgandhi 18:6a4db94011d3 281 /**
sahilmgandhi 18:6a4db94011d3 282 * @}
sahilmgandhi 18:6a4db94011d3 283 */
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
sahilmgandhi 18:6a4db94011d3 286 * @brief Force or release AHB1 peripheral reset.
sahilmgandhi 18:6a4db94011d3 287 * @{
sahilmgandhi 18:6a4db94011d3 288 */
sahilmgandhi 18:6a4db94011d3 289 #if defined(STM32F207xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 290 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
sahilmgandhi 18:6a4db94011d3 291 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
sahilmgandhi 18:6a4db94011d3 292 #endif /* STM32F207xx || STM32F217xx */
sahilmgandhi 18:6a4db94011d3 293 /**
sahilmgandhi 18:6a4db94011d3 294 * @}
sahilmgandhi 18:6a4db94011d3 295 */
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
sahilmgandhi 18:6a4db94011d3 298 * @brief Force or release AHB2 peripheral reset.
sahilmgandhi 18:6a4db94011d3 299 * @{
sahilmgandhi 18:6a4db94011d3 300 */
sahilmgandhi 18:6a4db94011d3 301 #if defined(STM32F207xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 302 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
sahilmgandhi 18:6a4db94011d3 303 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
sahilmgandhi 18:6a4db94011d3 304 #endif /* STM32F207xx || STM32F217xx */
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 #if defined(STM32F215xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 307 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
sahilmgandhi 18:6a4db94011d3 308 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
sahilmgandhi 18:6a4db94011d3 311 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
sahilmgandhi 18:6a4db94011d3 312 #endif /* STM32F215xx || STM32F217xx */
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 /**
sahilmgandhi 18:6a4db94011d3 315 * @}
sahilmgandhi 18:6a4db94011d3 316 */
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
sahilmgandhi 18:6a4db94011d3 319 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi 18:6a4db94011d3 320 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi 18:6a4db94011d3 321 * power consumption.
sahilmgandhi 18:6a4db94011d3 322 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi 18:6a4db94011d3 323 * @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi 18:6a4db94011d3 324 * @{
sahilmgandhi 18:6a4db94011d3 325 */
sahilmgandhi 18:6a4db94011d3 326 #if defined(STM32F207xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 327 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
sahilmgandhi 18:6a4db94011d3 328 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
sahilmgandhi 18:6a4db94011d3 329 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
sahilmgandhi 18:6a4db94011d3 330 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
sahilmgandhi 18:6a4db94011d3 333 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
sahilmgandhi 18:6a4db94011d3 334 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
sahilmgandhi 18:6a4db94011d3 335 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
sahilmgandhi 18:6a4db94011d3 336 #endif /* STM32F207xx || STM32F217xx */
sahilmgandhi 18:6a4db94011d3 337 /**
sahilmgandhi 18:6a4db94011d3 338 * @}
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
sahilmgandhi 18:6a4db94011d3 342 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi 18:6a4db94011d3 343 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi 18:6a4db94011d3 344 * power consumption.
sahilmgandhi 18:6a4db94011d3 345 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi 18:6a4db94011d3 346 * @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi 18:6a4db94011d3 347 * @{
sahilmgandhi 18:6a4db94011d3 348 */
sahilmgandhi 18:6a4db94011d3 349 #if defined(STM32F207xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 350 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
sahilmgandhi 18:6a4db94011d3 351 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
sahilmgandhi 18:6a4db94011d3 352 #endif /* STM32F207xx || STM32F217xx */
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 #if defined(STM32F215xx) || defined(STM32F217xx)
sahilmgandhi 18:6a4db94011d3 355 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
sahilmgandhi 18:6a4db94011d3 356 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
sahilmgandhi 18:6a4db94011d3 359 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
sahilmgandhi 18:6a4db94011d3 360 #endif /* STM32F215xx || STM32F217xx */
sahilmgandhi 18:6a4db94011d3 361 /**
sahilmgandhi 18:6a4db94011d3 362 * @}
sahilmgandhi 18:6a4db94011d3 363 */
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 /**
sahilmgandhi 18:6a4db94011d3 366 * @}
sahilmgandhi 18:6a4db94011d3 367 */
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 370 /** @addtogroup RCCEx_Exported_Functions
sahilmgandhi 18:6a4db94011d3 371 * @{
sahilmgandhi 18:6a4db94011d3 372 */
sahilmgandhi 18:6a4db94011d3 373
sahilmgandhi 18:6a4db94011d3 374 /** @addtogroup RCCEx_Exported_Functions_Group1
sahilmgandhi 18:6a4db94011d3 375 * @{
sahilmgandhi 18:6a4db94011d3 376 */
sahilmgandhi 18:6a4db94011d3 377 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
sahilmgandhi 18:6a4db94011d3 378 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 /**
sahilmgandhi 18:6a4db94011d3 381 * @}
sahilmgandhi 18:6a4db94011d3 382 */
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 /**
sahilmgandhi 18:6a4db94011d3 385 * @}
sahilmgandhi 18:6a4db94011d3 386 */
sahilmgandhi 18:6a4db94011d3 387 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 388 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 389 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 390 /** @defgroup RCCEx_Private_Constants RCC Private Constants
sahilmgandhi 18:6a4db94011d3 391 * @{
sahilmgandhi 18:6a4db94011d3 392 */
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
sahilmgandhi 18:6a4db94011d3 395 * @brief RCC registers bit address in the alias region
sahilmgandhi 18:6a4db94011d3 396 * @{
sahilmgandhi 18:6a4db94011d3 397 */
sahilmgandhi 18:6a4db94011d3 398 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
sahilmgandhi 18:6a4db94011d3 399 /**
sahilmgandhi 18:6a4db94011d3 400 * @}
sahilmgandhi 18:6a4db94011d3 401 */
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 /**
sahilmgandhi 18:6a4db94011d3 404 * @}
sahilmgandhi 18:6a4db94011d3 405 */
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 408 /** @defgroup RCCEx_Private_Macros RCC Private Macros
sahilmgandhi 18:6a4db94011d3 409 * @{
sahilmgandhi 18:6a4db94011d3 410 */
sahilmgandhi 18:6a4db94011d3 411 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
sahilmgandhi 18:6a4db94011d3 412 * @{
sahilmgandhi 18:6a4db94011d3 413 */
sahilmgandhi 18:6a4db94011d3 414 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000F))
sahilmgandhi 18:6a4db94011d3 415 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
sahilmgandhi 18:6a4db94011d3 416 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
sahilmgandhi 18:6a4db94011d3 417 /**
sahilmgandhi 18:6a4db94011d3 418 * @}
sahilmgandhi 18:6a4db94011d3 419 */
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 /**
sahilmgandhi 18:6a4db94011d3 422 * @}
sahilmgandhi 18:6a4db94011d3 423 */
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 /**
sahilmgandhi 18:6a4db94011d3 426 * @}
sahilmgandhi 18:6a4db94011d3 427 */
sahilmgandhi 18:6a4db94011d3 428
sahilmgandhi 18:6a4db94011d3 429 /**
sahilmgandhi 18:6a4db94011d3 430 * @}
sahilmgandhi 18:6a4db94011d3 431 */
sahilmgandhi 18:6a4db94011d3 432 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 433 }
sahilmgandhi 18:6a4db94011d3 434 #endif
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 #endif /* __STM32F2xx_HAL_RCC_EX_H */
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/