Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @file stm32f2xx_hal_rcc.h |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @author MCD Application Team |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @version V1.1.3 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @date 29-June-2016 |
sahilmgandhi | 18:6a4db94011d3 | 7 | * @brief Header file of RCC HAL module. |
sahilmgandhi | 18:6a4db94011d3 | 8 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 9 | * @attention |
sahilmgandhi | 18:6a4db94011d3 | 10 | * |
sahilmgandhi | 18:6a4db94011d3 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
sahilmgandhi | 18:6a4db94011d3 | 12 | * |
sahilmgandhi | 18:6a4db94011d3 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
sahilmgandhi | 18:6a4db94011d3 | 14 | * are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 18 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 19 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
sahilmgandhi | 18:6a4db94011d3 | 21 | * may be used to endorse or promote products derived from this software |
sahilmgandhi | 18:6a4db94011d3 | 22 | * without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 23 | * |
sahilmgandhi | 18:6a4db94011d3 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
sahilmgandhi | 18:6a4db94011d3 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
sahilmgandhi | 18:6a4db94011d3 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
sahilmgandhi | 18:6a4db94011d3 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
sahilmgandhi | 18:6a4db94011d3 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
sahilmgandhi | 18:6a4db94011d3 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
sahilmgandhi | 18:6a4db94011d3 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 34 | * |
sahilmgandhi | 18:6a4db94011d3 | 35 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 36 | */ |
sahilmgandhi | 18:6a4db94011d3 | 37 | |
sahilmgandhi | 18:6a4db94011d3 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 39 | #ifndef __STM32F2xx_HAL_RCC_H |
sahilmgandhi | 18:6a4db94011d3 | 40 | #define __STM32F2xx_HAL_RCC_H |
sahilmgandhi | 18:6a4db94011d3 | 41 | |
sahilmgandhi | 18:6a4db94011d3 | 42 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 43 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 44 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 45 | |
sahilmgandhi | 18:6a4db94011d3 | 46 | /* Includes ------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 47 | #include "stm32f2xx_hal_def.h" |
sahilmgandhi | 18:6a4db94011d3 | 48 | |
sahilmgandhi | 18:6a4db94011d3 | 49 | /** @addtogroup STM32F2xx_HAL_Driver |
sahilmgandhi | 18:6a4db94011d3 | 50 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 51 | */ |
sahilmgandhi | 18:6a4db94011d3 | 52 | |
sahilmgandhi | 18:6a4db94011d3 | 53 | /** @addtogroup RCC |
sahilmgandhi | 18:6a4db94011d3 | 54 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 55 | */ |
sahilmgandhi | 18:6a4db94011d3 | 56 | |
sahilmgandhi | 18:6a4db94011d3 | 57 | /* Exported types ------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 58 | /** @defgroup RCC_Exported_Types RCC Exported Types |
sahilmgandhi | 18:6a4db94011d3 | 59 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 60 | */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | |
sahilmgandhi | 18:6a4db94011d3 | 62 | /** |
sahilmgandhi | 18:6a4db94011d3 | 63 | * @brief RCC PLL configuration structure definition |
sahilmgandhi | 18:6a4db94011d3 | 64 | */ |
sahilmgandhi | 18:6a4db94011d3 | 65 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 66 | { |
sahilmgandhi | 18:6a4db94011d3 | 67 | uint32_t PLLState; /*!< The new state of the PLL. |
sahilmgandhi | 18:6a4db94011d3 | 68 | This parameter can be a value of @ref RCC_PLL_Config */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | |
sahilmgandhi | 18:6a4db94011d3 | 70 | uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. |
sahilmgandhi | 18:6a4db94011d3 | 71 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | |
sahilmgandhi | 18:6a4db94011d3 | 73 | uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. |
sahilmgandhi | 18:6a4db94011d3 | 74 | This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | |
sahilmgandhi | 18:6a4db94011d3 | 76 | uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. |
sahilmgandhi | 18:6a4db94011d3 | 77 | This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ |
sahilmgandhi | 18:6a4db94011d3 | 78 | |
sahilmgandhi | 18:6a4db94011d3 | 79 | uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). |
sahilmgandhi | 18:6a4db94011d3 | 80 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | |
sahilmgandhi | 18:6a4db94011d3 | 82 | uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. |
sahilmgandhi | 18:6a4db94011d3 | 83 | This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | |
sahilmgandhi | 18:6a4db94011d3 | 85 | }RCC_PLLInitTypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 86 | |
sahilmgandhi | 18:6a4db94011d3 | 87 | /** |
sahilmgandhi | 18:6a4db94011d3 | 88 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
sahilmgandhi | 18:6a4db94011d3 | 89 | */ |
sahilmgandhi | 18:6a4db94011d3 | 90 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 91 | { |
sahilmgandhi | 18:6a4db94011d3 | 92 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
sahilmgandhi | 18:6a4db94011d3 | 93 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
sahilmgandhi | 18:6a4db94011d3 | 94 | |
sahilmgandhi | 18:6a4db94011d3 | 95 | uint32_t HSEState; /*!< The new state of the HSE. |
sahilmgandhi | 18:6a4db94011d3 | 96 | This parameter can be a value of @ref RCC_HSE_Config */ |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | uint32_t LSEState; /*!< The new state of the LSE. |
sahilmgandhi | 18:6a4db94011d3 | 99 | This parameter can be a value of @ref RCC_LSE_Config */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | |
sahilmgandhi | 18:6a4db94011d3 | 101 | uint32_t HSIState; /*!< The new state of the HSI. |
sahilmgandhi | 18:6a4db94011d3 | 102 | This parameter can be a value of @ref RCC_HSI_Config */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | |
sahilmgandhi | 18:6a4db94011d3 | 104 | uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). |
sahilmgandhi | 18:6a4db94011d3 | 105 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | |
sahilmgandhi | 18:6a4db94011d3 | 107 | uint32_t LSIState; /*!< The new state of the LSI. |
sahilmgandhi | 18:6a4db94011d3 | 108 | This parameter can be a value of @ref RCC_LSI_Config */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | |
sahilmgandhi | 18:6a4db94011d3 | 110 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 111 | }RCC_OscInitTypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 112 | |
sahilmgandhi | 18:6a4db94011d3 | 113 | /** |
sahilmgandhi | 18:6a4db94011d3 | 114 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
sahilmgandhi | 18:6a4db94011d3 | 115 | */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 117 | { |
sahilmgandhi | 18:6a4db94011d3 | 118 | uint32_t ClockType; /*!< The clock to be configured. |
sahilmgandhi | 18:6a4db94011d3 | 119 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | |
sahilmgandhi | 18:6a4db94011d3 | 121 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
sahilmgandhi | 18:6a4db94011d3 | 122 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
sahilmgandhi | 18:6a4db94011d3 | 123 | |
sahilmgandhi | 18:6a4db94011d3 | 124 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
sahilmgandhi | 18:6a4db94011d3 | 125 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
sahilmgandhi | 18:6a4db94011d3 | 126 | |
sahilmgandhi | 18:6a4db94011d3 | 127 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
sahilmgandhi | 18:6a4db94011d3 | 128 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
sahilmgandhi | 18:6a4db94011d3 | 129 | |
sahilmgandhi | 18:6a4db94011d3 | 130 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
sahilmgandhi | 18:6a4db94011d3 | 131 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | }RCC_ClkInitTypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 134 | |
sahilmgandhi | 18:6a4db94011d3 | 135 | /** |
sahilmgandhi | 18:6a4db94011d3 | 136 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 137 | */ |
sahilmgandhi | 18:6a4db94011d3 | 138 | |
sahilmgandhi | 18:6a4db94011d3 | 139 | /* Exported constants --------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 140 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
sahilmgandhi | 18:6a4db94011d3 | 141 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 142 | */ |
sahilmgandhi | 18:6a4db94011d3 | 143 | |
sahilmgandhi | 18:6a4db94011d3 | 144 | /** @defgroup RCC_Oscillator_Type Oscillator Type |
sahilmgandhi | 18:6a4db94011d3 | 145 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 146 | */ |
sahilmgandhi | 18:6a4db94011d3 | 147 | #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) |
sahilmgandhi | 18:6a4db94011d3 | 148 | #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) |
sahilmgandhi | 18:6a4db94011d3 | 149 | #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) |
sahilmgandhi | 18:6a4db94011d3 | 150 | #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) |
sahilmgandhi | 18:6a4db94011d3 | 151 | #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) |
sahilmgandhi | 18:6a4db94011d3 | 152 | /** |
sahilmgandhi | 18:6a4db94011d3 | 153 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 154 | */ |
sahilmgandhi | 18:6a4db94011d3 | 155 | |
sahilmgandhi | 18:6a4db94011d3 | 156 | /** @defgroup RCC_HSE_Config HSE Config |
sahilmgandhi | 18:6a4db94011d3 | 157 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 158 | */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | #define RCC_HSE_OFF ((uint8_t)0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 160 | #define RCC_HSE_ON ((uint8_t)0x01U) |
sahilmgandhi | 18:6a4db94011d3 | 161 | #define RCC_HSE_BYPASS ((uint8_t)0x05U) |
sahilmgandhi | 18:6a4db94011d3 | 162 | /** |
sahilmgandhi | 18:6a4db94011d3 | 163 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 164 | */ |
sahilmgandhi | 18:6a4db94011d3 | 165 | |
sahilmgandhi | 18:6a4db94011d3 | 166 | /** @defgroup RCC_LSE_Config LSE Config |
sahilmgandhi | 18:6a4db94011d3 | 167 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 168 | */ |
sahilmgandhi | 18:6a4db94011d3 | 169 | #define RCC_LSE_OFF ((uint8_t)0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 170 | #define RCC_LSE_ON ((uint8_t)0x01U) |
sahilmgandhi | 18:6a4db94011d3 | 171 | #define RCC_LSE_BYPASS ((uint8_t)0x05U) |
sahilmgandhi | 18:6a4db94011d3 | 172 | /** |
sahilmgandhi | 18:6a4db94011d3 | 173 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 174 | */ |
sahilmgandhi | 18:6a4db94011d3 | 175 | |
sahilmgandhi | 18:6a4db94011d3 | 176 | /** @defgroup RCC_HSI_Config HSI Config |
sahilmgandhi | 18:6a4db94011d3 | 177 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 178 | */ |
sahilmgandhi | 18:6a4db94011d3 | 179 | #define RCC_HSI_OFF ((uint8_t)0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 180 | #define RCC_HSI_ON ((uint8_t)0x01U) |
sahilmgandhi | 18:6a4db94011d3 | 181 | |
sahilmgandhi | 18:6a4db94011d3 | 182 | #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ |
sahilmgandhi | 18:6a4db94011d3 | 183 | /** |
sahilmgandhi | 18:6a4db94011d3 | 184 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 185 | */ |
sahilmgandhi | 18:6a4db94011d3 | 186 | |
sahilmgandhi | 18:6a4db94011d3 | 187 | /** @defgroup RCC_LSI_Config LSI Config |
sahilmgandhi | 18:6a4db94011d3 | 188 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 189 | */ |
sahilmgandhi | 18:6a4db94011d3 | 190 | #define RCC_LSI_OFF ((uint8_t)0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 191 | #define RCC_LSI_ON ((uint8_t)0x01U) |
sahilmgandhi | 18:6a4db94011d3 | 192 | /** |
sahilmgandhi | 18:6a4db94011d3 | 193 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 194 | */ |
sahilmgandhi | 18:6a4db94011d3 | 195 | |
sahilmgandhi | 18:6a4db94011d3 | 196 | /** @defgroup RCC_PLL_Config PLL Config |
sahilmgandhi | 18:6a4db94011d3 | 197 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 198 | */ |
sahilmgandhi | 18:6a4db94011d3 | 199 | #define RCC_PLL_NONE ((uint8_t)0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 200 | #define RCC_PLL_OFF ((uint8_t)0x01U) |
sahilmgandhi | 18:6a4db94011d3 | 201 | #define RCC_PLL_ON ((uint8_t)0x02U) |
sahilmgandhi | 18:6a4db94011d3 | 202 | /** |
sahilmgandhi | 18:6a4db94011d3 | 203 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 204 | */ |
sahilmgandhi | 18:6a4db94011d3 | 205 | |
sahilmgandhi | 18:6a4db94011d3 | 206 | /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider |
sahilmgandhi | 18:6a4db94011d3 | 207 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 208 | */ |
sahilmgandhi | 18:6a4db94011d3 | 209 | #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) |
sahilmgandhi | 18:6a4db94011d3 | 210 | #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) |
sahilmgandhi | 18:6a4db94011d3 | 211 | #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) |
sahilmgandhi | 18:6a4db94011d3 | 212 | #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) |
sahilmgandhi | 18:6a4db94011d3 | 213 | /** |
sahilmgandhi | 18:6a4db94011d3 | 214 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 215 | */ |
sahilmgandhi | 18:6a4db94011d3 | 216 | |
sahilmgandhi | 18:6a4db94011d3 | 217 | /** @defgroup RCC_PLL_Clock_Source PLL Clock Source |
sahilmgandhi | 18:6a4db94011d3 | 218 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 219 | */ |
sahilmgandhi | 18:6a4db94011d3 | 220 | #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI |
sahilmgandhi | 18:6a4db94011d3 | 221 | #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE |
sahilmgandhi | 18:6a4db94011d3 | 222 | /** |
sahilmgandhi | 18:6a4db94011d3 | 223 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 224 | */ |
sahilmgandhi | 18:6a4db94011d3 | 225 | |
sahilmgandhi | 18:6a4db94011d3 | 226 | /** @defgroup RCC_System_Clock_Type System Clock Type |
sahilmgandhi | 18:6a4db94011d3 | 227 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 228 | */ |
sahilmgandhi | 18:6a4db94011d3 | 229 | #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) |
sahilmgandhi | 18:6a4db94011d3 | 230 | #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) |
sahilmgandhi | 18:6a4db94011d3 | 231 | #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) |
sahilmgandhi | 18:6a4db94011d3 | 232 | #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) |
sahilmgandhi | 18:6a4db94011d3 | 233 | /** |
sahilmgandhi | 18:6a4db94011d3 | 234 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 235 | */ |
sahilmgandhi | 18:6a4db94011d3 | 236 | |
sahilmgandhi | 18:6a4db94011d3 | 237 | /** @defgroup RCC_System_Clock_Source System Clock Source |
sahilmgandhi | 18:6a4db94011d3 | 238 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 239 | */ |
sahilmgandhi | 18:6a4db94011d3 | 240 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
sahilmgandhi | 18:6a4db94011d3 | 241 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
sahilmgandhi | 18:6a4db94011d3 | 242 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL |
sahilmgandhi | 18:6a4db94011d3 | 243 | /** |
sahilmgandhi | 18:6a4db94011d3 | 244 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 245 | */ |
sahilmgandhi | 18:6a4db94011d3 | 246 | |
sahilmgandhi | 18:6a4db94011d3 | 247 | /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status |
sahilmgandhi | 18:6a4db94011d3 | 248 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 249 | */ |
sahilmgandhi | 18:6a4db94011d3 | 250 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
sahilmgandhi | 18:6a4db94011d3 | 251 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
sahilmgandhi | 18:6a4db94011d3 | 252 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
sahilmgandhi | 18:6a4db94011d3 | 253 | /** |
sahilmgandhi | 18:6a4db94011d3 | 254 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 255 | */ |
sahilmgandhi | 18:6a4db94011d3 | 256 | |
sahilmgandhi | 18:6a4db94011d3 | 257 | /** @defgroup RCC_AHB_Clock_Source AHB Clock Source |
sahilmgandhi | 18:6a4db94011d3 | 258 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 259 | */ |
sahilmgandhi | 18:6a4db94011d3 | 260 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 |
sahilmgandhi | 18:6a4db94011d3 | 261 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 |
sahilmgandhi | 18:6a4db94011d3 | 262 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 |
sahilmgandhi | 18:6a4db94011d3 | 263 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 |
sahilmgandhi | 18:6a4db94011d3 | 264 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 |
sahilmgandhi | 18:6a4db94011d3 | 265 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 |
sahilmgandhi | 18:6a4db94011d3 | 266 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 |
sahilmgandhi | 18:6a4db94011d3 | 267 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 |
sahilmgandhi | 18:6a4db94011d3 | 268 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 |
sahilmgandhi | 18:6a4db94011d3 | 269 | /** |
sahilmgandhi | 18:6a4db94011d3 | 270 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 271 | */ |
sahilmgandhi | 18:6a4db94011d3 | 272 | |
sahilmgandhi | 18:6a4db94011d3 | 273 | /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source |
sahilmgandhi | 18:6a4db94011d3 | 274 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 275 | */ |
sahilmgandhi | 18:6a4db94011d3 | 276 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 |
sahilmgandhi | 18:6a4db94011d3 | 277 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 |
sahilmgandhi | 18:6a4db94011d3 | 278 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 |
sahilmgandhi | 18:6a4db94011d3 | 279 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 |
sahilmgandhi | 18:6a4db94011d3 | 280 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 |
sahilmgandhi | 18:6a4db94011d3 | 281 | /** |
sahilmgandhi | 18:6a4db94011d3 | 282 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 283 | */ |
sahilmgandhi | 18:6a4db94011d3 | 284 | |
sahilmgandhi | 18:6a4db94011d3 | 285 | /** @defgroup RCC_RTC_Clock_Source RTC Clock Source |
sahilmgandhi | 18:6a4db94011d3 | 286 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 287 | */ |
sahilmgandhi | 18:6a4db94011d3 | 288 | #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) |
sahilmgandhi | 18:6a4db94011d3 | 289 | #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) |
sahilmgandhi | 18:6a4db94011d3 | 290 | #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) |
sahilmgandhi | 18:6a4db94011d3 | 291 | #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) |
sahilmgandhi | 18:6a4db94011d3 | 292 | #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) |
sahilmgandhi | 18:6a4db94011d3 | 293 | #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) |
sahilmgandhi | 18:6a4db94011d3 | 294 | #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) |
sahilmgandhi | 18:6a4db94011d3 | 295 | #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) |
sahilmgandhi | 18:6a4db94011d3 | 296 | #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) |
sahilmgandhi | 18:6a4db94011d3 | 297 | #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) |
sahilmgandhi | 18:6a4db94011d3 | 298 | #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) |
sahilmgandhi | 18:6a4db94011d3 | 299 | #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) |
sahilmgandhi | 18:6a4db94011d3 | 300 | #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) |
sahilmgandhi | 18:6a4db94011d3 | 301 | #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) |
sahilmgandhi | 18:6a4db94011d3 | 302 | #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) |
sahilmgandhi | 18:6a4db94011d3 | 303 | #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) |
sahilmgandhi | 18:6a4db94011d3 | 304 | #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) |
sahilmgandhi | 18:6a4db94011d3 | 305 | #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) |
sahilmgandhi | 18:6a4db94011d3 | 306 | #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) |
sahilmgandhi | 18:6a4db94011d3 | 307 | #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) |
sahilmgandhi | 18:6a4db94011d3 | 308 | #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) |
sahilmgandhi | 18:6a4db94011d3 | 309 | #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) |
sahilmgandhi | 18:6a4db94011d3 | 310 | #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) |
sahilmgandhi | 18:6a4db94011d3 | 311 | #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) |
sahilmgandhi | 18:6a4db94011d3 | 312 | #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) |
sahilmgandhi | 18:6a4db94011d3 | 313 | #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) |
sahilmgandhi | 18:6a4db94011d3 | 314 | #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) |
sahilmgandhi | 18:6a4db94011d3 | 315 | #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) |
sahilmgandhi | 18:6a4db94011d3 | 316 | #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) |
sahilmgandhi | 18:6a4db94011d3 | 317 | #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) |
sahilmgandhi | 18:6a4db94011d3 | 318 | #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) |
sahilmgandhi | 18:6a4db94011d3 | 319 | #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) |
sahilmgandhi | 18:6a4db94011d3 | 320 | /** |
sahilmgandhi | 18:6a4db94011d3 | 321 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 322 | */ |
sahilmgandhi | 18:6a4db94011d3 | 323 | |
sahilmgandhi | 18:6a4db94011d3 | 324 | /** @defgroup RCC_MCO_Index MCO Index |
sahilmgandhi | 18:6a4db94011d3 | 325 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 326 | */ |
sahilmgandhi | 18:6a4db94011d3 | 327 | #define RCC_MCO1 ((uint32_t)0x00000000U) |
sahilmgandhi | 18:6a4db94011d3 | 328 | #define RCC_MCO2 ((uint32_t)0x00000001U) |
sahilmgandhi | 18:6a4db94011d3 | 329 | /** |
sahilmgandhi | 18:6a4db94011d3 | 330 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 331 | */ |
sahilmgandhi | 18:6a4db94011d3 | 332 | |
sahilmgandhi | 18:6a4db94011d3 | 333 | /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source |
sahilmgandhi | 18:6a4db94011d3 | 334 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 335 | */ |
sahilmgandhi | 18:6a4db94011d3 | 336 | #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) |
sahilmgandhi | 18:6a4db94011d3 | 337 | #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 |
sahilmgandhi | 18:6a4db94011d3 | 338 | #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 |
sahilmgandhi | 18:6a4db94011d3 | 339 | #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 |
sahilmgandhi | 18:6a4db94011d3 | 340 | /** |
sahilmgandhi | 18:6a4db94011d3 | 341 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 342 | */ |
sahilmgandhi | 18:6a4db94011d3 | 343 | |
sahilmgandhi | 18:6a4db94011d3 | 344 | /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source |
sahilmgandhi | 18:6a4db94011d3 | 345 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 346 | */ |
sahilmgandhi | 18:6a4db94011d3 | 347 | #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) |
sahilmgandhi | 18:6a4db94011d3 | 348 | #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 |
sahilmgandhi | 18:6a4db94011d3 | 349 | #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 |
sahilmgandhi | 18:6a4db94011d3 | 350 | #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 |
sahilmgandhi | 18:6a4db94011d3 | 351 | /** |
sahilmgandhi | 18:6a4db94011d3 | 352 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 353 | */ |
sahilmgandhi | 18:6a4db94011d3 | 354 | |
sahilmgandhi | 18:6a4db94011d3 | 355 | /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler |
sahilmgandhi | 18:6a4db94011d3 | 356 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 357 | */ |
sahilmgandhi | 18:6a4db94011d3 | 358 | #define RCC_MCODIV_1 ((uint32_t)0x00000000U) |
sahilmgandhi | 18:6a4db94011d3 | 359 | #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 |
sahilmgandhi | 18:6a4db94011d3 | 360 | #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) |
sahilmgandhi | 18:6a4db94011d3 | 361 | #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) |
sahilmgandhi | 18:6a4db94011d3 | 362 | #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE |
sahilmgandhi | 18:6a4db94011d3 | 363 | /** |
sahilmgandhi | 18:6a4db94011d3 | 364 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 365 | */ |
sahilmgandhi | 18:6a4db94011d3 | 366 | |
sahilmgandhi | 18:6a4db94011d3 | 367 | /** @defgroup RCC_Interrupt Interrupts |
sahilmgandhi | 18:6a4db94011d3 | 368 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 369 | */ |
sahilmgandhi | 18:6a4db94011d3 | 370 | #define RCC_IT_LSIRDY ((uint8_t)0x01U) |
sahilmgandhi | 18:6a4db94011d3 | 371 | #define RCC_IT_LSERDY ((uint8_t)0x02U) |
sahilmgandhi | 18:6a4db94011d3 | 372 | #define RCC_IT_HSIRDY ((uint8_t)0x04U) |
sahilmgandhi | 18:6a4db94011d3 | 373 | #define RCC_IT_HSERDY ((uint8_t)0x08U) |
sahilmgandhi | 18:6a4db94011d3 | 374 | #define RCC_IT_PLLRDY ((uint8_t)0x10U) |
sahilmgandhi | 18:6a4db94011d3 | 375 | #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) |
sahilmgandhi | 18:6a4db94011d3 | 376 | #define RCC_IT_CSS ((uint8_t)0x80U) |
sahilmgandhi | 18:6a4db94011d3 | 377 | /** |
sahilmgandhi | 18:6a4db94011d3 | 378 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 379 | */ |
sahilmgandhi | 18:6a4db94011d3 | 380 | |
sahilmgandhi | 18:6a4db94011d3 | 381 | /** @defgroup RCC_Flag Flags |
sahilmgandhi | 18:6a4db94011d3 | 382 | * Elements values convention: 0XXYYYYYb |
sahilmgandhi | 18:6a4db94011d3 | 383 | * - YYYYY : Flag position in the register |
sahilmgandhi | 18:6a4db94011d3 | 384 | * - 0XX : Register index |
sahilmgandhi | 18:6a4db94011d3 | 385 | * - 01: CR register |
sahilmgandhi | 18:6a4db94011d3 | 386 | * - 10: BDCR register |
sahilmgandhi | 18:6a4db94011d3 | 387 | * - 11: CSR register |
sahilmgandhi | 18:6a4db94011d3 | 388 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 389 | */ |
sahilmgandhi | 18:6a4db94011d3 | 390 | /* Flags in the CR register */ |
sahilmgandhi | 18:6a4db94011d3 | 391 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21U) |
sahilmgandhi | 18:6a4db94011d3 | 392 | #define RCC_FLAG_HSERDY ((uint8_t)0x31U) |
sahilmgandhi | 18:6a4db94011d3 | 393 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39U) |
sahilmgandhi | 18:6a4db94011d3 | 394 | #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) |
sahilmgandhi | 18:6a4db94011d3 | 395 | |
sahilmgandhi | 18:6a4db94011d3 | 396 | /* Flags in the BDCR register */ |
sahilmgandhi | 18:6a4db94011d3 | 397 | #define RCC_FLAG_LSERDY ((uint8_t)0x41U) |
sahilmgandhi | 18:6a4db94011d3 | 398 | |
sahilmgandhi | 18:6a4db94011d3 | 399 | /* Flags in the CSR register */ |
sahilmgandhi | 18:6a4db94011d3 | 400 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61U) |
sahilmgandhi | 18:6a4db94011d3 | 401 | #define RCC_FLAG_BORRST ((uint8_t)0x79U) |
sahilmgandhi | 18:6a4db94011d3 | 402 | #define RCC_FLAG_PINRST ((uint8_t)0x7AU) |
sahilmgandhi | 18:6a4db94011d3 | 403 | #define RCC_FLAG_PORRST ((uint8_t)0x7BU) |
sahilmgandhi | 18:6a4db94011d3 | 404 | #define RCC_FLAG_SFTRST ((uint8_t)0x7CU) |
sahilmgandhi | 18:6a4db94011d3 | 405 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) |
sahilmgandhi | 18:6a4db94011d3 | 406 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) |
sahilmgandhi | 18:6a4db94011d3 | 407 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) |
sahilmgandhi | 18:6a4db94011d3 | 408 | /** |
sahilmgandhi | 18:6a4db94011d3 | 409 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 410 | */ |
sahilmgandhi | 18:6a4db94011d3 | 411 | |
sahilmgandhi | 18:6a4db94011d3 | 412 | /** |
sahilmgandhi | 18:6a4db94011d3 | 413 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 414 | */ |
sahilmgandhi | 18:6a4db94011d3 | 415 | |
sahilmgandhi | 18:6a4db94011d3 | 416 | /* Exported macro ------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 417 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
sahilmgandhi | 18:6a4db94011d3 | 418 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 419 | */ |
sahilmgandhi | 18:6a4db94011d3 | 420 | |
sahilmgandhi | 18:6a4db94011d3 | 421 | /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 422 | * @brief Enable or disable the AHB1 peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 423 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 424 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 425 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 426 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 427 | */ |
sahilmgandhi | 18:6a4db94011d3 | 428 | #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 429 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 430 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 431 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 432 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 433 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 434 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 435 | #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 436 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 437 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 438 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 439 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 440 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 441 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 442 | #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 443 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 444 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 445 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 446 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 447 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 448 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 449 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 450 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 451 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 452 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 453 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 454 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 455 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 456 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 457 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 458 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 459 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 460 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 461 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 462 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 463 | #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 464 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 465 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 466 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 467 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 468 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 469 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 470 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 471 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 472 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 473 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 474 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 475 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 476 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 477 | #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 478 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 479 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 480 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 481 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 482 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 483 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 484 | #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 485 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 486 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 487 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 488 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 489 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 490 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 491 | #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 492 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 493 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 494 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 495 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 496 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 497 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 498 | #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 499 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 500 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 501 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 502 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 503 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 504 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 505 | #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 506 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 507 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 508 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 509 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 510 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 511 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 512 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 513 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 514 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 515 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 516 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 517 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 518 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 519 | #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 520 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 521 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 522 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 523 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 524 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 525 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 526 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 527 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 528 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 529 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 530 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 531 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 532 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 533 | #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) |
sahilmgandhi | 18:6a4db94011d3 | 534 | #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) |
sahilmgandhi | 18:6a4db94011d3 | 535 | #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) |
sahilmgandhi | 18:6a4db94011d3 | 536 | #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) |
sahilmgandhi | 18:6a4db94011d3 | 537 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) |
sahilmgandhi | 18:6a4db94011d3 | 538 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) |
sahilmgandhi | 18:6a4db94011d3 | 539 | #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) |
sahilmgandhi | 18:6a4db94011d3 | 540 | #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) |
sahilmgandhi | 18:6a4db94011d3 | 541 | #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) |
sahilmgandhi | 18:6a4db94011d3 | 542 | #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) |
sahilmgandhi | 18:6a4db94011d3 | 543 | #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) |
sahilmgandhi | 18:6a4db94011d3 | 544 | #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) |
sahilmgandhi | 18:6a4db94011d3 | 545 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) |
sahilmgandhi | 18:6a4db94011d3 | 546 | #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) |
sahilmgandhi | 18:6a4db94011d3 | 547 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) |
sahilmgandhi | 18:6a4db94011d3 | 548 | /** |
sahilmgandhi | 18:6a4db94011d3 | 549 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 550 | */ |
sahilmgandhi | 18:6a4db94011d3 | 551 | /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status |
sahilmgandhi | 18:6a4db94011d3 | 552 | * @brief Get the enable or disable status of the AHB1 peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 553 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 554 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 555 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 556 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 557 | */ |
sahilmgandhi | 18:6a4db94011d3 | 558 | #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 559 | #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 560 | #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 561 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 562 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 563 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 564 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 565 | #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 566 | #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 567 | #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 568 | #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 569 | #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 570 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 571 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 572 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 573 | |
sahilmgandhi | 18:6a4db94011d3 | 574 | #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 575 | #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 576 | #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 577 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 578 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 579 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 580 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 581 | #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 582 | #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 583 | #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 584 | #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 585 | #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 586 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 587 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 588 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 589 | /** |
sahilmgandhi | 18:6a4db94011d3 | 590 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 591 | */ |
sahilmgandhi | 18:6a4db94011d3 | 592 | |
sahilmgandhi | 18:6a4db94011d3 | 593 | /** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 594 | * @brief Enable or disable the AHB2 peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 595 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 596 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 597 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 598 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 599 | */ |
sahilmgandhi | 18:6a4db94011d3 | 600 | #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ |
sahilmgandhi | 18:6a4db94011d3 | 601 | __HAL_RCC_SYSCFG_CLK_ENABLE();\ |
sahilmgandhi | 18:6a4db94011d3 | 602 | }while(0) |
sahilmgandhi | 18:6a4db94011d3 | 603 | #define __HAL_RCC_RNG_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 604 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 605 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 606 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 607 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 608 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 609 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 610 | |
sahilmgandhi | 18:6a4db94011d3 | 611 | #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) |
sahilmgandhi | 18:6a4db94011d3 | 612 | #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) |
sahilmgandhi | 18:6a4db94011d3 | 613 | /** |
sahilmgandhi | 18:6a4db94011d3 | 614 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 615 | */ |
sahilmgandhi | 18:6a4db94011d3 | 616 | |
sahilmgandhi | 18:6a4db94011d3 | 617 | /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status |
sahilmgandhi | 18:6a4db94011d3 | 618 | * @brief Get the enable or disable status of the AHB2 peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 619 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 620 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 621 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 622 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 623 | */ |
sahilmgandhi | 18:6a4db94011d3 | 624 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 625 | #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 626 | |
sahilmgandhi | 18:6a4db94011d3 | 627 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 628 | #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 629 | /** |
sahilmgandhi | 18:6a4db94011d3 | 630 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 631 | */ |
sahilmgandhi | 18:6a4db94011d3 | 632 | |
sahilmgandhi | 18:6a4db94011d3 | 633 | /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 634 | * @brief Enables or disables the AHB3 peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 635 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 636 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 637 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 638 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 639 | */ |
sahilmgandhi | 18:6a4db94011d3 | 640 | #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 641 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 642 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 643 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 644 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 645 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 646 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 647 | #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) |
sahilmgandhi | 18:6a4db94011d3 | 648 | /** |
sahilmgandhi | 18:6a4db94011d3 | 649 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 650 | */ |
sahilmgandhi | 18:6a4db94011d3 | 651 | |
sahilmgandhi | 18:6a4db94011d3 | 652 | /** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status |
sahilmgandhi | 18:6a4db94011d3 | 653 | * @brief Get the enable or disable status of the AHB3 peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 654 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 655 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 656 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 657 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 658 | */ |
sahilmgandhi | 18:6a4db94011d3 | 659 | #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 660 | #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 661 | /** |
sahilmgandhi | 18:6a4db94011d3 | 662 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 663 | */ |
sahilmgandhi | 18:6a4db94011d3 | 664 | |
sahilmgandhi | 18:6a4db94011d3 | 665 | /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 666 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 667 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 668 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 669 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 670 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 671 | */ |
sahilmgandhi | 18:6a4db94011d3 | 672 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 673 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 674 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 675 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 676 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 677 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 678 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 679 | #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 680 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 681 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 682 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 683 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 684 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 685 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 686 | #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 687 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 688 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 689 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 690 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 691 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 692 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 693 | #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 694 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 695 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 696 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 697 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 698 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 699 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 700 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 701 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 702 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 703 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 704 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 705 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 706 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 707 | #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 708 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 709 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 710 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 711 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 712 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 713 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 714 | #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 715 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 716 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 717 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 718 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 719 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 720 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 721 | #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 722 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 723 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 724 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 725 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 726 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 727 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 728 | #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 729 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 730 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 731 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 732 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 733 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 734 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 735 | #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 736 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 737 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 738 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 739 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 740 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 741 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 742 | #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 743 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 744 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 745 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 746 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 747 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 748 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 749 | #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 750 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 751 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 752 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 753 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 754 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 755 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 756 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 757 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 758 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 759 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 760 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 761 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 762 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 763 | #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 764 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 765 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 766 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 767 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 768 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 769 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 770 | #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 771 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 772 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 773 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 774 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 775 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 776 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 777 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 778 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 779 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 780 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 781 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 782 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 783 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 784 | #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 785 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 786 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 787 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 788 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 789 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 790 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 791 | #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 792 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 793 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 794 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 795 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 796 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 797 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 798 | #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 799 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 800 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 801 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 802 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 803 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 804 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 805 | #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 806 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 807 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 808 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 809 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 810 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 811 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 812 | #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 813 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 814 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 815 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 816 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 817 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 818 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 819 | #define __HAL_RCC_PWR_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 820 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 821 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
sahilmgandhi | 18:6a4db94011d3 | 822 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 823 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
sahilmgandhi | 18:6a4db94011d3 | 824 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 825 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 826 | #define __HAL_RCC_DAC_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 827 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 828 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 829 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 830 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 831 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 832 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 833 | |
sahilmgandhi | 18:6a4db94011d3 | 834 | #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
sahilmgandhi | 18:6a4db94011d3 | 835 | #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
sahilmgandhi | 18:6a4db94011d3 | 836 | #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
sahilmgandhi | 18:6a4db94011d3 | 837 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
sahilmgandhi | 18:6a4db94011d3 | 838 | #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
sahilmgandhi | 18:6a4db94011d3 | 839 | #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
sahilmgandhi | 18:6a4db94011d3 | 840 | #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
sahilmgandhi | 18:6a4db94011d3 | 841 | #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
sahilmgandhi | 18:6a4db94011d3 | 842 | #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
sahilmgandhi | 18:6a4db94011d3 | 843 | #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
sahilmgandhi | 18:6a4db94011d3 | 844 | #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
sahilmgandhi | 18:6a4db94011d3 | 845 | #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
sahilmgandhi | 18:6a4db94011d3 | 846 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
sahilmgandhi | 18:6a4db94011d3 | 847 | #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
sahilmgandhi | 18:6a4db94011d3 | 848 | #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
sahilmgandhi | 18:6a4db94011d3 | 849 | #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
sahilmgandhi | 18:6a4db94011d3 | 850 | #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
sahilmgandhi | 18:6a4db94011d3 | 851 | #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
sahilmgandhi | 18:6a4db94011d3 | 852 | #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
sahilmgandhi | 18:6a4db94011d3 | 853 | #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
sahilmgandhi | 18:6a4db94011d3 | 854 | #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
sahilmgandhi | 18:6a4db94011d3 | 855 | #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
sahilmgandhi | 18:6a4db94011d3 | 856 | #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
sahilmgandhi | 18:6a4db94011d3 | 857 | /** |
sahilmgandhi | 18:6a4db94011d3 | 858 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 859 | */ |
sahilmgandhi | 18:6a4db94011d3 | 860 | |
sahilmgandhi | 18:6a4db94011d3 | 861 | /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
sahilmgandhi | 18:6a4db94011d3 | 862 | * @brief Get the enable or disable status of the APB1 peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 863 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 864 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 865 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 866 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 867 | */ |
sahilmgandhi | 18:6a4db94011d3 | 868 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 869 | #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 870 | #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 871 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 872 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 873 | #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 874 | #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 875 | #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 876 | #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 877 | #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 878 | #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 879 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 880 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 881 | #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 882 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 883 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 884 | #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 885 | #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 886 | #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 887 | #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 888 | #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 889 | #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 890 | #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 891 | |
sahilmgandhi | 18:6a4db94011d3 | 892 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 893 | #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 894 | #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 895 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 896 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 897 | #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 898 | #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 899 | #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 900 | #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 901 | #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 902 | #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 903 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 904 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 905 | #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 906 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 907 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 908 | #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 909 | #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 910 | #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 911 | #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 912 | #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 913 | #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 914 | #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 915 | /** |
sahilmgandhi | 18:6a4db94011d3 | 916 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 917 | */ |
sahilmgandhi | 18:6a4db94011d3 | 918 | |
sahilmgandhi | 18:6a4db94011d3 | 919 | /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 920 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 921 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 922 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 923 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 924 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 925 | */ |
sahilmgandhi | 18:6a4db94011d3 | 926 | #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 927 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 928 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 929 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 930 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 931 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 932 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 933 | #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 934 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 935 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 936 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 937 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 938 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 939 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 940 | #define __HAL_RCC_USART1_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 941 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 942 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 943 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 944 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 945 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 946 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 947 | #define __HAL_RCC_USART6_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 948 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 949 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 950 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 951 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 952 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 953 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 954 | #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 955 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 956 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 957 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 958 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 959 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 960 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 961 | #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 962 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 963 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 964 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 965 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 966 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 967 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 968 | #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 969 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 970 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 971 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 972 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 973 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 974 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 975 | #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 976 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 977 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 978 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 979 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 980 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 981 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 982 | #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 983 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 984 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 985 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 986 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 987 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 988 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 989 | #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 990 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 991 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 992 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 993 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
sahilmgandhi | 18:6a4db94011d3 | 994 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 995 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 996 | |
sahilmgandhi | 18:6a4db94011d3 | 997 | #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 998 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 999 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 1000 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 1001 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 1002 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 1003 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 1004 | #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 1005 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 1006 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 1007 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 1008 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 1009 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 1010 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 1011 | #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ |
sahilmgandhi | 18:6a4db94011d3 | 1012 | __IO uint32_t tmpreg = 0x00U; \ |
sahilmgandhi | 18:6a4db94011d3 | 1013 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 1014 | /* Delay after an RCC peripheral clock enabling */ \ |
sahilmgandhi | 18:6a4db94011d3 | 1015 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
sahilmgandhi | 18:6a4db94011d3 | 1016 | UNUSED(tmpreg); \ |
sahilmgandhi | 18:6a4db94011d3 | 1017 | } while(0) |
sahilmgandhi | 18:6a4db94011d3 | 1018 | #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1019 | #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1020 | #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1021 | #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1022 | #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1023 | #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1024 | #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1025 | #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1026 | #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1027 | #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1028 | #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1029 | #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1030 | #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) |
sahilmgandhi | 18:6a4db94011d3 | 1031 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1032 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1033 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1034 | |
sahilmgandhi | 18:6a4db94011d3 | 1035 | /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status |
sahilmgandhi | 18:6a4db94011d3 | 1036 | * @brief Get the enable or disable status of the APB2 peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 1037 | * @note After reset, the peripheral clock (used for registers read/write access) |
sahilmgandhi | 18:6a4db94011d3 | 1038 | * is disabled and the application software has to enable this clock before |
sahilmgandhi | 18:6a4db94011d3 | 1039 | * using it. |
sahilmgandhi | 18:6a4db94011d3 | 1040 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1041 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1042 | #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1043 | #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1044 | #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1045 | #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1046 | #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1047 | #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1048 | #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1049 | #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1050 | #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1051 | #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1052 | #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1053 | #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1054 | #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))!= RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1055 | |
sahilmgandhi | 18:6a4db94011d3 | 1056 | #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1057 | #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1058 | #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1059 | #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1060 | #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1061 | #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1062 | #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1063 | #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1064 | #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1065 | #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1066 | #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1067 | #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1068 | #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))== RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1069 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1070 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1071 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1072 | |
sahilmgandhi | 18:6a4db94011d3 | 1073 | /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset |
sahilmgandhi | 18:6a4db94011d3 | 1074 | * @brief Force or release AHB1 peripheral reset. |
sahilmgandhi | 18:6a4db94011d3 | 1075 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1076 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1077 | #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) |
sahilmgandhi | 18:6a4db94011d3 | 1078 | #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) |
sahilmgandhi | 18:6a4db94011d3 | 1079 | #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1080 | #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1081 | #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1082 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) |
sahilmgandhi | 18:6a4db94011d3 | 1083 | #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1084 | #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1085 | #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1086 | #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1087 | #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1088 | #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1089 | #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1090 | #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1091 | #define __HAL_RCC_OTGHSULPI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHSULPIRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1092 | |
sahilmgandhi | 18:6a4db94011d3 | 1093 | #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 1094 | #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) |
sahilmgandhi | 18:6a4db94011d3 | 1095 | #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1096 | #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1097 | #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1098 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) |
sahilmgandhi | 18:6a4db94011d3 | 1099 | #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1100 | #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1101 | #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1102 | #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1103 | #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1104 | #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1105 | #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1106 | #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1107 | #define __HAL_RCC_OTGHSULPI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHSULPIRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1108 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1109 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1110 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1111 | |
sahilmgandhi | 18:6a4db94011d3 | 1112 | /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset |
sahilmgandhi | 18:6a4db94011d3 | 1113 | * @brief Force or release AHB2 peripheral reset. |
sahilmgandhi | 18:6a4db94011d3 | 1114 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1115 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1116 | #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) |
sahilmgandhi | 18:6a4db94011d3 | 1117 | #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1118 | #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1119 | |
sahilmgandhi | 18:6a4db94011d3 | 1120 | #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 1121 | #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1122 | #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1123 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1124 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1125 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1126 | |
sahilmgandhi | 18:6a4db94011d3 | 1127 | /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset |
sahilmgandhi | 18:6a4db94011d3 | 1128 | * @brief Force or release APB1 peripheral reset. |
sahilmgandhi | 18:6a4db94011d3 | 1129 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1130 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1131 | #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) |
sahilmgandhi | 18:6a4db94011d3 | 1132 | #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1133 | #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1134 | #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1135 | #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1136 | #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1137 | #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1138 | #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1139 | #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1140 | #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1141 | #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1142 | #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1143 | #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1144 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1145 | #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1146 | #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1147 | #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1148 | #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1149 | #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1150 | #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1151 | #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1152 | #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1153 | #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1154 | #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1155 | |
sahilmgandhi | 18:6a4db94011d3 | 1156 | #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 1157 | #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1158 | #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1159 | #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1160 | #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1161 | #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1162 | #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1163 | #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1164 | #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1165 | #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1166 | #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1167 | #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1168 | #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1169 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1170 | #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1171 | #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1172 | #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1173 | #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1174 | #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1175 | #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1176 | #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1177 | #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1178 | #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1179 | #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1180 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1181 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1182 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1183 | |
sahilmgandhi | 18:6a4db94011d3 | 1184 | /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset |
sahilmgandhi | 18:6a4db94011d3 | 1185 | * @brief Force or release APB2 peripheral reset. |
sahilmgandhi | 18:6a4db94011d3 | 1186 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1187 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1188 | #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) |
sahilmgandhi | 18:6a4db94011d3 | 1189 | #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1190 | #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1191 | #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1192 | #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1193 | #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1194 | #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) |
sahilmgandhi | 18:6a4db94011d3 | 1195 | #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1196 | #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1197 | #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1198 | #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1199 | #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1200 | |
sahilmgandhi | 18:6a4db94011d3 | 1201 | #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 1202 | #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1203 | #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1204 | #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1205 | #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1206 | #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1207 | #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) |
sahilmgandhi | 18:6a4db94011d3 | 1208 | #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1209 | #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1210 | #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1211 | #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1212 | #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) |
sahilmgandhi | 18:6a4db94011d3 | 1213 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1214 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1215 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1216 | |
sahilmgandhi | 18:6a4db94011d3 | 1217 | /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset |
sahilmgandhi | 18:6a4db94011d3 | 1218 | * @brief Force or release AHB3 peripheral reset. |
sahilmgandhi | 18:6a4db94011d3 | 1219 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1220 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1221 | #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) |
sahilmgandhi | 18:6a4db94011d3 | 1222 | #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1223 | |
sahilmgandhi | 18:6a4db94011d3 | 1224 | #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 1225 | #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) |
sahilmgandhi | 18:6a4db94011d3 | 1226 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1227 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1228 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1229 | |
sahilmgandhi | 18:6a4db94011d3 | 1230 | /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 1231 | * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
sahilmgandhi | 18:6a4db94011d3 | 1232 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
sahilmgandhi | 18:6a4db94011d3 | 1233 | * power consumption. |
sahilmgandhi | 18:6a4db94011d3 | 1234 | * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. |
sahilmgandhi | 18:6a4db94011d3 | 1235 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
sahilmgandhi | 18:6a4db94011d3 | 1236 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1237 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1238 | #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1239 | #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1240 | #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1241 | #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1242 | #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1243 | #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1244 | #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1245 | #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1246 | #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1247 | #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1248 | #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1249 | #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1250 | #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1251 | #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1252 | #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1253 | #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1254 | #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1255 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1256 | |
sahilmgandhi | 18:6a4db94011d3 | 1257 | #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1258 | #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1259 | #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1260 | #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1261 | #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1262 | #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1263 | #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1264 | #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1265 | #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1266 | #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1267 | #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1268 | #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1269 | #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1270 | #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1271 | #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1272 | #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1273 | #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1274 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1275 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1276 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1277 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1278 | |
sahilmgandhi | 18:6a4db94011d3 | 1279 | /** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 1280 | * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
sahilmgandhi | 18:6a4db94011d3 | 1281 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
sahilmgandhi | 18:6a4db94011d3 | 1282 | * power consumption. |
sahilmgandhi | 18:6a4db94011d3 | 1283 | * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. |
sahilmgandhi | 18:6a4db94011d3 | 1284 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
sahilmgandhi | 18:6a4db94011d3 | 1285 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1286 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1287 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1288 | #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1289 | |
sahilmgandhi | 18:6a4db94011d3 | 1290 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1291 | #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1292 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1293 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1294 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1295 | |
sahilmgandhi | 18:6a4db94011d3 | 1296 | /** @defgroup RCC_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 1297 | * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. |
sahilmgandhi | 18:6a4db94011d3 | 1298 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
sahilmgandhi | 18:6a4db94011d3 | 1299 | * power consumption. |
sahilmgandhi | 18:6a4db94011d3 | 1300 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
sahilmgandhi | 18:6a4db94011d3 | 1301 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
sahilmgandhi | 18:6a4db94011d3 | 1302 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1303 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1304 | #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1305 | #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1306 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1307 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1308 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1309 | |
sahilmgandhi | 18:6a4db94011d3 | 1310 | /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 1311 | * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
sahilmgandhi | 18:6a4db94011d3 | 1312 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
sahilmgandhi | 18:6a4db94011d3 | 1313 | * power consumption. |
sahilmgandhi | 18:6a4db94011d3 | 1314 | * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. |
sahilmgandhi | 18:6a4db94011d3 | 1315 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
sahilmgandhi | 18:6a4db94011d3 | 1316 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1317 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1318 | #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1319 | #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1320 | #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1321 | #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1322 | #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1323 | #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1324 | #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1325 | #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1326 | #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1327 | #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1328 | #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1329 | #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1330 | #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1331 | #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1332 | #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1333 | #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1334 | #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1335 | #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1336 | #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1337 | #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1338 | #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1339 | #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1340 | #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1341 | #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1342 | #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1343 | #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1344 | #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1345 | #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1346 | #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1347 | #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1348 | #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1349 | #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1350 | #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1351 | #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1352 | #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1353 | #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1354 | #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1355 | #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1356 | #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1357 | #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1358 | #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1359 | #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1360 | #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1361 | #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1362 | #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1363 | #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1364 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1365 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1366 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1367 | |
sahilmgandhi | 18:6a4db94011d3 | 1368 | /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable |
sahilmgandhi | 18:6a4db94011d3 | 1369 | * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
sahilmgandhi | 18:6a4db94011d3 | 1370 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
sahilmgandhi | 18:6a4db94011d3 | 1371 | * power consumption. |
sahilmgandhi | 18:6a4db94011d3 | 1372 | * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. |
sahilmgandhi | 18:6a4db94011d3 | 1373 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
sahilmgandhi | 18:6a4db94011d3 | 1374 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1375 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1376 | #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1377 | #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1378 | #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1379 | #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1380 | #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1381 | #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1382 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1383 | #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1384 | #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1385 | #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1386 | #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1387 | #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1388 | #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1389 | |
sahilmgandhi | 18:6a4db94011d3 | 1390 | #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1391 | #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1392 | #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1393 | #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1394 | #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1395 | #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1396 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1397 | #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1398 | #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1399 | #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1400 | #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1401 | #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1402 | #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) |
sahilmgandhi | 18:6a4db94011d3 | 1403 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1404 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1405 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1406 | |
sahilmgandhi | 18:6a4db94011d3 | 1407 | /** @defgroup RCC_HSI_Configuration HSI Configuration |
sahilmgandhi | 18:6a4db94011d3 | 1408 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1409 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1410 | |
sahilmgandhi | 18:6a4db94011d3 | 1411 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
sahilmgandhi | 18:6a4db94011d3 | 1412 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
sahilmgandhi | 18:6a4db94011d3 | 1413 | * It is used (enabled by hardware) as system clock source after startup |
sahilmgandhi | 18:6a4db94011d3 | 1414 | * from Reset, wake-up from STOP and STANDBY mode, or in case of failure |
sahilmgandhi | 18:6a4db94011d3 | 1415 | * of the HSE used directly or indirectly as system clock (if the Clock |
sahilmgandhi | 18:6a4db94011d3 | 1416 | * Security System CSS is enabled). |
sahilmgandhi | 18:6a4db94011d3 | 1417 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
sahilmgandhi | 18:6a4db94011d3 | 1418 | * you have to select another source of the system clock then stop the HSI. |
sahilmgandhi | 18:6a4db94011d3 | 1419 | * @note After enabling the HSI, the application software should wait on HSIRDY |
sahilmgandhi | 18:6a4db94011d3 | 1420 | * flag to be set indicating that HSI clock is stable and can be used as |
sahilmgandhi | 18:6a4db94011d3 | 1421 | * system clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1422 | * This parameter can be: ENABLE or DISABLE. |
sahilmgandhi | 18:6a4db94011d3 | 1423 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
sahilmgandhi | 18:6a4db94011d3 | 1424 | * clock cycles. |
sahilmgandhi | 18:6a4db94011d3 | 1425 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1426 | #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1427 | #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1428 | |
sahilmgandhi | 18:6a4db94011d3 | 1429 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
sahilmgandhi | 18:6a4db94011d3 | 1430 | * @note The calibration is used to compensate for the variations in voltage |
sahilmgandhi | 18:6a4db94011d3 | 1431 | * and temperature that influence the frequency of the internal HSI RC. |
sahilmgandhi | 18:6a4db94011d3 | 1432 | * @param __HSICalibrationValue__: specifies the calibration trimming value. |
sahilmgandhi | 18:6a4db94011d3 | 1433 | * (default is RCC_HSICALIBRATION_DEFAULT). |
sahilmgandhi | 18:6a4db94011d3 | 1434 | * This parameter must be a number between 0 and 0x1F. |
sahilmgandhi | 18:6a4db94011d3 | 1435 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1436 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ |
sahilmgandhi | 18:6a4db94011d3 | 1437 | RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))) |
sahilmgandhi | 18:6a4db94011d3 | 1438 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1439 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1440 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1441 | |
sahilmgandhi | 18:6a4db94011d3 | 1442 | /** @defgroup RCC_LSI_Configuration LSI Configuration |
sahilmgandhi | 18:6a4db94011d3 | 1443 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1444 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1445 | |
sahilmgandhi | 18:6a4db94011d3 | 1446 | /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). |
sahilmgandhi | 18:6a4db94011d3 | 1447 | * @note After enabling the LSI, the application software should wait on |
sahilmgandhi | 18:6a4db94011d3 | 1448 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
sahilmgandhi | 18:6a4db94011d3 | 1449 | * be used to clock the IWDG and/or the RTC. |
sahilmgandhi | 18:6a4db94011d3 | 1450 | * @note LSI can not be disabled if the IWDG is running. |
sahilmgandhi | 18:6a4db94011d3 | 1451 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
sahilmgandhi | 18:6a4db94011d3 | 1452 | * clock cycles. |
sahilmgandhi | 18:6a4db94011d3 | 1453 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1454 | #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1455 | #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1456 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1457 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1458 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1459 | |
sahilmgandhi | 18:6a4db94011d3 | 1460 | /** @defgroup RCC_HSE_Configuration HSE Configuration |
sahilmgandhi | 18:6a4db94011d3 | 1461 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1462 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1463 | |
sahilmgandhi | 18:6a4db94011d3 | 1464 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1465 | * @brief Macro to configure the External High Speed oscillator (HSE). |
sahilmgandhi | 18:6a4db94011d3 | 1466 | * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. |
sahilmgandhi | 18:6a4db94011d3 | 1467 | * User should request a transition to HSE Off first and then HSE On or HSE Bypass. |
sahilmgandhi | 18:6a4db94011d3 | 1468 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
sahilmgandhi | 18:6a4db94011d3 | 1469 | * software should wait on HSERDY flag to be set indicating that HSE clock |
sahilmgandhi | 18:6a4db94011d3 | 1470 | * is stable and can be used to clock the PLL and/or system clock. |
sahilmgandhi | 18:6a4db94011d3 | 1471 | * @note HSE state can not be changed if it is used directly or through the |
sahilmgandhi | 18:6a4db94011d3 | 1472 | * PLL as system clock. In this case, you have to select another source |
sahilmgandhi | 18:6a4db94011d3 | 1473 | * of the system clock then change the HSE state (ex. disable it). |
sahilmgandhi | 18:6a4db94011d3 | 1474 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
sahilmgandhi | 18:6a4db94011d3 | 1475 | * @note This function reset the CSSON bit, so if the clock security system(CSS) |
sahilmgandhi | 18:6a4db94011d3 | 1476 | * was previously enabled you have to enable it again after calling this |
sahilmgandhi | 18:6a4db94011d3 | 1477 | * function. |
sahilmgandhi | 18:6a4db94011d3 | 1478 | * @param __STATE__: specifies the new state of the HSE. |
sahilmgandhi | 18:6a4db94011d3 | 1479 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1480 | * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after |
sahilmgandhi | 18:6a4db94011d3 | 1481 | * 6 HSE oscillator clock cycles. |
sahilmgandhi | 18:6a4db94011d3 | 1482 | * @arg RCC_HSE_ON: turn ON the HSE oscillator. |
sahilmgandhi | 18:6a4db94011d3 | 1483 | * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. |
sahilmgandhi | 18:6a4db94011d3 | 1484 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1485 | #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__)) |
sahilmgandhi | 18:6a4db94011d3 | 1486 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1487 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1488 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1489 | |
sahilmgandhi | 18:6a4db94011d3 | 1490 | /** @defgroup RCC_LSE_Configuration LSE Configuration |
sahilmgandhi | 18:6a4db94011d3 | 1491 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1492 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1493 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1494 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
sahilmgandhi | 18:6a4db94011d3 | 1495 | * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. |
sahilmgandhi | 18:6a4db94011d3 | 1496 | * User should request a transition to LSE Off first and then LSE On or LSE Bypass. |
sahilmgandhi | 18:6a4db94011d3 | 1497 | * @note As the LSE is in the Backup domain and write access is denied to |
sahilmgandhi | 18:6a4db94011d3 | 1498 | * this domain after reset, you have to enable write access using |
sahilmgandhi | 18:6a4db94011d3 | 1499 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
sahilmgandhi | 18:6a4db94011d3 | 1500 | * (to be done once after reset). |
sahilmgandhi | 18:6a4db94011d3 | 1501 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
sahilmgandhi | 18:6a4db94011d3 | 1502 | * software should wait on LSERDY flag to be set indicating that LSE clock |
sahilmgandhi | 18:6a4db94011d3 | 1503 | * is stable and can be used to clock the RTC. |
sahilmgandhi | 18:6a4db94011d3 | 1504 | * @param __STATE__: specifies the new state of the LSE. |
sahilmgandhi | 18:6a4db94011d3 | 1505 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1506 | * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after |
sahilmgandhi | 18:6a4db94011d3 | 1507 | * 6 LSE oscillator clock cycles. |
sahilmgandhi | 18:6a4db94011d3 | 1508 | * @arg RCC_LSE_ON: turn ON the LSE oscillator. |
sahilmgandhi | 18:6a4db94011d3 | 1509 | * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. |
sahilmgandhi | 18:6a4db94011d3 | 1510 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1511 | #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__)) |
sahilmgandhi | 18:6a4db94011d3 | 1512 | |
sahilmgandhi | 18:6a4db94011d3 | 1513 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1514 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1515 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1516 | |
sahilmgandhi | 18:6a4db94011d3 | 1517 | /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration |
sahilmgandhi | 18:6a4db94011d3 | 1518 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1519 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1520 | |
sahilmgandhi | 18:6a4db94011d3 | 1521 | /** @brief Macros to enable or disable the RTC clock. |
sahilmgandhi | 18:6a4db94011d3 | 1522 | * @note These macros must be used only after the RTC clock source was selected. |
sahilmgandhi | 18:6a4db94011d3 | 1523 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1524 | #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1525 | #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1526 | |
sahilmgandhi | 18:6a4db94011d3 | 1527 | /** @brief Macros to configure the RTC clock (RTCCLK). |
sahilmgandhi | 18:6a4db94011d3 | 1528 | * @note As the RTC clock configuration bits are in the Backup domain and write |
sahilmgandhi | 18:6a4db94011d3 | 1529 | * access is denied to this domain after reset, you have to enable write |
sahilmgandhi | 18:6a4db94011d3 | 1530 | * access using the Power Backup Access macro before to configure |
sahilmgandhi | 18:6a4db94011d3 | 1531 | * the RTC clock source (to be done once after reset). |
sahilmgandhi | 18:6a4db94011d3 | 1532 | * @note Once the RTC clock is configured it can't be changed unless the |
sahilmgandhi | 18:6a4db94011d3 | 1533 | * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by |
sahilmgandhi | 18:6a4db94011d3 | 1534 | * a Power On Reset (POR). |
sahilmgandhi | 18:6a4db94011d3 | 1535 | * @param __RTCCLKSource__: specifies the RTC clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1536 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1537 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. |
sahilmgandhi | 18:6a4db94011d3 | 1538 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. |
sahilmgandhi | 18:6a4db94011d3 | 1539 | * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected |
sahilmgandhi | 18:6a4db94011d3 | 1540 | * as RTC clock, where x:[2,31] |
sahilmgandhi | 18:6a4db94011d3 | 1541 | * @note If the LSE or LSI is used as RTC clock source, the RTC continues to |
sahilmgandhi | 18:6a4db94011d3 | 1542 | * work in STOP and STANDBY modes, and can be used as wake-up source. |
sahilmgandhi | 18:6a4db94011d3 | 1543 | * However, when the HSE clock is used as RTC clock source, the RTC |
sahilmgandhi | 18:6a4db94011d3 | 1544 | * cannot be used in STOP and STANDBY modes. |
sahilmgandhi | 18:6a4db94011d3 | 1545 | * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as |
sahilmgandhi | 18:6a4db94011d3 | 1546 | * RTC clock source). |
sahilmgandhi | 18:6a4db94011d3 | 1547 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1548 | #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ |
sahilmgandhi | 18:6a4db94011d3 | 1549 | MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) |
sahilmgandhi | 18:6a4db94011d3 | 1550 | |
sahilmgandhi | 18:6a4db94011d3 | 1551 | #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ |
sahilmgandhi | 18:6a4db94011d3 | 1552 | RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ |
sahilmgandhi | 18:6a4db94011d3 | 1553 | } while (0) |
sahilmgandhi | 18:6a4db94011d3 | 1554 | |
sahilmgandhi | 18:6a4db94011d3 | 1555 | /** @brief Macros to force or release the Backup domain reset. |
sahilmgandhi | 18:6a4db94011d3 | 1556 | * @note This function resets the RTC peripheral (including the backup registers) |
sahilmgandhi | 18:6a4db94011d3 | 1557 | * and the RTC clock source selection in RCC_CSR register. |
sahilmgandhi | 18:6a4db94011d3 | 1558 | * @note The BKPSRAM is not affected by this reset. |
sahilmgandhi | 18:6a4db94011d3 | 1559 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1560 | #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1561 | #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1562 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1563 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1564 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1565 | |
sahilmgandhi | 18:6a4db94011d3 | 1566 | /** @defgroup RCC_PLL_Configuration PLL Configuration |
sahilmgandhi | 18:6a4db94011d3 | 1567 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1568 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1569 | |
sahilmgandhi | 18:6a4db94011d3 | 1570 | /** @brief Macros to enable or disable the main PLL. |
sahilmgandhi | 18:6a4db94011d3 | 1571 | * @note After enabling the main PLL, the application software should wait on |
sahilmgandhi | 18:6a4db94011d3 | 1572 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
sahilmgandhi | 18:6a4db94011d3 | 1573 | * be used as system clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1574 | * @note The main PLL can not be disabled if it is used as system clock source |
sahilmgandhi | 18:6a4db94011d3 | 1575 | * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. |
sahilmgandhi | 18:6a4db94011d3 | 1576 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1577 | #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1578 | #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1579 | |
sahilmgandhi | 18:6a4db94011d3 | 1580 | |
sahilmgandhi | 18:6a4db94011d3 | 1581 | /** @brief Macro to configure the main PLL clock source, multiplication and division factors. |
sahilmgandhi | 18:6a4db94011d3 | 1582 | * @note This function must be used only when the main PLL is disabled. |
sahilmgandhi | 18:6a4db94011d3 | 1583 | * @param __RCC_PLLSource__: specifies the PLL entry clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1584 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1585 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
sahilmgandhi | 18:6a4db94011d3 | 1586 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
sahilmgandhi | 18:6a4db94011d3 | 1587 | * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. |
sahilmgandhi | 18:6a4db94011d3 | 1588 | * @param __PLLM__: specifies the division factor for PLL VCO input clock |
sahilmgandhi | 18:6a4db94011d3 | 1589 | * This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
sahilmgandhi | 18:6a4db94011d3 | 1590 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
sahilmgandhi | 18:6a4db94011d3 | 1591 | * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
sahilmgandhi | 18:6a4db94011d3 | 1592 | * of 2 MHz to limit PLL jitter. |
sahilmgandhi | 18:6a4db94011d3 | 1593 | * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock |
sahilmgandhi | 18:6a4db94011d3 | 1594 | * This parameter must be a number between Min_Data = 192 and Max_Data = 432. |
sahilmgandhi | 18:6a4db94011d3 | 1595 | * @note You have to set the PLLN parameter correctly to ensure that the VCO |
sahilmgandhi | 18:6a4db94011d3 | 1596 | * output frequency is between 192 and 432 MHz. |
sahilmgandhi | 18:6a4db94011d3 | 1597 | * |
sahilmgandhi | 18:6a4db94011d3 | 1598 | * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) |
sahilmgandhi | 18:6a4db94011d3 | 1599 | * This parameter must be a number in the range {2, 4, 6, or 8}. |
sahilmgandhi | 18:6a4db94011d3 | 1600 | * |
sahilmgandhi | 18:6a4db94011d3 | 1601 | * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks |
sahilmgandhi | 18:6a4db94011d3 | 1602 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
sahilmgandhi | 18:6a4db94011d3 | 1603 | * @note If the USB OTG FS is used in your application, you have to set the |
sahilmgandhi | 18:6a4db94011d3 | 1604 | * PLLQ parameter correctly to have 48 MHz clock for the USB. However, |
sahilmgandhi | 18:6a4db94011d3 | 1605 | * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work |
sahilmgandhi | 18:6a4db94011d3 | 1606 | * correctly. |
sahilmgandhi | 18:6a4db94011d3 | 1607 | * |
sahilmgandhi | 18:6a4db94011d3 | 1608 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1609 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ |
sahilmgandhi | 18:6a4db94011d3 | 1610 | (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ |
sahilmgandhi | 18:6a4db94011d3 | 1611 | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ |
sahilmgandhi | 18:6a4db94011d3 | 1612 | ((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ |
sahilmgandhi | 18:6a4db94011d3 | 1613 | ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) |
sahilmgandhi | 18:6a4db94011d3 | 1614 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1615 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1616 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1617 | |
sahilmgandhi | 18:6a4db94011d3 | 1618 | /** @brief Macro to configure the PLL clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1619 | * @note This function must be used only when the main PLL is disabled. |
sahilmgandhi | 18:6a4db94011d3 | 1620 | * @param __PLLSOURCE__: specifies the PLL entry clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1621 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1622 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
sahilmgandhi | 18:6a4db94011d3 | 1623 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
sahilmgandhi | 18:6a4db94011d3 | 1624 | * |
sahilmgandhi | 18:6a4db94011d3 | 1625 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1626 | #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
sahilmgandhi | 18:6a4db94011d3 | 1627 | |
sahilmgandhi | 18:6a4db94011d3 | 1628 | /** @brief Macro to configure the PLL multiplication factor. |
sahilmgandhi | 18:6a4db94011d3 | 1629 | * @note This function must be used only when the main PLL is disabled. |
sahilmgandhi | 18:6a4db94011d3 | 1630 | * @param __PLLM__: specifies the division factor for PLL VCO input clock |
sahilmgandhi | 18:6a4db94011d3 | 1631 | * This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
sahilmgandhi | 18:6a4db94011d3 | 1632 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
sahilmgandhi | 18:6a4db94011d3 | 1633 | * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
sahilmgandhi | 18:6a4db94011d3 | 1634 | * of 2 MHz to limit PLL jitter. |
sahilmgandhi | 18:6a4db94011d3 | 1635 | * |
sahilmgandhi | 18:6a4db94011d3 | 1636 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1637 | #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
sahilmgandhi | 18:6a4db94011d3 | 1638 | |
sahilmgandhi | 18:6a4db94011d3 | 1639 | /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration |
sahilmgandhi | 18:6a4db94011d3 | 1640 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1641 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1642 | |
sahilmgandhi | 18:6a4db94011d3 | 1643 | /** @brief Macros to enable or disable the PLLI2S. |
sahilmgandhi | 18:6a4db94011d3 | 1644 | * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. |
sahilmgandhi | 18:6a4db94011d3 | 1645 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1646 | #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1647 | #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) |
sahilmgandhi | 18:6a4db94011d3 | 1648 | |
sahilmgandhi | 18:6a4db94011d3 | 1649 | /** @brief Macro to configure the PLLI2S clock multiplication and division factors . |
sahilmgandhi | 18:6a4db94011d3 | 1650 | * @note This macro must be used only when the PLLI2S is disabled. |
sahilmgandhi | 18:6a4db94011d3 | 1651 | * @note PLLI2S clock source is common with the main PLL (configured in |
sahilmgandhi | 18:6a4db94011d3 | 1652 | * HAL_RCC_ClockConfig() API). |
sahilmgandhi | 18:6a4db94011d3 | 1653 | * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock |
sahilmgandhi | 18:6a4db94011d3 | 1654 | * This parameter must be a number between Min_Data = 192 and Max_Data = 432. |
sahilmgandhi | 18:6a4db94011d3 | 1655 | * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO |
sahilmgandhi | 18:6a4db94011d3 | 1656 | * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. |
sahilmgandhi | 18:6a4db94011d3 | 1657 | * @param __PLLI2SR__: specifies the division factor for I2S clock |
sahilmgandhi | 18:6a4db94011d3 | 1658 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
sahilmgandhi | 18:6a4db94011d3 | 1659 | * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz |
sahilmgandhi | 18:6a4db94011d3 | 1660 | * on the I2S clock frequency. |
sahilmgandhi | 18:6a4db94011d3 | 1661 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1662 | #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) |
sahilmgandhi | 18:6a4db94011d3 | 1663 | |
sahilmgandhi | 18:6a4db94011d3 | 1664 | /** @brief Macro to configure the I2S clock source (I2SCLK). |
sahilmgandhi | 18:6a4db94011d3 | 1665 | * @note This function must be called before enabling the I2S APB clock. |
sahilmgandhi | 18:6a4db94011d3 | 1666 | * @param __SOURCE__: specifies the I2S clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1667 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1668 | * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1669 | * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin |
sahilmgandhi | 18:6a4db94011d3 | 1670 | * used as I2S clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1671 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1672 | #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) |
sahilmgandhi | 18:6a4db94011d3 | 1673 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1674 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1675 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1676 | |
sahilmgandhi | 18:6a4db94011d3 | 1677 | /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config |
sahilmgandhi | 18:6a4db94011d3 | 1678 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1679 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1680 | |
sahilmgandhi | 18:6a4db94011d3 | 1681 | /** @brief Macro to configure the MCO1 clock. |
sahilmgandhi | 18:6a4db94011d3 | 1682 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1683 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1684 | * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source |
sahilmgandhi | 18:6a4db94011d3 | 1685 | * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source |
sahilmgandhi | 18:6a4db94011d3 | 1686 | * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source |
sahilmgandhi | 18:6a4db94011d3 | 1687 | * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source |
sahilmgandhi | 18:6a4db94011d3 | 1688 | * @param __MCODIV__ specifies the MCO clock prescaler. |
sahilmgandhi | 18:6a4db94011d3 | 1689 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1690 | * @arg RCC_MCODIV_1: no division applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1691 | * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1692 | * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1693 | * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1694 | * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1695 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1696 | #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
sahilmgandhi | 18:6a4db94011d3 | 1697 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) |
sahilmgandhi | 18:6a4db94011d3 | 1698 | |
sahilmgandhi | 18:6a4db94011d3 | 1699 | /** @brief Macro to configure the MCO2 clock. |
sahilmgandhi | 18:6a4db94011d3 | 1700 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1701 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1702 | * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source |
sahilmgandhi | 18:6a4db94011d3 | 1703 | * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source |
sahilmgandhi | 18:6a4db94011d3 | 1704 | * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source |
sahilmgandhi | 18:6a4db94011d3 | 1705 | * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source |
sahilmgandhi | 18:6a4db94011d3 | 1706 | * @param __MCODIV__ specifies the MCO clock prescaler. |
sahilmgandhi | 18:6a4db94011d3 | 1707 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1708 | * @arg RCC_MCODIV_1: no division applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1709 | * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1710 | * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1711 | * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1712 | * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock |
sahilmgandhi | 18:6a4db94011d3 | 1713 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1714 | #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
sahilmgandhi | 18:6a4db94011d3 | 1715 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U))); |
sahilmgandhi | 18:6a4db94011d3 | 1716 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1717 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1718 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1719 | |
sahilmgandhi | 18:6a4db94011d3 | 1720 | /** @defgroup RCC_Get_Clock_source Get Clock source |
sahilmgandhi | 18:6a4db94011d3 | 1721 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1722 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1723 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1724 | * @brief Macro to configure the system clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1725 | * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1726 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1727 | * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1728 | * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1729 | * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1730 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1731 | #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) |
sahilmgandhi | 18:6a4db94011d3 | 1732 | |
sahilmgandhi | 18:6a4db94011d3 | 1733 | /** @brief Macro to get the clock source used as system clock. |
sahilmgandhi | 18:6a4db94011d3 | 1734 | * @retval The clock source used as system clock. The returned value can be one |
sahilmgandhi | 18:6a4db94011d3 | 1735 | * of the following: |
sahilmgandhi | 18:6a4db94011d3 | 1736 | * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. |
sahilmgandhi | 18:6a4db94011d3 | 1737 | * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. |
sahilmgandhi | 18:6a4db94011d3 | 1738 | * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. |
sahilmgandhi | 18:6a4db94011d3 | 1739 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1740 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) |
sahilmgandhi | 18:6a4db94011d3 | 1741 | |
sahilmgandhi | 18:6a4db94011d3 | 1742 | /** @brief Macro to get the oscillator used as PLL clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1743 | * @retval The oscillator used as PLL clock source. The returned value can be one |
sahilmgandhi | 18:6a4db94011d3 | 1744 | * of the following: |
sahilmgandhi | 18:6a4db94011d3 | 1745 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1746 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
sahilmgandhi | 18:6a4db94011d3 | 1747 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1748 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) |
sahilmgandhi | 18:6a4db94011d3 | 1749 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1750 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1751 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1752 | |
sahilmgandhi | 18:6a4db94011d3 | 1753 | /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management |
sahilmgandhi | 18:6a4db94011d3 | 1754 | * @brief macros to manage the specified RCC Flags and interrupts. |
sahilmgandhi | 18:6a4db94011d3 | 1755 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1756 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1757 | |
sahilmgandhi | 18:6a4db94011d3 | 1758 | /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable |
sahilmgandhi | 18:6a4db94011d3 | 1759 | * the selected interrupts). |
sahilmgandhi | 18:6a4db94011d3 | 1760 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. |
sahilmgandhi | 18:6a4db94011d3 | 1761 | * This parameter can be any combination of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1762 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1763 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1764 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1765 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1766 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1767 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1768 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1769 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
sahilmgandhi | 18:6a4db94011d3 | 1770 | |
sahilmgandhi | 18:6a4db94011d3 | 1771 | /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable |
sahilmgandhi | 18:6a4db94011d3 | 1772 | * the selected interrupts). |
sahilmgandhi | 18:6a4db94011d3 | 1773 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. |
sahilmgandhi | 18:6a4db94011d3 | 1774 | * This parameter can be any combination of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1775 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1776 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1777 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1778 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1779 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1780 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1781 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1782 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) |
sahilmgandhi | 18:6a4db94011d3 | 1783 | |
sahilmgandhi | 18:6a4db94011d3 | 1784 | /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] |
sahilmgandhi | 18:6a4db94011d3 | 1785 | * bits to clear the selected interrupt pending bits. |
sahilmgandhi | 18:6a4db94011d3 | 1786 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
sahilmgandhi | 18:6a4db94011d3 | 1787 | * This parameter can be any combination of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1788 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1789 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1790 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1791 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1792 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1793 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1794 | * @arg RCC_IT_CSS: Clock Security System interrupt |
sahilmgandhi | 18:6a4db94011d3 | 1795 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1796 | #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) |
sahilmgandhi | 18:6a4db94011d3 | 1797 | |
sahilmgandhi | 18:6a4db94011d3 | 1798 | /** @brief Check the RCC's interrupt has occurred or not. |
sahilmgandhi | 18:6a4db94011d3 | 1799 | * @param __INTERRUPT__: specifies the RCC interrupt source to check. |
sahilmgandhi | 18:6a4db94011d3 | 1800 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1801 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1802 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1803 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1804 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1805 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1806 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 1807 | * @arg RCC_IT_CSS: Clock Security System interrupt |
sahilmgandhi | 18:6a4db94011d3 | 1808 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
sahilmgandhi | 18:6a4db94011d3 | 1809 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1810 | #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) |
sahilmgandhi | 18:6a4db94011d3 | 1811 | |
sahilmgandhi | 18:6a4db94011d3 | 1812 | /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, |
sahilmgandhi | 18:6a4db94011d3 | 1813 | * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. |
sahilmgandhi | 18:6a4db94011d3 | 1814 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1815 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) |
sahilmgandhi | 18:6a4db94011d3 | 1816 | |
sahilmgandhi | 18:6a4db94011d3 | 1817 | /** @brief Check RCC flag is set or not. |
sahilmgandhi | 18:6a4db94011d3 | 1818 | * @param __FLAG__: specifies the flag to check. |
sahilmgandhi | 18:6a4db94011d3 | 1819 | * This parameter can be one of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1820 | * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. |
sahilmgandhi | 18:6a4db94011d3 | 1821 | * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. |
sahilmgandhi | 18:6a4db94011d3 | 1822 | * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. |
sahilmgandhi | 18:6a4db94011d3 | 1823 | * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. |
sahilmgandhi | 18:6a4db94011d3 | 1824 | * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. |
sahilmgandhi | 18:6a4db94011d3 | 1825 | * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. |
sahilmgandhi | 18:6a4db94011d3 | 1826 | * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. |
sahilmgandhi | 18:6a4db94011d3 | 1827 | * @arg RCC_FLAG_PINRST: Pin reset. |
sahilmgandhi | 18:6a4db94011d3 | 1828 | * @arg RCC_FLAG_PORRST: POR/PDR reset. |
sahilmgandhi | 18:6a4db94011d3 | 1829 | * @arg RCC_FLAG_SFTRST: Software reset. |
sahilmgandhi | 18:6a4db94011d3 | 1830 | * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. |
sahilmgandhi | 18:6a4db94011d3 | 1831 | * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. |
sahilmgandhi | 18:6a4db94011d3 | 1832 | * @arg RCC_FLAG_LPWRRST: Low Power reset. |
sahilmgandhi | 18:6a4db94011d3 | 1833 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
sahilmgandhi | 18:6a4db94011d3 | 1834 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1835 | #define RCC_FLAG_MASK ((uint8_t)0x1FU) |
sahilmgandhi | 18:6a4db94011d3 | 1836 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) |
sahilmgandhi | 18:6a4db94011d3 | 1837 | |
sahilmgandhi | 18:6a4db94011d3 | 1838 | #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC)) |
sahilmgandhi | 18:6a4db94011d3 | 1839 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1840 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1841 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1842 | |
sahilmgandhi | 18:6a4db94011d3 | 1843 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1844 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1845 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1846 | |
sahilmgandhi | 18:6a4db94011d3 | 1847 | /* Include RCC HAL Extended module */ |
sahilmgandhi | 18:6a4db94011d3 | 1848 | #include "stm32f2xx_hal_rcc_ex.h" |
sahilmgandhi | 18:6a4db94011d3 | 1849 | /* Exported functions --------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 1850 | /** @addtogroup RCC_Exported_Functions |
sahilmgandhi | 18:6a4db94011d3 | 1851 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1852 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1853 | |
sahilmgandhi | 18:6a4db94011d3 | 1854 | /** @addtogroup RCC_Exported_Functions_Group1 |
sahilmgandhi | 18:6a4db94011d3 | 1855 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1856 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1857 | /* Initialization and de-initialization functions ******************************/ |
sahilmgandhi | 18:6a4db94011d3 | 1858 | void HAL_RCC_DeInit(void); |
sahilmgandhi | 18:6a4db94011d3 | 1859 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
sahilmgandhi | 18:6a4db94011d3 | 1860 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
sahilmgandhi | 18:6a4db94011d3 | 1861 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1862 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1863 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1864 | |
sahilmgandhi | 18:6a4db94011d3 | 1865 | /** @addtogroup RCC_Exported_Functions_Group2 |
sahilmgandhi | 18:6a4db94011d3 | 1866 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1867 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1868 | /* Peripheral Control functions ************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 1869 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
sahilmgandhi | 18:6a4db94011d3 | 1870 | void HAL_RCC_EnableCSS(void); |
sahilmgandhi | 18:6a4db94011d3 | 1871 | void HAL_RCC_DisableCSS(void); |
sahilmgandhi | 18:6a4db94011d3 | 1872 | uint32_t HAL_RCC_GetSysClockFreq(void); |
sahilmgandhi | 18:6a4db94011d3 | 1873 | uint32_t HAL_RCC_GetHCLKFreq(void); |
sahilmgandhi | 18:6a4db94011d3 | 1874 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
sahilmgandhi | 18:6a4db94011d3 | 1875 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
sahilmgandhi | 18:6a4db94011d3 | 1876 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
sahilmgandhi | 18:6a4db94011d3 | 1877 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
sahilmgandhi | 18:6a4db94011d3 | 1878 | |
sahilmgandhi | 18:6a4db94011d3 | 1879 | /* CSS NMI IRQ handler */ |
sahilmgandhi | 18:6a4db94011d3 | 1880 | void HAL_RCC_NMI_IRQHandler(void); |
sahilmgandhi | 18:6a4db94011d3 | 1881 | |
sahilmgandhi | 18:6a4db94011d3 | 1882 | /* User Callbacks in non blocking mode (IT mode) */ |
sahilmgandhi | 18:6a4db94011d3 | 1883 | void HAL_RCC_CSSCallback(void); |
sahilmgandhi | 18:6a4db94011d3 | 1884 | |
sahilmgandhi | 18:6a4db94011d3 | 1885 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1886 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1887 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1888 | |
sahilmgandhi | 18:6a4db94011d3 | 1889 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1890 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1891 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1892 | |
sahilmgandhi | 18:6a4db94011d3 | 1893 | /* Private types -------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 1894 | /* Private variables ---------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 1895 | /* Private constants ---------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 1896 | /** @defgroup RCC_Private_Constants RCC Private Constants |
sahilmgandhi | 18:6a4db94011d3 | 1897 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1898 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1899 | |
sahilmgandhi | 18:6a4db94011d3 | 1900 | /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion |
sahilmgandhi | 18:6a4db94011d3 | 1901 | * @brief RCC registers bit address in the alias region |
sahilmgandhi | 18:6a4db94011d3 | 1902 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1903 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1904 | #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 1905 | /* --- CR Register ---*/ |
sahilmgandhi | 18:6a4db94011d3 | 1906 | /* Alias word address of HSION bit */ |
sahilmgandhi | 18:6a4db94011d3 | 1907 | #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 1908 | #define RCC_HSION_BIT_NUMBER 0x00U |
sahilmgandhi | 18:6a4db94011d3 | 1909 | #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U)) |
sahilmgandhi | 18:6a4db94011d3 | 1910 | /* Alias word address of CSSON bit */ |
sahilmgandhi | 18:6a4db94011d3 | 1911 | #define RCC_CSSON_BIT_NUMBER 0x13U |
sahilmgandhi | 18:6a4db94011d3 | 1912 | #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)) |
sahilmgandhi | 18:6a4db94011d3 | 1913 | /* Alias word address of PLLON bit */ |
sahilmgandhi | 18:6a4db94011d3 | 1914 | #define RCC_PLLON_BIT_NUMBER 0x18U |
sahilmgandhi | 18:6a4db94011d3 | 1915 | #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) |
sahilmgandhi | 18:6a4db94011d3 | 1916 | /* Alias word address of PLLI2SON bit */ |
sahilmgandhi | 18:6a4db94011d3 | 1917 | #define RCC_PLLI2SON_BIT_NUMBER 0x1AU |
sahilmgandhi | 18:6a4db94011d3 | 1918 | #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) |
sahilmgandhi | 18:6a4db94011d3 | 1919 | |
sahilmgandhi | 18:6a4db94011d3 | 1920 | /* --- CFGR Register ---*/ |
sahilmgandhi | 18:6a4db94011d3 | 1921 | /* Alias word address of I2SSRC bit */ |
sahilmgandhi | 18:6a4db94011d3 | 1922 | #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) |
sahilmgandhi | 18:6a4db94011d3 | 1923 | #define RCC_I2SSRC_BIT_NUMBER 0x17U |
sahilmgandhi | 18:6a4db94011d3 | 1924 | #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) |
sahilmgandhi | 18:6a4db94011d3 | 1925 | |
sahilmgandhi | 18:6a4db94011d3 | 1926 | /* --- BDCR Register ---*/ |
sahilmgandhi | 18:6a4db94011d3 | 1927 | /* Alias word address of RTCEN bit */ |
sahilmgandhi | 18:6a4db94011d3 | 1928 | #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) |
sahilmgandhi | 18:6a4db94011d3 | 1929 | #define RCC_RTCEN_BIT_NUMBER 0x0FU |
sahilmgandhi | 18:6a4db94011d3 | 1930 | #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)) |
sahilmgandhi | 18:6a4db94011d3 | 1931 | /* Alias word address of BDRST bit */ |
sahilmgandhi | 18:6a4db94011d3 | 1932 | #define RCC_BDRST_BIT_NUMBER 0x10U |
sahilmgandhi | 18:6a4db94011d3 | 1933 | #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) |
sahilmgandhi | 18:6a4db94011d3 | 1934 | |
sahilmgandhi | 18:6a4db94011d3 | 1935 | /* --- CSR Register ---*/ |
sahilmgandhi | 18:6a4db94011d3 | 1936 | /* Alias word address of LSION bit */ |
sahilmgandhi | 18:6a4db94011d3 | 1937 | #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) |
sahilmgandhi | 18:6a4db94011d3 | 1938 | #define RCC_LSION_BIT_NUMBER 0x00U |
sahilmgandhi | 18:6a4db94011d3 | 1939 | #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U)) |
sahilmgandhi | 18:6a4db94011d3 | 1940 | |
sahilmgandhi | 18:6a4db94011d3 | 1941 | /* CR register byte 3 (Bits[23:16]) base address */ |
sahilmgandhi | 18:6a4db94011d3 | 1942 | #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U) |
sahilmgandhi | 18:6a4db94011d3 | 1943 | |
sahilmgandhi | 18:6a4db94011d3 | 1944 | /* CIR register byte 2 (Bits[15:8]) base address */ |
sahilmgandhi | 18:6a4db94011d3 | 1945 | #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U)) |
sahilmgandhi | 18:6a4db94011d3 | 1946 | |
sahilmgandhi | 18:6a4db94011d3 | 1947 | /* CIR register byte 3 (Bits[23:16]) base address */ |
sahilmgandhi | 18:6a4db94011d3 | 1948 | #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U)) |
sahilmgandhi | 18:6a4db94011d3 | 1949 | |
sahilmgandhi | 18:6a4db94011d3 | 1950 | /* BDCR register base address */ |
sahilmgandhi | 18:6a4db94011d3 | 1951 | #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) |
sahilmgandhi | 18:6a4db94011d3 | 1952 | |
sahilmgandhi | 18:6a4db94011d3 | 1953 | #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) |
sahilmgandhi | 18:6a4db94011d3 | 1954 | #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
sahilmgandhi | 18:6a4db94011d3 | 1955 | |
sahilmgandhi | 18:6a4db94011d3 | 1956 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
sahilmgandhi | 18:6a4db94011d3 | 1957 | #define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */ |
sahilmgandhi | 18:6a4db94011d3 | 1958 | #define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */ |
sahilmgandhi | 18:6a4db94011d3 | 1959 | |
sahilmgandhi | 18:6a4db94011d3 | 1960 | #define PLLI2S_TIMEOUT_VALUE ((uint32_t)2U) /* Timeout value fixed to 100 ms */ |
sahilmgandhi | 18:6a4db94011d3 | 1961 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1962 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1963 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1964 | |
sahilmgandhi | 18:6a4db94011d3 | 1965 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1966 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1967 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1968 | |
sahilmgandhi | 18:6a4db94011d3 | 1969 | /* Private macros ------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 1970 | /** @defgroup RCC_Private_Macros RCC Private Macros |
sahilmgandhi | 18:6a4db94011d3 | 1971 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1972 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1973 | |
sahilmgandhi | 18:6a4db94011d3 | 1974 | /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters |
sahilmgandhi | 18:6a4db94011d3 | 1975 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1976 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1977 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) |
sahilmgandhi | 18:6a4db94011d3 | 1978 | |
sahilmgandhi | 18:6a4db94011d3 | 1979 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
sahilmgandhi | 18:6a4db94011d3 | 1980 | ((HSE) == RCC_HSE_BYPASS)) |
sahilmgandhi | 18:6a4db94011d3 | 1981 | |
sahilmgandhi | 18:6a4db94011d3 | 1982 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
sahilmgandhi | 18:6a4db94011d3 | 1983 | ((LSE) == RCC_LSE_BYPASS)) |
sahilmgandhi | 18:6a4db94011d3 | 1984 | |
sahilmgandhi | 18:6a4db94011d3 | 1985 | #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) |
sahilmgandhi | 18:6a4db94011d3 | 1986 | |
sahilmgandhi | 18:6a4db94011d3 | 1987 | #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) |
sahilmgandhi | 18:6a4db94011d3 | 1988 | |
sahilmgandhi | 18:6a4db94011d3 | 1989 | #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) |
sahilmgandhi | 18:6a4db94011d3 | 1990 | |
sahilmgandhi | 18:6a4db94011d3 | 1991 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
sahilmgandhi | 18:6a4db94011d3 | 1992 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
sahilmgandhi | 18:6a4db94011d3 | 1993 | |
sahilmgandhi | 18:6a4db94011d3 | 1994 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
sahilmgandhi | 18:6a4db94011d3 | 1995 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
sahilmgandhi | 18:6a4db94011d3 | 1996 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
sahilmgandhi | 18:6a4db94011d3 | 1997 | |
sahilmgandhi | 18:6a4db94011d3 | 1998 | #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ |
sahilmgandhi | 18:6a4db94011d3 | 1999 | ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2000 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2001 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2002 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2003 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2004 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2005 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2006 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2007 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2008 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2009 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2010 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2011 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2012 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2013 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2014 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2015 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2016 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2017 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2018 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2019 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2020 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2021 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2022 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2023 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2024 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2025 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2026 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2027 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2028 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2029 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) |
sahilmgandhi | 18:6a4db94011d3 | 2030 | |
sahilmgandhi | 18:6a4db94011d3 | 2031 | #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) |
sahilmgandhi | 18:6a4db94011d3 | 2032 | |
sahilmgandhi | 18:6a4db94011d3 | 2033 | #define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U)) |
sahilmgandhi | 18:6a4db94011d3 | 2034 | |
sahilmgandhi | 18:6a4db94011d3 | 2035 | #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) |
sahilmgandhi | 18:6a4db94011d3 | 2036 | |
sahilmgandhi | 18:6a4db94011d3 | 2037 | #define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U)) |
sahilmgandhi | 18:6a4db94011d3 | 2038 | |
sahilmgandhi | 18:6a4db94011d3 | 2039 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2040 | ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2041 | ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2042 | ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2043 | ((HCLK) == RCC_SYSCLK_DIV512)) |
sahilmgandhi | 18:6a4db94011d3 | 2044 | |
sahilmgandhi | 18:6a4db94011d3 | 2045 | #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U)) |
sahilmgandhi | 18:6a4db94011d3 | 2046 | |
sahilmgandhi | 18:6a4db94011d3 | 2047 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2048 | ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2049 | ((PCLK) == RCC_HCLK_DIV16)) |
sahilmgandhi | 18:6a4db94011d3 | 2050 | |
sahilmgandhi | 18:6a4db94011d3 | 2051 | #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) |
sahilmgandhi | 18:6a4db94011d3 | 2052 | |
sahilmgandhi | 18:6a4db94011d3 | 2053 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2054 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) |
sahilmgandhi | 18:6a4db94011d3 | 2055 | |
sahilmgandhi | 18:6a4db94011d3 | 2056 | #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ |
sahilmgandhi | 18:6a4db94011d3 | 2057 | ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) |
sahilmgandhi | 18:6a4db94011d3 | 2058 | |
sahilmgandhi | 18:6a4db94011d3 | 2059 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2060 | ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ |
sahilmgandhi | 18:6a4db94011d3 | 2061 | ((DIV) == RCC_MCODIV_5)) |
sahilmgandhi | 18:6a4db94011d3 | 2062 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) |
sahilmgandhi | 18:6a4db94011d3 | 2063 | |
sahilmgandhi | 18:6a4db94011d3 | 2064 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2065 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 2066 | */ |
sahilmgandhi | 18:6a4db94011d3 | 2067 | |
sahilmgandhi | 18:6a4db94011d3 | 2068 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2069 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 2070 | */ |
sahilmgandhi | 18:6a4db94011d3 | 2071 | |
sahilmgandhi | 18:6a4db94011d3 | 2072 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2073 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 2074 | */ |
sahilmgandhi | 18:6a4db94011d3 | 2075 | |
sahilmgandhi | 18:6a4db94011d3 | 2076 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2077 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 2078 | */ |
sahilmgandhi | 18:6a4db94011d3 | 2079 | |
sahilmgandhi | 18:6a4db94011d3 | 2080 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 2081 | } |
sahilmgandhi | 18:6a4db94011d3 | 2082 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 2083 | |
sahilmgandhi | 18:6a4db94011d3 | 2084 | #endif /* __STM32F2xx_HAL_RCC_H */ |
sahilmgandhi | 18:6a4db94011d3 | 2085 | |
sahilmgandhi | 18:6a4db94011d3 | 2086 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |