MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f2xx_hal_rcc.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.1.3
sahilmgandhi 18:6a4db94011d3 6 * @date 29-June-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief RCC HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
sahilmgandhi 18:6a4db94011d3 10 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 11 * + Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 @verbatim
sahilmgandhi 18:6a4db94011d3 14 ==============================================================================
sahilmgandhi 18:6a4db94011d3 15 ##### RCC specific features #####
sahilmgandhi 18:6a4db94011d3 16 ==============================================================================
sahilmgandhi 18:6a4db94011d3 17 [..]
sahilmgandhi 18:6a4db94011d3 18 After reset the device is running from Internal High Speed oscillator
sahilmgandhi 18:6a4db94011d3 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
sahilmgandhi 18:6a4db94011d3 20 and I-Cache are disabled, and all peripherals are off except internal
sahilmgandhi 18:6a4db94011d3 21 SRAM, Flash and JTAG.
sahilmgandhi 18:6a4db94011d3 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
sahilmgandhi 18:6a4db94011d3 23 all peripherals mapped on these busses are running at HSI speed.
sahilmgandhi 18:6a4db94011d3 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
sahilmgandhi 18:6a4db94011d3 25 (+) All GPIOs are in input floating state, except the JTAG pins which
sahilmgandhi 18:6a4db94011d3 26 are assigned to be used for debug purpose.
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 [..]
sahilmgandhi 18:6a4db94011d3 29 Once the device started from reset, the user application has to:
sahilmgandhi 18:6a4db94011d3 30 (+) Configure the clock source to be used to drive the System clock
sahilmgandhi 18:6a4db94011d3 31 (if the application needs higher frequency/performance)
sahilmgandhi 18:6a4db94011d3 32 (+) Configure the System clock frequency and Flash settings
sahilmgandhi 18:6a4db94011d3 33 (+) Configure the AHB and APB busses prescalers
sahilmgandhi 18:6a4db94011d3 34 (+) Enable the clock for the peripheral(s) to be used
sahilmgandhi 18:6a4db94011d3 35 (+) Configure the clock source(s) for peripherals which clocks are not
sahilmgandhi 18:6a4db94011d3 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 ##### RCC Limitations #####
sahilmgandhi 18:6a4db94011d3 39 ==============================================================================
sahilmgandhi 18:6a4db94011d3 40 [..]
sahilmgandhi 18:6a4db94011d3 41 A delay between an RCC peripheral clock enable and the effective peripheral
sahilmgandhi 18:6a4db94011d3 42 enabling should be taken into account in order to manage the peripheral read/write
sahilmgandhi 18:6a4db94011d3 43 from/to registers.
sahilmgandhi 18:6a4db94011d3 44 (+) This delay depends on the peripheral mapping.
sahilmgandhi 18:6a4db94011d3 45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
sahilmgandhi 18:6a4db94011d3 46 after the clock enable bit is set on the hardware register
sahilmgandhi 18:6a4db94011d3 47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
sahilmgandhi 18:6a4db94011d3 48 after the clock enable bit is set on the hardware register
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 [..]
sahilmgandhi 18:6a4db94011d3 51 Possible Workarounds:
sahilmgandhi 18:6a4db94011d3 52 (#) Enable the peripheral clock sometimes before the peripheral read/write
sahilmgandhi 18:6a4db94011d3 53 register is required.
sahilmgandhi 18:6a4db94011d3 54 (#) For AHB peripheral, insert two dummy read to the peripheral register.
sahilmgandhi 18:6a4db94011d3 55 (#) For APB peripheral, insert a dummy read to the peripheral register.
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 @endverbatim
sahilmgandhi 18:6a4db94011d3 58 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 59 * @attention
sahilmgandhi 18:6a4db94011d3 60 *
sahilmgandhi 18:6a4db94011d3 61 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 62 *
sahilmgandhi 18:6a4db94011d3 63 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 64 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 65 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 66 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 67 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 68 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 69 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 70 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 71 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 72 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 73 *
sahilmgandhi 18:6a4db94011d3 74 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 75 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 76 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 77 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 78 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 79 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 80 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 81 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 82 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 83 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 84 *
sahilmgandhi 18:6a4db94011d3 85 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 86 */
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 89 #include "stm32f2xx_hal.h"
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 /** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 92 * @{
sahilmgandhi 18:6a4db94011d3 93 */
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /** @defgroup RCC RCC
sahilmgandhi 18:6a4db94011d3 96 * @brief RCC HAL module driver
sahilmgandhi 18:6a4db94011d3 97 * @{
sahilmgandhi 18:6a4db94011d3 98 */
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 #ifdef HAL_RCC_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 103 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 104 /** @addtogroup RCC_Private_Constants
sahilmgandhi 18:6a4db94011d3 105 * @{
sahilmgandhi 18:6a4db94011d3 106 */
sahilmgandhi 18:6a4db94011d3 107 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 110 #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
sahilmgandhi 18:6a4db94011d3 111 #define MCO1_GPIO_PORT GPIOA
sahilmgandhi 18:6a4db94011d3 112 #define MCO1_PIN GPIO_PIN_8
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
sahilmgandhi 18:6a4db94011d3 115 #define MCO2_GPIO_PORT GPIOC
sahilmgandhi 18:6a4db94011d3 116 #define MCO2_PIN GPIO_PIN_9
sahilmgandhi 18:6a4db94011d3 117 /**
sahilmgandhi 18:6a4db94011d3 118 * @}
sahilmgandhi 18:6a4db94011d3 119 */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 122 /** @defgroup RCC_Private_Variables RCC Private Variables
sahilmgandhi 18:6a4db94011d3 123 * @{
sahilmgandhi 18:6a4db94011d3 124 */
sahilmgandhi 18:6a4db94011d3 125 const uint8_t APBAHBPrescTable[16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
sahilmgandhi 18:6a4db94011d3 126 /**
sahilmgandhi 18:6a4db94011d3 127 * @}
sahilmgandhi 18:6a4db94011d3 128 */
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 131 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 /** @defgroup RCC_Exported_Functions RCC Exported Functions
sahilmgandhi 18:6a4db94011d3 134 * @{
sahilmgandhi 18:6a4db94011d3 135 */
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 138 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 139 *
sahilmgandhi 18:6a4db94011d3 140 @verbatim
sahilmgandhi 18:6a4db94011d3 141 ===============================================================================
sahilmgandhi 18:6a4db94011d3 142 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 143 ===============================================================================
sahilmgandhi 18:6a4db94011d3 144 [..]
sahilmgandhi 18:6a4db94011d3 145 This section provides functions allowing to configure the internal/external oscillators
sahilmgandhi 18:6a4db94011d3 146 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
sahilmgandhi 18:6a4db94011d3 147 and APB2).
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 [..] Internal/external clock and PLL configuration
sahilmgandhi 18:6a4db94011d3 150 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
sahilmgandhi 18:6a4db94011d3 151 the PLL as System clock source.
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
sahilmgandhi 18:6a4db94011d3 154 clock source.
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
sahilmgandhi 18:6a4db94011d3 157 through the PLL as System clock source. Can be used also as RTC clock source.
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
sahilmgandhi 18:6a4db94011d3 162 (++) The first output is used to generate the high speed system clock (up to 120 MHz)
sahilmgandhi 18:6a4db94011d3 163 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
sahilmgandhi 18:6a4db94011d3 164 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
sahilmgandhi 18:6a4db94011d3 167 and if a HSE clock failure occurs(HSE used directly or through PLL as System
sahilmgandhi 18:6a4db94011d3 168 clock source), the System clocks automatically switched to HSI and an interrupt
sahilmgandhi 18:6a4db94011d3 169 is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
sahilmgandhi 18:6a4db94011d3 170 (Non-Maskable Interrupt) exception vector.
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
sahilmgandhi 18:6a4db94011d3 173 clock (through a configurable prescaler) on PA8 pin.
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
sahilmgandhi 18:6a4db94011d3 176 clock (through a configurable prescaler) on PC9 pin.
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 [..] System, AHB and APB busses clocks configuration
sahilmgandhi 18:6a4db94011d3 179 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
sahilmgandhi 18:6a4db94011d3 180 HSE and PLL.
sahilmgandhi 18:6a4db94011d3 181 The AHB clock (HCLK) is derived from System clock through configurable
sahilmgandhi 18:6a4db94011d3 182 prescaler and used to clock the CPU, memory and peripherals mapped
sahilmgandhi 18:6a4db94011d3 183 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
sahilmgandhi 18:6a4db94011d3 184 from AHB clock through configurable prescalers and used to clock
sahilmgandhi 18:6a4db94011d3 185 the peripherals mapped on these busses. You can use
sahilmgandhi 18:6a4db94011d3 186 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
sahilmgandhi 18:6a4db94011d3 189 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
sahilmgandhi 18:6a4db94011d3 190 from an external clock mapped on the I2S_CKIN pin.
sahilmgandhi 18:6a4db94011d3 191 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
sahilmgandhi 18:6a4db94011d3 192 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
sahilmgandhi 18:6a4db94011d3 193 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
sahilmgandhi 18:6a4db94011d3 194 macros to configure this clock.
sahilmgandhi 18:6a4db94011d3 195 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
sahilmgandhi 18:6a4db94011d3 196 to work correctly, while the SDIO require a frequency equal or lower than
sahilmgandhi 18:6a4db94011d3 197 to 48. This clock is derived of the main PLL through PLLQ divider.
sahilmgandhi 18:6a4db94011d3 198 (+@) IWDG clock which is always the LSI clock.
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 (#) For the stm32f2xx devices, the maximum
sahilmgandhi 18:6a4db94011d3 201 frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
sahilmgandhi 18:6a4db94011d3 202 Depending on the device voltage range, the maximum frequency should
sahilmgandhi 18:6a4db94011d3 203 be adapted accordingly:
sahilmgandhi 18:6a4db94011d3 204 +-------------------------------------------------------------------------------------+
sahilmgandhi 18:6a4db94011d3 205 | Latency | HCLK clock frequency (MHz) |
sahilmgandhi 18:6a4db94011d3 206 | |---------------------------------------------------------------------|
sahilmgandhi 18:6a4db94011d3 207 | | voltage range | voltage range | voltage range | voltage range |
sahilmgandhi 18:6a4db94011d3 208 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
sahilmgandhi 18:6a4db94011d3 209 |---------------|----------------|----------------|-----------------|-----------------|
sahilmgandhi 18:6a4db94011d3 210 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
sahilmgandhi 18:6a4db94011d3 211 |---------------|----------------|----------------|-----------------|-----------------|
sahilmgandhi 18:6a4db94011d3 212 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
sahilmgandhi 18:6a4db94011d3 213 |---------------|----------------|----------------|-----------------|-----------------|
sahilmgandhi 18:6a4db94011d3 214 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
sahilmgandhi 18:6a4db94011d3 215 |---------------|----------------|----------------|-----------------|-----------------|
sahilmgandhi 18:6a4db94011d3 216 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
sahilmgandhi 18:6a4db94011d3 217 |---------------|----------------|----------------|-----------------|-----------------|
sahilmgandhi 18:6a4db94011d3 218 |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
sahilmgandhi 18:6a4db94011d3 219 |---------------|----------------|----------------|-----------------|-----------------|
sahilmgandhi 18:6a4db94011d3 220 |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
sahilmgandhi 18:6a4db94011d3 221 |---------------|----------------|----------------|-----------------|-----------------|
sahilmgandhi 18:6a4db94011d3 222 |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
sahilmgandhi 18:6a4db94011d3 223 |---------------|----------------|----------------|-----------------|-----------------|
sahilmgandhi 18:6a4db94011d3 224 |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
sahilmgandhi 18:6a4db94011d3 225 +-------------------------------------------------------------------------------------+
sahilmgandhi 18:6a4db94011d3 226 @endverbatim
sahilmgandhi 18:6a4db94011d3 227 * @{
sahilmgandhi 18:6a4db94011d3 228 */
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 /**
sahilmgandhi 18:6a4db94011d3 231 * @brief Resets the RCC clock configuration to the default reset state.
sahilmgandhi 18:6a4db94011d3 232 * @note The default reset state of the clock configuration is given below:
sahilmgandhi 18:6a4db94011d3 233 * - HSI ON and used as system clock source
sahilmgandhi 18:6a4db94011d3 234 * - HSE, PLL and PLLI2S OFF
sahilmgandhi 18:6a4db94011d3 235 * - AHB, APB1 and APB2 prescaler set to 1.
sahilmgandhi 18:6a4db94011d3 236 * - CSS, MCO1 and MCO2 OFF
sahilmgandhi 18:6a4db94011d3 237 * - All interrupts disabled
sahilmgandhi 18:6a4db94011d3 238 * @note This function doesn't modify the configuration of the
sahilmgandhi 18:6a4db94011d3 239 * - Peripheral clocks
sahilmgandhi 18:6a4db94011d3 240 * - LSI, LSE and RTC clocks
sahilmgandhi 18:6a4db94011d3 241 * @retval None
sahilmgandhi 18:6a4db94011d3 242 */
sahilmgandhi 18:6a4db94011d3 243 void HAL_RCC_DeInit(void)
sahilmgandhi 18:6a4db94011d3 244 {
sahilmgandhi 18:6a4db94011d3 245 /* Set HSION bit */
sahilmgandhi 18:6a4db94011d3 246 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /* Reset CFGR register */
sahilmgandhi 18:6a4db94011d3 249 CLEAR_REG(RCC->CFGR);
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /* Reset HSEON, CSSON, PLLON, PLLI2S */
sahilmgandhi 18:6a4db94011d3 252 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /* Reset PLLCFGR register */
sahilmgandhi 18:6a4db94011d3 255 CLEAR_REG(RCC->PLLCFGR);
sahilmgandhi 18:6a4db94011d3 256 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 /* Reset PLLI2SCFGR register */
sahilmgandhi 18:6a4db94011d3 259 CLEAR_REG(RCC->PLLI2SCFGR);
sahilmgandhi 18:6a4db94011d3 260 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /* Reset HSEBYP bit */
sahilmgandhi 18:6a4db94011d3 263 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /* Disable all interrupts */
sahilmgandhi 18:6a4db94011d3 266 CLEAR_REG(RCC->CIR);
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /* Update the SystemCoreClock global variable */
sahilmgandhi 18:6a4db94011d3 269 SystemCoreClock = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 270 }
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /**
sahilmgandhi 18:6a4db94011d3 273 * @brief Initializes the RCC Oscillators according to the specified parameters in the
sahilmgandhi 18:6a4db94011d3 274 * RCC_OscInitTypeDef.
sahilmgandhi 18:6a4db94011d3 275 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
sahilmgandhi 18:6a4db94011d3 276 * contains the configuration information for the RCC Oscillators.
sahilmgandhi 18:6a4db94011d3 277 * @note The PLL is not disabled when used as system clock.
sahilmgandhi 18:6a4db94011d3 278 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
sahilmgandhi 18:6a4db94011d3 279 * supported by this API. User should request a transition to LSE Off
sahilmgandhi 18:6a4db94011d3 280 * first and then LSE On or LSE Bypass.
sahilmgandhi 18:6a4db94011d3 281 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
sahilmgandhi 18:6a4db94011d3 282 * supported by this API. User should request a transition to HSE Off
sahilmgandhi 18:6a4db94011d3 283 * first and then HSE On or HSE Bypass.
sahilmgandhi 18:6a4db94011d3 284 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 285 */
sahilmgandhi 18:6a4db94011d3 286 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
sahilmgandhi 18:6a4db94011d3 287 {
sahilmgandhi 18:6a4db94011d3 288 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 291 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sahilmgandhi 18:6a4db94011d3 292 /*------------------------------- HSE Configuration ------------------------*/
sahilmgandhi 18:6a4db94011d3 293 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
sahilmgandhi 18:6a4db94011d3 294 {
sahilmgandhi 18:6a4db94011d3 295 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 296 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
sahilmgandhi 18:6a4db94011d3 297 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
sahilmgandhi 18:6a4db94011d3 298 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
sahilmgandhi 18:6a4db94011d3 299 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
sahilmgandhi 18:6a4db94011d3 300 {
sahilmgandhi 18:6a4db94011d3 301 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
sahilmgandhi 18:6a4db94011d3 302 {
sahilmgandhi 18:6a4db94011d3 303 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 304 }
sahilmgandhi 18:6a4db94011d3 305 }
sahilmgandhi 18:6a4db94011d3 306 else
sahilmgandhi 18:6a4db94011d3 307 {
sahilmgandhi 18:6a4db94011d3 308 /* Set the new HSE configuration ---------------------------------------*/
sahilmgandhi 18:6a4db94011d3 309 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 /* Check the HSE State */
sahilmgandhi 18:6a4db94011d3 312 if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
sahilmgandhi 18:6a4db94011d3 313 {
sahilmgandhi 18:6a4db94011d3 314 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 315 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 /* Wait till HSE is ready */
sahilmgandhi 18:6a4db94011d3 318 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
sahilmgandhi 18:6a4db94011d3 319 {
sahilmgandhi 18:6a4db94011d3 320 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 321 {
sahilmgandhi 18:6a4db94011d3 322 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 323 }
sahilmgandhi 18:6a4db94011d3 324 }
sahilmgandhi 18:6a4db94011d3 325 }
sahilmgandhi 18:6a4db94011d3 326 else
sahilmgandhi 18:6a4db94011d3 327 {
sahilmgandhi 18:6a4db94011d3 328 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 329 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 /* Wait till HSE is bypassed or disabled */
sahilmgandhi 18:6a4db94011d3 332 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
sahilmgandhi 18:6a4db94011d3 333 {
sahilmgandhi 18:6a4db94011d3 334 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 335 {
sahilmgandhi 18:6a4db94011d3 336 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 337 }
sahilmgandhi 18:6a4db94011d3 338 }
sahilmgandhi 18:6a4db94011d3 339 }
sahilmgandhi 18:6a4db94011d3 340 }
sahilmgandhi 18:6a4db94011d3 341 }
sahilmgandhi 18:6a4db94011d3 342 /*----------------------------- HSI Configuration --------------------------*/
sahilmgandhi 18:6a4db94011d3 343 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
sahilmgandhi 18:6a4db94011d3 344 {
sahilmgandhi 18:6a4db94011d3 345 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 346 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
sahilmgandhi 18:6a4db94011d3 347 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
sahilmgandhi 18:6a4db94011d3 350 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
sahilmgandhi 18:6a4db94011d3 351 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
sahilmgandhi 18:6a4db94011d3 352 {
sahilmgandhi 18:6a4db94011d3 353 /* When HSI is used as system clock it will not disabled */
sahilmgandhi 18:6a4db94011d3 354 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
sahilmgandhi 18:6a4db94011d3 355 {
sahilmgandhi 18:6a4db94011d3 356 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 357 }
sahilmgandhi 18:6a4db94011d3 358 /* Otherwise, just the calibration is allowed */
sahilmgandhi 18:6a4db94011d3 359 else
sahilmgandhi 18:6a4db94011d3 360 {
sahilmgandhi 18:6a4db94011d3 361 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
sahilmgandhi 18:6a4db94011d3 362 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
sahilmgandhi 18:6a4db94011d3 363 }
sahilmgandhi 18:6a4db94011d3 364 }
sahilmgandhi 18:6a4db94011d3 365 else
sahilmgandhi 18:6a4db94011d3 366 {
sahilmgandhi 18:6a4db94011d3 367 /* Check the HSI State */
sahilmgandhi 18:6a4db94011d3 368 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
sahilmgandhi 18:6a4db94011d3 369 {
sahilmgandhi 18:6a4db94011d3 370 /* Enable the Internal High Speed oscillator (HSI). */
sahilmgandhi 18:6a4db94011d3 371 __HAL_RCC_HSI_ENABLE();
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 374 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /* Wait till HSI is ready */
sahilmgandhi 18:6a4db94011d3 377 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 378 {
sahilmgandhi 18:6a4db94011d3 379 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 380 {
sahilmgandhi 18:6a4db94011d3 381 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 382 }
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
sahilmgandhi 18:6a4db94011d3 386 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
sahilmgandhi 18:6a4db94011d3 387 }
sahilmgandhi 18:6a4db94011d3 388 else
sahilmgandhi 18:6a4db94011d3 389 {
sahilmgandhi 18:6a4db94011d3 390 /* Disable the Internal High Speed oscillator (HSI). */
sahilmgandhi 18:6a4db94011d3 391 __HAL_RCC_HSI_DISABLE();
sahilmgandhi 18:6a4db94011d3 392
sahilmgandhi 18:6a4db94011d3 393 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 394 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 /* Wait till HSI is ready */
sahilmgandhi 18:6a4db94011d3 397 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
sahilmgandhi 18:6a4db94011d3 398 {
sahilmgandhi 18:6a4db94011d3 399 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 400 {
sahilmgandhi 18:6a4db94011d3 401 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 402 }
sahilmgandhi 18:6a4db94011d3 403 }
sahilmgandhi 18:6a4db94011d3 404 }
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406 }
sahilmgandhi 18:6a4db94011d3 407 /*------------------------------ LSI Configuration -------------------------*/
sahilmgandhi 18:6a4db94011d3 408 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
sahilmgandhi 18:6a4db94011d3 409 {
sahilmgandhi 18:6a4db94011d3 410 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 411 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 /* Check the LSI State */
sahilmgandhi 18:6a4db94011d3 414 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
sahilmgandhi 18:6a4db94011d3 415 {
sahilmgandhi 18:6a4db94011d3 416 /* Enable the Internal Low Speed oscillator (LSI). */
sahilmgandhi 18:6a4db94011d3 417 __HAL_RCC_LSI_ENABLE();
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 420 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 /* Wait till LSI is ready */
sahilmgandhi 18:6a4db94011d3 423 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 424 {
sahilmgandhi 18:6a4db94011d3 425 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 426 {
sahilmgandhi 18:6a4db94011d3 427 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 428 }
sahilmgandhi 18:6a4db94011d3 429 }
sahilmgandhi 18:6a4db94011d3 430 }
sahilmgandhi 18:6a4db94011d3 431 else
sahilmgandhi 18:6a4db94011d3 432 {
sahilmgandhi 18:6a4db94011d3 433 /* Disable the Internal Low Speed oscillator (LSI). */
sahilmgandhi 18:6a4db94011d3 434 __HAL_RCC_LSI_DISABLE();
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 437 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 /* Wait till LSI is ready */
sahilmgandhi 18:6a4db94011d3 440 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
sahilmgandhi 18:6a4db94011d3 441 {
sahilmgandhi 18:6a4db94011d3 442 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 443 {
sahilmgandhi 18:6a4db94011d3 444 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 445 }
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447 }
sahilmgandhi 18:6a4db94011d3 448 }
sahilmgandhi 18:6a4db94011d3 449 /*------------------------------ LSE Configuration -------------------------*/
sahilmgandhi 18:6a4db94011d3 450 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
sahilmgandhi 18:6a4db94011d3 451 {
sahilmgandhi 18:6a4db94011d3 452 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 453 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 /* Enable Power Clock*/
sahilmgandhi 18:6a4db94011d3 456 __HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 /* Enable write access to Backup domain */
sahilmgandhi 18:6a4db94011d3 459 PWR->CR |= PWR_CR_DBP;
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /* Wait for Backup domain Write protection enable */
sahilmgandhi 18:6a4db94011d3 462 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 while((PWR->CR & PWR_CR_DBP) == RESET)
sahilmgandhi 18:6a4db94011d3 465 {
sahilmgandhi 18:6a4db94011d3 466 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 467 {
sahilmgandhi 18:6a4db94011d3 468 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 469 }
sahilmgandhi 18:6a4db94011d3 470 }
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 /* Set the new LSE configuration -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 473 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
sahilmgandhi 18:6a4db94011d3 474 /* Check the LSE State */
sahilmgandhi 18:6a4db94011d3 475 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
sahilmgandhi 18:6a4db94011d3 476 {
sahilmgandhi 18:6a4db94011d3 477 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 478 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /* Wait till LSE is ready */
sahilmgandhi 18:6a4db94011d3 481 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
sahilmgandhi 18:6a4db94011d3 482 {
sahilmgandhi 18:6a4db94011d3 483 if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 484 {
sahilmgandhi 18:6a4db94011d3 485 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 486 }
sahilmgandhi 18:6a4db94011d3 487 }
sahilmgandhi 18:6a4db94011d3 488 }
sahilmgandhi 18:6a4db94011d3 489 else
sahilmgandhi 18:6a4db94011d3 490 {
sahilmgandhi 18:6a4db94011d3 491 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 492 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 /* Wait till LSE is ready */
sahilmgandhi 18:6a4db94011d3 495 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
sahilmgandhi 18:6a4db94011d3 496 {
sahilmgandhi 18:6a4db94011d3 497 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 498 {
sahilmgandhi 18:6a4db94011d3 499 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 500 }
sahilmgandhi 18:6a4db94011d3 501 }
sahilmgandhi 18:6a4db94011d3 502 }
sahilmgandhi 18:6a4db94011d3 503 }
sahilmgandhi 18:6a4db94011d3 504 /*-------------------------------- PLL Configuration -----------------------*/
sahilmgandhi 18:6a4db94011d3 505 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 506 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
sahilmgandhi 18:6a4db94011d3 507 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
sahilmgandhi 18:6a4db94011d3 508 {
sahilmgandhi 18:6a4db94011d3 509 /* Check if the PLL is used as system clock or not */
sahilmgandhi 18:6a4db94011d3 510 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
sahilmgandhi 18:6a4db94011d3 511 {
sahilmgandhi 18:6a4db94011d3 512 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
sahilmgandhi 18:6a4db94011d3 513 {
sahilmgandhi 18:6a4db94011d3 514 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 515 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
sahilmgandhi 18:6a4db94011d3 516 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
sahilmgandhi 18:6a4db94011d3 517 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
sahilmgandhi 18:6a4db94011d3 518 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
sahilmgandhi 18:6a4db94011d3 519 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
sahilmgandhi 18:6a4db94011d3 520
sahilmgandhi 18:6a4db94011d3 521 /* Disable the main PLL. */
sahilmgandhi 18:6a4db94011d3 522 __HAL_RCC_PLL_DISABLE();
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 525 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527 /* Wait till PLL is ready */
sahilmgandhi 18:6a4db94011d3 528 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
sahilmgandhi 18:6a4db94011d3 529 {
sahilmgandhi 18:6a4db94011d3 530 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 531 {
sahilmgandhi 18:6a4db94011d3 532 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 533 }
sahilmgandhi 18:6a4db94011d3 534 }
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 /* Configure the main PLL clock source, multiplication and division factors. */
sahilmgandhi 18:6a4db94011d3 537 WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
sahilmgandhi 18:6a4db94011d3 538 RCC_OscInitStruct->PLL.PLLM | \
sahilmgandhi 18:6a4db94011d3 539 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
sahilmgandhi 18:6a4db94011d3 540 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
sahilmgandhi 18:6a4db94011d3 541 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
sahilmgandhi 18:6a4db94011d3 542 /* Enable the main PLL. */
sahilmgandhi 18:6a4db94011d3 543 __HAL_RCC_PLL_ENABLE();
sahilmgandhi 18:6a4db94011d3 544
sahilmgandhi 18:6a4db94011d3 545 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 546 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 547
sahilmgandhi 18:6a4db94011d3 548 /* Wait till PLL is ready */
sahilmgandhi 18:6a4db94011d3 549 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 550 {
sahilmgandhi 18:6a4db94011d3 551 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 552 {
sahilmgandhi 18:6a4db94011d3 553 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 554 }
sahilmgandhi 18:6a4db94011d3 555 }
sahilmgandhi 18:6a4db94011d3 556 }
sahilmgandhi 18:6a4db94011d3 557 else
sahilmgandhi 18:6a4db94011d3 558 {
sahilmgandhi 18:6a4db94011d3 559 /* Disable the main PLL. */
sahilmgandhi 18:6a4db94011d3 560 __HAL_RCC_PLL_DISABLE();
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 563 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 /* Wait till PLL is ready */
sahilmgandhi 18:6a4db94011d3 566 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
sahilmgandhi 18:6a4db94011d3 567 {
sahilmgandhi 18:6a4db94011d3 568 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 569 {
sahilmgandhi 18:6a4db94011d3 570 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 571 }
sahilmgandhi 18:6a4db94011d3 572 }
sahilmgandhi 18:6a4db94011d3 573 }
sahilmgandhi 18:6a4db94011d3 574 }
sahilmgandhi 18:6a4db94011d3 575 else
sahilmgandhi 18:6a4db94011d3 576 {
sahilmgandhi 18:6a4db94011d3 577 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 578 }
sahilmgandhi 18:6a4db94011d3 579 }
sahilmgandhi 18:6a4db94011d3 580 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 581 }
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583 /**
sahilmgandhi 18:6a4db94011d3 584 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
sahilmgandhi 18:6a4db94011d3 585 * parameters in the RCC_ClkInitStruct.
sahilmgandhi 18:6a4db94011d3 586 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
sahilmgandhi 18:6a4db94011d3 587 * contains the configuration information for the RCC peripheral.
sahilmgandhi 18:6a4db94011d3 588 * @param FLatency: FLASH Latency, this parameter depend on device selected
sahilmgandhi 18:6a4db94011d3 589 *
sahilmgandhi 18:6a4db94011d3 590 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
sahilmgandhi 18:6a4db94011d3 591 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
sahilmgandhi 18:6a4db94011d3 592 *
sahilmgandhi 18:6a4db94011d3 593 * @note The HSI is used (enabled by hardware) as system clock source after
sahilmgandhi 18:6a4db94011d3 594 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
sahilmgandhi 18:6a4db94011d3 595 * of failure of the HSE used directly or indirectly as system clock
sahilmgandhi 18:6a4db94011d3 596 * (if the Clock Security System CSS is enabled).
sahilmgandhi 18:6a4db94011d3 597 *
sahilmgandhi 18:6a4db94011d3 598 * @note A switch from one clock source to another occurs only if the target
sahilmgandhi 18:6a4db94011d3 599 * clock source is ready (clock stable after startup delay or PLL locked).
sahilmgandhi 18:6a4db94011d3 600 * If a clock source which is not yet ready is selected, the switch will
sahilmgandhi 18:6a4db94011d3 601 * occur when the clock source will be ready.
sahilmgandhi 18:6a4db94011d3 602 *
sahilmgandhi 18:6a4db94011d3 603 * @note Depending on the device voltage range, the software has to set correctly
sahilmgandhi 18:6a4db94011d3 604 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
sahilmgandhi 18:6a4db94011d3 605 * (for more details refer to section above "Initialization/de-initialization functions")
sahilmgandhi 18:6a4db94011d3 606 * @retval None
sahilmgandhi 18:6a4db94011d3 607 */
sahilmgandhi 18:6a4db94011d3 608 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
sahilmgandhi 18:6a4db94011d3 609 {
sahilmgandhi 18:6a4db94011d3 610 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 613 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
sahilmgandhi 18:6a4db94011d3 614 assert_param(IS_FLASH_LATENCY(FLatency));
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
sahilmgandhi 18:6a4db94011d3 617 must be correctly programmed according to the frequency of the CPU clock
sahilmgandhi 18:6a4db94011d3 618 (HCLK) and the supply voltage of the device. */
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 /* Increasing the number of wait states because of higher CPU frequency */
sahilmgandhi 18:6a4db94011d3 621 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
sahilmgandhi 18:6a4db94011d3 622 {
sahilmgandhi 18:6a4db94011d3 623 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
sahilmgandhi 18:6a4db94011d3 624 __HAL_FLASH_SET_LATENCY(FLatency);
sahilmgandhi 18:6a4db94011d3 625
sahilmgandhi 18:6a4db94011d3 626 /* Check that the new number of wait states is taken into account to access the Flash
sahilmgandhi 18:6a4db94011d3 627 memory by reading the FLASH_ACR register */
sahilmgandhi 18:6a4db94011d3 628 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
sahilmgandhi 18:6a4db94011d3 629 {
sahilmgandhi 18:6a4db94011d3 630 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 631 }
sahilmgandhi 18:6a4db94011d3 632 }
sahilmgandhi 18:6a4db94011d3 633
sahilmgandhi 18:6a4db94011d3 634 /*-------------------------- HCLK Configuration --------------------------*/
sahilmgandhi 18:6a4db94011d3 635 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
sahilmgandhi 18:6a4db94011d3 636 {
sahilmgandhi 18:6a4db94011d3 637 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
sahilmgandhi 18:6a4db94011d3 638 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
sahilmgandhi 18:6a4db94011d3 639 }
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641 /*------------------------- SYSCLK Configuration ---------------------------*/
sahilmgandhi 18:6a4db94011d3 642 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
sahilmgandhi 18:6a4db94011d3 643 {
sahilmgandhi 18:6a4db94011d3 644 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 /* HSE is selected as System Clock Source */
sahilmgandhi 18:6a4db94011d3 647 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 648 {
sahilmgandhi 18:6a4db94011d3 649 /* Check the HSE ready flag */
sahilmgandhi 18:6a4db94011d3 650 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
sahilmgandhi 18:6a4db94011d3 651 {
sahilmgandhi 18:6a4db94011d3 652 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 653 }
sahilmgandhi 18:6a4db94011d3 654 }
sahilmgandhi 18:6a4db94011d3 655 /* PLL is selected as System Clock Source */
sahilmgandhi 18:6a4db94011d3 656 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
sahilmgandhi 18:6a4db94011d3 657 {
sahilmgandhi 18:6a4db94011d3 658 /* Check the PLL ready flag */
sahilmgandhi 18:6a4db94011d3 659 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 660 {
sahilmgandhi 18:6a4db94011d3 661 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 662 }
sahilmgandhi 18:6a4db94011d3 663 }
sahilmgandhi 18:6a4db94011d3 664 /* HSI is selected as System Clock Source */
sahilmgandhi 18:6a4db94011d3 665 else
sahilmgandhi 18:6a4db94011d3 666 {
sahilmgandhi 18:6a4db94011d3 667 /* Check the HSI ready flag */
sahilmgandhi 18:6a4db94011d3 668 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 669 {
sahilmgandhi 18:6a4db94011d3 670 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 671 }
sahilmgandhi 18:6a4db94011d3 672 }
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
sahilmgandhi 18:6a4db94011d3 675 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 676 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 677
sahilmgandhi 18:6a4db94011d3 678 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 679 {
sahilmgandhi 18:6a4db94011d3 680 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
sahilmgandhi 18:6a4db94011d3 681 {
sahilmgandhi 18:6a4db94011d3 682 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 683 {
sahilmgandhi 18:6a4db94011d3 684 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 685 }
sahilmgandhi 18:6a4db94011d3 686 }
sahilmgandhi 18:6a4db94011d3 687 }
sahilmgandhi 18:6a4db94011d3 688 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
sahilmgandhi 18:6a4db94011d3 689 {
sahilmgandhi 18:6a4db94011d3 690 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
sahilmgandhi 18:6a4db94011d3 691 {
sahilmgandhi 18:6a4db94011d3 692 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 693 {
sahilmgandhi 18:6a4db94011d3 694 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 695 }
sahilmgandhi 18:6a4db94011d3 696 }
sahilmgandhi 18:6a4db94011d3 697 }
sahilmgandhi 18:6a4db94011d3 698 else
sahilmgandhi 18:6a4db94011d3 699 {
sahilmgandhi 18:6a4db94011d3 700 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
sahilmgandhi 18:6a4db94011d3 701 {
sahilmgandhi 18:6a4db94011d3 702 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 703 {
sahilmgandhi 18:6a4db94011d3 704 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 705 }
sahilmgandhi 18:6a4db94011d3 706 }
sahilmgandhi 18:6a4db94011d3 707 }
sahilmgandhi 18:6a4db94011d3 708 }
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 /* Decreasing the number of wait states because of lower CPU frequency */
sahilmgandhi 18:6a4db94011d3 711 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
sahilmgandhi 18:6a4db94011d3 712 {
sahilmgandhi 18:6a4db94011d3 713 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
sahilmgandhi 18:6a4db94011d3 714 __HAL_FLASH_SET_LATENCY(FLatency);
sahilmgandhi 18:6a4db94011d3 715
sahilmgandhi 18:6a4db94011d3 716 /* Check that the new number of wait states is taken into account to access the Flash
sahilmgandhi 18:6a4db94011d3 717 memory by reading the FLASH_ACR register */
sahilmgandhi 18:6a4db94011d3 718 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
sahilmgandhi 18:6a4db94011d3 719 {
sahilmgandhi 18:6a4db94011d3 720 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 721 }
sahilmgandhi 18:6a4db94011d3 722 }
sahilmgandhi 18:6a4db94011d3 723
sahilmgandhi 18:6a4db94011d3 724 /*-------------------------- PCLK1 Configuration ---------------------------*/
sahilmgandhi 18:6a4db94011d3 725 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
sahilmgandhi 18:6a4db94011d3 726 {
sahilmgandhi 18:6a4db94011d3 727 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
sahilmgandhi 18:6a4db94011d3 728 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
sahilmgandhi 18:6a4db94011d3 729 }
sahilmgandhi 18:6a4db94011d3 730
sahilmgandhi 18:6a4db94011d3 731 /*-------------------------- PCLK2 Configuration ---------------------------*/
sahilmgandhi 18:6a4db94011d3 732 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
sahilmgandhi 18:6a4db94011d3 733 {
sahilmgandhi 18:6a4db94011d3 734 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
sahilmgandhi 18:6a4db94011d3 735 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
sahilmgandhi 18:6a4db94011d3 736 }
sahilmgandhi 18:6a4db94011d3 737
sahilmgandhi 18:6a4db94011d3 738 /* Update the SystemCoreClock global variable */
sahilmgandhi 18:6a4db94011d3 739 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 /* Configure the source of time base considering new system clocks settings*/
sahilmgandhi 18:6a4db94011d3 742 HAL_InitTick (TICK_INT_PRIORITY);
sahilmgandhi 18:6a4db94011d3 743
sahilmgandhi 18:6a4db94011d3 744 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 745 }
sahilmgandhi 18:6a4db94011d3 746
sahilmgandhi 18:6a4db94011d3 747 /**
sahilmgandhi 18:6a4db94011d3 748 * @}
sahilmgandhi 18:6a4db94011d3 749 */
sahilmgandhi 18:6a4db94011d3 750
sahilmgandhi 18:6a4db94011d3 751 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 752 * @brief RCC clocks control functions
sahilmgandhi 18:6a4db94011d3 753 *
sahilmgandhi 18:6a4db94011d3 754 @verbatim
sahilmgandhi 18:6a4db94011d3 755 ===============================================================================
sahilmgandhi 18:6a4db94011d3 756 ##### Peripheral Control functions #####
sahilmgandhi 18:6a4db94011d3 757 ===============================================================================
sahilmgandhi 18:6a4db94011d3 758 [..]
sahilmgandhi 18:6a4db94011d3 759 This subsection provides a set of functions allowing to control the RCC Clocks
sahilmgandhi 18:6a4db94011d3 760 frequencies.
sahilmgandhi 18:6a4db94011d3 761
sahilmgandhi 18:6a4db94011d3 762 @endverbatim
sahilmgandhi 18:6a4db94011d3 763 * @{
sahilmgandhi 18:6a4db94011d3 764 */
sahilmgandhi 18:6a4db94011d3 765
sahilmgandhi 18:6a4db94011d3 766 /**
sahilmgandhi 18:6a4db94011d3 767 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
sahilmgandhi 18:6a4db94011d3 768 * @note PA8/PC9 should be configured in alternate function mode.
sahilmgandhi 18:6a4db94011d3 769 * @param RCC_MCOx: specifies the output direction for the clock source.
sahilmgandhi 18:6a4db94011d3 770 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 771 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
sahilmgandhi 18:6a4db94011d3 772 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
sahilmgandhi 18:6a4db94011d3 773 * @param RCC_MCOSource: specifies the clock source to output.
sahilmgandhi 18:6a4db94011d3 774 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 775 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 776 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 777 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 778 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 779 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 780 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 781 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 782 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 783 * @param RCC_MCODiv: specifies the MCOx prescaler.
sahilmgandhi 18:6a4db94011d3 784 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 785 * @arg RCC_MCODIV_1: no division applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 786 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 787 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 788 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 789 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 790 * @retval None
sahilmgandhi 18:6a4db94011d3 791 */
sahilmgandhi 18:6a4db94011d3 792 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
sahilmgandhi 18:6a4db94011d3 793 {
sahilmgandhi 18:6a4db94011d3 794 GPIO_InitTypeDef GPIO_InitStruct;
sahilmgandhi 18:6a4db94011d3 795 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 796 assert_param(IS_RCC_MCO(RCC_MCOx));
sahilmgandhi 18:6a4db94011d3 797 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
sahilmgandhi 18:6a4db94011d3 798 /* RCC_MCO1 */
sahilmgandhi 18:6a4db94011d3 799 if(RCC_MCOx == RCC_MCO1)
sahilmgandhi 18:6a4db94011d3 800 {
sahilmgandhi 18:6a4db94011d3 801 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
sahilmgandhi 18:6a4db94011d3 802
sahilmgandhi 18:6a4db94011d3 803 /* MCO1 Clock Enable */
sahilmgandhi 18:6a4db94011d3 804 __MCO1_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 805
sahilmgandhi 18:6a4db94011d3 806 /* Configure the MCO1 pin in alternate function mode */
sahilmgandhi 18:6a4db94011d3 807 GPIO_InitStruct.Pin = MCO1_PIN;
sahilmgandhi 18:6a4db94011d3 808 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
sahilmgandhi 18:6a4db94011d3 809 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
sahilmgandhi 18:6a4db94011d3 810 GPIO_InitStruct.Pull = GPIO_NOPULL;
sahilmgandhi 18:6a4db94011d3 811 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
sahilmgandhi 18:6a4db94011d3 812 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
sahilmgandhi 18:6a4db94011d3 815 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
sahilmgandhi 18:6a4db94011d3 816 }
sahilmgandhi 18:6a4db94011d3 817 else
sahilmgandhi 18:6a4db94011d3 818 {
sahilmgandhi 18:6a4db94011d3 819 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
sahilmgandhi 18:6a4db94011d3 820
sahilmgandhi 18:6a4db94011d3 821 /* MCO2 Clock Enable */
sahilmgandhi 18:6a4db94011d3 822 __MCO2_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 823
sahilmgandhi 18:6a4db94011d3 824 /* Configure the MCO2 pin in alternate function mode */
sahilmgandhi 18:6a4db94011d3 825 GPIO_InitStruct.Pin = MCO2_PIN;
sahilmgandhi 18:6a4db94011d3 826 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
sahilmgandhi 18:6a4db94011d3 827 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
sahilmgandhi 18:6a4db94011d3 828 GPIO_InitStruct.Pull = GPIO_NOPULL;
sahilmgandhi 18:6a4db94011d3 829 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
sahilmgandhi 18:6a4db94011d3 830 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
sahilmgandhi 18:6a4db94011d3 831
sahilmgandhi 18:6a4db94011d3 832 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
sahilmgandhi 18:6a4db94011d3 833 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
sahilmgandhi 18:6a4db94011d3 834 }
sahilmgandhi 18:6a4db94011d3 835 }
sahilmgandhi 18:6a4db94011d3 836
sahilmgandhi 18:6a4db94011d3 837 /**
sahilmgandhi 18:6a4db94011d3 838 * @brief Enables the Clock Security System.
sahilmgandhi 18:6a4db94011d3 839 * @note If a failure is detected on the HSE oscillator clock, this oscillator
sahilmgandhi 18:6a4db94011d3 840 * is automatically disabled and an interrupt is generated to inform the
sahilmgandhi 18:6a4db94011d3 841 * software about the failure (Clock Security System Interrupt, CSSI),
sahilmgandhi 18:6a4db94011d3 842 * allowing the MCU to perform rescue operations. The CSSI is linked to
sahilmgandhi 18:6a4db94011d3 843 * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
sahilmgandhi 18:6a4db94011d3 844 * @retval None
sahilmgandhi 18:6a4db94011d3 845 */
sahilmgandhi 18:6a4db94011d3 846 void HAL_RCC_EnableCSS(void)
sahilmgandhi 18:6a4db94011d3 847 {
sahilmgandhi 18:6a4db94011d3 848 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
sahilmgandhi 18:6a4db94011d3 849 }
sahilmgandhi 18:6a4db94011d3 850
sahilmgandhi 18:6a4db94011d3 851 /**
sahilmgandhi 18:6a4db94011d3 852 * @brief Disables the Clock Security System.
sahilmgandhi 18:6a4db94011d3 853 * @retval None
sahilmgandhi 18:6a4db94011d3 854 */
sahilmgandhi 18:6a4db94011d3 855 void HAL_RCC_DisableCSS(void)
sahilmgandhi 18:6a4db94011d3 856 {
sahilmgandhi 18:6a4db94011d3 857 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
sahilmgandhi 18:6a4db94011d3 858 }
sahilmgandhi 18:6a4db94011d3 859
sahilmgandhi 18:6a4db94011d3 860 /**
sahilmgandhi 18:6a4db94011d3 861 * @brief Returns the SYSCLK frequency
sahilmgandhi 18:6a4db94011d3 862 *
sahilmgandhi 18:6a4db94011d3 863 * @note The system frequency computed by this function is not the real
sahilmgandhi 18:6a4db94011d3 864 * frequency in the chip. It is calculated based on the predefined
sahilmgandhi 18:6a4db94011d3 865 * constant and the selected clock source:
sahilmgandhi 18:6a4db94011d3 866 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
sahilmgandhi 18:6a4db94011d3 867 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
sahilmgandhi 18:6a4db94011d3 868 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
sahilmgandhi 18:6a4db94011d3 869 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
sahilmgandhi 18:6a4db94011d3 870 * @note (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
sahilmgandhi 18:6a4db94011d3 871 * 16 MHz) but the real value may vary depending on the variations
sahilmgandhi 18:6a4db94011d3 872 * in voltage and temperature.
sahilmgandhi 18:6a4db94011d3 873 * @note (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
sahilmgandhi 18:6a4db94011d3 874 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
sahilmgandhi 18:6a4db94011d3 875 * frequency of the crystal used. Otherwise, this function may
sahilmgandhi 18:6a4db94011d3 876 * have wrong result.
sahilmgandhi 18:6a4db94011d3 877 *
sahilmgandhi 18:6a4db94011d3 878 * @note The result of this function could be not correct when using fractional
sahilmgandhi 18:6a4db94011d3 879 * value for HSE crystal.
sahilmgandhi 18:6a4db94011d3 880 *
sahilmgandhi 18:6a4db94011d3 881 * @note This function can be used by the user application to compute the
sahilmgandhi 18:6a4db94011d3 882 * baudrate for the communication peripherals or configure other parameters.
sahilmgandhi 18:6a4db94011d3 883 *
sahilmgandhi 18:6a4db94011d3 884 * @note Each time SYSCLK changes, this function must be called to update the
sahilmgandhi 18:6a4db94011d3 885 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
sahilmgandhi 18:6a4db94011d3 886 *
sahilmgandhi 18:6a4db94011d3 887 *
sahilmgandhi 18:6a4db94011d3 888 * @retval SYSCLK frequency
sahilmgandhi 18:6a4db94011d3 889 */
sahilmgandhi 18:6a4db94011d3 890 uint32_t HAL_RCC_GetSysClockFreq(void)
sahilmgandhi 18:6a4db94011d3 891 {
sahilmgandhi 18:6a4db94011d3 892 uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
sahilmgandhi 18:6a4db94011d3 893 uint32_t sysclockfreq = 0U;
sahilmgandhi 18:6a4db94011d3 894
sahilmgandhi 18:6a4db94011d3 895 /* Get SYSCLK source -------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 896 switch (RCC->CFGR & RCC_CFGR_SWS)
sahilmgandhi 18:6a4db94011d3 897 {
sahilmgandhi 18:6a4db94011d3 898 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
sahilmgandhi 18:6a4db94011d3 899 {
sahilmgandhi 18:6a4db94011d3 900 sysclockfreq = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 901 break;
sahilmgandhi 18:6a4db94011d3 902 }
sahilmgandhi 18:6a4db94011d3 903 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
sahilmgandhi 18:6a4db94011d3 904 {
sahilmgandhi 18:6a4db94011d3 905 sysclockfreq = HSE_VALUE;
sahilmgandhi 18:6a4db94011d3 906 break;
sahilmgandhi 18:6a4db94011d3 907 }
sahilmgandhi 18:6a4db94011d3 908 case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
sahilmgandhi 18:6a4db94011d3 909 {
sahilmgandhi 18:6a4db94011d3 910 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
sahilmgandhi 18:6a4db94011d3 911 SYSCLK = PLL_VCO / PLLP */
sahilmgandhi 18:6a4db94011d3 912 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
sahilmgandhi 18:6a4db94011d3 913 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
sahilmgandhi 18:6a4db94011d3 914 {
sahilmgandhi 18:6a4db94011d3 915 /* HSE used as PLL clock source */
sahilmgandhi 18:6a4db94011d3 916 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
sahilmgandhi 18:6a4db94011d3 917 }
sahilmgandhi 18:6a4db94011d3 918 else
sahilmgandhi 18:6a4db94011d3 919 {
sahilmgandhi 18:6a4db94011d3 920 /* HSI used as PLL clock source */
sahilmgandhi 18:6a4db94011d3 921 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
sahilmgandhi 18:6a4db94011d3 922 }
sahilmgandhi 18:6a4db94011d3 923 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
sahilmgandhi 18:6a4db94011d3 924
sahilmgandhi 18:6a4db94011d3 925 sysclockfreq = pllvco/pllp;
sahilmgandhi 18:6a4db94011d3 926 break;
sahilmgandhi 18:6a4db94011d3 927 }
sahilmgandhi 18:6a4db94011d3 928 default:
sahilmgandhi 18:6a4db94011d3 929 {
sahilmgandhi 18:6a4db94011d3 930 sysclockfreq = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 931 break;
sahilmgandhi 18:6a4db94011d3 932 }
sahilmgandhi 18:6a4db94011d3 933 }
sahilmgandhi 18:6a4db94011d3 934 return sysclockfreq;
sahilmgandhi 18:6a4db94011d3 935 }
sahilmgandhi 18:6a4db94011d3 936
sahilmgandhi 18:6a4db94011d3 937 /**
sahilmgandhi 18:6a4db94011d3 938 * @brief Returns the HCLK frequency
sahilmgandhi 18:6a4db94011d3 939 * @note Each time HCLK changes, this function must be called to update the
sahilmgandhi 18:6a4db94011d3 940 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
sahilmgandhi 18:6a4db94011d3 941 *
sahilmgandhi 18:6a4db94011d3 942 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
sahilmgandhi 18:6a4db94011d3 943 * and updated within this function
sahilmgandhi 18:6a4db94011d3 944 * @retval HCLK frequency
sahilmgandhi 18:6a4db94011d3 945 */
sahilmgandhi 18:6a4db94011d3 946 uint32_t HAL_RCC_GetHCLKFreq(void)
sahilmgandhi 18:6a4db94011d3 947 {
sahilmgandhi 18:6a4db94011d3 948 return SystemCoreClock;
sahilmgandhi 18:6a4db94011d3 949 }
sahilmgandhi 18:6a4db94011d3 950
sahilmgandhi 18:6a4db94011d3 951 /**
sahilmgandhi 18:6a4db94011d3 952 * @brief Returns the PCLK1 frequency
sahilmgandhi 18:6a4db94011d3 953 * @note Each time PCLK1 changes, this function must be called to update the
sahilmgandhi 18:6a4db94011d3 954 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
sahilmgandhi 18:6a4db94011d3 955 * @retval PCLK1 frequency
sahilmgandhi 18:6a4db94011d3 956 */
sahilmgandhi 18:6a4db94011d3 957 uint32_t HAL_RCC_GetPCLK1Freq(void)
sahilmgandhi 18:6a4db94011d3 958 {
sahilmgandhi 18:6a4db94011d3 959 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
sahilmgandhi 18:6a4db94011d3 960 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
sahilmgandhi 18:6a4db94011d3 961 }
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 /**
sahilmgandhi 18:6a4db94011d3 964 * @brief Returns the PCLK2 frequency
sahilmgandhi 18:6a4db94011d3 965 * @note Each time PCLK2 changes, this function must be called to update the
sahilmgandhi 18:6a4db94011d3 966 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
sahilmgandhi 18:6a4db94011d3 967 * @retval PCLK2 frequency
sahilmgandhi 18:6a4db94011d3 968 */
sahilmgandhi 18:6a4db94011d3 969 uint32_t HAL_RCC_GetPCLK2Freq(void)
sahilmgandhi 18:6a4db94011d3 970 {
sahilmgandhi 18:6a4db94011d3 971 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
sahilmgandhi 18:6a4db94011d3 972 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
sahilmgandhi 18:6a4db94011d3 973 }
sahilmgandhi 18:6a4db94011d3 974
sahilmgandhi 18:6a4db94011d3 975 /**
sahilmgandhi 18:6a4db94011d3 976 * @brief Configures the RCC_OscInitStruct according to the internal
sahilmgandhi 18:6a4db94011d3 977 * RCC configuration registers.
sahilmgandhi 18:6a4db94011d3 978 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
sahilmgandhi 18:6a4db94011d3 979 * will be configured.
sahilmgandhi 18:6a4db94011d3 980 * @retval None
sahilmgandhi 18:6a4db94011d3 981 */
sahilmgandhi 18:6a4db94011d3 982 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
sahilmgandhi 18:6a4db94011d3 983 {
sahilmgandhi 18:6a4db94011d3 984 /* Set all possible values for the Oscillator type parameter ---------------*/
sahilmgandhi 18:6a4db94011d3 985 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
sahilmgandhi 18:6a4db94011d3 986
sahilmgandhi 18:6a4db94011d3 987 /* Get the HSE configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 988 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
sahilmgandhi 18:6a4db94011d3 989 {
sahilmgandhi 18:6a4db94011d3 990 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
sahilmgandhi 18:6a4db94011d3 991 }
sahilmgandhi 18:6a4db94011d3 992 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
sahilmgandhi 18:6a4db94011d3 993 {
sahilmgandhi 18:6a4db94011d3 994 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
sahilmgandhi 18:6a4db94011d3 995 }
sahilmgandhi 18:6a4db94011d3 996 else
sahilmgandhi 18:6a4db94011d3 997 {
sahilmgandhi 18:6a4db94011d3 998 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
sahilmgandhi 18:6a4db94011d3 999 }
sahilmgandhi 18:6a4db94011d3 1000
sahilmgandhi 18:6a4db94011d3 1001 /* Get the HSI configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1002 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
sahilmgandhi 18:6a4db94011d3 1003 {
sahilmgandhi 18:6a4db94011d3 1004 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
sahilmgandhi 18:6a4db94011d3 1005 }
sahilmgandhi 18:6a4db94011d3 1006 else
sahilmgandhi 18:6a4db94011d3 1007 {
sahilmgandhi 18:6a4db94011d3 1008 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
sahilmgandhi 18:6a4db94011d3 1009 }
sahilmgandhi 18:6a4db94011d3 1010
sahilmgandhi 18:6a4db94011d3 1011 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 /* Get the LSE configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1014 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
sahilmgandhi 18:6a4db94011d3 1015 {
sahilmgandhi 18:6a4db94011d3 1016 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
sahilmgandhi 18:6a4db94011d3 1017 }
sahilmgandhi 18:6a4db94011d3 1018 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
sahilmgandhi 18:6a4db94011d3 1019 {
sahilmgandhi 18:6a4db94011d3 1020 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
sahilmgandhi 18:6a4db94011d3 1021 }
sahilmgandhi 18:6a4db94011d3 1022 else
sahilmgandhi 18:6a4db94011d3 1023 {
sahilmgandhi 18:6a4db94011d3 1024 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
sahilmgandhi 18:6a4db94011d3 1025 }
sahilmgandhi 18:6a4db94011d3 1026
sahilmgandhi 18:6a4db94011d3 1027 /* Get the LSI configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1028 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
sahilmgandhi 18:6a4db94011d3 1029 {
sahilmgandhi 18:6a4db94011d3 1030 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
sahilmgandhi 18:6a4db94011d3 1031 }
sahilmgandhi 18:6a4db94011d3 1032 else
sahilmgandhi 18:6a4db94011d3 1033 {
sahilmgandhi 18:6a4db94011d3 1034 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
sahilmgandhi 18:6a4db94011d3 1035 }
sahilmgandhi 18:6a4db94011d3 1036
sahilmgandhi 18:6a4db94011d3 1037 /* Get the PLL configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1038 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
sahilmgandhi 18:6a4db94011d3 1039 {
sahilmgandhi 18:6a4db94011d3 1040 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
sahilmgandhi 18:6a4db94011d3 1041 }
sahilmgandhi 18:6a4db94011d3 1042 else
sahilmgandhi 18:6a4db94011d3 1043 {
sahilmgandhi 18:6a4db94011d3 1044 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
sahilmgandhi 18:6a4db94011d3 1045 }
sahilmgandhi 18:6a4db94011d3 1046 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
sahilmgandhi 18:6a4db94011d3 1047 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
sahilmgandhi 18:6a4db94011d3 1048 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
sahilmgandhi 18:6a4db94011d3 1049 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
sahilmgandhi 18:6a4db94011d3 1050 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
sahilmgandhi 18:6a4db94011d3 1051 }
sahilmgandhi 18:6a4db94011d3 1052
sahilmgandhi 18:6a4db94011d3 1053 /**
sahilmgandhi 18:6a4db94011d3 1054 * @brief Configures the RCC_ClkInitStruct according to the internal
sahilmgandhi 18:6a4db94011d3 1055 * RCC configuration registers.
sahilmgandhi 18:6a4db94011d3 1056 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
sahilmgandhi 18:6a4db94011d3 1057 * will be configured.
sahilmgandhi 18:6a4db94011d3 1058 * @param pFLatency: Pointer on the Flash Latency.
sahilmgandhi 18:6a4db94011d3 1059 * @retval None
sahilmgandhi 18:6a4db94011d3 1060 */
sahilmgandhi 18:6a4db94011d3 1061 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
sahilmgandhi 18:6a4db94011d3 1062 {
sahilmgandhi 18:6a4db94011d3 1063 /* Set all possible values for the Clock type parameter --------------------*/
sahilmgandhi 18:6a4db94011d3 1064 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066 /* Get the SYSCLK configuration --------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1067 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
sahilmgandhi 18:6a4db94011d3 1068
sahilmgandhi 18:6a4db94011d3 1069 /* Get the HCLK configuration ----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1070 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 /* Get the APB1 configuration ----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1073 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075 /* Get the APB2 configuration ----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1076 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 /* Get the Flash Wait State (Latency) configuration ------------------------*/
sahilmgandhi 18:6a4db94011d3 1079 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
sahilmgandhi 18:6a4db94011d3 1080 }
sahilmgandhi 18:6a4db94011d3 1081
sahilmgandhi 18:6a4db94011d3 1082 /**
sahilmgandhi 18:6a4db94011d3 1083 * @brief This function handles the RCC CSS interrupt request.
sahilmgandhi 18:6a4db94011d3 1084 * @note This API should be called under the NMI_Handler().
sahilmgandhi 18:6a4db94011d3 1085 * @retval None
sahilmgandhi 18:6a4db94011d3 1086 */
sahilmgandhi 18:6a4db94011d3 1087 void HAL_RCC_NMI_IRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1088 {
sahilmgandhi 18:6a4db94011d3 1089 /* Check RCC CSSF flag */
sahilmgandhi 18:6a4db94011d3 1090 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
sahilmgandhi 18:6a4db94011d3 1091 {
sahilmgandhi 18:6a4db94011d3 1092 /* RCC Clock Security System interrupt user callback */
sahilmgandhi 18:6a4db94011d3 1093 HAL_RCC_CSSCallback();
sahilmgandhi 18:6a4db94011d3 1094
sahilmgandhi 18:6a4db94011d3 1095 /* Clear RCC CSS pending bit */
sahilmgandhi 18:6a4db94011d3 1096 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
sahilmgandhi 18:6a4db94011d3 1097 }
sahilmgandhi 18:6a4db94011d3 1098 }
sahilmgandhi 18:6a4db94011d3 1099
sahilmgandhi 18:6a4db94011d3 1100 /**
sahilmgandhi 18:6a4db94011d3 1101 * @brief RCC Clock Security System interrupt callback
sahilmgandhi 18:6a4db94011d3 1102 * @retval None
sahilmgandhi 18:6a4db94011d3 1103 */
sahilmgandhi 18:6a4db94011d3 1104 __weak void HAL_RCC_CSSCallback(void)
sahilmgandhi 18:6a4db94011d3 1105 {
sahilmgandhi 18:6a4db94011d3 1106 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1107 the HAL_RCC_CSSCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1108 */
sahilmgandhi 18:6a4db94011d3 1109 }
sahilmgandhi 18:6a4db94011d3 1110
sahilmgandhi 18:6a4db94011d3 1111 /**
sahilmgandhi 18:6a4db94011d3 1112 * @}
sahilmgandhi 18:6a4db94011d3 1113 */
sahilmgandhi 18:6a4db94011d3 1114
sahilmgandhi 18:6a4db94011d3 1115 /**
sahilmgandhi 18:6a4db94011d3 1116 * @}
sahilmgandhi 18:6a4db94011d3 1117 */
sahilmgandhi 18:6a4db94011d3 1118
sahilmgandhi 18:6a4db94011d3 1119 #endif /* HAL_RCC_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1120 /**
sahilmgandhi 18:6a4db94011d3 1121 * @}
sahilmgandhi 18:6a4db94011d3 1122 */
sahilmgandhi 18:6a4db94011d3 1123
sahilmgandhi 18:6a4db94011d3 1124 /**
sahilmgandhi 18:6a4db94011d3 1125 * @}
sahilmgandhi 18:6a4db94011d3 1126 */
sahilmgandhi 18:6a4db94011d3 1127
sahilmgandhi 18:6a4db94011d3 1128 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/