MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2s.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f2xx_hal_i2s.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.1.3
sahilmgandhi 18:6a4db94011d3 6 * @date 29-June-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief I2S HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
sahilmgandhi 18:6a4db94011d3 10 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 11 * + IO operation functions
sahilmgandhi 18:6a4db94011d3 12 * + Peripheral State and Errors functions
sahilmgandhi 18:6a4db94011d3 13 @verbatim
sahilmgandhi 18:6a4db94011d3 14 ===============================================================================
sahilmgandhi 18:6a4db94011d3 15 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 16 ===============================================================================
sahilmgandhi 18:6a4db94011d3 17 [..]
sahilmgandhi 18:6a4db94011d3 18 The I2S HAL driver can be used as follow:
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 (#) Declare a I2S_HandleTypeDef handle structure.
sahilmgandhi 18:6a4db94011d3 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
sahilmgandhi 18:6a4db94011d3 22 (##) Enable the SPIx interface clock.
sahilmgandhi 18:6a4db94011d3 23 (##) I2S pins configuration:
sahilmgandhi 18:6a4db94011d3 24 (+++) Enable the clock for the I2S GPIOs.
sahilmgandhi 18:6a4db94011d3 25 (+++) Configure these I2S pins as alternate function pull-up.
sahilmgandhi 18:6a4db94011d3 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
sahilmgandhi 18:6a4db94011d3 27 and HAL_I2S_Receive_IT() APIs).
sahilmgandhi 18:6a4db94011d3 28 (+++) Configure the I2Sx interrupt priority.
sahilmgandhi 18:6a4db94011d3 29 (+++) Enable the NVIC I2S IRQ handle.
sahilmgandhi 18:6a4db94011d3 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
sahilmgandhi 18:6a4db94011d3 31 and HAL_I2S_Receive_DMA() APIs:
sahilmgandhi 18:6a4db94011d3 32 (+++) Declare a DMA handle structure for the Tx/Rx stream.
sahilmgandhi 18:6a4db94011d3 33 (+++) Enable the DMAx interface clock.
sahilmgandhi 18:6a4db94011d3 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
sahilmgandhi 18:6a4db94011d3 35 (+++) Configure the DMA Tx/Rx Stream.
sahilmgandhi 18:6a4db94011d3 36 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
sahilmgandhi 18:6a4db94011d3 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
sahilmgandhi 18:6a4db94011d3 38 DMA Tx/Rx Stream.
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
sahilmgandhi 18:6a4db94011d3 41 using HAL_I2S_Init() function.
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 -@- The specific I2S interrupts (Transmission complete interrupt,
sahilmgandhi 18:6a4db94011d3 44 RXNE interrupt and Error Interrupts) will be managed using the macros
sahilmgandhi 18:6a4db94011d3 45 __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
sahilmgandhi 18:6a4db94011d3 46 -@- Make sure that either:
sahilmgandhi 18:6a4db94011d3 47 (+@) I2S PLL is configured or
sahilmgandhi 18:6a4db94011d3 48 (+@) External clock source is configured after setting correctly
sahilmgandhi 18:6a4db94011d3 49 the define constant EXTERNAL_CLOCK_VALUE in the stm32f2xx_hal_conf.h file.
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 (#) Three operation modes are available within this driver :
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 *** Polling mode IO operation ***
sahilmgandhi 18:6a4db94011d3 54 =================================
sahilmgandhi 18:6a4db94011d3 55 [..]
sahilmgandhi 18:6a4db94011d3 56 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
sahilmgandhi 18:6a4db94011d3 57 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 *** Interrupt mode IO operation ***
sahilmgandhi 18:6a4db94011d3 60 ===================================
sahilmgandhi 18:6a4db94011d3 61 [..]
sahilmgandhi 18:6a4db94011d3 62 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
sahilmgandhi 18:6a4db94011d3 63 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 64 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 65 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 66 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
sahilmgandhi 18:6a4db94011d3 67 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
sahilmgandhi 18:6a4db94011d3 68 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 69 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 70 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 71 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
sahilmgandhi 18:6a4db94011d3 72 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 73 add his own code by customization of function pointer HAL_I2S_ErrorCallback
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 *** DMA mode IO operation ***
sahilmgandhi 18:6a4db94011d3 76 ==============================
sahilmgandhi 18:6a4db94011d3 77 [..]
sahilmgandhi 18:6a4db94011d3 78 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
sahilmgandhi 18:6a4db94011d3 79 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 80 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 81 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 82 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
sahilmgandhi 18:6a4db94011d3 83 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
sahilmgandhi 18:6a4db94011d3 84 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 85 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 86 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 87 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
sahilmgandhi 18:6a4db94011d3 88 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 89 add his own code by customization of function pointer HAL_I2S_ErrorCallback
sahilmgandhi 18:6a4db94011d3 90 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
sahilmgandhi 18:6a4db94011d3 91 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
sahilmgandhi 18:6a4db94011d3 92 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 *** I2S HAL driver macros list ***
sahilmgandhi 18:6a4db94011d3 95 =============================================
sahilmgandhi 18:6a4db94011d3 96 [..]
sahilmgandhi 18:6a4db94011d3 97 Below the list of most used macros in USART HAL driver.
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
sahilmgandhi 18:6a4db94011d3 100 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
sahilmgandhi 18:6a4db94011d3 101 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
sahilmgandhi 18:6a4db94011d3 102 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
sahilmgandhi 18:6a4db94011d3 103 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 [..]
sahilmgandhi 18:6a4db94011d3 106 (@) You can refer to the I2S HAL driver header file for more useful macros
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 @endverbatim
sahilmgandhi 18:6a4db94011d3 109 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 110 * @attention
sahilmgandhi 18:6a4db94011d3 111 *
sahilmgandhi 18:6a4db94011d3 112 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 113 *
sahilmgandhi 18:6a4db94011d3 114 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 115 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 116 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 117 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 118 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 119 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 120 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 121 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 122 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 123 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 124 *
sahilmgandhi 18:6a4db94011d3 125 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 126 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 127 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 128 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 129 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 130 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 131 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 132 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 133 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 134 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 135 *
sahilmgandhi 18:6a4db94011d3 136 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 137 */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 140 #include "stm32f2xx_hal.h"
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 143 * @{
sahilmgandhi 18:6a4db94011d3 144 */
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /** @defgroup I2S I2S
sahilmgandhi 18:6a4db94011d3 147 * @brief I2S HAL module driver
sahilmgandhi 18:6a4db94011d3 148 * @{
sahilmgandhi 18:6a4db94011d3 149 */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 #ifdef HAL_I2S_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 154 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 155 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 156 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 157 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 158 /** @addtogroup I2S_Private_Functions
sahilmgandhi 18:6a4db94011d3 159 * @{
sahilmgandhi 18:6a4db94011d3 160 */
sahilmgandhi 18:6a4db94011d3 161 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 162 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 163 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 164 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 165 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 166 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 167 static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 168 static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 169 /**
sahilmgandhi 18:6a4db94011d3 170 * @}
sahilmgandhi 18:6a4db94011d3 171 */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 174 /** @defgroup I2S_Exported_Functions I2S Exported Functions
sahilmgandhi 18:6a4db94011d3 175 * @{
sahilmgandhi 18:6a4db94011d3 176 */
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 179 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 180 *
sahilmgandhi 18:6a4db94011d3 181 @verbatim
sahilmgandhi 18:6a4db94011d3 182 ===============================================================================
sahilmgandhi 18:6a4db94011d3 183 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 184 ===============================================================================
sahilmgandhi 18:6a4db94011d3 185 [..] This subsection provides a set of functions allowing to initialize and
sahilmgandhi 18:6a4db94011d3 186 de-initialize the I2Sx peripheral in simplex mode:
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 (+) User must Implement HAL_I2S_MspInit() function in which he configures
sahilmgandhi 18:6a4db94011d3 189 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 (+) Call the function HAL_I2S_Init() to configure the selected device with
sahilmgandhi 18:6a4db94011d3 192 the selected configuration:
sahilmgandhi 18:6a4db94011d3 193 (++) Mode
sahilmgandhi 18:6a4db94011d3 194 (++) Standard
sahilmgandhi 18:6a4db94011d3 195 (++) Data Format
sahilmgandhi 18:6a4db94011d3 196 (++) MCLK Output
sahilmgandhi 18:6a4db94011d3 197 (++) Audio frequency
sahilmgandhi 18:6a4db94011d3 198 (++) Polarity
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
sahilmgandhi 18:6a4db94011d3 201 of the selected I2Sx peripheral.
sahilmgandhi 18:6a4db94011d3 202 @endverbatim
sahilmgandhi 18:6a4db94011d3 203 * @{
sahilmgandhi 18:6a4db94011d3 204 */
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 /**
sahilmgandhi 18:6a4db94011d3 207 * @brief Initializes the I2S according to the specified parameters
sahilmgandhi 18:6a4db94011d3 208 * in the I2S_InitTypeDef and create the associated handle.
sahilmgandhi 18:6a4db94011d3 209 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 210 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 211 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 212 */
sahilmgandhi 18:6a4db94011d3 213 __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 214 {
sahilmgandhi 18:6a4db94011d3 215 uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
sahilmgandhi 18:6a4db94011d3 216 uint32_t tmp = 0U, i2sclk = 0U;
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /* Check the I2S handle allocation */
sahilmgandhi 18:6a4db94011d3 219 if(hi2s == NULL)
sahilmgandhi 18:6a4db94011d3 220 {
sahilmgandhi 18:6a4db94011d3 221 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 222 }
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 /* Check the I2S parameters */
sahilmgandhi 18:6a4db94011d3 225 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
sahilmgandhi 18:6a4db94011d3 226 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
sahilmgandhi 18:6a4db94011d3 227 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
sahilmgandhi 18:6a4db94011d3 228 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
sahilmgandhi 18:6a4db94011d3 229 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
sahilmgandhi 18:6a4db94011d3 230 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
sahilmgandhi 18:6a4db94011d3 231 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
sahilmgandhi 18:6a4db94011d3 232 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 if(hi2s->State == HAL_I2S_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 235 {
sahilmgandhi 18:6a4db94011d3 236 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 237 hi2s->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 238 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
sahilmgandhi 18:6a4db94011d3 239 HAL_I2S_MspInit(hi2s);
sahilmgandhi 18:6a4db94011d3 240 }
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 hi2s->State = HAL_I2S_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
sahilmgandhi 18:6a4db94011d3 245 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
sahilmgandhi 18:6a4db94011d3 246 hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
sahilmgandhi 18:6a4db94011d3 247 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
sahilmgandhi 18:6a4db94011d3 248 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
sahilmgandhi 18:6a4db94011d3 249 hi2s->Instance->I2SPR = 0x0002U;
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /* Get the I2SCFGR register value */
sahilmgandhi 18:6a4db94011d3 252 tmpreg = hi2s->Instance->I2SCFGR;
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
sahilmgandhi 18:6a4db94011d3 255 /* If the requested audio frequency is not the default, compute the prescaler */
sahilmgandhi 18:6a4db94011d3 256 if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 /* Check the frame length (For the Prescaler computing) *******************/
sahilmgandhi 18:6a4db94011d3 259 if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
sahilmgandhi 18:6a4db94011d3 260 {
sahilmgandhi 18:6a4db94011d3 261 /* Packet length is 32 bits */
sahilmgandhi 18:6a4db94011d3 262 packetlength = 2U;
sahilmgandhi 18:6a4db94011d3 263 }
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /* Get I2S source Clock frequency ****************************************/
sahilmgandhi 18:6a4db94011d3 266 /* If an external I2S clock has to be used, the specific define should be set
sahilmgandhi 18:6a4db94011d3 267 in the project configuration or in the stm32f2xx_conf.h file */
sahilmgandhi 18:6a4db94011d3 268 if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
sahilmgandhi 18:6a4db94011d3 269 {
sahilmgandhi 18:6a4db94011d3 270 /* Set external clock as I2S clock source */
sahilmgandhi 18:6a4db94011d3 271 if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0U)
sahilmgandhi 18:6a4db94011d3 272 {
sahilmgandhi 18:6a4db94011d3 273 RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
sahilmgandhi 18:6a4db94011d3 274 }
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 /* Set the I2S clock to the external clock value */
sahilmgandhi 18:6a4db94011d3 277 i2sclk = EXTERNAL_CLOCK_VALUE;
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279 else
sahilmgandhi 18:6a4db94011d3 280 {
sahilmgandhi 18:6a4db94011d3 281 /* Check if PLLI2S is enabled or Not */
sahilmgandhi 18:6a4db94011d3 282 if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
sahilmgandhi 18:6a4db94011d3 283 {
sahilmgandhi 18:6a4db94011d3 284 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 287 }
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 /* Set PLLI2S as I2S clock source */
sahilmgandhi 18:6a4db94011d3 290 if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0U)
sahilmgandhi 18:6a4db94011d3 291 {
sahilmgandhi 18:6a4db94011d3 292 RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
sahilmgandhi 18:6a4db94011d3 293 }
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /* Get the PLLM value */
sahilmgandhi 18:6a4db94011d3 296 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 297 {
sahilmgandhi 18:6a4db94011d3 298 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 299 i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
sahilmgandhi 18:6a4db94011d3 300 }
sahilmgandhi 18:6a4db94011d3 301 else
sahilmgandhi 18:6a4db94011d3 302 {
sahilmgandhi 18:6a4db94011d3 303 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 304 i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
sahilmgandhi 18:6a4db94011d3 305 }
sahilmgandhi 18:6a4db94011d3 306 i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U));
sahilmgandhi 18:6a4db94011d3 307 i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U));
sahilmgandhi 18:6a4db94011d3 308 }
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 /* Compute the Real divider depending on the MCLK output state, with a floating point */
sahilmgandhi 18:6a4db94011d3 311 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
sahilmgandhi 18:6a4db94011d3 312 {
sahilmgandhi 18:6a4db94011d3 313 /* MCLK output is enabled */
sahilmgandhi 18:6a4db94011d3 314 tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
sahilmgandhi 18:6a4db94011d3 315 }
sahilmgandhi 18:6a4db94011d3 316 else
sahilmgandhi 18:6a4db94011d3 317 {
sahilmgandhi 18:6a4db94011d3 318 /* MCLK output is disabled */
sahilmgandhi 18:6a4db94011d3 319 tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
sahilmgandhi 18:6a4db94011d3 320 }
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 /* Remove the flatting point */
sahilmgandhi 18:6a4db94011d3 323 tmp = tmp / 10U;
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 /* Check the parity of the divider */
sahilmgandhi 18:6a4db94011d3 326 i2sodd = (uint32_t)(tmp & (uint32_t)1U);
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 /* Compute the i2sdiv prescaler */
sahilmgandhi 18:6a4db94011d3 329 i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
sahilmgandhi 18:6a4db94011d3 332 i2sodd = (uint32_t) (i2sodd << 8U);
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 /* Test if the divider is 1 or 0 or greater than 0xFF */
sahilmgandhi 18:6a4db94011d3 336 if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
sahilmgandhi 18:6a4db94011d3 337 {
sahilmgandhi 18:6a4db94011d3 338 /* Set the default values */
sahilmgandhi 18:6a4db94011d3 339 i2sdiv = 2U;
sahilmgandhi 18:6a4db94011d3 340 i2sodd = 0U;
sahilmgandhi 18:6a4db94011d3 341 }
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 /* Write to SPIx I2SPR register the computed value */
sahilmgandhi 18:6a4db94011d3 344 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 /* Configure the I2S with the I2S_InitStruct values */
sahilmgandhi 18:6a4db94011d3 347 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /* Write to SPIx I2SCFGR */
sahilmgandhi 18:6a4db94011d3 350 hi2s->Instance->I2SCFGR = tmpreg;
sahilmgandhi 18:6a4db94011d3 351 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 352 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 355 }
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 /**
sahilmgandhi 18:6a4db94011d3 358 * @brief DeInitializes the I2S peripheral
sahilmgandhi 18:6a4db94011d3 359 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 360 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 361 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 362 */
sahilmgandhi 18:6a4db94011d3 363 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 364 {
sahilmgandhi 18:6a4db94011d3 365 /* Check the I2S handle allocation */
sahilmgandhi 18:6a4db94011d3 366 if(hi2s == NULL)
sahilmgandhi 18:6a4db94011d3 367 {
sahilmgandhi 18:6a4db94011d3 368 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 369 }
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 hi2s->State = HAL_I2S_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
sahilmgandhi 18:6a4db94011d3 374 HAL_I2S_MspDeInit(hi2s);
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 377 hi2s->State = HAL_I2S_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 380 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /**
sahilmgandhi 18:6a4db94011d3 386 * @brief I2S MSP Init
sahilmgandhi 18:6a4db94011d3 387 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 388 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 389 * @retval None
sahilmgandhi 18:6a4db94011d3 390 */
sahilmgandhi 18:6a4db94011d3 391 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 392 {
sahilmgandhi 18:6a4db94011d3 393 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 394 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 395 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 396 the HAL_I2S_MspInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 397 */
sahilmgandhi 18:6a4db94011d3 398 }
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 /**
sahilmgandhi 18:6a4db94011d3 401 * @brief I2S MSP DeInit
sahilmgandhi 18:6a4db94011d3 402 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 403 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 404 * @retval None
sahilmgandhi 18:6a4db94011d3 405 */
sahilmgandhi 18:6a4db94011d3 406 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 407 {
sahilmgandhi 18:6a4db94011d3 408 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 409 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 410 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 411 the HAL_I2S_MspDeInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 412 */
sahilmgandhi 18:6a4db94011d3 413 }
sahilmgandhi 18:6a4db94011d3 414 /**
sahilmgandhi 18:6a4db94011d3 415 * @}
sahilmgandhi 18:6a4db94011d3 416 */
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
sahilmgandhi 18:6a4db94011d3 419 * @brief Data transfers functions
sahilmgandhi 18:6a4db94011d3 420 *
sahilmgandhi 18:6a4db94011d3 421 @verbatim
sahilmgandhi 18:6a4db94011d3 422 ===============================================================================
sahilmgandhi 18:6a4db94011d3 423 ##### IO operation functions #####
sahilmgandhi 18:6a4db94011d3 424 ===============================================================================
sahilmgandhi 18:6a4db94011d3 425 [..]
sahilmgandhi 18:6a4db94011d3 426 This subsection provides a set of functions allowing to manage the I2S data
sahilmgandhi 18:6a4db94011d3 427 transfers.
sahilmgandhi 18:6a4db94011d3 428
sahilmgandhi 18:6a4db94011d3 429 (#) There are two modes of transfer:
sahilmgandhi 18:6a4db94011d3 430 (++) Blocking mode : The communication is performed in the polling mode.
sahilmgandhi 18:6a4db94011d3 431 The status of all data processing is returned by the same function
sahilmgandhi 18:6a4db94011d3 432 after finishing transfer.
sahilmgandhi 18:6a4db94011d3 433 (++) No-Blocking mode : The communication is performed using Interrupts
sahilmgandhi 18:6a4db94011d3 434 or DMA. These functions return the status of the transfer startup.
sahilmgandhi 18:6a4db94011d3 435 The end of the data processing will be indicated through the
sahilmgandhi 18:6a4db94011d3 436 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
sahilmgandhi 18:6a4db94011d3 437 using DMA mode.
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 (#) Blocking mode functions are :
sahilmgandhi 18:6a4db94011d3 440 (++) HAL_I2S_Transmit()
sahilmgandhi 18:6a4db94011d3 441 (++) HAL_I2S_Receive()
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 (#) No-Blocking mode functions with Interrupt are :
sahilmgandhi 18:6a4db94011d3 444 (++) HAL_I2S_Transmit_IT()
sahilmgandhi 18:6a4db94011d3 445 (++) HAL_I2S_Receive_IT()
sahilmgandhi 18:6a4db94011d3 446
sahilmgandhi 18:6a4db94011d3 447 (#) No-Blocking mode functions with DMA are :
sahilmgandhi 18:6a4db94011d3 448 (++) HAL_I2S_Transmit_DMA()
sahilmgandhi 18:6a4db94011d3 449 (++) HAL_I2S_Receive_DMA()
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
sahilmgandhi 18:6a4db94011d3 452 (++) HAL_I2S_TxCpltCallback()
sahilmgandhi 18:6a4db94011d3 453 (++) HAL_I2S_RxCpltCallback()
sahilmgandhi 18:6a4db94011d3 454 (++) HAL_I2S_ErrorCallback()
sahilmgandhi 18:6a4db94011d3 455
sahilmgandhi 18:6a4db94011d3 456 @endverbatim
sahilmgandhi 18:6a4db94011d3 457 * @{
sahilmgandhi 18:6a4db94011d3 458 */
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 /**
sahilmgandhi 18:6a4db94011d3 461 * @brief Transmit an amount of data in blocking mode
sahilmgandhi 18:6a4db94011d3 462 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 463 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 464 * @param pData: a 16-bit pointer to data buffer.
sahilmgandhi 18:6a4db94011d3 465 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 466 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 467 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 468 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 469 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 470 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 471 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 472 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 473 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 474 */
sahilmgandhi 18:6a4db94011d3 475 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 476 {
sahilmgandhi 18:6a4db94011d3 477 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 478 if((pData == NULL ) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 479 {
sahilmgandhi 18:6a4db94011d3 480 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 481 }
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 484 {
sahilmgandhi 18:6a4db94011d3 485 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 488 {
sahilmgandhi 18:6a4db94011d3 489 hi2s->TxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 490 hi2s->TxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 491 }
sahilmgandhi 18:6a4db94011d3 492 else
sahilmgandhi 18:6a4db94011d3 493 {
sahilmgandhi 18:6a4db94011d3 494 hi2s->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 495 hi2s->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 496 }
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 499 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 hi2s->State = HAL_I2S_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 504 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 505 {
sahilmgandhi 18:6a4db94011d3 506 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 507 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 508 }
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 while(hi2s->TxXferCount > 0U)
sahilmgandhi 18:6a4db94011d3 511 {
sahilmgandhi 18:6a4db94011d3 512 hi2s->Instance->DR = (*pData++);
sahilmgandhi 18:6a4db94011d3 513 hi2s->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 514 /* Wait until TXE flag is set */
sahilmgandhi 18:6a4db94011d3 515 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 516 {
sahilmgandhi 18:6a4db94011d3 517 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 518 }
sahilmgandhi 18:6a4db94011d3 519 }
sahilmgandhi 18:6a4db94011d3 520
sahilmgandhi 18:6a4db94011d3 521 /* Check if Slave mode is selected */
sahilmgandhi 18:6a4db94011d3 522 if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
sahilmgandhi 18:6a4db94011d3 523 {
sahilmgandhi 18:6a4db94011d3 524 /* Wait until Busy flag is reset */
sahilmgandhi 18:6a4db94011d3 525 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 526 {
sahilmgandhi 18:6a4db94011d3 527 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 528 }
sahilmgandhi 18:6a4db94011d3 529 }
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 534 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 537 }
sahilmgandhi 18:6a4db94011d3 538 else
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 541 }
sahilmgandhi 18:6a4db94011d3 542 }
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 /**
sahilmgandhi 18:6a4db94011d3 545 * @brief Receive an amount of data in blocking mode
sahilmgandhi 18:6a4db94011d3 546 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 547 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 548 * @param pData: a 16-bit pointer to data buffer.
sahilmgandhi 18:6a4db94011d3 549 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 550 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 551 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 552 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 553 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 554 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 555 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 556 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 557 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
sahilmgandhi 18:6a4db94011d3 558 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
sahilmgandhi 18:6a4db94011d3 559 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 560 */
sahilmgandhi 18:6a4db94011d3 561 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 562 {
sahilmgandhi 18:6a4db94011d3 563 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 564 if((pData == NULL ) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 565 {
sahilmgandhi 18:6a4db94011d3 566 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 567 }
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 570 {
sahilmgandhi 18:6a4db94011d3 571 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 574 {
sahilmgandhi 18:6a4db94011d3 575 hi2s->RxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 576 hi2s->RxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 577 }
sahilmgandhi 18:6a4db94011d3 578 else
sahilmgandhi 18:6a4db94011d3 579 {
sahilmgandhi 18:6a4db94011d3 580 hi2s->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 581 hi2s->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 582 }
sahilmgandhi 18:6a4db94011d3 583 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 584 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 585
sahilmgandhi 18:6a4db94011d3 586 hi2s->State = HAL_I2S_STATE_BUSY_RX;
sahilmgandhi 18:6a4db94011d3 587
sahilmgandhi 18:6a4db94011d3 588 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 589 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 590 {
sahilmgandhi 18:6a4db94011d3 591 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 592 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 593 }
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 /* Check if Master Receiver mode is selected */
sahilmgandhi 18:6a4db94011d3 596 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
sahilmgandhi 18:6a4db94011d3 597 {
sahilmgandhi 18:6a4db94011d3 598 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
sahilmgandhi 18:6a4db94011d3 599 access to the SPI_SR register. */
sahilmgandhi 18:6a4db94011d3 600 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 601 }
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 /* Receive data */
sahilmgandhi 18:6a4db94011d3 604 while(hi2s->RxXferCount > 0U)
sahilmgandhi 18:6a4db94011d3 605 {
sahilmgandhi 18:6a4db94011d3 606 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 607 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 608 {
sahilmgandhi 18:6a4db94011d3 609 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 610 }
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 (*pData++) = hi2s->Instance->DR;
sahilmgandhi 18:6a4db94011d3 613 hi2s->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 614 }
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 619 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 622 }
sahilmgandhi 18:6a4db94011d3 623 else
sahilmgandhi 18:6a4db94011d3 624 {
sahilmgandhi 18:6a4db94011d3 625 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 626 }
sahilmgandhi 18:6a4db94011d3 627 }
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 /**
sahilmgandhi 18:6a4db94011d3 630 * @brief Transmit an amount of data in non-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 631 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 632 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 633 * @param pData: a 16-bit pointer to data buffer.
sahilmgandhi 18:6a4db94011d3 634 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 635 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 636 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 637 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 638 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 639 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 640 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 641 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 642 */
sahilmgandhi 18:6a4db94011d3 643 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 644 {
sahilmgandhi 18:6a4db94011d3 645 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 646 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 647 {
sahilmgandhi 18:6a4db94011d3 648 if((pData == NULL) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 649 {
sahilmgandhi 18:6a4db94011d3 650 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 651 }
sahilmgandhi 18:6a4db94011d3 652
sahilmgandhi 18:6a4db94011d3 653 hi2s->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 654 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 657 {
sahilmgandhi 18:6a4db94011d3 658 hi2s->TxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 659 hi2s->TxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 660 }
sahilmgandhi 18:6a4db94011d3 661 else
sahilmgandhi 18:6a4db94011d3 662 {
sahilmgandhi 18:6a4db94011d3 663 hi2s->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 664 hi2s->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 665 }
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 668 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 hi2s->State = HAL_I2S_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 671 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 /* Enable TXE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 674 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 677 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 678 {
sahilmgandhi 18:6a4db94011d3 679 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 680 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 681 }
sahilmgandhi 18:6a4db94011d3 682
sahilmgandhi 18:6a4db94011d3 683 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 684 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 685
sahilmgandhi 18:6a4db94011d3 686 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 687 }
sahilmgandhi 18:6a4db94011d3 688 else
sahilmgandhi 18:6a4db94011d3 689 {
sahilmgandhi 18:6a4db94011d3 690 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 691 }
sahilmgandhi 18:6a4db94011d3 692 }
sahilmgandhi 18:6a4db94011d3 693
sahilmgandhi 18:6a4db94011d3 694 /**
sahilmgandhi 18:6a4db94011d3 695 * @brief Receive an amount of data in non-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 696 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 697 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 698 * @param pData: a 16-bit pointer to the Receive data buffer.
sahilmgandhi 18:6a4db94011d3 699 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 700 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 701 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 702 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 703 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 704 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 705 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 706 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
sahilmgandhi 18:6a4db94011d3 707 * between Master and Slave otherwise the I2S interrupt should be optimized.
sahilmgandhi 18:6a4db94011d3 708 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 709 */
sahilmgandhi 18:6a4db94011d3 710 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 711 {
sahilmgandhi 18:6a4db94011d3 712 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 713 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 714 {
sahilmgandhi 18:6a4db94011d3 715 if((pData == NULL) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 716 {
sahilmgandhi 18:6a4db94011d3 717 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 718 }
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 hi2s->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 721 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 722
sahilmgandhi 18:6a4db94011d3 723 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 724 {
sahilmgandhi 18:6a4db94011d3 725 hi2s->RxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 726 hi2s->RxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 727 }
sahilmgandhi 18:6a4db94011d3 728 else
sahilmgandhi 18:6a4db94011d3 729 {
sahilmgandhi 18:6a4db94011d3 730 hi2s->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 731 hi2s->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 732 }
sahilmgandhi 18:6a4db94011d3 733 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 734 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 735
sahilmgandhi 18:6a4db94011d3 736 hi2s->State = HAL_I2S_STATE_BUSY_RX;
sahilmgandhi 18:6a4db94011d3 737 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 738
sahilmgandhi 18:6a4db94011d3 739 /* Enable TXE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 740 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
sahilmgandhi 18:6a4db94011d3 741
sahilmgandhi 18:6a4db94011d3 742 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 743 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 744 {
sahilmgandhi 18:6a4db94011d3 745 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 746 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 747 }
sahilmgandhi 18:6a4db94011d3 748
sahilmgandhi 18:6a4db94011d3 749 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 750 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 753 }
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 else
sahilmgandhi 18:6a4db94011d3 756 {
sahilmgandhi 18:6a4db94011d3 757 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 758 }
sahilmgandhi 18:6a4db94011d3 759 }
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 /**
sahilmgandhi 18:6a4db94011d3 762 * @brief Transmit an amount of data in non-blocking mode with DMA
sahilmgandhi 18:6a4db94011d3 763 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 764 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 765 * @param pData: a 16-bit pointer to the Transmit data buffer.
sahilmgandhi 18:6a4db94011d3 766 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 767 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 768 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 769 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 770 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 771 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 772 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 773 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 774 */
sahilmgandhi 18:6a4db94011d3 775 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 776 {
sahilmgandhi 18:6a4db94011d3 777 uint32_t *tmp;
sahilmgandhi 18:6a4db94011d3 778 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 779
sahilmgandhi 18:6a4db94011d3 780 if((pData == NULL) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 781 {
sahilmgandhi 18:6a4db94011d3 782 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 783 }
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 786 {
sahilmgandhi 18:6a4db94011d3 787 hi2s->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 788 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 789
sahilmgandhi 18:6a4db94011d3 790 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 791 {
sahilmgandhi 18:6a4db94011d3 792 hi2s->TxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 793 hi2s->TxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 794 }
sahilmgandhi 18:6a4db94011d3 795 else
sahilmgandhi 18:6a4db94011d3 796 {
sahilmgandhi 18:6a4db94011d3 797 hi2s->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 798 hi2s->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 799 }
sahilmgandhi 18:6a4db94011d3 800
sahilmgandhi 18:6a4db94011d3 801 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 802 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 803
sahilmgandhi 18:6a4db94011d3 804 hi2s->State = HAL_I2S_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 805 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 806
sahilmgandhi 18:6a4db94011d3 807 /* Set the I2S Tx DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 808 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
sahilmgandhi 18:6a4db94011d3 809
sahilmgandhi 18:6a4db94011d3 810 /* Set the I2S Tx DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 811 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
sahilmgandhi 18:6a4db94011d3 812
sahilmgandhi 18:6a4db94011d3 813 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 814 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 /* Enable the Tx DMA Stream */
sahilmgandhi 18:6a4db94011d3 817 tmp = (uint32_t*)&pData;
sahilmgandhi 18:6a4db94011d3 818 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
sahilmgandhi 18:6a4db94011d3 819
sahilmgandhi 18:6a4db94011d3 820 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 821 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 822 {
sahilmgandhi 18:6a4db94011d3 823 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 824 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 825 }
sahilmgandhi 18:6a4db94011d3 826
sahilmgandhi 18:6a4db94011d3 827 /* Check if the I2S Tx request is already enabled */
sahilmgandhi 18:6a4db94011d3 828 if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
sahilmgandhi 18:6a4db94011d3 829 {
sahilmgandhi 18:6a4db94011d3 830 /* Enable Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 831 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 832 }
sahilmgandhi 18:6a4db94011d3 833
sahilmgandhi 18:6a4db94011d3 834 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 835 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 836
sahilmgandhi 18:6a4db94011d3 837 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 838 }
sahilmgandhi 18:6a4db94011d3 839 else
sahilmgandhi 18:6a4db94011d3 840 {
sahilmgandhi 18:6a4db94011d3 841 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 842 }
sahilmgandhi 18:6a4db94011d3 843 }
sahilmgandhi 18:6a4db94011d3 844
sahilmgandhi 18:6a4db94011d3 845 /**
sahilmgandhi 18:6a4db94011d3 846 * @brief Receive an amount of data in non-blocking mode with DMA
sahilmgandhi 18:6a4db94011d3 847 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 848 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 849 * @param pData: a 16-bit pointer to the Receive data buffer.
sahilmgandhi 18:6a4db94011d3 850 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 851 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 852 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 853 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 854 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 855 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 856 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 857 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 858 */
sahilmgandhi 18:6a4db94011d3 859 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 860 {
sahilmgandhi 18:6a4db94011d3 861 uint32_t *tmp;
sahilmgandhi 18:6a4db94011d3 862 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 if((pData == NULL) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 865 {
sahilmgandhi 18:6a4db94011d3 866 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 867 }
sahilmgandhi 18:6a4db94011d3 868
sahilmgandhi 18:6a4db94011d3 869 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 870 {
sahilmgandhi 18:6a4db94011d3 871 hi2s->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 872 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 873 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 874 {
sahilmgandhi 18:6a4db94011d3 875 hi2s->RxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 876 hi2s->RxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 877 }
sahilmgandhi 18:6a4db94011d3 878 else
sahilmgandhi 18:6a4db94011d3 879 {
sahilmgandhi 18:6a4db94011d3 880 hi2s->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 881 hi2s->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 882 }
sahilmgandhi 18:6a4db94011d3 883 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 884 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 885
sahilmgandhi 18:6a4db94011d3 886 hi2s->State = HAL_I2S_STATE_BUSY_RX;
sahilmgandhi 18:6a4db94011d3 887 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 888
sahilmgandhi 18:6a4db94011d3 889 /* Set the I2S Rx DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 890 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
sahilmgandhi 18:6a4db94011d3 891
sahilmgandhi 18:6a4db94011d3 892 /* Set the I2S Rx DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 893 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
sahilmgandhi 18:6a4db94011d3 894
sahilmgandhi 18:6a4db94011d3 895 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 896 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
sahilmgandhi 18:6a4db94011d3 897
sahilmgandhi 18:6a4db94011d3 898 /* Check if Master Receiver mode is selected */
sahilmgandhi 18:6a4db94011d3 899 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
sahilmgandhi 18:6a4db94011d3 900 {
sahilmgandhi 18:6a4db94011d3 901 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
sahilmgandhi 18:6a4db94011d3 902 access to the SPI_SR register. */
sahilmgandhi 18:6a4db94011d3 903 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 904 }
sahilmgandhi 18:6a4db94011d3 905
sahilmgandhi 18:6a4db94011d3 906 /* Enable the Rx DMA Stream */
sahilmgandhi 18:6a4db94011d3 907 tmp = (uint32_t*)&pData;
sahilmgandhi 18:6a4db94011d3 908 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
sahilmgandhi 18:6a4db94011d3 909
sahilmgandhi 18:6a4db94011d3 910 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 911 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 912 {
sahilmgandhi 18:6a4db94011d3 913 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 914 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917 /* Check if the I2S Rx request is already enabled */
sahilmgandhi 18:6a4db94011d3 918 if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
sahilmgandhi 18:6a4db94011d3 919 {
sahilmgandhi 18:6a4db94011d3 920 /* Enable Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 921 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 922 }
sahilmgandhi 18:6a4db94011d3 923
sahilmgandhi 18:6a4db94011d3 924 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 925 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 928 }
sahilmgandhi 18:6a4db94011d3 929 else
sahilmgandhi 18:6a4db94011d3 930 {
sahilmgandhi 18:6a4db94011d3 931 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 932 }
sahilmgandhi 18:6a4db94011d3 933 }
sahilmgandhi 18:6a4db94011d3 934
sahilmgandhi 18:6a4db94011d3 935 /**
sahilmgandhi 18:6a4db94011d3 936 * @brief Pauses the audio stream playing from the Media.
sahilmgandhi 18:6a4db94011d3 937 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 938 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 939 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 940 */
sahilmgandhi 18:6a4db94011d3 941 __weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 942 {
sahilmgandhi 18:6a4db94011d3 943 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 944 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 945
sahilmgandhi 18:6a4db94011d3 946 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 947 {
sahilmgandhi 18:6a4db94011d3 948 /* Disable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 949 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 950 }
sahilmgandhi 18:6a4db94011d3 951 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 952 {
sahilmgandhi 18:6a4db94011d3 953 /* Disable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 954 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 955 }
sahilmgandhi 18:6a4db94011d3 956 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 957 {
sahilmgandhi 18:6a4db94011d3 958 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
sahilmgandhi 18:6a4db94011d3 959 {
sahilmgandhi 18:6a4db94011d3 960 /* Disable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 961 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 962 }
sahilmgandhi 18:6a4db94011d3 963 else
sahilmgandhi 18:6a4db94011d3 964 {
sahilmgandhi 18:6a4db94011d3 965 /* Disable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 966 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 967 }
sahilmgandhi 18:6a4db94011d3 968 }
sahilmgandhi 18:6a4db94011d3 969
sahilmgandhi 18:6a4db94011d3 970 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 971 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 972
sahilmgandhi 18:6a4db94011d3 973 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 974 }
sahilmgandhi 18:6a4db94011d3 975
sahilmgandhi 18:6a4db94011d3 976 /**
sahilmgandhi 18:6a4db94011d3 977 * @brief Resumes the audio stream playing from the Media.
sahilmgandhi 18:6a4db94011d3 978 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 979 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 980 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 981 */
sahilmgandhi 18:6a4db94011d3 982 __weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 983 {
sahilmgandhi 18:6a4db94011d3 984 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 985 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 986
sahilmgandhi 18:6a4db94011d3 987 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 988 {
sahilmgandhi 18:6a4db94011d3 989 /* Enable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 990 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 991 }
sahilmgandhi 18:6a4db94011d3 992 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 993 {
sahilmgandhi 18:6a4db94011d3 994 /* Enable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 995 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 996 }
sahilmgandhi 18:6a4db94011d3 997 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 998 {
sahilmgandhi 18:6a4db94011d3 999 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
sahilmgandhi 18:6a4db94011d3 1000 {
sahilmgandhi 18:6a4db94011d3 1001 /* Enable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 1002 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 1003 }
sahilmgandhi 18:6a4db94011d3 1004 else
sahilmgandhi 18:6a4db94011d3 1005 {
sahilmgandhi 18:6a4db94011d3 1006 /* Enable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 1007 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 1008 }
sahilmgandhi 18:6a4db94011d3 1009 }
sahilmgandhi 18:6a4db94011d3 1010
sahilmgandhi 18:6a4db94011d3 1011 /* If the I2S peripheral is still not enabled, enable it */
sahilmgandhi 18:6a4db94011d3 1012 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
sahilmgandhi 18:6a4db94011d3 1013 {
sahilmgandhi 18:6a4db94011d3 1014 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 1015 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 1016 }
sahilmgandhi 18:6a4db94011d3 1017
sahilmgandhi 18:6a4db94011d3 1018 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1019 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1020
sahilmgandhi 18:6a4db94011d3 1021 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1022 }
sahilmgandhi 18:6a4db94011d3 1023
sahilmgandhi 18:6a4db94011d3 1024 /**
sahilmgandhi 18:6a4db94011d3 1025 * @brief Resumes the audio stream playing from the Media.
sahilmgandhi 18:6a4db94011d3 1026 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1027 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1028 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1029 */
sahilmgandhi 18:6a4db94011d3 1030 __weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1031 {
sahilmgandhi 18:6a4db94011d3 1032 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1033 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1034
sahilmgandhi 18:6a4db94011d3 1035 /* Disable the I2S Tx/Rx DMA requests */
sahilmgandhi 18:6a4db94011d3 1036 hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 1037 hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 1038
sahilmgandhi 18:6a4db94011d3 1039 /* Abort the I2S DMA Stream tx */
sahilmgandhi 18:6a4db94011d3 1040 if(hi2s->hdmatx != NULL)
sahilmgandhi 18:6a4db94011d3 1041 {
sahilmgandhi 18:6a4db94011d3 1042 HAL_DMA_Abort(hi2s->hdmatx);
sahilmgandhi 18:6a4db94011d3 1043 }
sahilmgandhi 18:6a4db94011d3 1044 /* Abort the I2S DMA Stream rx */
sahilmgandhi 18:6a4db94011d3 1045 if(hi2s->hdmarx != NULL)
sahilmgandhi 18:6a4db94011d3 1046 {
sahilmgandhi 18:6a4db94011d3 1047 HAL_DMA_Abort(hi2s->hdmarx);
sahilmgandhi 18:6a4db94011d3 1048 }
sahilmgandhi 18:6a4db94011d3 1049
sahilmgandhi 18:6a4db94011d3 1050 /* Disable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 1051 __HAL_I2S_DISABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 1052
sahilmgandhi 18:6a4db94011d3 1053 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1054
sahilmgandhi 18:6a4db94011d3 1055 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1056 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1057
sahilmgandhi 18:6a4db94011d3 1058 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1059 }
sahilmgandhi 18:6a4db94011d3 1060
sahilmgandhi 18:6a4db94011d3 1061 /**
sahilmgandhi 18:6a4db94011d3 1062 * @brief This function handles I2S interrupt request.
sahilmgandhi 18:6a4db94011d3 1063 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1064 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1065 * @retval None
sahilmgandhi 18:6a4db94011d3 1066 */
sahilmgandhi 18:6a4db94011d3 1067 __weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1068 {
sahilmgandhi 18:6a4db94011d3 1069 uint32_t tmp1 = 0U, tmp2 = 0U;
sahilmgandhi 18:6a4db94011d3 1070
sahilmgandhi 18:6a4db94011d3 1071 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 1072 {
sahilmgandhi 18:6a4db94011d3 1073 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
sahilmgandhi 18:6a4db94011d3 1074 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
sahilmgandhi 18:6a4db94011d3 1075 /* I2S in mode Receiver ------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1076 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1077 {
sahilmgandhi 18:6a4db94011d3 1078 I2S_Receive_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 1079 }
sahilmgandhi 18:6a4db94011d3 1080
sahilmgandhi 18:6a4db94011d3 1081 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 1082 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1083 /* I2S Overrun error interrupt occurred ---------------------------------*/
sahilmgandhi 18:6a4db94011d3 1084 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1085 {
sahilmgandhi 18:6a4db94011d3 1086 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 1087 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
sahilmgandhi 18:6a4db94011d3 1088 }
sahilmgandhi 18:6a4db94011d3 1089 }
sahilmgandhi 18:6a4db94011d3 1090
sahilmgandhi 18:6a4db94011d3 1091 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 1092 {
sahilmgandhi 18:6a4db94011d3 1093 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
sahilmgandhi 18:6a4db94011d3 1094 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
sahilmgandhi 18:6a4db94011d3 1095 /* I2S in mode Transmitter -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1096 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1097 {
sahilmgandhi 18:6a4db94011d3 1098 I2S_Transmit_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 1099 }
sahilmgandhi 18:6a4db94011d3 1100
sahilmgandhi 18:6a4db94011d3 1101 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
sahilmgandhi 18:6a4db94011d3 1102 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1103 /* I2S Underrun error interrupt occurred --------------------------------*/
sahilmgandhi 18:6a4db94011d3 1104 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1105 {
sahilmgandhi 18:6a4db94011d3 1106 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 1107 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
sahilmgandhi 18:6a4db94011d3 1108 }
sahilmgandhi 18:6a4db94011d3 1109 }
sahilmgandhi 18:6a4db94011d3 1110
sahilmgandhi 18:6a4db94011d3 1111 /* Call the Error call Back in case of Errors */
sahilmgandhi 18:6a4db94011d3 1112 if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 1113 {
sahilmgandhi 18:6a4db94011d3 1114 /* Set the I2S state ready to be able to start again the process */
sahilmgandhi 18:6a4db94011d3 1115 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1116 HAL_I2S_ErrorCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1117 }
sahilmgandhi 18:6a4db94011d3 1118 }
sahilmgandhi 18:6a4db94011d3 1119
sahilmgandhi 18:6a4db94011d3 1120 /**
sahilmgandhi 18:6a4db94011d3 1121 * @brief Tx Transfer Half completed callbacks
sahilmgandhi 18:6a4db94011d3 1122 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1123 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1124 * @retval None
sahilmgandhi 18:6a4db94011d3 1125 */
sahilmgandhi 18:6a4db94011d3 1126 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1127 {
sahilmgandhi 18:6a4db94011d3 1128 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1129 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1130 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1131 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1132 */
sahilmgandhi 18:6a4db94011d3 1133 }
sahilmgandhi 18:6a4db94011d3 1134
sahilmgandhi 18:6a4db94011d3 1135 /**
sahilmgandhi 18:6a4db94011d3 1136 * @brief Tx Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1137 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1138 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1139 * @retval None
sahilmgandhi 18:6a4db94011d3 1140 */
sahilmgandhi 18:6a4db94011d3 1141 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1142 {
sahilmgandhi 18:6a4db94011d3 1143 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1144 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1145 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1146 the HAL_I2S_TxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1147 */
sahilmgandhi 18:6a4db94011d3 1148 }
sahilmgandhi 18:6a4db94011d3 1149
sahilmgandhi 18:6a4db94011d3 1150 /**
sahilmgandhi 18:6a4db94011d3 1151 * @brief Rx Transfer half completed callbacks
sahilmgandhi 18:6a4db94011d3 1152 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1153 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1154 * @retval None
sahilmgandhi 18:6a4db94011d3 1155 */
sahilmgandhi 18:6a4db94011d3 1156 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1157 {
sahilmgandhi 18:6a4db94011d3 1158 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1159 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1160 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1161 the HAL_I2S_RxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1162 */
sahilmgandhi 18:6a4db94011d3 1163 }
sahilmgandhi 18:6a4db94011d3 1164
sahilmgandhi 18:6a4db94011d3 1165 /**
sahilmgandhi 18:6a4db94011d3 1166 * @brief Rx Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1167 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1168 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1169 * @retval None
sahilmgandhi 18:6a4db94011d3 1170 */
sahilmgandhi 18:6a4db94011d3 1171 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1172 {
sahilmgandhi 18:6a4db94011d3 1173 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1174 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1175 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1176 the HAL_I2S_RxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1177 */
sahilmgandhi 18:6a4db94011d3 1178 }
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180 /**
sahilmgandhi 18:6a4db94011d3 1181 * @brief I2S error callbacks
sahilmgandhi 18:6a4db94011d3 1182 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1183 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1184 * @retval None
sahilmgandhi 18:6a4db94011d3 1185 */
sahilmgandhi 18:6a4db94011d3 1186 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1187 {
sahilmgandhi 18:6a4db94011d3 1188 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1189 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1190 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1191 the HAL_I2S_ErrorCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1192 */
sahilmgandhi 18:6a4db94011d3 1193 }
sahilmgandhi 18:6a4db94011d3 1194
sahilmgandhi 18:6a4db94011d3 1195 /**
sahilmgandhi 18:6a4db94011d3 1196 * @}
sahilmgandhi 18:6a4db94011d3 1197 */
sahilmgandhi 18:6a4db94011d3 1198
sahilmgandhi 18:6a4db94011d3 1199 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
sahilmgandhi 18:6a4db94011d3 1200 * @brief Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1201 @verbatim
sahilmgandhi 18:6a4db94011d3 1202 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1203 ##### Peripheral State and Errors functions #####
sahilmgandhi 18:6a4db94011d3 1204 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1205 [..]
sahilmgandhi 18:6a4db94011d3 1206 This subsection permits to get in run-time the status of the peripheral
sahilmgandhi 18:6a4db94011d3 1207 and the data flow.
sahilmgandhi 18:6a4db94011d3 1208
sahilmgandhi 18:6a4db94011d3 1209 @endverbatim
sahilmgandhi 18:6a4db94011d3 1210 * @{
sahilmgandhi 18:6a4db94011d3 1211 */
sahilmgandhi 18:6a4db94011d3 1212
sahilmgandhi 18:6a4db94011d3 1213 /**
sahilmgandhi 18:6a4db94011d3 1214 * @brief Return the I2S state
sahilmgandhi 18:6a4db94011d3 1215 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1216 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1217 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1218 */
sahilmgandhi 18:6a4db94011d3 1219 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1220 {
sahilmgandhi 18:6a4db94011d3 1221 return hi2s->State;
sahilmgandhi 18:6a4db94011d3 1222 }
sahilmgandhi 18:6a4db94011d3 1223
sahilmgandhi 18:6a4db94011d3 1224 /**
sahilmgandhi 18:6a4db94011d3 1225 * @brief Return the I2S error code
sahilmgandhi 18:6a4db94011d3 1226 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1227 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1228 * @retval I2S Error Code
sahilmgandhi 18:6a4db94011d3 1229 */
sahilmgandhi 18:6a4db94011d3 1230 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1231 {
sahilmgandhi 18:6a4db94011d3 1232 return hi2s->ErrorCode;
sahilmgandhi 18:6a4db94011d3 1233 }
sahilmgandhi 18:6a4db94011d3 1234 /**
sahilmgandhi 18:6a4db94011d3 1235 * @}
sahilmgandhi 18:6a4db94011d3 1236 */
sahilmgandhi 18:6a4db94011d3 1237
sahilmgandhi 18:6a4db94011d3 1238 /**
sahilmgandhi 18:6a4db94011d3 1239 * @brief DMA I2S transmit process complete callback
sahilmgandhi 18:6a4db94011d3 1240 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1241 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1242 * @retval None
sahilmgandhi 18:6a4db94011d3 1243 */
sahilmgandhi 18:6a4db94011d3 1244 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1245 {
sahilmgandhi 18:6a4db94011d3 1246 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1247
sahilmgandhi 18:6a4db94011d3 1248 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
sahilmgandhi 18:6a4db94011d3 1249 {
sahilmgandhi 18:6a4db94011d3 1250 hi2s->TxXferCount = 0U;
sahilmgandhi 18:6a4db94011d3 1251
sahilmgandhi 18:6a4db94011d3 1252 /* Disable Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 1253 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 1254
sahilmgandhi 18:6a4db94011d3 1255 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 1256 {
sahilmgandhi 18:6a4db94011d3 1257 if(hi2s->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1258 {
sahilmgandhi 18:6a4db94011d3 1259 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1260 }
sahilmgandhi 18:6a4db94011d3 1261 }
sahilmgandhi 18:6a4db94011d3 1262 else
sahilmgandhi 18:6a4db94011d3 1263 {
sahilmgandhi 18:6a4db94011d3 1264 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1265 }
sahilmgandhi 18:6a4db94011d3 1266 }
sahilmgandhi 18:6a4db94011d3 1267 HAL_I2S_TxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1268 }
sahilmgandhi 18:6a4db94011d3 1269
sahilmgandhi 18:6a4db94011d3 1270 /**
sahilmgandhi 18:6a4db94011d3 1271 * @brief DMA I2S transmit process half complete callback
sahilmgandhi 18:6a4db94011d3 1272 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1273 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1274 * @retval None
sahilmgandhi 18:6a4db94011d3 1275 */
sahilmgandhi 18:6a4db94011d3 1276 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1277 {
sahilmgandhi 18:6a4db94011d3 1278 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1279
sahilmgandhi 18:6a4db94011d3 1280 HAL_I2S_TxHalfCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1281 }
sahilmgandhi 18:6a4db94011d3 1282
sahilmgandhi 18:6a4db94011d3 1283 /**
sahilmgandhi 18:6a4db94011d3 1284 * @brief DMA I2S receive process complete callback
sahilmgandhi 18:6a4db94011d3 1285 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1286 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1287 * @retval None
sahilmgandhi 18:6a4db94011d3 1288 */
sahilmgandhi 18:6a4db94011d3 1289 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1290 {
sahilmgandhi 18:6a4db94011d3 1291 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1292
sahilmgandhi 18:6a4db94011d3 1293 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
sahilmgandhi 18:6a4db94011d3 1294 {
sahilmgandhi 18:6a4db94011d3 1295 /* Disable Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 1296 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 1297 hi2s->RxXferCount = 0U;
sahilmgandhi 18:6a4db94011d3 1298 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 1299 {
sahilmgandhi 18:6a4db94011d3 1300 if(hi2s->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1301 {
sahilmgandhi 18:6a4db94011d3 1302 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1303 }
sahilmgandhi 18:6a4db94011d3 1304 }
sahilmgandhi 18:6a4db94011d3 1305 else
sahilmgandhi 18:6a4db94011d3 1306 {
sahilmgandhi 18:6a4db94011d3 1307 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1308 }
sahilmgandhi 18:6a4db94011d3 1309 }
sahilmgandhi 18:6a4db94011d3 1310 HAL_I2S_RxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1311 }
sahilmgandhi 18:6a4db94011d3 1312
sahilmgandhi 18:6a4db94011d3 1313 /**
sahilmgandhi 18:6a4db94011d3 1314 * @brief DMA I2S receive process half complete callback
sahilmgandhi 18:6a4db94011d3 1315 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1316 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1317 * @retval None
sahilmgandhi 18:6a4db94011d3 1318 */
sahilmgandhi 18:6a4db94011d3 1319 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1320 {
sahilmgandhi 18:6a4db94011d3 1321 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1322
sahilmgandhi 18:6a4db94011d3 1323 HAL_I2S_RxHalfCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1324 }
sahilmgandhi 18:6a4db94011d3 1325
sahilmgandhi 18:6a4db94011d3 1326 /**
sahilmgandhi 18:6a4db94011d3 1327 * @brief DMA I2S communication error callback
sahilmgandhi 18:6a4db94011d3 1328 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1329 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1330 * @retval None
sahilmgandhi 18:6a4db94011d3 1331 */
sahilmgandhi 18:6a4db94011d3 1332 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1333 {
sahilmgandhi 18:6a4db94011d3 1334 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1335
sahilmgandhi 18:6a4db94011d3 1336 hi2s->TxXferCount = 0U;
sahilmgandhi 18:6a4db94011d3 1337 hi2s->RxXferCount = 0U;
sahilmgandhi 18:6a4db94011d3 1338
sahilmgandhi 18:6a4db94011d3 1339 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1340
sahilmgandhi 18:6a4db94011d3 1341 hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
sahilmgandhi 18:6a4db94011d3 1342 HAL_I2S_ErrorCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1343 }
sahilmgandhi 18:6a4db94011d3 1344
sahilmgandhi 18:6a4db94011d3 1345 /**
sahilmgandhi 18:6a4db94011d3 1346 * @brief Transmit an amount of data in non-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 1347 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1348 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1349 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1350 */
sahilmgandhi 18:6a4db94011d3 1351 static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1352 {
sahilmgandhi 18:6a4db94011d3 1353 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 1354 {
sahilmgandhi 18:6a4db94011d3 1355 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1356 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1357
sahilmgandhi 18:6a4db94011d3 1358 /* Transmit data */
sahilmgandhi 18:6a4db94011d3 1359 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 1360
sahilmgandhi 18:6a4db94011d3 1361 hi2s->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 1362
sahilmgandhi 18:6a4db94011d3 1363 if(hi2s->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1364 {
sahilmgandhi 18:6a4db94011d3 1365 /* Disable TXE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 1366 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
sahilmgandhi 18:6a4db94011d3 1367
sahilmgandhi 18:6a4db94011d3 1368 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1369
sahilmgandhi 18:6a4db94011d3 1370 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1371 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1372 HAL_I2S_TxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1373 }
sahilmgandhi 18:6a4db94011d3 1374 else
sahilmgandhi 18:6a4db94011d3 1375 {
sahilmgandhi 18:6a4db94011d3 1376 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1377 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1378 }
sahilmgandhi 18:6a4db94011d3 1379
sahilmgandhi 18:6a4db94011d3 1380 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1381 }
sahilmgandhi 18:6a4db94011d3 1382
sahilmgandhi 18:6a4db94011d3 1383 else
sahilmgandhi 18:6a4db94011d3 1384 {
sahilmgandhi 18:6a4db94011d3 1385 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1386 }
sahilmgandhi 18:6a4db94011d3 1387 }
sahilmgandhi 18:6a4db94011d3 1388
sahilmgandhi 18:6a4db94011d3 1389 /**
sahilmgandhi 18:6a4db94011d3 1390 * @brief Receive an amount of data in non-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 1391 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1392 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1393 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1394 */
sahilmgandhi 18:6a4db94011d3 1395 static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1396 {
sahilmgandhi 18:6a4db94011d3 1397 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 1398 {
sahilmgandhi 18:6a4db94011d3 1399 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1400 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1401
sahilmgandhi 18:6a4db94011d3 1402 /* Receive data */
sahilmgandhi 18:6a4db94011d3 1403 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
sahilmgandhi 18:6a4db94011d3 1404
sahilmgandhi 18:6a4db94011d3 1405 hi2s->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 1406
sahilmgandhi 18:6a4db94011d3 1407 /* Check if Master Receiver mode is selected */
sahilmgandhi 18:6a4db94011d3 1408 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
sahilmgandhi 18:6a4db94011d3 1409 {
sahilmgandhi 18:6a4db94011d3 1410 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
sahilmgandhi 18:6a4db94011d3 1411 access to the SPI_SR register. */
sahilmgandhi 18:6a4db94011d3 1412 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 1413 }
sahilmgandhi 18:6a4db94011d3 1414
sahilmgandhi 18:6a4db94011d3 1415 if(hi2s->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1416 {
sahilmgandhi 18:6a4db94011d3 1417 /* Disable RXNE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 1418 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1419
sahilmgandhi 18:6a4db94011d3 1420 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1421
sahilmgandhi 18:6a4db94011d3 1422 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1423 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1424
sahilmgandhi 18:6a4db94011d3 1425 HAL_I2S_RxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1426 }
sahilmgandhi 18:6a4db94011d3 1427 else
sahilmgandhi 18:6a4db94011d3 1428 {
sahilmgandhi 18:6a4db94011d3 1429 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1430 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1431 }
sahilmgandhi 18:6a4db94011d3 1432
sahilmgandhi 18:6a4db94011d3 1433 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1434 }
sahilmgandhi 18:6a4db94011d3 1435 else
sahilmgandhi 18:6a4db94011d3 1436 {
sahilmgandhi 18:6a4db94011d3 1437 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1438 }
sahilmgandhi 18:6a4db94011d3 1439 }
sahilmgandhi 18:6a4db94011d3 1440
sahilmgandhi 18:6a4db94011d3 1441 /**
sahilmgandhi 18:6a4db94011d3 1442 * @brief This function handles I2S Communication Timeout.
sahilmgandhi 18:6a4db94011d3 1443 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1444 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1445 * @param Flag: Flag checked
sahilmgandhi 18:6a4db94011d3 1446 * @param Status: Value of the flag expected
sahilmgandhi 18:6a4db94011d3 1447 * @param Timeout: Duration of the timeout
sahilmgandhi 18:6a4db94011d3 1448 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1449 */
sahilmgandhi 18:6a4db94011d3 1450 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 1451 {
sahilmgandhi 18:6a4db94011d3 1452 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 1453
sahilmgandhi 18:6a4db94011d3 1454 /* Get tick */
sahilmgandhi 18:6a4db94011d3 1455 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 1456
sahilmgandhi 18:6a4db94011d3 1457 /* Wait until flag is set */
sahilmgandhi 18:6a4db94011d3 1458 if(Status == RESET)
sahilmgandhi 18:6a4db94011d3 1459 {
sahilmgandhi 18:6a4db94011d3 1460 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
sahilmgandhi 18:6a4db94011d3 1461 {
sahilmgandhi 18:6a4db94011d3 1462 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 1463 {
sahilmgandhi 18:6a4db94011d3 1464 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 1465 {
sahilmgandhi 18:6a4db94011d3 1466 /* Set the I2S State ready */
sahilmgandhi 18:6a4db94011d3 1467 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1468
sahilmgandhi 18:6a4db94011d3 1469 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1470 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1471
sahilmgandhi 18:6a4db94011d3 1472 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1473 }
sahilmgandhi 18:6a4db94011d3 1474 }
sahilmgandhi 18:6a4db94011d3 1475 }
sahilmgandhi 18:6a4db94011d3 1476 }
sahilmgandhi 18:6a4db94011d3 1477 else
sahilmgandhi 18:6a4db94011d3 1478 {
sahilmgandhi 18:6a4db94011d3 1479 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
sahilmgandhi 18:6a4db94011d3 1480 {
sahilmgandhi 18:6a4db94011d3 1481 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 1482 {
sahilmgandhi 18:6a4db94011d3 1483 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 1484 {
sahilmgandhi 18:6a4db94011d3 1485 /* Set the I2S State ready */
sahilmgandhi 18:6a4db94011d3 1486 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1487
sahilmgandhi 18:6a4db94011d3 1488 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1489 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1490
sahilmgandhi 18:6a4db94011d3 1491 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1492 }
sahilmgandhi 18:6a4db94011d3 1493 }
sahilmgandhi 18:6a4db94011d3 1494 }
sahilmgandhi 18:6a4db94011d3 1495 }
sahilmgandhi 18:6a4db94011d3 1496 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1497 }
sahilmgandhi 18:6a4db94011d3 1498
sahilmgandhi 18:6a4db94011d3 1499 /**
sahilmgandhi 18:6a4db94011d3 1500 * @}
sahilmgandhi 18:6a4db94011d3 1501 */
sahilmgandhi 18:6a4db94011d3 1502
sahilmgandhi 18:6a4db94011d3 1503 #endif /* HAL_I2S_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1504 /**
sahilmgandhi 18:6a4db94011d3 1505 * @}
sahilmgandhi 18:6a4db94011d3 1506 */
sahilmgandhi 18:6a4db94011d3 1507
sahilmgandhi 18:6a4db94011d3 1508 /**
sahilmgandhi 18:6a4db94011d3 1509 * @}
sahilmgandhi 18:6a4db94011d3 1510 */
sahilmgandhi 18:6a4db94011d3 1511
sahilmgandhi 18:6a4db94011d3 1512 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/