MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_dma.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f2xx_hal_dma.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.1.3
sahilmgandhi 18:6a4db94011d3 6 * @date 29-June-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief DMA HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 10 * functionalities of the Direct Memory Access (DMA) peripheral:
sahilmgandhi 18:6a4db94011d3 11 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 12 * + IO operation functions
sahilmgandhi 18:6a4db94011d3 13 * + Peripheral State and errors functions
sahilmgandhi 18:6a4db94011d3 14 @verbatim
sahilmgandhi 18:6a4db94011d3 15 ==============================================================================
sahilmgandhi 18:6a4db94011d3 16 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 17 ==============================================================================
sahilmgandhi 18:6a4db94011d3 18 [..]
sahilmgandhi 18:6a4db94011d3 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
sahilmgandhi 18:6a4db94011d3 20 (except for internal SRAM/FLASH memories: no initialization is
sahilmgandhi 18:6a4db94011d3 21 necessary) please refer to Reference manual for connection between peripherals
sahilmgandhi 18:6a4db94011d3 22 and DMA requests.
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 (#) For a given Stream, program the required configuration through the following parameters:
sahilmgandhi 18:6a4db94011d3 25 Transfer Direction, Source and Destination data formats,
sahilmgandhi 18:6a4db94011d3 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
sahilmgandhi 18:6a4db94011d3 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
sahilmgandhi 18:6a4db94011d3 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
sahilmgandhi 18:6a4db94011d3 31 __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 *** Polling mode IO operation ***
sahilmgandhi 18:6a4db94011d3 34 =================================
sahilmgandhi 18:6a4db94011d3 35 [..]
sahilmgandhi 18:6a4db94011d3 36 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
sahilmgandhi 18:6a4db94011d3 37 address and destination address and the Length of data to be transferred.
sahilmgandhi 18:6a4db94011d3 38 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
sahilmgandhi 18:6a4db94011d3 39 case a fixed Timeout can be configured by User depending from his application.
sahilmgandhi 18:6a4db94011d3 40 (+) Use HAL_DMA_Abort() function to abort the current transfer.
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 *** Interrupt mode IO operation ***
sahilmgandhi 18:6a4db94011d3 43 ===================================
sahilmgandhi 18:6a4db94011d3 44 [..]
sahilmgandhi 18:6a4db94011d3 45 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
sahilmgandhi 18:6a4db94011d3 46 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
sahilmgandhi 18:6a4db94011d3 47 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
sahilmgandhi 18:6a4db94011d3 48 Source address and destination address and the Length of data to be transferred. In this
sahilmgandhi 18:6a4db94011d3 49 case the DMA interrupt is configured
sahilmgandhi 18:6a4db94011d3 50 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
sahilmgandhi 18:6a4db94011d3 51 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
sahilmgandhi 18:6a4db94011d3 52 add his own function by customization of function pointer XferCpltCallback and
sahilmgandhi 18:6a4db94011d3 53 XferErrorCallback (i.e a member of DMA handle structure).
sahilmgandhi 18:6a4db94011d3 54 [..]
sahilmgandhi 18:6a4db94011d3 55 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
sahilmgandhi 18:6a4db94011d3 56 detection.
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
sahilmgandhi 18:6a4db94011d3 63 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
sahilmgandhi 18:6a4db94011d3 64 Half-Word data size for the peripheral to access its data register and set Word data size
sahilmgandhi 18:6a4db94011d3 65 for the Memory to gain in access time. Each two half words will be packed and written in
sahilmgandhi 18:6a4db94011d3 66 a single access to a Word in the Memory).
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
sahilmgandhi 18:6a4db94011d3 69 and Destination. In this case the Peripheral Data Size will be applied to both Source
sahilmgandhi 18:6a4db94011d3 70 and Destination.
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 *** DMA HAL driver macros list ***
sahilmgandhi 18:6a4db94011d3 73 =============================================
sahilmgandhi 18:6a4db94011d3 74 [..]
sahilmgandhi 18:6a4db94011d3 75 Below the list of most used macros in DMA HAL driver.
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 78 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 79 (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
sahilmgandhi 18:6a4db94011d3 80 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
sahilmgandhi 18:6a4db94011d3 81 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
sahilmgandhi 18:6a4db94011d3 82 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 [..]
sahilmgandhi 18:6a4db94011d3 85 (@) You can refer to the DMA HAL driver header file for more useful macros
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 @endverbatim
sahilmgandhi 18:6a4db94011d3 88 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 89 * @attention
sahilmgandhi 18:6a4db94011d3 90 *
sahilmgandhi 18:6a4db94011d3 91 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 92 *
sahilmgandhi 18:6a4db94011d3 93 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 94 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 95 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 96 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 97 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 98 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 99 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 100 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 101 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 102 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 103 *
sahilmgandhi 18:6a4db94011d3 104 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 105 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 106 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 107 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 108 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 109 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 110 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 111 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 112 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 113 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 114 *
sahilmgandhi 18:6a4db94011d3 115 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 116 */
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 119 #include "stm32f2xx_hal.h"
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 122 * @{
sahilmgandhi 18:6a4db94011d3 123 */
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /** @defgroup DMA DMA
sahilmgandhi 18:6a4db94011d3 126 * @brief DMA HAL module driver
sahilmgandhi 18:6a4db94011d3 127 * @{
sahilmgandhi 18:6a4db94011d3 128 */
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 #ifdef HAL_DMA_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 133 typedef struct
sahilmgandhi 18:6a4db94011d3 134 {
sahilmgandhi 18:6a4db94011d3 135 __IO uint32_t ISR; /*!< DMA interrupt status register */
sahilmgandhi 18:6a4db94011d3 136 __IO uint32_t Reserved0;
sahilmgandhi 18:6a4db94011d3 137 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
sahilmgandhi 18:6a4db94011d3 138 } DMA_Base_Registers;
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 141 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 142 /** @addtogroup DMA_Private_Constants
sahilmgandhi 18:6a4db94011d3 143 * @{
sahilmgandhi 18:6a4db94011d3 144 */
sahilmgandhi 18:6a4db94011d3 145 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */
sahilmgandhi 18:6a4db94011d3 146 /**
sahilmgandhi 18:6a4db94011d3 147 * @}
sahilmgandhi 18:6a4db94011d3 148 */
sahilmgandhi 18:6a4db94011d3 149 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 150 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 151 /** @addtogroup DMA_Private_Functions
sahilmgandhi 18:6a4db94011d3 152 * @{
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
sahilmgandhi 18:6a4db94011d3 155 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 156 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 /**
sahilmgandhi 18:6a4db94011d3 159 * @}
sahilmgandhi 18:6a4db94011d3 160 */
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 163 /** @addtogroup DMA_Exported_Functions
sahilmgandhi 18:6a4db94011d3 164 * @{
sahilmgandhi 18:6a4db94011d3 165 */
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /** @addtogroup DMA_Exported_Functions_Group1
sahilmgandhi 18:6a4db94011d3 168 *
sahilmgandhi 18:6a4db94011d3 169 @verbatim
sahilmgandhi 18:6a4db94011d3 170 ===============================================================================
sahilmgandhi 18:6a4db94011d3 171 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 172 ===============================================================================
sahilmgandhi 18:6a4db94011d3 173 [..]
sahilmgandhi 18:6a4db94011d3 174 This section provides functions allowing to initialize the DMA Stream source
sahilmgandhi 18:6a4db94011d3 175 and destination addresses, incrementation and data sizes, transfer direction,
sahilmgandhi 18:6a4db94011d3 176 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
sahilmgandhi 18:6a4db94011d3 177 [..]
sahilmgandhi 18:6a4db94011d3 178 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
sahilmgandhi 18:6a4db94011d3 179 reference manual.
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 @endverbatim
sahilmgandhi 18:6a4db94011d3 182 * @{
sahilmgandhi 18:6a4db94011d3 183 */
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /**
sahilmgandhi 18:6a4db94011d3 186 * @brief Initializes the DMA according to the specified
sahilmgandhi 18:6a4db94011d3 187 * parameters in the DMA_InitTypeDef and create the associated handle.
sahilmgandhi 18:6a4db94011d3 188 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 189 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 190 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 191 */
sahilmgandhi 18:6a4db94011d3 192 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 193 {
sahilmgandhi 18:6a4db94011d3 194 uint32_t tmp = 0U;
sahilmgandhi 18:6a4db94011d3 195 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 196 DMA_Base_Registers *regs;
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 /* Check the DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 199 if(hdma == NULL)
sahilmgandhi 18:6a4db94011d3 200 {
sahilmgandhi 18:6a4db94011d3 201 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 202 }
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 205 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
sahilmgandhi 18:6a4db94011d3 206 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
sahilmgandhi 18:6a4db94011d3 207 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
sahilmgandhi 18:6a4db94011d3 208 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
sahilmgandhi 18:6a4db94011d3 209 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
sahilmgandhi 18:6a4db94011d3 210 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
sahilmgandhi 18:6a4db94011d3 211 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
sahilmgandhi 18:6a4db94011d3 212 assert_param(IS_DMA_MODE(hdma->Init.Mode));
sahilmgandhi 18:6a4db94011d3 213 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
sahilmgandhi 18:6a4db94011d3 214 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
sahilmgandhi 18:6a4db94011d3 215 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
sahilmgandhi 18:6a4db94011d3 216 when FIFO mode is enabled */
sahilmgandhi 18:6a4db94011d3 217 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
sahilmgandhi 18:6a4db94011d3 218 {
sahilmgandhi 18:6a4db94011d3 219 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
sahilmgandhi 18:6a4db94011d3 220 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
sahilmgandhi 18:6a4db94011d3 221 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
sahilmgandhi 18:6a4db94011d3 222 }
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 /* Allocate lock resource */
sahilmgandhi 18:6a4db94011d3 225 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 228 hdma->State = HAL_DMA_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 /* Disable the peripheral */
sahilmgandhi 18:6a4db94011d3 231 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /* Check if the DMA Stream is effectively disabled */
sahilmgandhi 18:6a4db94011d3 234 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
sahilmgandhi 18:6a4db94011d3 235 {
sahilmgandhi 18:6a4db94011d3 236 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 237 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
sahilmgandhi 18:6a4db94011d3 238 {
sahilmgandhi 18:6a4db94011d3 239 /* Update error code */
sahilmgandhi 18:6a4db94011d3 240 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 243 hdma->State = HAL_DMA_STATE_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 246 }
sahilmgandhi 18:6a4db94011d3 247 }
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 /* Get the CR register value */
sahilmgandhi 18:6a4db94011d3 250 tmp = hdma->Instance->CR;
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
sahilmgandhi 18:6a4db94011d3 253 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
sahilmgandhi 18:6a4db94011d3 254 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
sahilmgandhi 18:6a4db94011d3 255 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
sahilmgandhi 18:6a4db94011d3 256 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 /* Prepare the DMA Stream configuration */
sahilmgandhi 18:6a4db94011d3 259 tmp |= hdma->Init.Channel | hdma->Init.Direction |
sahilmgandhi 18:6a4db94011d3 260 hdma->Init.PeriphInc | hdma->Init.MemInc |
sahilmgandhi 18:6a4db94011d3 261 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
sahilmgandhi 18:6a4db94011d3 262 hdma->Init.Mode | hdma->Init.Priority;
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
sahilmgandhi 18:6a4db94011d3 265 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 266 {
sahilmgandhi 18:6a4db94011d3 267 /* Get memory burst and peripheral burst */
sahilmgandhi 18:6a4db94011d3 268 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
sahilmgandhi 18:6a4db94011d3 269 }
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 /* Write to DMA Stream CR register */
sahilmgandhi 18:6a4db94011d3 272 hdma->Instance->CR = tmp;
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /* Get the FCR register value */
sahilmgandhi 18:6a4db94011d3 275 tmp = hdma->Instance->FCR;
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 /* Clear Direct mode and FIFO threshold bits */
sahilmgandhi 18:6a4db94011d3 278 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 /* Prepare the DMA Stream FIFO configuration */
sahilmgandhi 18:6a4db94011d3 281 tmp |= hdma->Init.FIFOMode;
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 /* the FIFO threshold is not used when the FIFO mode is disabled */
sahilmgandhi 18:6a4db94011d3 284 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 285 {
sahilmgandhi 18:6a4db94011d3 286 /* Get the FIFO threshold */
sahilmgandhi 18:6a4db94011d3 287 tmp |= hdma->Init.FIFOThreshold;
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 if(DMA_CheckFifoParam(hdma) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 290 {
sahilmgandhi 18:6a4db94011d3 291 /* Update error code */
sahilmgandhi 18:6a4db94011d3 292 hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 295 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 298 }
sahilmgandhi 18:6a4db94011d3 299 }
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 /* Write to DMA Stream FCR */
sahilmgandhi 18:6a4db94011d3 302 hdma->Instance->FCR = tmp;
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
sahilmgandhi 18:6a4db94011d3 305 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
sahilmgandhi 18:6a4db94011d3 306 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 /* Clear all interrupt flags */
sahilmgandhi 18:6a4db94011d3 309 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 /* Initialize the error code */
sahilmgandhi 18:6a4db94011d3 312 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 /* Initialize the DMA state */
sahilmgandhi 18:6a4db94011d3 315 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 /**
sahilmgandhi 18:6a4db94011d3 321 * @brief DeInitializes the DMA peripheral
sahilmgandhi 18:6a4db94011d3 322 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 323 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 324 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 325 */
sahilmgandhi 18:6a4db94011d3 326 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 327 {
sahilmgandhi 18:6a4db94011d3 328 DMA_Base_Registers *regs;
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 /* Check the DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 331 if(hdma == NULL)
sahilmgandhi 18:6a4db94011d3 332 {
sahilmgandhi 18:6a4db94011d3 333 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 334 }
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 /* Check the DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 337 if(hdma->State == HAL_DMA_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 338 {
sahilmgandhi 18:6a4db94011d3 339 /* Return error status */
sahilmgandhi 18:6a4db94011d3 340 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 341 }
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 /* Disable the selected DMA Streamx */
sahilmgandhi 18:6a4db94011d3 344 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 /* Reset DMA Streamx control register */
sahilmgandhi 18:6a4db94011d3 347 hdma->Instance->CR = 0U;
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /* Reset DMA Streamx number of data to transfer register */
sahilmgandhi 18:6a4db94011d3 350 hdma->Instance->NDTR = 0U;
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 /* Reset DMA Streamx peripheral address register */
sahilmgandhi 18:6a4db94011d3 353 hdma->Instance->PAR = 0U;
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 /* Reset DMA Streamx memory 0 address register */
sahilmgandhi 18:6a4db94011d3 356 hdma->Instance->M0AR = 0U;
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 /* Reset DMA Streamx memory 1 address register */
sahilmgandhi 18:6a4db94011d3 359 hdma->Instance->M1AR = 0U;
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 /* Reset DMA Streamx FIFO control register */
sahilmgandhi 18:6a4db94011d3 362 hdma->Instance->FCR = (uint32_t)0x00000021U;
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 /* Get DMA steam Base Address */
sahilmgandhi 18:6a4db94011d3 365 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 /* Clear all interrupt flags at correct offset within the register */
sahilmgandhi 18:6a4db94011d3 368 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 /* Initialize the error code */
sahilmgandhi 18:6a4db94011d3 371 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /* Initialize the DMA state */
sahilmgandhi 18:6a4db94011d3 374 hdma->State = HAL_DMA_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 377 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 380 }
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 /**
sahilmgandhi 18:6a4db94011d3 383 * @}
sahilmgandhi 18:6a4db94011d3 384 */
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 /** @addtogroup DMA_Exported_Functions_Group2
sahilmgandhi 18:6a4db94011d3 387 *
sahilmgandhi 18:6a4db94011d3 388 @verbatim
sahilmgandhi 18:6a4db94011d3 389 ===============================================================================
sahilmgandhi 18:6a4db94011d3 390 ##### IO operation functions #####
sahilmgandhi 18:6a4db94011d3 391 ===============================================================================
sahilmgandhi 18:6a4db94011d3 392 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 393 (+) Configure the source, destination address and data length and Start DMA transfer
sahilmgandhi 18:6a4db94011d3 394 (+) Configure the source, destination address and data length and
sahilmgandhi 18:6a4db94011d3 395 Start DMA transfer with interrupt
sahilmgandhi 18:6a4db94011d3 396 (+) Abort DMA transfer
sahilmgandhi 18:6a4db94011d3 397 (+) Poll for transfer complete
sahilmgandhi 18:6a4db94011d3 398 (+) Handle DMA interrupt request
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 @endverbatim
sahilmgandhi 18:6a4db94011d3 401 * @{
sahilmgandhi 18:6a4db94011d3 402 */
sahilmgandhi 18:6a4db94011d3 403
sahilmgandhi 18:6a4db94011d3 404 /**
sahilmgandhi 18:6a4db94011d3 405 * @brief Starts the DMA Transfer.
sahilmgandhi 18:6a4db94011d3 406 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 407 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 408 * @param SrcAddress: The source memory Buffer address
sahilmgandhi 18:6a4db94011d3 409 * @param DstAddress: The destination memory Buffer address
sahilmgandhi 18:6a4db94011d3 410 * @param DataLength: The length of data to be transferred from source to destination
sahilmgandhi 18:6a4db94011d3 411 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 412 */
sahilmgandhi 18:6a4db94011d3 413 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
sahilmgandhi 18:6a4db94011d3 414 {
sahilmgandhi 18:6a4db94011d3 415 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 418 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 /* Process locked */
sahilmgandhi 18:6a4db94011d3 421 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 424 {
sahilmgandhi 18:6a4db94011d3 425 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 426 hdma->State = HAL_DMA_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 /* Initialize the error code */
sahilmgandhi 18:6a4db94011d3 429 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 430
sahilmgandhi 18:6a4db94011d3 431 /* Configure the source, destination address and the data length */
sahilmgandhi 18:6a4db94011d3 432 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 /* Enable the Peripheral */
sahilmgandhi 18:6a4db94011d3 435 __HAL_DMA_ENABLE(hdma);
sahilmgandhi 18:6a4db94011d3 436 }
sahilmgandhi 18:6a4db94011d3 437 else
sahilmgandhi 18:6a4db94011d3 438 {
sahilmgandhi 18:6a4db94011d3 439 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 440 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 /* Return error status */
sahilmgandhi 18:6a4db94011d3 443 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 444 }
sahilmgandhi 18:6a4db94011d3 445 return status;
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /**
sahilmgandhi 18:6a4db94011d3 449 * @brief Starts the DMA Transfer with interrupt enabled.
sahilmgandhi 18:6a4db94011d3 450 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 451 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 452 * @param SrcAddress: The source memory Buffer address
sahilmgandhi 18:6a4db94011d3 453 * @param DstAddress: The destination memory Buffer address
sahilmgandhi 18:6a4db94011d3 454 * @param DataLength: The length of data to be transferred from source to destination
sahilmgandhi 18:6a4db94011d3 455 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 456 */
sahilmgandhi 18:6a4db94011d3 457 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
sahilmgandhi 18:6a4db94011d3 458 {
sahilmgandhi 18:6a4db94011d3 459 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /* calculate DMA base and stream number */
sahilmgandhi 18:6a4db94011d3 462 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 465 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 /* Process locked */
sahilmgandhi 18:6a4db94011d3 468 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 471 {
sahilmgandhi 18:6a4db94011d3 472 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 473 hdma->State = HAL_DMA_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /* Initialize the error code */
sahilmgandhi 18:6a4db94011d3 476 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 /* Configure the source, destination address and the data length */
sahilmgandhi 18:6a4db94011d3 479 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 /* Clear all interrupt flags at correct offset within the register */
sahilmgandhi 18:6a4db94011d3 482 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 /* Enable Common interrupts*/
sahilmgandhi 18:6a4db94011d3 485 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
sahilmgandhi 18:6a4db94011d3 486 hdma->Instance->FCR |= DMA_IT_FE;
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 if(hdma->XferHalfCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 489 {
sahilmgandhi 18:6a4db94011d3 490 hdma->Instance->CR |= DMA_IT_HT;
sahilmgandhi 18:6a4db94011d3 491 }
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 /* Enable the Peripheral */
sahilmgandhi 18:6a4db94011d3 494 __HAL_DMA_ENABLE(hdma);
sahilmgandhi 18:6a4db94011d3 495 }
sahilmgandhi 18:6a4db94011d3 496 else
sahilmgandhi 18:6a4db94011d3 497 {
sahilmgandhi 18:6a4db94011d3 498 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 499 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 /* Return error status */
sahilmgandhi 18:6a4db94011d3 502 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 503 }
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 return status;
sahilmgandhi 18:6a4db94011d3 506 }
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508 /**
sahilmgandhi 18:6a4db94011d3 509 * @brief Aborts the DMA Transfer.
sahilmgandhi 18:6a4db94011d3 510 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 511 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 512 *
sahilmgandhi 18:6a4db94011d3 513 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
sahilmgandhi 18:6a4db94011d3 514 * effectively disabled is added. If a Stream is disabled
sahilmgandhi 18:6a4db94011d3 515 * while a data transfer is ongoing, the current data will be transferred
sahilmgandhi 18:6a4db94011d3 516 * and the Stream will be effectively disabled only after the transfer of
sahilmgandhi 18:6a4db94011d3 517 * this single data is finished.
sahilmgandhi 18:6a4db94011d3 518 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 519 */
sahilmgandhi 18:6a4db94011d3 520 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 521 {
sahilmgandhi 18:6a4db94011d3 522 /* calculate DMA base and stream number */
sahilmgandhi 18:6a4db94011d3 523 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 524
sahilmgandhi 18:6a4db94011d3 525 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527 if(hdma->State != HAL_DMA_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 528 {
sahilmgandhi 18:6a4db94011d3 529 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 532 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 535 }
sahilmgandhi 18:6a4db94011d3 536 else
sahilmgandhi 18:6a4db94011d3 537 {
sahilmgandhi 18:6a4db94011d3 538 /* Disable all the transfer interrupts */
sahilmgandhi 18:6a4db94011d3 539 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
sahilmgandhi 18:6a4db94011d3 540 hdma->Instance->FCR &= ~(DMA_IT_FE);
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
sahilmgandhi 18:6a4db94011d3 543 {
sahilmgandhi 18:6a4db94011d3 544 hdma->Instance->CR &= ~(DMA_IT_HT);
sahilmgandhi 18:6a4db94011d3 545 }
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 /* Disable the stream */
sahilmgandhi 18:6a4db94011d3 548 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 /* Check if the DMA Stream is effectively disabled */
sahilmgandhi 18:6a4db94011d3 551 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
sahilmgandhi 18:6a4db94011d3 552 {
sahilmgandhi 18:6a4db94011d3 553 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 554 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
sahilmgandhi 18:6a4db94011d3 555 {
sahilmgandhi 18:6a4db94011d3 556 /* Update error code */
sahilmgandhi 18:6a4db94011d3 557 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 560 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 563 hdma->State = HAL_DMA_STATE_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 566 }
sahilmgandhi 18:6a4db94011d3 567 }
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 /* Clear all interrupt flags at correct offset within the register */
sahilmgandhi 18:6a4db94011d3 570 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 573 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 /* Change the DMA state*/
sahilmgandhi 18:6a4db94011d3 576 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 577 }
sahilmgandhi 18:6a4db94011d3 578 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 579 }
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 /**
sahilmgandhi 18:6a4db94011d3 582 * @brief Aborts the DMA Transfer in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 583 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 584 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 585 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 586 */
sahilmgandhi 18:6a4db94011d3 587 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 588 {
sahilmgandhi 18:6a4db94011d3 589 if(hdma->State != HAL_DMA_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 590 {
sahilmgandhi 18:6a4db94011d3 591 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
sahilmgandhi 18:6a4db94011d3 592 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 593 }
sahilmgandhi 18:6a4db94011d3 594 else
sahilmgandhi 18:6a4db94011d3 595 {
sahilmgandhi 18:6a4db94011d3 596 /* Set Abort State */
sahilmgandhi 18:6a4db94011d3 597 hdma->State = HAL_DMA_STATE_ABORT;
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 /* Disable the stream */
sahilmgandhi 18:6a4db94011d3 600 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 601 }
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 604 }
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 /**
sahilmgandhi 18:6a4db94011d3 607 * @brief Polling for transfer complete.
sahilmgandhi 18:6a4db94011d3 608 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 609 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 610 * @param CompleteLevel: Specifies the DMA level complete.
sahilmgandhi 18:6a4db94011d3 611 * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
sahilmgandhi 18:6a4db94011d3 612 * This model could be used for debug purpose.
sahilmgandhi 18:6a4db94011d3 613 * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
sahilmgandhi 18:6a4db94011d3 614 * @param Timeout: Timeout duration.
sahilmgandhi 18:6a4db94011d3 615 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 616 */
sahilmgandhi 18:6a4db94011d3 617 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 618 {
sahilmgandhi 18:6a4db94011d3 619 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 620 uint32_t mask_cpltlevel;
sahilmgandhi 18:6a4db94011d3 621 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 622 uint32_t tmpisr;
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 /* calculate DMA base and stream number */
sahilmgandhi 18:6a4db94011d3 625 DMA_Base_Registers *regs;
sahilmgandhi 18:6a4db94011d3 626
sahilmgandhi 18:6a4db94011d3 627 if(HAL_DMA_STATE_BUSY != hdma->State)
sahilmgandhi 18:6a4db94011d3 628 {
sahilmgandhi 18:6a4db94011d3 629 /* No transfer ongoing */
sahilmgandhi 18:6a4db94011d3 630 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
sahilmgandhi 18:6a4db94011d3 631 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 632 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 633 }
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 /* Polling mode not supported in circular mode and double buffering mode */
sahilmgandhi 18:6a4db94011d3 636 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
sahilmgandhi 18:6a4db94011d3 637 {
sahilmgandhi 18:6a4db94011d3 638 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
sahilmgandhi 18:6a4db94011d3 639 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 640 }
sahilmgandhi 18:6a4db94011d3 641
sahilmgandhi 18:6a4db94011d3 642 /* Get the level transfer complete flag */
sahilmgandhi 18:6a4db94011d3 643 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
sahilmgandhi 18:6a4db94011d3 644 {
sahilmgandhi 18:6a4db94011d3 645 /* Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 646 mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 647 }
sahilmgandhi 18:6a4db94011d3 648 else
sahilmgandhi 18:6a4db94011d3 649 {
sahilmgandhi 18:6a4db94011d3 650 /* Half Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 651 mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 652 }
sahilmgandhi 18:6a4db94011d3 653
sahilmgandhi 18:6a4db94011d3 654 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 655 tmpisr = regs->ISR;
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657 while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
sahilmgandhi 18:6a4db94011d3 658 {
sahilmgandhi 18:6a4db94011d3 659 /* Check for the Timeout (Not applicable in circular mode)*/
sahilmgandhi 18:6a4db94011d3 660 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 661 {
sahilmgandhi 18:6a4db94011d3 662 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 663 {
sahilmgandhi 18:6a4db94011d3 664 /* Update error code */
sahilmgandhi 18:6a4db94011d3 665 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 668 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 671 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 674 }
sahilmgandhi 18:6a4db94011d3 675 }
sahilmgandhi 18:6a4db94011d3 676
sahilmgandhi 18:6a4db94011d3 677 /* Get the ISR register value */
sahilmgandhi 18:6a4db94011d3 678 tmpisr = regs->ISR;
sahilmgandhi 18:6a4db94011d3 679
sahilmgandhi 18:6a4db94011d3 680 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 681 {
sahilmgandhi 18:6a4db94011d3 682 /* Update error code */
sahilmgandhi 18:6a4db94011d3 683 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 /* Clear the transfer error flag */
sahilmgandhi 18:6a4db94011d3 686 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 687 }
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 690 {
sahilmgandhi 18:6a4db94011d3 691 /* Update error code */
sahilmgandhi 18:6a4db94011d3 692 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
sahilmgandhi 18:6a4db94011d3 693
sahilmgandhi 18:6a4db94011d3 694 /* Clear the FIFO error flag */
sahilmgandhi 18:6a4db94011d3 695 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 696 }
sahilmgandhi 18:6a4db94011d3 697
sahilmgandhi 18:6a4db94011d3 698 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 699 {
sahilmgandhi 18:6a4db94011d3 700 /* Update error code */
sahilmgandhi 18:6a4db94011d3 701 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 /* Clear the Direct Mode error flag */
sahilmgandhi 18:6a4db94011d3 704 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 705 }
sahilmgandhi 18:6a4db94011d3 706 }
sahilmgandhi 18:6a4db94011d3 707
sahilmgandhi 18:6a4db94011d3 708 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 709 {
sahilmgandhi 18:6a4db94011d3 710 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
sahilmgandhi 18:6a4db94011d3 711 {
sahilmgandhi 18:6a4db94011d3 712 HAL_DMA_Abort(hdma);
sahilmgandhi 18:6a4db94011d3 713
sahilmgandhi 18:6a4db94011d3 714 /* Clear the half transfer and transfer complete flags */
sahilmgandhi 18:6a4db94011d3 715 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 718 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 721 hdma->State= HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 722
sahilmgandhi 18:6a4db94011d3 723 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 724 }
sahilmgandhi 18:6a4db94011d3 725 }
sahilmgandhi 18:6a4db94011d3 726
sahilmgandhi 18:6a4db94011d3 727 /* Get the level transfer complete flag */
sahilmgandhi 18:6a4db94011d3 728 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
sahilmgandhi 18:6a4db94011d3 729 {
sahilmgandhi 18:6a4db94011d3 730 /* Clear the half transfer and transfer complete flags */
sahilmgandhi 18:6a4db94011d3 731 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 732
sahilmgandhi 18:6a4db94011d3 733 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 734 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 735
sahilmgandhi 18:6a4db94011d3 736 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 737 }
sahilmgandhi 18:6a4db94011d3 738 else
sahilmgandhi 18:6a4db94011d3 739 {
sahilmgandhi 18:6a4db94011d3 740 /* Clear the half transfer and transfer complete flags */
sahilmgandhi 18:6a4db94011d3 741 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 742 }
sahilmgandhi 18:6a4db94011d3 743
sahilmgandhi 18:6a4db94011d3 744 return status;
sahilmgandhi 18:6a4db94011d3 745 }
sahilmgandhi 18:6a4db94011d3 746
sahilmgandhi 18:6a4db94011d3 747 /**
sahilmgandhi 18:6a4db94011d3 748 * @brief Handles DMA interrupt request.
sahilmgandhi 18:6a4db94011d3 749 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 750 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 751 * @retval None
sahilmgandhi 18:6a4db94011d3 752 */
sahilmgandhi 18:6a4db94011d3 753 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 754 {
sahilmgandhi 18:6a4db94011d3 755 uint32_t tmpisr;
sahilmgandhi 18:6a4db94011d3 756 __IO uint32_t count = 0;
sahilmgandhi 18:6a4db94011d3 757 uint32_t timeout = SystemCoreClock / 9600;
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 /* calculate DMA base and stream number */
sahilmgandhi 18:6a4db94011d3 760 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 761
sahilmgandhi 18:6a4db94011d3 762 tmpisr = regs->ISR;
sahilmgandhi 18:6a4db94011d3 763
sahilmgandhi 18:6a4db94011d3 764 /* Transfer Error Interrupt management ***************************************/
sahilmgandhi 18:6a4db94011d3 765 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 766 {
sahilmgandhi 18:6a4db94011d3 767 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
sahilmgandhi 18:6a4db94011d3 768 {
sahilmgandhi 18:6a4db94011d3 769 /* Disable the transfer error interrupt */
sahilmgandhi 18:6a4db94011d3 770 hdma->Instance->CR &= ~(DMA_IT_TE);
sahilmgandhi 18:6a4db94011d3 771
sahilmgandhi 18:6a4db94011d3 772 /* Clear the transfer error flag */
sahilmgandhi 18:6a4db94011d3 773 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 774
sahilmgandhi 18:6a4db94011d3 775 /* Update error code */
sahilmgandhi 18:6a4db94011d3 776 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
sahilmgandhi 18:6a4db94011d3 777 }
sahilmgandhi 18:6a4db94011d3 778 }
sahilmgandhi 18:6a4db94011d3 779 /* FIFO Error Interrupt management ******************************************/
sahilmgandhi 18:6a4db94011d3 780 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 781 {
sahilmgandhi 18:6a4db94011d3 782 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
sahilmgandhi 18:6a4db94011d3 783 {
sahilmgandhi 18:6a4db94011d3 784 /* Clear the FIFO error flag */
sahilmgandhi 18:6a4db94011d3 785 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 786
sahilmgandhi 18:6a4db94011d3 787 /* Update error code */
sahilmgandhi 18:6a4db94011d3 788 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
sahilmgandhi 18:6a4db94011d3 789 }
sahilmgandhi 18:6a4db94011d3 790 }
sahilmgandhi 18:6a4db94011d3 791 /* Direct Mode Error Interrupt management ***********************************/
sahilmgandhi 18:6a4db94011d3 792 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 793 {
sahilmgandhi 18:6a4db94011d3 794 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
sahilmgandhi 18:6a4db94011d3 795 {
sahilmgandhi 18:6a4db94011d3 796 /* Clear the direct mode error flag */
sahilmgandhi 18:6a4db94011d3 797 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 /* Update error code */
sahilmgandhi 18:6a4db94011d3 800 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
sahilmgandhi 18:6a4db94011d3 801 }
sahilmgandhi 18:6a4db94011d3 802 }
sahilmgandhi 18:6a4db94011d3 803 /* Half Transfer Complete Interrupt management ******************************/
sahilmgandhi 18:6a4db94011d3 804 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 805 {
sahilmgandhi 18:6a4db94011d3 806 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
sahilmgandhi 18:6a4db94011d3 807 {
sahilmgandhi 18:6a4db94011d3 808 /* Clear the half transfer complete flag */
sahilmgandhi 18:6a4db94011d3 809 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 810
sahilmgandhi 18:6a4db94011d3 811 /* Multi_Buffering mode enabled */
sahilmgandhi 18:6a4db94011d3 812 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
sahilmgandhi 18:6a4db94011d3 813 {
sahilmgandhi 18:6a4db94011d3 814 /* Current memory buffer used is Memory 0 */
sahilmgandhi 18:6a4db94011d3 815 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
sahilmgandhi 18:6a4db94011d3 816 {
sahilmgandhi 18:6a4db94011d3 817 if(hdma->XferHalfCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 818 {
sahilmgandhi 18:6a4db94011d3 819 /* Half transfer callback */
sahilmgandhi 18:6a4db94011d3 820 hdma->XferHalfCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 821 }
sahilmgandhi 18:6a4db94011d3 822 }
sahilmgandhi 18:6a4db94011d3 823 /* Current memory buffer used is Memory 1 */
sahilmgandhi 18:6a4db94011d3 824 else
sahilmgandhi 18:6a4db94011d3 825 {
sahilmgandhi 18:6a4db94011d3 826 if(hdma->XferM1HalfCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 827 {
sahilmgandhi 18:6a4db94011d3 828 /* Half transfer callback */
sahilmgandhi 18:6a4db94011d3 829 hdma->XferM1HalfCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 830 }
sahilmgandhi 18:6a4db94011d3 831 }
sahilmgandhi 18:6a4db94011d3 832 }
sahilmgandhi 18:6a4db94011d3 833 else
sahilmgandhi 18:6a4db94011d3 834 {
sahilmgandhi 18:6a4db94011d3 835 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
sahilmgandhi 18:6a4db94011d3 836 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
sahilmgandhi 18:6a4db94011d3 837 {
sahilmgandhi 18:6a4db94011d3 838 /* Disable the half transfer interrupt */
sahilmgandhi 18:6a4db94011d3 839 hdma->Instance->CR &= ~(DMA_IT_HT);
sahilmgandhi 18:6a4db94011d3 840 }
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 if(hdma->XferHalfCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 843 {
sahilmgandhi 18:6a4db94011d3 844 /* Half transfer callback */
sahilmgandhi 18:6a4db94011d3 845 hdma->XferHalfCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 846 }
sahilmgandhi 18:6a4db94011d3 847 }
sahilmgandhi 18:6a4db94011d3 848 }
sahilmgandhi 18:6a4db94011d3 849 }
sahilmgandhi 18:6a4db94011d3 850 /* Transfer Complete Interrupt management ***********************************/
sahilmgandhi 18:6a4db94011d3 851 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
sahilmgandhi 18:6a4db94011d3 852 {
sahilmgandhi 18:6a4db94011d3 853 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
sahilmgandhi 18:6a4db94011d3 854 {
sahilmgandhi 18:6a4db94011d3 855 /* Clear the transfer complete flag */
sahilmgandhi 18:6a4db94011d3 856 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 if(HAL_DMA_STATE_ABORT == hdma->State)
sahilmgandhi 18:6a4db94011d3 859 {
sahilmgandhi 18:6a4db94011d3 860 /* Disable all the transfer interrupts */
sahilmgandhi 18:6a4db94011d3 861 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
sahilmgandhi 18:6a4db94011d3 862 hdma->Instance->FCR &= ~(DMA_IT_FE);
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
sahilmgandhi 18:6a4db94011d3 865 {
sahilmgandhi 18:6a4db94011d3 866 hdma->Instance->CR &= ~(DMA_IT_HT);
sahilmgandhi 18:6a4db94011d3 867 }
sahilmgandhi 18:6a4db94011d3 868
sahilmgandhi 18:6a4db94011d3 869 /* Clear all interrupt flags at correct offset within the register */
sahilmgandhi 18:6a4db94011d3 870 regs->IFCR = 0x3FU << hdma->StreamIndex;
sahilmgandhi 18:6a4db94011d3 871
sahilmgandhi 18:6a4db94011d3 872 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 873 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 874
sahilmgandhi 18:6a4db94011d3 875 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 876 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 877
sahilmgandhi 18:6a4db94011d3 878 if(hdma->XferAbortCallback != NULL)
sahilmgandhi 18:6a4db94011d3 879 {
sahilmgandhi 18:6a4db94011d3 880 hdma->XferAbortCallback(hdma);
sahilmgandhi 18:6a4db94011d3 881 }
sahilmgandhi 18:6a4db94011d3 882 return;
sahilmgandhi 18:6a4db94011d3 883 }
sahilmgandhi 18:6a4db94011d3 884
sahilmgandhi 18:6a4db94011d3 885 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
sahilmgandhi 18:6a4db94011d3 886 {
sahilmgandhi 18:6a4db94011d3 887 /* Current memory buffer used is Memory 0 */
sahilmgandhi 18:6a4db94011d3 888 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
sahilmgandhi 18:6a4db94011d3 889 {
sahilmgandhi 18:6a4db94011d3 890 if(hdma->XferM1CpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 891 {
sahilmgandhi 18:6a4db94011d3 892 /* Transfer complete Callback for memory1 */
sahilmgandhi 18:6a4db94011d3 893 hdma->XferM1CpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 894 }
sahilmgandhi 18:6a4db94011d3 895 }
sahilmgandhi 18:6a4db94011d3 896 /* Current memory buffer used is Memory 1 */
sahilmgandhi 18:6a4db94011d3 897 else
sahilmgandhi 18:6a4db94011d3 898 {
sahilmgandhi 18:6a4db94011d3 899 if(hdma->XferCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 900 {
sahilmgandhi 18:6a4db94011d3 901 /* Transfer complete Callback for memory0 */
sahilmgandhi 18:6a4db94011d3 902 hdma->XferCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 903 }
sahilmgandhi 18:6a4db94011d3 904 }
sahilmgandhi 18:6a4db94011d3 905 }
sahilmgandhi 18:6a4db94011d3 906 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
sahilmgandhi 18:6a4db94011d3 907 else
sahilmgandhi 18:6a4db94011d3 908 {
sahilmgandhi 18:6a4db94011d3 909 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
sahilmgandhi 18:6a4db94011d3 910 {
sahilmgandhi 18:6a4db94011d3 911 /* Disable the transfer complete interrupt */
sahilmgandhi 18:6a4db94011d3 912 hdma->Instance->CR &= ~(DMA_IT_TC);
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 915 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 918 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 919 }
sahilmgandhi 18:6a4db94011d3 920
sahilmgandhi 18:6a4db94011d3 921 if(hdma->XferCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 922 {
sahilmgandhi 18:6a4db94011d3 923 /* Transfer complete callback */
sahilmgandhi 18:6a4db94011d3 924 hdma->XferCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 925 }
sahilmgandhi 18:6a4db94011d3 926 }
sahilmgandhi 18:6a4db94011d3 927 }
sahilmgandhi 18:6a4db94011d3 928 }
sahilmgandhi 18:6a4db94011d3 929
sahilmgandhi 18:6a4db94011d3 930 /* manage error case */
sahilmgandhi 18:6a4db94011d3 931 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 932 {
sahilmgandhi 18:6a4db94011d3 933 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
sahilmgandhi 18:6a4db94011d3 934 {
sahilmgandhi 18:6a4db94011d3 935 hdma->State = HAL_DMA_STATE_ABORT;
sahilmgandhi 18:6a4db94011d3 936
sahilmgandhi 18:6a4db94011d3 937 /* Disable the stream */
sahilmgandhi 18:6a4db94011d3 938 __HAL_DMA_DISABLE(hdma);
sahilmgandhi 18:6a4db94011d3 939
sahilmgandhi 18:6a4db94011d3 940 do
sahilmgandhi 18:6a4db94011d3 941 {
sahilmgandhi 18:6a4db94011d3 942 if (++count > timeout)
sahilmgandhi 18:6a4db94011d3 943 {
sahilmgandhi 18:6a4db94011d3 944 break;
sahilmgandhi 18:6a4db94011d3 945 }
sahilmgandhi 18:6a4db94011d3 946 }
sahilmgandhi 18:6a4db94011d3 947 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
sahilmgandhi 18:6a4db94011d3 948
sahilmgandhi 18:6a4db94011d3 949 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 950 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 951
sahilmgandhi 18:6a4db94011d3 952 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 953 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 954 }
sahilmgandhi 18:6a4db94011d3 955
sahilmgandhi 18:6a4db94011d3 956 if(hdma->XferErrorCallback != NULL)
sahilmgandhi 18:6a4db94011d3 957 {
sahilmgandhi 18:6a4db94011d3 958 /* Transfer error callback */
sahilmgandhi 18:6a4db94011d3 959 hdma->XferErrorCallback(hdma);
sahilmgandhi 18:6a4db94011d3 960 }
sahilmgandhi 18:6a4db94011d3 961 }
sahilmgandhi 18:6a4db94011d3 962 }
sahilmgandhi 18:6a4db94011d3 963
sahilmgandhi 18:6a4db94011d3 964 /**
sahilmgandhi 18:6a4db94011d3 965 * @brief Register callbacks
sahilmgandhi 18:6a4db94011d3 966 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 967 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 968 * @param CallbackID: User Callback identifer
sahilmgandhi 18:6a4db94011d3 969 * a DMA_HandleTypeDef structure as parameter.
sahilmgandhi 18:6a4db94011d3 970 * @param pCallback: pointer to private callbacsk function which has pointer to
sahilmgandhi 18:6a4db94011d3 971 * a DMA_HandleTypeDef structure as parameter.
sahilmgandhi 18:6a4db94011d3 972 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 973 */
sahilmgandhi 18:6a4db94011d3 974 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
sahilmgandhi 18:6a4db94011d3 975 {
sahilmgandhi 18:6a4db94011d3 976
sahilmgandhi 18:6a4db94011d3 977 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 978
sahilmgandhi 18:6a4db94011d3 979 /* Process locked */
sahilmgandhi 18:6a4db94011d3 980 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 981
sahilmgandhi 18:6a4db94011d3 982 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 983 {
sahilmgandhi 18:6a4db94011d3 984 switch (CallbackID)
sahilmgandhi 18:6a4db94011d3 985 {
sahilmgandhi 18:6a4db94011d3 986 case HAL_DMA_XFER_CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 987 hdma->XferCpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 988 break;
sahilmgandhi 18:6a4db94011d3 989
sahilmgandhi 18:6a4db94011d3 990 case HAL_DMA_XFER_HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 991 hdma->XferHalfCpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 992 break;
sahilmgandhi 18:6a4db94011d3 993
sahilmgandhi 18:6a4db94011d3 994 case HAL_DMA_XFER_M1CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 995 hdma->XferM1CpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 996 break;
sahilmgandhi 18:6a4db94011d3 997
sahilmgandhi 18:6a4db94011d3 998 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 999 hdma->XferM1HalfCpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 1000 break;
sahilmgandhi 18:6a4db94011d3 1001
sahilmgandhi 18:6a4db94011d3 1002 case HAL_DMA_XFER_ERROR_CB_ID:
sahilmgandhi 18:6a4db94011d3 1003 hdma->XferErrorCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 1004 break;
sahilmgandhi 18:6a4db94011d3 1005
sahilmgandhi 18:6a4db94011d3 1006 case HAL_DMA_XFER_ABORT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1007 hdma->XferAbortCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 1008 break;
sahilmgandhi 18:6a4db94011d3 1009
sahilmgandhi 18:6a4db94011d3 1010 default:
sahilmgandhi 18:6a4db94011d3 1011 break;
sahilmgandhi 18:6a4db94011d3 1012 }
sahilmgandhi 18:6a4db94011d3 1013 }
sahilmgandhi 18:6a4db94011d3 1014 else
sahilmgandhi 18:6a4db94011d3 1015 {
sahilmgandhi 18:6a4db94011d3 1016 /* Return error status */
sahilmgandhi 18:6a4db94011d3 1017 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1018 }
sahilmgandhi 18:6a4db94011d3 1019
sahilmgandhi 18:6a4db94011d3 1020 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 1021 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 1022
sahilmgandhi 18:6a4db94011d3 1023 return status;
sahilmgandhi 18:6a4db94011d3 1024 }
sahilmgandhi 18:6a4db94011d3 1025
sahilmgandhi 18:6a4db94011d3 1026 /**
sahilmgandhi 18:6a4db94011d3 1027 * @brief UnRegister callbacks
sahilmgandhi 18:6a4db94011d3 1028 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1029 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1030 * @param CallbackID: User Callback identifer
sahilmgandhi 18:6a4db94011d3 1031 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
sahilmgandhi 18:6a4db94011d3 1032 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1033 */
sahilmgandhi 18:6a4db94011d3 1034 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
sahilmgandhi 18:6a4db94011d3 1035 {
sahilmgandhi 18:6a4db94011d3 1036 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1037
sahilmgandhi 18:6a4db94011d3 1038 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1039 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 1042 {
sahilmgandhi 18:6a4db94011d3 1043 switch (CallbackID)
sahilmgandhi 18:6a4db94011d3 1044 {
sahilmgandhi 18:6a4db94011d3 1045 case HAL_DMA_XFER_CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1046 hdma->XferCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1047 break;
sahilmgandhi 18:6a4db94011d3 1048
sahilmgandhi 18:6a4db94011d3 1049 case HAL_DMA_XFER_HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1050 hdma->XferHalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1051 break;
sahilmgandhi 18:6a4db94011d3 1052
sahilmgandhi 18:6a4db94011d3 1053 case HAL_DMA_XFER_M1CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1054 hdma->XferM1CpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1055 break;
sahilmgandhi 18:6a4db94011d3 1056
sahilmgandhi 18:6a4db94011d3 1057 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1058 hdma->XferM1HalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1059 break;
sahilmgandhi 18:6a4db94011d3 1060
sahilmgandhi 18:6a4db94011d3 1061 case HAL_DMA_XFER_ERROR_CB_ID:
sahilmgandhi 18:6a4db94011d3 1062 hdma->XferErrorCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1063 break;
sahilmgandhi 18:6a4db94011d3 1064
sahilmgandhi 18:6a4db94011d3 1065 case HAL_DMA_XFER_ABORT_CB_ID:
sahilmgandhi 18:6a4db94011d3 1066 hdma->XferAbortCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1067 break;
sahilmgandhi 18:6a4db94011d3 1068
sahilmgandhi 18:6a4db94011d3 1069 case HAL_DMA_XFER_ALL_CB_ID:
sahilmgandhi 18:6a4db94011d3 1070 hdma->XferCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1071 hdma->XferHalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1072 hdma->XferM1CpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1073 hdma->XferM1HalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1074 hdma->XferErrorCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1075 hdma->XferAbortCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1076 break;
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 default:
sahilmgandhi 18:6a4db94011d3 1079 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1080 break;
sahilmgandhi 18:6a4db94011d3 1081 }
sahilmgandhi 18:6a4db94011d3 1082 }
sahilmgandhi 18:6a4db94011d3 1083 else
sahilmgandhi 18:6a4db94011d3 1084 {
sahilmgandhi 18:6a4db94011d3 1085 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1086 }
sahilmgandhi 18:6a4db94011d3 1087
sahilmgandhi 18:6a4db94011d3 1088 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 1089 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 1090
sahilmgandhi 18:6a4db94011d3 1091 return status;
sahilmgandhi 18:6a4db94011d3 1092 }
sahilmgandhi 18:6a4db94011d3 1093
sahilmgandhi 18:6a4db94011d3 1094 /**
sahilmgandhi 18:6a4db94011d3 1095 * @}
sahilmgandhi 18:6a4db94011d3 1096 */
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 /** @addtogroup DMA_Exported_Functions_Group3
sahilmgandhi 18:6a4db94011d3 1099 *
sahilmgandhi 18:6a4db94011d3 1100 @verbatim
sahilmgandhi 18:6a4db94011d3 1101 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1102 ##### State and Errors functions #####
sahilmgandhi 18:6a4db94011d3 1103 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1104 [..]
sahilmgandhi 18:6a4db94011d3 1105 This subsection provides functions allowing to
sahilmgandhi 18:6a4db94011d3 1106 (+) Check the DMA state
sahilmgandhi 18:6a4db94011d3 1107 (+) Get error code
sahilmgandhi 18:6a4db94011d3 1108
sahilmgandhi 18:6a4db94011d3 1109 @endverbatim
sahilmgandhi 18:6a4db94011d3 1110 * @{
sahilmgandhi 18:6a4db94011d3 1111 */
sahilmgandhi 18:6a4db94011d3 1112
sahilmgandhi 18:6a4db94011d3 1113 /**
sahilmgandhi 18:6a4db94011d3 1114 * @brief Returns the DMA state.
sahilmgandhi 18:6a4db94011d3 1115 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1116 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1117 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1118 */
sahilmgandhi 18:6a4db94011d3 1119 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1120 {
sahilmgandhi 18:6a4db94011d3 1121 return hdma->State;
sahilmgandhi 18:6a4db94011d3 1122 }
sahilmgandhi 18:6a4db94011d3 1123
sahilmgandhi 18:6a4db94011d3 1124 /**
sahilmgandhi 18:6a4db94011d3 1125 * @brief Return the DMA error code
sahilmgandhi 18:6a4db94011d3 1126 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1127 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1128 * @retval DMA Error Code
sahilmgandhi 18:6a4db94011d3 1129 */
sahilmgandhi 18:6a4db94011d3 1130 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1131 {
sahilmgandhi 18:6a4db94011d3 1132 return hdma->ErrorCode;
sahilmgandhi 18:6a4db94011d3 1133 }
sahilmgandhi 18:6a4db94011d3 1134
sahilmgandhi 18:6a4db94011d3 1135 /**
sahilmgandhi 18:6a4db94011d3 1136 * @}
sahilmgandhi 18:6a4db94011d3 1137 */
sahilmgandhi 18:6a4db94011d3 1138
sahilmgandhi 18:6a4db94011d3 1139 /**
sahilmgandhi 18:6a4db94011d3 1140 * @}
sahilmgandhi 18:6a4db94011d3 1141 */
sahilmgandhi 18:6a4db94011d3 1142
sahilmgandhi 18:6a4db94011d3 1143 /** @addtogroup DMA_Private_Functions
sahilmgandhi 18:6a4db94011d3 1144 * @{
sahilmgandhi 18:6a4db94011d3 1145 */
sahilmgandhi 18:6a4db94011d3 1146
sahilmgandhi 18:6a4db94011d3 1147 /**
sahilmgandhi 18:6a4db94011d3 1148 * @brief Sets the DMA Transfer parameter.
sahilmgandhi 18:6a4db94011d3 1149 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1150 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1151 * @param SrcAddress: The source memory Buffer address
sahilmgandhi 18:6a4db94011d3 1152 * @param DstAddress: The destination memory Buffer address
sahilmgandhi 18:6a4db94011d3 1153 * @param DataLength: The length of data to be transferred from source to destination
sahilmgandhi 18:6a4db94011d3 1154 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1155 */
sahilmgandhi 18:6a4db94011d3 1156 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
sahilmgandhi 18:6a4db94011d3 1157 {
sahilmgandhi 18:6a4db94011d3 1158 /* Clear DBM bit */
sahilmgandhi 18:6a4db94011d3 1159 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
sahilmgandhi 18:6a4db94011d3 1160
sahilmgandhi 18:6a4db94011d3 1161 /* Configure DMA Stream data length */
sahilmgandhi 18:6a4db94011d3 1162 hdma->Instance->NDTR = DataLength;
sahilmgandhi 18:6a4db94011d3 1163
sahilmgandhi 18:6a4db94011d3 1164 /* Peripheral to Memory */
sahilmgandhi 18:6a4db94011d3 1165 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
sahilmgandhi 18:6a4db94011d3 1166 {
sahilmgandhi 18:6a4db94011d3 1167 /* Configure DMA Stream destination address */
sahilmgandhi 18:6a4db94011d3 1168 hdma->Instance->PAR = DstAddress;
sahilmgandhi 18:6a4db94011d3 1169
sahilmgandhi 18:6a4db94011d3 1170 /* Configure DMA Stream source address */
sahilmgandhi 18:6a4db94011d3 1171 hdma->Instance->M0AR = SrcAddress;
sahilmgandhi 18:6a4db94011d3 1172 }
sahilmgandhi 18:6a4db94011d3 1173 /* Memory to Peripheral */
sahilmgandhi 18:6a4db94011d3 1174 else
sahilmgandhi 18:6a4db94011d3 1175 {
sahilmgandhi 18:6a4db94011d3 1176 /* Configure DMA Stream source address */
sahilmgandhi 18:6a4db94011d3 1177 hdma->Instance->PAR = SrcAddress;
sahilmgandhi 18:6a4db94011d3 1178
sahilmgandhi 18:6a4db94011d3 1179 /* Configure DMA Stream destination address */
sahilmgandhi 18:6a4db94011d3 1180 hdma->Instance->M0AR = DstAddress;
sahilmgandhi 18:6a4db94011d3 1181 }
sahilmgandhi 18:6a4db94011d3 1182 }
sahilmgandhi 18:6a4db94011d3 1183
sahilmgandhi 18:6a4db94011d3 1184 /**
sahilmgandhi 18:6a4db94011d3 1185 * @brief Returns the DMA Stream base address depending on stream number
sahilmgandhi 18:6a4db94011d3 1186 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1187 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1188 * @retval Stream base address
sahilmgandhi 18:6a4db94011d3 1189 */
sahilmgandhi 18:6a4db94011d3 1190 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1191 {
sahilmgandhi 18:6a4db94011d3 1192 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
sahilmgandhi 18:6a4db94011d3 1193
sahilmgandhi 18:6a4db94011d3 1194 /* lookup table for necessary bitshift of flags within status registers */
sahilmgandhi 18:6a4db94011d3 1195 static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
sahilmgandhi 18:6a4db94011d3 1196 hdma->StreamIndex = flagBitshiftOffset[stream_number];
sahilmgandhi 18:6a4db94011d3 1197
sahilmgandhi 18:6a4db94011d3 1198 if (stream_number > 3U)
sahilmgandhi 18:6a4db94011d3 1199 {
sahilmgandhi 18:6a4db94011d3 1200 /* return pointer to HISR and HIFCR */
sahilmgandhi 18:6a4db94011d3 1201 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
sahilmgandhi 18:6a4db94011d3 1202 }
sahilmgandhi 18:6a4db94011d3 1203 else
sahilmgandhi 18:6a4db94011d3 1204 {
sahilmgandhi 18:6a4db94011d3 1205 /* return pointer to LISR and LIFCR */
sahilmgandhi 18:6a4db94011d3 1206 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
sahilmgandhi 18:6a4db94011d3 1207 }
sahilmgandhi 18:6a4db94011d3 1208
sahilmgandhi 18:6a4db94011d3 1209 return hdma->StreamBaseAddress;
sahilmgandhi 18:6a4db94011d3 1210 }
sahilmgandhi 18:6a4db94011d3 1211
sahilmgandhi 18:6a4db94011d3 1212 /**
sahilmgandhi 18:6a4db94011d3 1213 * @brief Checks compatibility between FIFO threshold level and size of the memory burst
sahilmgandhi 18:6a4db94011d3 1214 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1215 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 1216 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1217 */
sahilmgandhi 18:6a4db94011d3 1218 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1219 {
sahilmgandhi 18:6a4db94011d3 1220 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1221 uint32_t tmp = hdma->Init.FIFOThreshold;
sahilmgandhi 18:6a4db94011d3 1222
sahilmgandhi 18:6a4db94011d3 1223 /* Memory Data size equal to Byte */
sahilmgandhi 18:6a4db94011d3 1224 if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
sahilmgandhi 18:6a4db94011d3 1225 {
sahilmgandhi 18:6a4db94011d3 1226 switch (tmp)
sahilmgandhi 18:6a4db94011d3 1227 {
sahilmgandhi 18:6a4db94011d3 1228 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
sahilmgandhi 18:6a4db94011d3 1229 if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
sahilmgandhi 18:6a4db94011d3 1230 {
sahilmgandhi 18:6a4db94011d3 1231 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1232 }
sahilmgandhi 18:6a4db94011d3 1233 break;
sahilmgandhi 18:6a4db94011d3 1234 case DMA_FIFO_THRESHOLD_HALFFULL:
sahilmgandhi 18:6a4db94011d3 1235 if(hdma->Init.MemBurst == DMA_MBURST_INC16)
sahilmgandhi 18:6a4db94011d3 1236 {
sahilmgandhi 18:6a4db94011d3 1237 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1238 }
sahilmgandhi 18:6a4db94011d3 1239 break;
sahilmgandhi 18:6a4db94011d3 1240 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
sahilmgandhi 18:6a4db94011d3 1241 if((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
sahilmgandhi 18:6a4db94011d3 1242 {
sahilmgandhi 18:6a4db94011d3 1243 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1244 }
sahilmgandhi 18:6a4db94011d3 1245 break;
sahilmgandhi 18:6a4db94011d3 1246 case DMA_FIFO_THRESHOLD_FULL:
sahilmgandhi 18:6a4db94011d3 1247 break;
sahilmgandhi 18:6a4db94011d3 1248 default:
sahilmgandhi 18:6a4db94011d3 1249 break;
sahilmgandhi 18:6a4db94011d3 1250 }
sahilmgandhi 18:6a4db94011d3 1251 }
sahilmgandhi 18:6a4db94011d3 1252
sahilmgandhi 18:6a4db94011d3 1253 /* Memory Data size equal to Half-Word */
sahilmgandhi 18:6a4db94011d3 1254 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
sahilmgandhi 18:6a4db94011d3 1255 {
sahilmgandhi 18:6a4db94011d3 1256 switch (tmp)
sahilmgandhi 18:6a4db94011d3 1257 {
sahilmgandhi 18:6a4db94011d3 1258 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
sahilmgandhi 18:6a4db94011d3 1259 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1260 break;
sahilmgandhi 18:6a4db94011d3 1261 case DMA_FIFO_THRESHOLD_HALFFULL:
sahilmgandhi 18:6a4db94011d3 1262 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
sahilmgandhi 18:6a4db94011d3 1263 {
sahilmgandhi 18:6a4db94011d3 1264 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1265 }
sahilmgandhi 18:6a4db94011d3 1266 break;
sahilmgandhi 18:6a4db94011d3 1267 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
sahilmgandhi 18:6a4db94011d3 1268 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1269 break;
sahilmgandhi 18:6a4db94011d3 1270 case DMA_FIFO_THRESHOLD_FULL:
sahilmgandhi 18:6a4db94011d3 1271 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
sahilmgandhi 18:6a4db94011d3 1272 {
sahilmgandhi 18:6a4db94011d3 1273 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1274 }
sahilmgandhi 18:6a4db94011d3 1275 break;
sahilmgandhi 18:6a4db94011d3 1276 default:
sahilmgandhi 18:6a4db94011d3 1277 break;
sahilmgandhi 18:6a4db94011d3 1278 }
sahilmgandhi 18:6a4db94011d3 1279 }
sahilmgandhi 18:6a4db94011d3 1280
sahilmgandhi 18:6a4db94011d3 1281 /* Memory Data size equal to Word */
sahilmgandhi 18:6a4db94011d3 1282 else
sahilmgandhi 18:6a4db94011d3 1283 {
sahilmgandhi 18:6a4db94011d3 1284 switch (tmp)
sahilmgandhi 18:6a4db94011d3 1285 {
sahilmgandhi 18:6a4db94011d3 1286 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
sahilmgandhi 18:6a4db94011d3 1287 case DMA_FIFO_THRESHOLD_HALFFULL:
sahilmgandhi 18:6a4db94011d3 1288 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
sahilmgandhi 18:6a4db94011d3 1289 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1290 break;
sahilmgandhi 18:6a4db94011d3 1291 case DMA_FIFO_THRESHOLD_FULL:
sahilmgandhi 18:6a4db94011d3 1292 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
sahilmgandhi 18:6a4db94011d3 1293 {
sahilmgandhi 18:6a4db94011d3 1294 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1295 }
sahilmgandhi 18:6a4db94011d3 1296 break;
sahilmgandhi 18:6a4db94011d3 1297 default:
sahilmgandhi 18:6a4db94011d3 1298 break;
sahilmgandhi 18:6a4db94011d3 1299 }
sahilmgandhi 18:6a4db94011d3 1300 }
sahilmgandhi 18:6a4db94011d3 1301
sahilmgandhi 18:6a4db94011d3 1302 return status;
sahilmgandhi 18:6a4db94011d3 1303 }
sahilmgandhi 18:6a4db94011d3 1304
sahilmgandhi 18:6a4db94011d3 1305 /**
sahilmgandhi 18:6a4db94011d3 1306 * @}
sahilmgandhi 18:6a4db94011d3 1307 */
sahilmgandhi 18:6a4db94011d3 1308
sahilmgandhi 18:6a4db94011d3 1309 #endif /* HAL_DMA_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1310 /**
sahilmgandhi 18:6a4db94011d3 1311 * @}
sahilmgandhi 18:6a4db94011d3 1312 */
sahilmgandhi 18:6a4db94011d3 1313
sahilmgandhi 18:6a4db94011d3 1314 /**
sahilmgandhi 18:6a4db94011d3 1315 * @}
sahilmgandhi 18:6a4db94011d3 1316 */
sahilmgandhi 18:6a4db94011d3 1317
sahilmgandhi 18:6a4db94011d3 1318 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/