MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_cortex.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f2xx_hal_cortex.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.1.3
sahilmgandhi 18:6a4db94011d3 6 * @date 29-June-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief CORTEX HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 9 * functionalities of the CORTEX:
sahilmgandhi 18:6a4db94011d3 10 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 11 * + Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 @verbatim
sahilmgandhi 18:6a4db94011d3 14 ==============================================================================
sahilmgandhi 18:6a4db94011d3 15 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 16 ==============================================================================
sahilmgandhi 18:6a4db94011d3 17
sahilmgandhi 18:6a4db94011d3 18 [..]
sahilmgandhi 18:6a4db94011d3 19 *** How to configure Interrupts using CORTEX HAL driver ***
sahilmgandhi 18:6a4db94011d3 20 ===========================================================
sahilmgandhi 18:6a4db94011d3 21 [..]
sahilmgandhi 18:6a4db94011d3 22 This section provides functions allowing to configure the NVIC interrupts (IRQ).
sahilmgandhi 18:6a4db94011d3 23 The Cortex-M3 exceptions are managed by CMSIS functions.
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
sahilmgandhi 18:6a4db94011d3 26 function according to the following table.
sahilmgandhi 18:6a4db94011d3 27 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
sahilmgandhi 18:6a4db94011d3 28 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
sahilmgandhi 18:6a4db94011d3 29 (#) please refer to programing manual for details in how to configure priority.
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
sahilmgandhi 18:6a4db94011d3 32 The pending IRQ priority will be managed only by the sub priority.
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 -@- IRQ priority order (sorted by highest to lowest priority):
sahilmgandhi 18:6a4db94011d3 35 (+@) Lowest preemption priority
sahilmgandhi 18:6a4db94011d3 36 (+@) Lowest sub priority
sahilmgandhi 18:6a4db94011d3 37 (+@) Lowest hardware priority (IRQ number)
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 [..]
sahilmgandhi 18:6a4db94011d3 40 *** How to configure Systick using CORTEX HAL driver ***
sahilmgandhi 18:6a4db94011d3 41 ========================================================
sahilmgandhi 18:6a4db94011d3 42 [..]
sahilmgandhi 18:6a4db94011d3 43 Setup SysTick Timer for time base.
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
sahilmgandhi 18:6a4db94011d3 46 is a CMSIS function that:
sahilmgandhi 18:6a4db94011d3 47 (++) Configures the SysTick Reload register with value passed as function parameter.
sahilmgandhi 18:6a4db94011d3 48 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
sahilmgandhi 18:6a4db94011d3 49 (++) Resets the SysTick Counter register.
sahilmgandhi 18:6a4db94011d3 50 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
sahilmgandhi 18:6a4db94011d3 51 (++) Enables the SysTick Interrupt.
sahilmgandhi 18:6a4db94011d3 52 (++) Starts the SysTick Counter.
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
sahilmgandhi 18:6a4db94011d3 55 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
sahilmgandhi 18:6a4db94011d3 56 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
sahilmgandhi 18:6a4db94011d3 57 inside the stm32f2xx_hal_cortex.h file.
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 (+) You can change the SysTick IRQ priority by calling the
sahilmgandhi 18:6a4db94011d3 60 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
sahilmgandhi 18:6a4db94011d3 61 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 (+) To adjust the SysTick time base, use the following formula:
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
sahilmgandhi 18:6a4db94011d3 66 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
sahilmgandhi 18:6a4db94011d3 67 (++) Reload Value should not exceed 0xFFFFFF
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 @endverbatim
sahilmgandhi 18:6a4db94011d3 70 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 71 * @attention
sahilmgandhi 18:6a4db94011d3 72 *
sahilmgandhi 18:6a4db94011d3 73 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 74 *
sahilmgandhi 18:6a4db94011d3 75 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 76 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 77 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 78 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 79 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 80 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 81 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 83 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 84 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 85 *
sahilmgandhi 18:6a4db94011d3 86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 96 *
sahilmgandhi 18:6a4db94011d3 97 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 98 */
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 101 #include "stm32f2xx_hal.h"
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 /** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 104 * @{
sahilmgandhi 18:6a4db94011d3 105 */
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 /** @defgroup CORTEX CORTEX
sahilmgandhi 18:6a4db94011d3 108 * @brief CORTEX HAL module driver
sahilmgandhi 18:6a4db94011d3 109 * @{
sahilmgandhi 18:6a4db94011d3 110 */
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 #ifdef HAL_CORTEX_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 115 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 116 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 117 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 118 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 119 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
sahilmgandhi 18:6a4db94011d3 122 * @{
sahilmgandhi 18:6a4db94011d3 123 */
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 127 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 128 *
sahilmgandhi 18:6a4db94011d3 129 @verbatim
sahilmgandhi 18:6a4db94011d3 130 ==============================================================================
sahilmgandhi 18:6a4db94011d3 131 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 132 ==============================================================================
sahilmgandhi 18:6a4db94011d3 133 [..]
sahilmgandhi 18:6a4db94011d3 134 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
sahilmgandhi 18:6a4db94011d3 135 Systick functionalities
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 @endverbatim
sahilmgandhi 18:6a4db94011d3 138 * @{
sahilmgandhi 18:6a4db94011d3 139 */
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /**
sahilmgandhi 18:6a4db94011d3 143 * @brief Sets the priority grouping field (preemption priority and subpriority)
sahilmgandhi 18:6a4db94011d3 144 * using the required unlock sequence.
sahilmgandhi 18:6a4db94011d3 145 * @param PriorityGroup: The priority grouping bits length.
sahilmgandhi 18:6a4db94011d3 146 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 147 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 148 * 4 bits for subpriority
sahilmgandhi 18:6a4db94011d3 149 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 150 * 3 bits for subpriority
sahilmgandhi 18:6a4db94011d3 151 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 152 * 2 bits for subpriority
sahilmgandhi 18:6a4db94011d3 153 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 154 * 1 bits for subpriority
sahilmgandhi 18:6a4db94011d3 155 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 156 * 0 bits for subpriority
sahilmgandhi 18:6a4db94011d3 157 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
sahilmgandhi 18:6a4db94011d3 158 * The pending IRQ priority will be managed only by the subpriority.
sahilmgandhi 18:6a4db94011d3 159 * @retval None
sahilmgandhi 18:6a4db94011d3 160 */
sahilmgandhi 18:6a4db94011d3 161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
sahilmgandhi 18:6a4db94011d3 162 {
sahilmgandhi 18:6a4db94011d3 163 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 164 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
sahilmgandhi 18:6a4db94011d3 167 NVIC_SetPriorityGrouping(PriorityGroup);
sahilmgandhi 18:6a4db94011d3 168 }
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 /**
sahilmgandhi 18:6a4db94011d3 171 * @brief Sets the priority of an interrupt.
sahilmgandhi 18:6a4db94011d3 172 * @param IRQn: External interrupt number.
sahilmgandhi 18:6a4db94011d3 173 * This parameter can be an enumerator of IRQn_Type enumeration
sahilmgandhi 18:6a4db94011d3 174 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
sahilmgandhi 18:6a4db94011d3 175 * @param PreemptPriority: The preemption priority for the IRQn channel.
sahilmgandhi 18:6a4db94011d3 176 * This parameter can be a value between 0 and 15
sahilmgandhi 18:6a4db94011d3 177 * A lower priority value indicates a higher priority
sahilmgandhi 18:6a4db94011d3 178 * @param SubPriority: the subpriority level for the IRQ channel.
sahilmgandhi 18:6a4db94011d3 179 * This parameter can be a value between 0 and 15
sahilmgandhi 18:6a4db94011d3 180 * A lower priority value indicates a higher priority.
sahilmgandhi 18:6a4db94011d3 181 * @retval None
sahilmgandhi 18:6a4db94011d3 182 */
sahilmgandhi 18:6a4db94011d3 183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
sahilmgandhi 18:6a4db94011d3 184 {
sahilmgandhi 18:6a4db94011d3 185 uint32_t prioritygroup = 0x00U;
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 188 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
sahilmgandhi 18:6a4db94011d3 189 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 prioritygroup = NVIC_GetPriorityGrouping();
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
sahilmgandhi 18:6a4db94011d3 194 }
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 /**
sahilmgandhi 18:6a4db94011d3 197 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 198 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
sahilmgandhi 18:6a4db94011d3 199 * function should be called before.
sahilmgandhi 18:6a4db94011d3 200 * @param IRQn External interrupt number.
sahilmgandhi 18:6a4db94011d3 201 * This parameter can be an enumerator of IRQn_Type enumeration
sahilmgandhi 18:6a4db94011d3 202 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
sahilmgandhi 18:6a4db94011d3 203 * @retval None
sahilmgandhi 18:6a4db94011d3 204 */
sahilmgandhi 18:6a4db94011d3 205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 206 {
sahilmgandhi 18:6a4db94011d3 207 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 208 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 /* Enable interrupt */
sahilmgandhi 18:6a4db94011d3 211 NVIC_EnableIRQ(IRQn);
sahilmgandhi 18:6a4db94011d3 212 }
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /**
sahilmgandhi 18:6a4db94011d3 215 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 216 * @param IRQn External interrupt number.
sahilmgandhi 18:6a4db94011d3 217 * This parameter can be an enumerator of IRQn_Type enumeration
sahilmgandhi 18:6a4db94011d3 218 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
sahilmgandhi 18:6a4db94011d3 219 * @retval None
sahilmgandhi 18:6a4db94011d3 220 */
sahilmgandhi 18:6a4db94011d3 221 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 222 {
sahilmgandhi 18:6a4db94011d3 223 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 224 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /* Disable interrupt */
sahilmgandhi 18:6a4db94011d3 227 NVIC_DisableIRQ(IRQn);
sahilmgandhi 18:6a4db94011d3 228 }
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 /**
sahilmgandhi 18:6a4db94011d3 231 * @brief Initiates a system reset request to reset the MCU.
sahilmgandhi 18:6a4db94011d3 232 * @retval None
sahilmgandhi 18:6a4db94011d3 233 */
sahilmgandhi 18:6a4db94011d3 234 void HAL_NVIC_SystemReset(void)
sahilmgandhi 18:6a4db94011d3 235 {
sahilmgandhi 18:6a4db94011d3 236 /* System Reset */
sahilmgandhi 18:6a4db94011d3 237 NVIC_SystemReset();
sahilmgandhi 18:6a4db94011d3 238 }
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 /**
sahilmgandhi 18:6a4db94011d3 241 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
sahilmgandhi 18:6a4db94011d3 242 * Counter is in free running mode to generate periodic interrupts.
sahilmgandhi 18:6a4db94011d3 243 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
sahilmgandhi 18:6a4db94011d3 244 * @retval status: - 0 Function succeeded.
sahilmgandhi 18:6a4db94011d3 245 * - 1 Function failed.
sahilmgandhi 18:6a4db94011d3 246 */
sahilmgandhi 18:6a4db94011d3 247 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
sahilmgandhi 18:6a4db94011d3 248 {
sahilmgandhi 18:6a4db94011d3 249 return SysTick_Config(TicksNumb);
sahilmgandhi 18:6a4db94011d3 250 }
sahilmgandhi 18:6a4db94011d3 251 /**
sahilmgandhi 18:6a4db94011d3 252 * @}
sahilmgandhi 18:6a4db94011d3 253 */
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 256 * @brief Cortex control functions
sahilmgandhi 18:6a4db94011d3 257 *
sahilmgandhi 18:6a4db94011d3 258 @verbatim
sahilmgandhi 18:6a4db94011d3 259 ==============================================================================
sahilmgandhi 18:6a4db94011d3 260 ##### Peripheral Control functions #####
sahilmgandhi 18:6a4db94011d3 261 ==============================================================================
sahilmgandhi 18:6a4db94011d3 262 [..]
sahilmgandhi 18:6a4db94011d3 263 This subsection provides a set of functions allowing to control the CORTEX
sahilmgandhi 18:6a4db94011d3 264 (NVIC, SYSTICK, MPU) functionalities.
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 @endverbatim
sahilmgandhi 18:6a4db94011d3 268 * @{
sahilmgandhi 18:6a4db94011d3 269 */
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 #if (__MPU_PRESENT == 1U)
sahilmgandhi 18:6a4db94011d3 272 /**
sahilmgandhi 18:6a4db94011d3 273 * @brief Initializes and configures the Region and the memory to be protected.
sahilmgandhi 18:6a4db94011d3 274 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 275 * the initialization and configuration information.
sahilmgandhi 18:6a4db94011d3 276 * @retval None
sahilmgandhi 18:6a4db94011d3 277 */
sahilmgandhi 18:6a4db94011d3 278 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
sahilmgandhi 18:6a4db94011d3 279 {
sahilmgandhi 18:6a4db94011d3 280 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 281 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
sahilmgandhi 18:6a4db94011d3 282 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 /* Set the Region number */
sahilmgandhi 18:6a4db94011d3 285 MPU->RNR = MPU_Init->Number;
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 if ((MPU_Init->Enable) != RESET)
sahilmgandhi 18:6a4db94011d3 288 {
sahilmgandhi 18:6a4db94011d3 289 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 290 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
sahilmgandhi 18:6a4db94011d3 291 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
sahilmgandhi 18:6a4db94011d3 292 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
sahilmgandhi 18:6a4db94011d3 293 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
sahilmgandhi 18:6a4db94011d3 294 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
sahilmgandhi 18:6a4db94011d3 295 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
sahilmgandhi 18:6a4db94011d3 296 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
sahilmgandhi 18:6a4db94011d3 297 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 MPU->RBAR = MPU_Init->BaseAddress;
sahilmgandhi 18:6a4db94011d3 300 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
sahilmgandhi 18:6a4db94011d3 301 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
sahilmgandhi 18:6a4db94011d3 302 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
sahilmgandhi 18:6a4db94011d3 303 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
sahilmgandhi 18:6a4db94011d3 304 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
sahilmgandhi 18:6a4db94011d3 305 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
sahilmgandhi 18:6a4db94011d3 306 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
sahilmgandhi 18:6a4db94011d3 307 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
sahilmgandhi 18:6a4db94011d3 308 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
sahilmgandhi 18:6a4db94011d3 309 }
sahilmgandhi 18:6a4db94011d3 310 else
sahilmgandhi 18:6a4db94011d3 311 {
sahilmgandhi 18:6a4db94011d3 312 MPU->RBAR = 0x00U;
sahilmgandhi 18:6a4db94011d3 313 MPU->RASR = 0x00U;
sahilmgandhi 18:6a4db94011d3 314 }
sahilmgandhi 18:6a4db94011d3 315 }
sahilmgandhi 18:6a4db94011d3 316 #endif /* __MPU_PRESENT */
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 /**
sahilmgandhi 18:6a4db94011d3 319 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
sahilmgandhi 18:6a4db94011d3 320 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
sahilmgandhi 18:6a4db94011d3 321 */
sahilmgandhi 18:6a4db94011d3 322 uint32_t HAL_NVIC_GetPriorityGrouping(void)
sahilmgandhi 18:6a4db94011d3 323 {
sahilmgandhi 18:6a4db94011d3 324 /* Get the PRIGROUP[10:8] field value */
sahilmgandhi 18:6a4db94011d3 325 return NVIC_GetPriorityGrouping();
sahilmgandhi 18:6a4db94011d3 326 }
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 /**
sahilmgandhi 18:6a4db94011d3 329 * @brief Gets the priority of an interrupt.
sahilmgandhi 18:6a4db94011d3 330 * @param IRQn: External interrupt number.
sahilmgandhi 18:6a4db94011d3 331 * This parameter can be an enumerator of IRQn_Type enumeration
sahilmgandhi 18:6a4db94011d3 332 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
sahilmgandhi 18:6a4db94011d3 333 * @param PriorityGroup: the priority grouping bits length.
sahilmgandhi 18:6a4db94011d3 334 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 335 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 336 * 4 bits for subpriority
sahilmgandhi 18:6a4db94011d3 337 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 338 * 3 bits for subpriority
sahilmgandhi 18:6a4db94011d3 339 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 340 * 2 bits for subpriority
sahilmgandhi 18:6a4db94011d3 341 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 342 * 1 bits for subpriority
sahilmgandhi 18:6a4db94011d3 343 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
sahilmgandhi 18:6a4db94011d3 344 * 0 bits for subpriority
sahilmgandhi 18:6a4db94011d3 345 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
sahilmgandhi 18:6a4db94011d3 346 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
sahilmgandhi 18:6a4db94011d3 347 * @retval None
sahilmgandhi 18:6a4db94011d3 348 */
sahilmgandhi 18:6a4db94011d3 349 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
sahilmgandhi 18:6a4db94011d3 350 {
sahilmgandhi 18:6a4db94011d3 351 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 352 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
sahilmgandhi 18:6a4db94011d3 353 /* Get priority for Cortex-M system or device specific interrupts */
sahilmgandhi 18:6a4db94011d3 354 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
sahilmgandhi 18:6a4db94011d3 355 }
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 /**
sahilmgandhi 18:6a4db94011d3 358 * @brief Sets Pending bit of an external interrupt.
sahilmgandhi 18:6a4db94011d3 359 * @param IRQn External interrupt number
sahilmgandhi 18:6a4db94011d3 360 * This parameter can be an enumerator of IRQn_Type enumeration
sahilmgandhi 18:6a4db94011d3 361 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
sahilmgandhi 18:6a4db94011d3 362 * @retval None
sahilmgandhi 18:6a4db94011d3 363 */
sahilmgandhi 18:6a4db94011d3 364 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 365 {
sahilmgandhi 18:6a4db94011d3 366 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 367 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 /* Set interrupt pending */
sahilmgandhi 18:6a4db94011d3 370 NVIC_SetPendingIRQ(IRQn);
sahilmgandhi 18:6a4db94011d3 371 }
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /**
sahilmgandhi 18:6a4db94011d3 374 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
sahilmgandhi 18:6a4db94011d3 375 * and returns the pending bit for the specified interrupt).
sahilmgandhi 18:6a4db94011d3 376 * @param IRQn External interrupt number.
sahilmgandhi 18:6a4db94011d3 377 * This parameter can be an enumerator of IRQn_Type enumeration
sahilmgandhi 18:6a4db94011d3 378 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
sahilmgandhi 18:6a4db94011d3 379 * @retval status: - 0 Interrupt status is not pending.
sahilmgandhi 18:6a4db94011d3 380 * - 1 Interrupt status is pending.
sahilmgandhi 18:6a4db94011d3 381 */
sahilmgandhi 18:6a4db94011d3 382 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 383 {
sahilmgandhi 18:6a4db94011d3 384 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 385 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 /* Return 1 if pending else 0 */
sahilmgandhi 18:6a4db94011d3 388 return NVIC_GetPendingIRQ(IRQn);
sahilmgandhi 18:6a4db94011d3 389 }
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 /**
sahilmgandhi 18:6a4db94011d3 392 * @brief Clears the pending bit of an external interrupt.
sahilmgandhi 18:6a4db94011d3 393 * @param IRQn External interrupt number.
sahilmgandhi 18:6a4db94011d3 394 * This parameter can be an enumerator of IRQn_Type enumeration
sahilmgandhi 18:6a4db94011d3 395 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
sahilmgandhi 18:6a4db94011d3 396 * @retval None
sahilmgandhi 18:6a4db94011d3 397 */
sahilmgandhi 18:6a4db94011d3 398 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 399 {
sahilmgandhi 18:6a4db94011d3 400 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 401 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 /* Clear pending interrupt */
sahilmgandhi 18:6a4db94011d3 404 NVIC_ClearPendingIRQ(IRQn);
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /**
sahilmgandhi 18:6a4db94011d3 408 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
sahilmgandhi 18:6a4db94011d3 409 * @param IRQn External interrupt number
sahilmgandhi 18:6a4db94011d3 410 * This parameter can be an enumerator of IRQn_Type enumeration
sahilmgandhi 18:6a4db94011d3 411 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
sahilmgandhi 18:6a4db94011d3 412 * @retval status: - 0 Interrupt status is not pending.
sahilmgandhi 18:6a4db94011d3 413 * - 1 Interrupt status is pending.
sahilmgandhi 18:6a4db94011d3 414 */
sahilmgandhi 18:6a4db94011d3 415 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 416 {
sahilmgandhi 18:6a4db94011d3 417 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 418 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 /* Return 1 if active else 0 */
sahilmgandhi 18:6a4db94011d3 421 return NVIC_GetActive(IRQn);
sahilmgandhi 18:6a4db94011d3 422 }
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 /**
sahilmgandhi 18:6a4db94011d3 425 * @brief Configures the SysTick clock source.
sahilmgandhi 18:6a4db94011d3 426 * @param CLKSource: specifies the SysTick clock source.
sahilmgandhi 18:6a4db94011d3 427 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 428 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
sahilmgandhi 18:6a4db94011d3 429 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
sahilmgandhi 18:6a4db94011d3 430 * @retval None
sahilmgandhi 18:6a4db94011d3 431 */
sahilmgandhi 18:6a4db94011d3 432 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
sahilmgandhi 18:6a4db94011d3 433 {
sahilmgandhi 18:6a4db94011d3 434 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 435 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
sahilmgandhi 18:6a4db94011d3 436 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
sahilmgandhi 18:6a4db94011d3 437 {
sahilmgandhi 18:6a4db94011d3 438 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
sahilmgandhi 18:6a4db94011d3 439 }
sahilmgandhi 18:6a4db94011d3 440 else
sahilmgandhi 18:6a4db94011d3 441 {
sahilmgandhi 18:6a4db94011d3 442 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
sahilmgandhi 18:6a4db94011d3 443 }
sahilmgandhi 18:6a4db94011d3 444 }
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 /**
sahilmgandhi 18:6a4db94011d3 447 * @brief This function handles SYSTICK interrupt request.
sahilmgandhi 18:6a4db94011d3 448 * @retval None
sahilmgandhi 18:6a4db94011d3 449 */
sahilmgandhi 18:6a4db94011d3 450 void HAL_SYSTICK_IRQHandler(void)
sahilmgandhi 18:6a4db94011d3 451 {
sahilmgandhi 18:6a4db94011d3 452 HAL_SYSTICK_Callback();
sahilmgandhi 18:6a4db94011d3 453 }
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 /**
sahilmgandhi 18:6a4db94011d3 456 * @brief SYSTICK callback.
sahilmgandhi 18:6a4db94011d3 457 * @retval None
sahilmgandhi 18:6a4db94011d3 458 */
sahilmgandhi 18:6a4db94011d3 459 __weak void HAL_SYSTICK_Callback(void)
sahilmgandhi 18:6a4db94011d3 460 {
sahilmgandhi 18:6a4db94011d3 461 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 462 the HAL_SYSTICK_Callback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 463 */
sahilmgandhi 18:6a4db94011d3 464 }
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 /**
sahilmgandhi 18:6a4db94011d3 467 * @}
sahilmgandhi 18:6a4db94011d3 468 */
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 /**
sahilmgandhi 18:6a4db94011d3 471 * @}
sahilmgandhi 18:6a4db94011d3 472 */
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 #endif /* HAL_CORTEX_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 475 /**
sahilmgandhi 18:6a4db94011d3 476 * @}
sahilmgandhi 18:6a4db94011d3 477 */
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 /**
sahilmgandhi 18:6a4db94011d3 480 * @}
sahilmgandhi 18:6a4db94011d3 481 */
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/