Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_stm32f2xx.c@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @file system_stm32f2xx.c |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @author MCD Application Team |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @version V2.1.2 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @date 29-June-2016 |
sahilmgandhi | 18:6a4db94011d3 | 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. |
sahilmgandhi | 18:6a4db94011d3 | 8 | * |
sahilmgandhi | 18:6a4db94011d3 | 9 | * This file provides two functions and one global variable to be called from |
sahilmgandhi | 18:6a4db94011d3 | 10 | * user application: |
sahilmgandhi | 18:6a4db94011d3 | 11 | * - SystemInit(): This function is called at startup just after reset and |
sahilmgandhi | 18:6a4db94011d3 | 12 | * before branch to main program. This call is made inside |
sahilmgandhi | 18:6a4db94011d3 | 13 | * the "startup_stm32f2xx.s" file. |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
sahilmgandhi | 18:6a4db94011d3 | 16 | * by the user application to setup the SysTick |
sahilmgandhi | 18:6a4db94011d3 | 17 | * timer or configure other parameters. |
sahilmgandhi | 18:6a4db94011d3 | 18 | * |
sahilmgandhi | 18:6a4db94011d3 | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
sahilmgandhi | 18:6a4db94011d3 | 20 | * be called whenever the core clock is changed |
sahilmgandhi | 18:6a4db94011d3 | 21 | * during program execution. |
sahilmgandhi | 18:6a4db94011d3 | 22 | * |
sahilmgandhi | 18:6a4db94011d3 | 23 | * This file configures the system clock as follows: |
sahilmgandhi | 18:6a4db94011d3 | 24 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 25 | * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails |
sahilmgandhi | 18:6a4db94011d3 | 26 | * | (external 25MHz xtal) | (internal 16MHz clock) |
sahilmgandhi | 18:6a4db94011d3 | 27 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 28 | * SYSCLK(MHz) | 120 | 96 |
sahilmgandhi | 18:6a4db94011d3 | 29 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 30 | * AHBCLK (MHz) | 120 | 96 |
sahilmgandhi | 18:6a4db94011d3 | 31 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 32 | * APB1CLK (MHz) | 30 | 12 |
sahilmgandhi | 18:6a4db94011d3 | 33 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 34 | * APB2CLK (MHz) | 60 | 24 |
sahilmgandhi | 18:6a4db94011d3 | 35 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 36 | * USB capable | YES | NO |
sahilmgandhi | 18:6a4db94011d3 | 37 | * with 48 MHz precise clock | | |
sahilmgandhi | 18:6a4db94011d3 | 38 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 39 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 40 | * @attention |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
sahilmgandhi | 18:6a4db94011d3 | 43 | * |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Redistribution and use in source and binary forms, with or without modification, |
sahilmgandhi | 18:6a4db94011d3 | 45 | * are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 46 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 47 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 48 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 49 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 50 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 51 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
sahilmgandhi | 18:6a4db94011d3 | 52 | * may be used to endorse or promote products derived from this software |
sahilmgandhi | 18:6a4db94011d3 | 53 | * without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 54 | * |
sahilmgandhi | 18:6a4db94011d3 | 55 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 56 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 57 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
sahilmgandhi | 18:6a4db94011d3 | 58 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
sahilmgandhi | 18:6a4db94011d3 | 59 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 60 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
sahilmgandhi | 18:6a4db94011d3 | 61 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
sahilmgandhi | 18:6a4db94011d3 | 62 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
sahilmgandhi | 18:6a4db94011d3 | 63 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
sahilmgandhi | 18:6a4db94011d3 | 64 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 65 | * |
sahilmgandhi | 18:6a4db94011d3 | 66 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 67 | */ |
sahilmgandhi | 18:6a4db94011d3 | 68 | |
sahilmgandhi | 18:6a4db94011d3 | 69 | /** @addtogroup CMSIS |
sahilmgandhi | 18:6a4db94011d3 | 70 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 71 | */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | |
sahilmgandhi | 18:6a4db94011d3 | 73 | /** @addtogroup stm32f2xx_system |
sahilmgandhi | 18:6a4db94011d3 | 74 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 75 | */ |
sahilmgandhi | 18:6a4db94011d3 | 76 | |
sahilmgandhi | 18:6a4db94011d3 | 77 | /** @addtogroup STM32F2xx_System_Private_Includes |
sahilmgandhi | 18:6a4db94011d3 | 78 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 79 | */ |
sahilmgandhi | 18:6a4db94011d3 | 80 | |
sahilmgandhi | 18:6a4db94011d3 | 81 | #include "stm32f2xx.h" |
sahilmgandhi | 18:6a4db94011d3 | 82 | #include "hal_tick.h" |
sahilmgandhi | 18:6a4db94011d3 | 83 | |
sahilmgandhi | 18:6a4db94011d3 | 84 | /** |
sahilmgandhi | 18:6a4db94011d3 | 85 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 86 | */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | |
sahilmgandhi | 18:6a4db94011d3 | 88 | /** @addtogroup STM32F2xx_System_Private_TypesDefinitions |
sahilmgandhi | 18:6a4db94011d3 | 89 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 90 | */ |
sahilmgandhi | 18:6a4db94011d3 | 91 | |
sahilmgandhi | 18:6a4db94011d3 | 92 | /** |
sahilmgandhi | 18:6a4db94011d3 | 93 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 94 | */ |
sahilmgandhi | 18:6a4db94011d3 | 95 | |
sahilmgandhi | 18:6a4db94011d3 | 96 | /** @addtogroup STM32F2xx_System_Private_Defines |
sahilmgandhi | 18:6a4db94011d3 | 97 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 98 | */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | /************************* Miscellaneous Configuration ************************/ |
sahilmgandhi | 18:6a4db94011d3 | 100 | /*!< Uncomment the following line if you need to use external SRAM mounted |
sahilmgandhi | 18:6a4db94011d3 | 101 | on STM322xG_EVAL board as data memory */ |
sahilmgandhi | 18:6a4db94011d3 | 102 | /* #define DATA_IN_ExtSRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | |
sahilmgandhi | 18:6a4db94011d3 | 104 | /*!< Uncomment the following line if you need to relocate your vector Table in |
sahilmgandhi | 18:6a4db94011d3 | 105 | Internal SRAM. */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | /* #define VECT_TAB_SRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 107 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
sahilmgandhi | 18:6a4db94011d3 | 108 | This value must be a multiple of 0x200. */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 110 | |
sahilmgandhi | 18:6a4db94011d3 | 111 | /** |
sahilmgandhi | 18:6a4db94011d3 | 112 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 113 | */ |
sahilmgandhi | 18:6a4db94011d3 | 114 | |
sahilmgandhi | 18:6a4db94011d3 | 115 | /** @addtogroup STM32F2xx_System_Private_Macros |
sahilmgandhi | 18:6a4db94011d3 | 116 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 117 | */ |
sahilmgandhi | 18:6a4db94011d3 | 118 | |
sahilmgandhi | 18:6a4db94011d3 | 119 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
sahilmgandhi | 18:6a4db94011d3 | 121 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
sahilmgandhi | 18:6a4db94011d3 | 122 | |
sahilmgandhi | 18:6a4db94011d3 | 123 | /** |
sahilmgandhi | 18:6a4db94011d3 | 124 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 125 | */ |
sahilmgandhi | 18:6a4db94011d3 | 126 | |
sahilmgandhi | 18:6a4db94011d3 | 127 | /** @addtogroup STM32F2xx_System_Private_Variables |
sahilmgandhi | 18:6a4db94011d3 | 128 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 129 | */ |
sahilmgandhi | 18:6a4db94011d3 | 130 | |
sahilmgandhi | 18:6a4db94011d3 | 131 | /* This variable can be updated in Three ways : |
sahilmgandhi | 18:6a4db94011d3 | 132 | 1) by calling CMSIS function SystemCoreClockUpdate() |
sahilmgandhi | 18:6a4db94011d3 | 133 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
sahilmgandhi | 18:6a4db94011d3 | 134 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
sahilmgandhi | 18:6a4db94011d3 | 135 | Note: If you use this function to configure the system clock; then there |
sahilmgandhi | 18:6a4db94011d3 | 136 | is no need to call the 2 first functions listed above, since SystemCoreClock |
sahilmgandhi | 18:6a4db94011d3 | 137 | variable is updated automatically. |
sahilmgandhi | 18:6a4db94011d3 | 138 | */ |
sahilmgandhi | 18:6a4db94011d3 | 139 | uint32_t SystemCoreClock = 120000000; |
sahilmgandhi | 18:6a4db94011d3 | 140 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
sahilmgandhi | 18:6a4db94011d3 | 141 | |
sahilmgandhi | 18:6a4db94011d3 | 142 | /** |
sahilmgandhi | 18:6a4db94011d3 | 143 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 144 | */ |
sahilmgandhi | 18:6a4db94011d3 | 145 | |
sahilmgandhi | 18:6a4db94011d3 | 146 | /** @addtogroup STM32F2xx_System_Private_FunctionPrototypes |
sahilmgandhi | 18:6a4db94011d3 | 147 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 148 | */ |
sahilmgandhi | 18:6a4db94011d3 | 149 | |
sahilmgandhi | 18:6a4db94011d3 | 150 | #ifdef DATA_IN_ExtSRAM |
sahilmgandhi | 18:6a4db94011d3 | 151 | static void SystemInit_ExtMemCtl(void); |
sahilmgandhi | 18:6a4db94011d3 | 152 | #endif /* DATA_IN_ExtSRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 153 | |
sahilmgandhi | 18:6a4db94011d3 | 154 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
sahilmgandhi | 18:6a4db94011d3 | 155 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
sahilmgandhi | 18:6a4db94011d3 | 156 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 157 | |
sahilmgandhi | 18:6a4db94011d3 | 158 | uint8_t SetSysClock_PLL_HSI(void); |
sahilmgandhi | 18:6a4db94011d3 | 159 | /** |
sahilmgandhi | 18:6a4db94011d3 | 160 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 161 | */ |
sahilmgandhi | 18:6a4db94011d3 | 162 | |
sahilmgandhi | 18:6a4db94011d3 | 163 | /** @addtogroup STM32F2xx_System_Private_Functions |
sahilmgandhi | 18:6a4db94011d3 | 164 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 165 | */ |
sahilmgandhi | 18:6a4db94011d3 | 166 | |
sahilmgandhi | 18:6a4db94011d3 | 167 | /** |
sahilmgandhi | 18:6a4db94011d3 | 168 | * @brief Setup the microcontroller system |
sahilmgandhi | 18:6a4db94011d3 | 169 | * Initialize the Embedded Flash Interface, the PLL and update the |
sahilmgandhi | 18:6a4db94011d3 | 170 | * SystemFrequency variable. |
sahilmgandhi | 18:6a4db94011d3 | 171 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 172 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 173 | */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | void SystemInit(void) |
sahilmgandhi | 18:6a4db94011d3 | 175 | { |
sahilmgandhi | 18:6a4db94011d3 | 176 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 177 | /* Set HSION bit */ |
sahilmgandhi | 18:6a4db94011d3 | 178 | RCC->CR |= (uint32_t)0x00000001; |
sahilmgandhi | 18:6a4db94011d3 | 179 | |
sahilmgandhi | 18:6a4db94011d3 | 180 | /* Reset CFGR register */ |
sahilmgandhi | 18:6a4db94011d3 | 181 | RCC->CFGR = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 182 | |
sahilmgandhi | 18:6a4db94011d3 | 183 | /* Reset HSEON, CSSON and PLLON bits */ |
sahilmgandhi | 18:6a4db94011d3 | 184 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
sahilmgandhi | 18:6a4db94011d3 | 185 | |
sahilmgandhi | 18:6a4db94011d3 | 186 | /* Reset PLLCFGR register */ |
sahilmgandhi | 18:6a4db94011d3 | 187 | RCC->PLLCFGR = 0x24003010; |
sahilmgandhi | 18:6a4db94011d3 | 188 | |
sahilmgandhi | 18:6a4db94011d3 | 189 | /* Reset HSEBYP bit */ |
sahilmgandhi | 18:6a4db94011d3 | 190 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
sahilmgandhi | 18:6a4db94011d3 | 191 | |
sahilmgandhi | 18:6a4db94011d3 | 192 | /* Disable all interrupts */ |
sahilmgandhi | 18:6a4db94011d3 | 193 | RCC->CIR = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 194 | |
sahilmgandhi | 18:6a4db94011d3 | 195 | #ifdef DATA_IN_ExtSRAM |
sahilmgandhi | 18:6a4db94011d3 | 196 | SystemInit_ExtMemCtl(); |
sahilmgandhi | 18:6a4db94011d3 | 197 | #endif /* DATA_IN_ExtSRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 198 | |
sahilmgandhi | 18:6a4db94011d3 | 199 | /* Configure the Vector Table location add offset address ------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 200 | #ifdef VECT_TAB_SRAM |
sahilmgandhi | 18:6a4db94011d3 | 201 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 202 | #else |
sahilmgandhi | 18:6a4db94011d3 | 203 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 205 | |
sahilmgandhi | 18:6a4db94011d3 | 206 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
sahilmgandhi | 18:6a4db94011d3 | 207 | SystemCoreClock = 120000000; |
sahilmgandhi | 18:6a4db94011d3 | 208 | #else |
sahilmgandhi | 18:6a4db94011d3 | 209 | SystemCoreClock = 96000000; |
sahilmgandhi | 18:6a4db94011d3 | 210 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 211 | HAL_Init(); |
sahilmgandhi | 18:6a4db94011d3 | 212 | |
sahilmgandhi | 18:6a4db94011d3 | 213 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
sahilmgandhi | 18:6a4db94011d3 | 214 | AHB/APBx prescalers and Flash settings */ |
sahilmgandhi | 18:6a4db94011d3 | 215 | SetSysClock(); |
sahilmgandhi | 18:6a4db94011d3 | 216 | |
sahilmgandhi | 18:6a4db94011d3 | 217 | /* Reset the timer to avoid issues after the RAM initialization */ |
sahilmgandhi | 18:6a4db94011d3 | 218 | TIM_MST_RESET_ON; |
sahilmgandhi | 18:6a4db94011d3 | 219 | TIM_MST_RESET_OFF; |
sahilmgandhi | 18:6a4db94011d3 | 220 | } |
sahilmgandhi | 18:6a4db94011d3 | 221 | |
sahilmgandhi | 18:6a4db94011d3 | 222 | /** |
sahilmgandhi | 18:6a4db94011d3 | 223 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
sahilmgandhi | 18:6a4db94011d3 | 224 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
sahilmgandhi | 18:6a4db94011d3 | 225 | * be used by the user application to setup the SysTick timer or configure |
sahilmgandhi | 18:6a4db94011d3 | 226 | * other parameters. |
sahilmgandhi | 18:6a4db94011d3 | 227 | * |
sahilmgandhi | 18:6a4db94011d3 | 228 | * @note Each time the core clock (HCLK) changes, this function must be called |
sahilmgandhi | 18:6a4db94011d3 | 229 | * to update SystemCoreClock variable value. Otherwise, any configuration |
sahilmgandhi | 18:6a4db94011d3 | 230 | * based on this variable will be incorrect. |
sahilmgandhi | 18:6a4db94011d3 | 231 | * |
sahilmgandhi | 18:6a4db94011d3 | 232 | * @note - The system frequency computed by this function is not the real |
sahilmgandhi | 18:6a4db94011d3 | 233 | * frequency in the chip. It is calculated based on the predefined |
sahilmgandhi | 18:6a4db94011d3 | 234 | * constant and the selected clock source: |
sahilmgandhi | 18:6a4db94011d3 | 235 | * |
sahilmgandhi | 18:6a4db94011d3 | 236 | * - The result of this function could be not correct when using fractional |
sahilmgandhi | 18:6a4db94011d3 | 237 | * value for HSE crystal. |
sahilmgandhi | 18:6a4db94011d3 | 238 | * |
sahilmgandhi | 18:6a4db94011d3 | 239 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 240 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 241 | */ |
sahilmgandhi | 18:6a4db94011d3 | 242 | void SystemCoreClockUpdate(void) |
sahilmgandhi | 18:6a4db94011d3 | 243 | { |
sahilmgandhi | 18:6a4db94011d3 | 244 | SystemCoreClock = HAL_RCC_GetSysClockFreq(); |
sahilmgandhi | 18:6a4db94011d3 | 245 | } |
sahilmgandhi | 18:6a4db94011d3 | 246 | |
sahilmgandhi | 18:6a4db94011d3 | 247 | #ifdef DATA_IN_ExtSRAM |
sahilmgandhi | 18:6a4db94011d3 | 248 | /** |
sahilmgandhi | 18:6a4db94011d3 | 249 | * @brief Setup the external memory controller. |
sahilmgandhi | 18:6a4db94011d3 | 250 | * Called in startup_stm32f2xx.s before jump to main. |
sahilmgandhi | 18:6a4db94011d3 | 251 | * This function configures the external SRAM mounted on STM322xG_EVAL board |
sahilmgandhi | 18:6a4db94011d3 | 252 | * This SRAM will be used as program data memory (including heap and stack). |
sahilmgandhi | 18:6a4db94011d3 | 253 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 254 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 255 | */ |
sahilmgandhi | 18:6a4db94011d3 | 256 | void SystemInit_ExtMemCtl(void) |
sahilmgandhi | 18:6a4db94011d3 | 257 | { |
sahilmgandhi | 18:6a4db94011d3 | 258 | __IO uint32_t tmp = 0x00; |
sahilmgandhi | 18:6a4db94011d3 | 259 | |
sahilmgandhi | 18:6a4db94011d3 | 260 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 261 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
sahilmgandhi | 18:6a4db94011d3 | 262 | RCC->AHB1ENR |= 0x00000078; |
sahilmgandhi | 18:6a4db94011d3 | 263 | /* Delay after an RCC peripheral clock enabling */ |
sahilmgandhi | 18:6a4db94011d3 | 264 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); |
sahilmgandhi | 18:6a4db94011d3 | 265 | (void)(tmp); |
sahilmgandhi | 18:6a4db94011d3 | 266 | |
sahilmgandhi | 18:6a4db94011d3 | 267 | /* Connect PDx pins to FSMC Alternate function */ |
sahilmgandhi | 18:6a4db94011d3 | 268 | GPIOD->AFR[0] = 0x00CCC0CC; |
sahilmgandhi | 18:6a4db94011d3 | 269 | GPIOD->AFR[1] = 0xCCCCCCCC; |
sahilmgandhi | 18:6a4db94011d3 | 270 | /* Configure PDx pins in Alternate function mode */ |
sahilmgandhi | 18:6a4db94011d3 | 271 | GPIOD->MODER = 0xAAAA0A8A; |
sahilmgandhi | 18:6a4db94011d3 | 272 | /* Configure PDx pins speed to 100 MHz */ |
sahilmgandhi | 18:6a4db94011d3 | 273 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
sahilmgandhi | 18:6a4db94011d3 | 274 | /* Configure PDx pins Output type to push-pull */ |
sahilmgandhi | 18:6a4db94011d3 | 275 | GPIOD->OTYPER = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 276 | /* No pull-up, pull-down for PDx pins */ |
sahilmgandhi | 18:6a4db94011d3 | 277 | GPIOD->PUPDR = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 278 | |
sahilmgandhi | 18:6a4db94011d3 | 279 | /* Connect PEx pins to FSMC Alternate function */ |
sahilmgandhi | 18:6a4db94011d3 | 280 | GPIOE->AFR[0] = 0xC00CC0CC; |
sahilmgandhi | 18:6a4db94011d3 | 281 | GPIOE->AFR[1] = 0xCCCCCCCC; |
sahilmgandhi | 18:6a4db94011d3 | 282 | /* Configure PEx pins in Alternate function mode */ |
sahilmgandhi | 18:6a4db94011d3 | 283 | GPIOE->MODER = 0xAAAA828A; |
sahilmgandhi | 18:6a4db94011d3 | 284 | /* Configure PEx pins speed to 100 MHz */ |
sahilmgandhi | 18:6a4db94011d3 | 285 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
sahilmgandhi | 18:6a4db94011d3 | 286 | /* Configure PEx pins Output type to push-pull */ |
sahilmgandhi | 18:6a4db94011d3 | 287 | GPIOE->OTYPER = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 288 | /* No pull-up, pull-down for PEx pins */ |
sahilmgandhi | 18:6a4db94011d3 | 289 | GPIOE->PUPDR = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 290 | |
sahilmgandhi | 18:6a4db94011d3 | 291 | /* Connect PFx pins to FSMC Alternate function */ |
sahilmgandhi | 18:6a4db94011d3 | 292 | GPIOF->AFR[0] = 0x00CCCCCC; |
sahilmgandhi | 18:6a4db94011d3 | 293 | GPIOF->AFR[1] = 0xCCCC0000; |
sahilmgandhi | 18:6a4db94011d3 | 294 | /* Configure PFx pins in Alternate function mode */ |
sahilmgandhi | 18:6a4db94011d3 | 295 | GPIOF->MODER = 0xAA000AAA; |
sahilmgandhi | 18:6a4db94011d3 | 296 | /* Configure PFx pins speed to 100 MHz */ |
sahilmgandhi | 18:6a4db94011d3 | 297 | GPIOF->OSPEEDR = 0xFF000FFF; |
sahilmgandhi | 18:6a4db94011d3 | 298 | /* Configure PFx pins Output type to push-pull */ |
sahilmgandhi | 18:6a4db94011d3 | 299 | GPIOF->OTYPER = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 300 | /* No pull-up, pull-down for PFx pins */ |
sahilmgandhi | 18:6a4db94011d3 | 301 | GPIOF->PUPDR = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 302 | |
sahilmgandhi | 18:6a4db94011d3 | 303 | /* Connect PGx pins to FSMC Alternate function */ |
sahilmgandhi | 18:6a4db94011d3 | 304 | GPIOG->AFR[0] = 0x00CCCCCC; |
sahilmgandhi | 18:6a4db94011d3 | 305 | GPIOG->AFR[1] = 0x000000C0; |
sahilmgandhi | 18:6a4db94011d3 | 306 | /* Configure PGx pins in Alternate function mode */ |
sahilmgandhi | 18:6a4db94011d3 | 307 | GPIOG->MODER = 0x00085AAA; |
sahilmgandhi | 18:6a4db94011d3 | 308 | /* Configure PGx pins speed to 100 MHz */ |
sahilmgandhi | 18:6a4db94011d3 | 309 | GPIOG->OSPEEDR = 0x000CAFFF; |
sahilmgandhi | 18:6a4db94011d3 | 310 | /* Configure PGx pins Output type to push-pull */ |
sahilmgandhi | 18:6a4db94011d3 | 311 | GPIOG->OTYPER = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 312 | /* No pull-up, pull-down for PGx pins */ |
sahilmgandhi | 18:6a4db94011d3 | 313 | GPIOG->PUPDR = 0x00000000; |
sahilmgandhi | 18:6a4db94011d3 | 314 | |
sahilmgandhi | 18:6a4db94011d3 | 315 | /*--FSMC Configuration -------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 316 | /* Enable the FSMC interface clock */ |
sahilmgandhi | 18:6a4db94011d3 | 317 | RCC->AHB3ENR |= 0x00000001; |
sahilmgandhi | 18:6a4db94011d3 | 318 | |
sahilmgandhi | 18:6a4db94011d3 | 319 | /* Configure and enable Bank1_SRAM2 */ |
sahilmgandhi | 18:6a4db94011d3 | 320 | FSMC_Bank1->BTCR[2] = 0x00001011; |
sahilmgandhi | 18:6a4db94011d3 | 321 | FSMC_Bank1->BTCR[3] = 0x00000201; |
sahilmgandhi | 18:6a4db94011d3 | 322 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; |
sahilmgandhi | 18:6a4db94011d3 | 323 | } |
sahilmgandhi | 18:6a4db94011d3 | 324 | #endif /* DATA_IN_ExtSRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 325 | |
sahilmgandhi | 18:6a4db94011d3 | 326 | /** |
sahilmgandhi | 18:6a4db94011d3 | 327 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
sahilmgandhi | 18:6a4db94011d3 | 328 | * AHB/APBx prescalers and Flash settings |
sahilmgandhi | 18:6a4db94011d3 | 329 | * @note This function should be called only once the RCC clock configuration |
sahilmgandhi | 18:6a4db94011d3 | 330 | * is reset to the default reset state (done in SystemInit() function). |
sahilmgandhi | 18:6a4db94011d3 | 331 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 332 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 333 | */ |
sahilmgandhi | 18:6a4db94011d3 | 334 | void SetSysClock(void) |
sahilmgandhi | 18:6a4db94011d3 | 335 | { |
sahilmgandhi | 18:6a4db94011d3 | 336 | /* 1- Try to start with HSE and external clock */ |
sahilmgandhi | 18:6a4db94011d3 | 337 | #if USE_PLL_HSE_EXTC != 0 |
sahilmgandhi | 18:6a4db94011d3 | 338 | if (SetSysClock_PLL_HSE(1) == 0) |
sahilmgandhi | 18:6a4db94011d3 | 339 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 340 | { |
sahilmgandhi | 18:6a4db94011d3 | 341 | /* 2- If fail try to start with HSE and external xtal */ |
sahilmgandhi | 18:6a4db94011d3 | 342 | #if USE_PLL_HSE_XTAL != 0 |
sahilmgandhi | 18:6a4db94011d3 | 343 | if (SetSysClock_PLL_HSE(0) == 0) |
sahilmgandhi | 18:6a4db94011d3 | 344 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 345 | { |
sahilmgandhi | 18:6a4db94011d3 | 346 | /* 3- If fail start with HSI clock */ |
sahilmgandhi | 18:6a4db94011d3 | 347 | if (SetSysClock_PLL_HSI() == 0) { |
sahilmgandhi | 18:6a4db94011d3 | 348 | while (1) { |
sahilmgandhi | 18:6a4db94011d3 | 349 | // [TODO] Put something here to tell the user that a problem occured... |
sahilmgandhi | 18:6a4db94011d3 | 350 | } |
sahilmgandhi | 18:6a4db94011d3 | 351 | } |
sahilmgandhi | 18:6a4db94011d3 | 352 | } |
sahilmgandhi | 18:6a4db94011d3 | 353 | } |
sahilmgandhi | 18:6a4db94011d3 | 354 | |
sahilmgandhi | 18:6a4db94011d3 | 355 | #if 0 // SYSCLK can be map to PC_9 |
sahilmgandhi | 18:6a4db94011d3 | 356 | HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_2); |
sahilmgandhi | 18:6a4db94011d3 | 357 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 358 | } |
sahilmgandhi | 18:6a4db94011d3 | 359 | |
sahilmgandhi | 18:6a4db94011d3 | 360 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
sahilmgandhi | 18:6a4db94011d3 | 361 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 362 | /* PLL (clocked by HSE) used as System clock source */ |
sahilmgandhi | 18:6a4db94011d3 | 363 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 364 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
sahilmgandhi | 18:6a4db94011d3 | 365 | { |
sahilmgandhi | 18:6a4db94011d3 | 366 | |
sahilmgandhi | 18:6a4db94011d3 | 367 | RCC_OscInitTypeDef RCC_OscInitStruct; |
sahilmgandhi | 18:6a4db94011d3 | 368 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
sahilmgandhi | 18:6a4db94011d3 | 369 | |
sahilmgandhi | 18:6a4db94011d3 | 370 | /* The voltage scaling allows optimizing the power consumption when the device is |
sahilmgandhi | 18:6a4db94011d3 | 371 | clocked below the maximum system frequency, to update the voltage scaling value |
sahilmgandhi | 18:6a4db94011d3 | 372 | regarding system frequency refer to product datasheet. */ |
sahilmgandhi | 18:6a4db94011d3 | 373 | __HAL_RCC_PWR_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 374 | |
sahilmgandhi | 18:6a4db94011d3 | 375 | // Enable HSE oscillator and activate PLL with HSE as source |
sahilmgandhi | 18:6a4db94011d3 | 376 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
sahilmgandhi | 18:6a4db94011d3 | 377 | if (bypass == 0) { |
sahilmgandhi | 18:6a4db94011d3 | 378 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */ |
sahilmgandhi | 18:6a4db94011d3 | 379 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 380 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */ |
sahilmgandhi | 18:6a4db94011d3 | 381 | } |
sahilmgandhi | 18:6a4db94011d3 | 382 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
sahilmgandhi | 18:6a4db94011d3 | 383 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
sahilmgandhi | 18:6a4db94011d3 | 384 | RCC_OscInitStruct.PLL.PLLM = 8; |
sahilmgandhi | 18:6a4db94011d3 | 385 | RCC_OscInitStruct.PLL.PLLN = 240; |
sahilmgandhi | 18:6a4db94011d3 | 386 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; |
sahilmgandhi | 18:6a4db94011d3 | 387 | RCC_OscInitStruct.PLL.PLLQ = 5; |
sahilmgandhi | 18:6a4db94011d3 | 388 | |
sahilmgandhi | 18:6a4db94011d3 | 389 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
sahilmgandhi | 18:6a4db94011d3 | 390 | return 0; // FAIL |
sahilmgandhi | 18:6a4db94011d3 | 391 | } |
sahilmgandhi | 18:6a4db94011d3 | 392 | |
sahilmgandhi | 18:6a4db94011d3 | 393 | |
sahilmgandhi | 18:6a4db94011d3 | 394 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
sahilmgandhi | 18:6a4db94011d3 | 395 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
sahilmgandhi | 18:6a4db94011d3 | 396 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
sahilmgandhi | 18:6a4db94011d3 | 397 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
sahilmgandhi | 18:6a4db94011d3 | 398 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; |
sahilmgandhi | 18:6a4db94011d3 | 399 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; |
sahilmgandhi | 18:6a4db94011d3 | 400 | |
sahilmgandhi | 18:6a4db94011d3 | 401 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { |
sahilmgandhi | 18:6a4db94011d3 | 402 | return 0; // FAIL |
sahilmgandhi | 18:6a4db94011d3 | 403 | } |
sahilmgandhi | 18:6a4db94011d3 | 404 | |
sahilmgandhi | 18:6a4db94011d3 | 405 | return 1; // OK |
sahilmgandhi | 18:6a4db94011d3 | 406 | } |
sahilmgandhi | 18:6a4db94011d3 | 407 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 408 | |
sahilmgandhi | 18:6a4db94011d3 | 409 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 410 | /* PLL (clocked by HSI) used as System clock source */ |
sahilmgandhi | 18:6a4db94011d3 | 411 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 412 | uint8_t SetSysClock_PLL_HSI(void) |
sahilmgandhi | 18:6a4db94011d3 | 413 | { |
sahilmgandhi | 18:6a4db94011d3 | 414 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
sahilmgandhi | 18:6a4db94011d3 | 415 | RCC_OscInitTypeDef RCC_OscInitStruct; |
sahilmgandhi | 18:6a4db94011d3 | 416 | |
sahilmgandhi | 18:6a4db94011d3 | 417 | /* The voltage scaling allows optimizing the power consumption when the device is |
sahilmgandhi | 18:6a4db94011d3 | 418 | clocked below the maximum system frequency, to update the voltage scaling value |
sahilmgandhi | 18:6a4db94011d3 | 419 | regarding system frequency refer to product datasheet. */ |
sahilmgandhi | 18:6a4db94011d3 | 420 | __HAL_RCC_PWR_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 421 | |
sahilmgandhi | 18:6a4db94011d3 | 422 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
sahilmgandhi | 18:6a4db94011d3 | 423 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
sahilmgandhi | 18:6a4db94011d3 | 424 | RCC_OscInitStruct.HSICalibrationValue = 16; |
sahilmgandhi | 18:6a4db94011d3 | 425 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
sahilmgandhi | 18:6a4db94011d3 | 426 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
sahilmgandhi | 18:6a4db94011d3 | 427 | RCC_OscInitStruct.PLL.PLLM = 8; |
sahilmgandhi | 18:6a4db94011d3 | 428 | RCC_OscInitStruct.PLL.PLLN = 192; |
sahilmgandhi | 18:6a4db94011d3 | 429 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; |
sahilmgandhi | 18:6a4db94011d3 | 430 | RCC_OscInitStruct.PLL.PLLQ = 8; |
sahilmgandhi | 18:6a4db94011d3 | 431 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
sahilmgandhi | 18:6a4db94011d3 | 432 | return 0; // FAIL |
sahilmgandhi | 18:6a4db94011d3 | 433 | } |
sahilmgandhi | 18:6a4db94011d3 | 434 | |
sahilmgandhi | 18:6a4db94011d3 | 435 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
sahilmgandhi | 18:6a4db94011d3 | 436 | | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
sahilmgandhi | 18:6a4db94011d3 | 437 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
sahilmgandhi | 18:6a4db94011d3 | 438 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
sahilmgandhi | 18:6a4db94011d3 | 439 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; |
sahilmgandhi | 18:6a4db94011d3 | 440 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; |
sahilmgandhi | 18:6a4db94011d3 | 441 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { |
sahilmgandhi | 18:6a4db94011d3 | 442 | return 0; // FAIL |
sahilmgandhi | 18:6a4db94011d3 | 443 | } |
sahilmgandhi | 18:6a4db94011d3 | 444 | |
sahilmgandhi | 18:6a4db94011d3 | 445 | |
sahilmgandhi | 18:6a4db94011d3 | 446 | return 1; // OK |
sahilmgandhi | 18:6a4db94011d3 | 447 | } |
sahilmgandhi | 18:6a4db94011d3 | 448 | |
sahilmgandhi | 18:6a4db94011d3 | 449 | /** |
sahilmgandhi | 18:6a4db94011d3 | 450 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 451 | */ |
sahilmgandhi | 18:6a4db94011d3 | 452 | |
sahilmgandhi | 18:6a4db94011d3 | 453 | /** |
sahilmgandhi | 18:6a4db94011d3 | 454 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 455 | */ |
sahilmgandhi | 18:6a4db94011d3 | 456 | |
sahilmgandhi | 18:6a4db94011d3 | 457 | /** |
sahilmgandhi | 18:6a4db94011d3 | 458 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 459 | */ |
sahilmgandhi | 18:6a4db94011d3 | 460 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |