MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file system_stm32f0xx.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V2.3.1
sahilmgandhi 18:6a4db94011d3 6 * @date 04-November-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * 1. This file provides two functions and one global variable to be called from
sahilmgandhi 18:6a4db94011d3 10 * user application:
sahilmgandhi 18:6a4db94011d3 11 * - SystemInit(): This function is called at startup just after reset and
sahilmgandhi 18:6a4db94011d3 12 * before branch to main program. This call is made inside
sahilmgandhi 18:6a4db94011d3 13 * the "startup_stm32f0xx.s" file.
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
sahilmgandhi 18:6a4db94011d3 16 * by the user application to setup the SysTick
sahilmgandhi 18:6a4db94011d3 17 * timer or configure other parameters.
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
sahilmgandhi 18:6a4db94011d3 20 * be called whenever the core clock is changed
sahilmgandhi 18:6a4db94011d3 21 * during program execution.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
sahilmgandhi 18:6a4db94011d3 24 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
sahilmgandhi 18:6a4db94011d3 25 * configure the system clock before to branch to main program.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * 3. This file configures the system clock as follows:
sahilmgandhi 18:6a4db94011d3 28 *=============================================================================
sahilmgandhi 18:6a4db94011d3 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
sahilmgandhi 18:6a4db94011d3 30 * | (external 8 MHz clock) | (internal 48 MHz)
sahilmgandhi 18:6a4db94011d3 31 * | 2- PLL_HSE_XTAL |
sahilmgandhi 18:6a4db94011d3 32 * | (external 8 MHz xtal) |
sahilmgandhi 18:6a4db94011d3 33 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 34 * SYSCLK(MHz) | 48 | 48
sahilmgandhi 18:6a4db94011d3 35 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 36 * AHBCLK (MHz) | 48 | 48
sahilmgandhi 18:6a4db94011d3 37 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 38 * APB1CLK (MHz) | 48 | 48
sahilmgandhi 18:6a4db94011d3 39 *-----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 40 * USB capable (48 MHz precise clock) | YES | YES
sahilmgandhi 18:6a4db94011d3 41 *=============================================================================
sahilmgandhi 18:6a4db94011d3 42 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 43 * @attention
sahilmgandhi 18:6a4db94011d3 44 *
sahilmgandhi 18:6a4db94011d3 45 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 46 *
sahilmgandhi 18:6a4db94011d3 47 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 48 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 49 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 50 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 51 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 52 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 53 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 54 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 55 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 56 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 57 *
sahilmgandhi 18:6a4db94011d3 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 68 *
sahilmgandhi 18:6a4db94011d3 69 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 70 */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 /** @addtogroup CMSIS
sahilmgandhi 18:6a4db94011d3 73 * @{
sahilmgandhi 18:6a4db94011d3 74 */
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 /** @addtogroup stm32f0xx_system
sahilmgandhi 18:6a4db94011d3 77 * @{
sahilmgandhi 18:6a4db94011d3 78 */
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 /** @addtogroup STM32F0xx_System_Private_Includes
sahilmgandhi 18:6a4db94011d3 81 * @{
sahilmgandhi 18:6a4db94011d3 82 */
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 #include "stm32f0xx.h"
sahilmgandhi 18:6a4db94011d3 85 #include "hal_tick.h"
sahilmgandhi 18:6a4db94011d3 86 /**
sahilmgandhi 18:6a4db94011d3 87 * @}
sahilmgandhi 18:6a4db94011d3 88 */
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
sahilmgandhi 18:6a4db94011d3 91 * @{
sahilmgandhi 18:6a4db94011d3 92 */
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /**
sahilmgandhi 18:6a4db94011d3 95 * @}
sahilmgandhi 18:6a4db94011d3 96 */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /** @addtogroup STM32F0xx_System_Private_Defines
sahilmgandhi 18:6a4db94011d3 99 * @{
sahilmgandhi 18:6a4db94011d3 100 */
sahilmgandhi 18:6a4db94011d3 101 #if !defined (HSE_VALUE)
sahilmgandhi 18:6a4db94011d3 102 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
sahilmgandhi 18:6a4db94011d3 103 This value can be provided and adapted by the user application. */
sahilmgandhi 18:6a4db94011d3 104 #endif /* HSE_VALUE */
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 #if !defined (HSI_VALUE)
sahilmgandhi 18:6a4db94011d3 107 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
sahilmgandhi 18:6a4db94011d3 108 This value can be provided and adapted by the user application. */
sahilmgandhi 18:6a4db94011d3 109 #endif /* HSI_VALUE */
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 #if !defined (HSI48_VALUE)
sahilmgandhi 18:6a4db94011d3 112 #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
sahilmgandhi 18:6a4db94011d3 113 This value can be provided and adapted by the user application. */
sahilmgandhi 18:6a4db94011d3 114 #endif /* HSI48_VALUE */
sahilmgandhi 18:6a4db94011d3 115 /**
sahilmgandhi 18:6a4db94011d3 116 * @}
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /** @addtogroup STM32F0xx_System_Private_Macros
sahilmgandhi 18:6a4db94011d3 120 * @{
sahilmgandhi 18:6a4db94011d3 121 */
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
sahilmgandhi 18:6a4db94011d3 124 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
sahilmgandhi 18:6a4db94011d3 125 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 /**
sahilmgandhi 18:6a4db94011d3 128 * @}
sahilmgandhi 18:6a4db94011d3 129 */
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /** @addtogroup STM32F0xx_System_Private_Variables
sahilmgandhi 18:6a4db94011d3 132 * @{
sahilmgandhi 18:6a4db94011d3 133 */
sahilmgandhi 18:6a4db94011d3 134 /* This variable is updated in three ways:
sahilmgandhi 18:6a4db94011d3 135 1) by calling CMSIS function SystemCoreClockUpdate()
sahilmgandhi 18:6a4db94011d3 136 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
sahilmgandhi 18:6a4db94011d3 137 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
sahilmgandhi 18:6a4db94011d3 138 Note: If you use this function to configure the system clock there is no need to
sahilmgandhi 18:6a4db94011d3 139 call the 2 first functions listed above, since SystemCoreClock variable is
sahilmgandhi 18:6a4db94011d3 140 updated automatically.
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142 uint32_t SystemCoreClock = 48000000;
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
sahilmgandhi 18:6a4db94011d3 145 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 /**
sahilmgandhi 18:6a4db94011d3 148 * @}
sahilmgandhi 18:6a4db94011d3 149 */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
sahilmgandhi 18:6a4db94011d3 152 * @{
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
sahilmgandhi 18:6a4db94011d3 156 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
sahilmgandhi 18:6a4db94011d3 157 #endif
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 uint8_t SetSysClock_PLL_HSI(void);
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 /**
sahilmgandhi 18:6a4db94011d3 162 * @}
sahilmgandhi 18:6a4db94011d3 163 */
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /** @addtogroup STM32F0xx_System_Private_Functions
sahilmgandhi 18:6a4db94011d3 166 * @{
sahilmgandhi 18:6a4db94011d3 167 */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 /**
sahilmgandhi 18:6a4db94011d3 171 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 172 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
sahilmgandhi 18:6a4db94011d3 173 * @param None
sahilmgandhi 18:6a4db94011d3 174 * @retval None
sahilmgandhi 18:6a4db94011d3 175 */
sahilmgandhi 18:6a4db94011d3 176 void SystemInit(void)
sahilmgandhi 18:6a4db94011d3 177 {
sahilmgandhi 18:6a4db94011d3 178 /* Reset the RCC clock configuration to the default reset state ------------*/
sahilmgandhi 18:6a4db94011d3 179 /* Set HSION bit */
sahilmgandhi 18:6a4db94011d3 180 RCC->CR |= (uint32_t)0x00000001U;
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 #if defined (STM32F051x8) || defined (STM32F058x8)
sahilmgandhi 18:6a4db94011d3 183 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
sahilmgandhi 18:6a4db94011d3 184 RCC->CFGR &= (uint32_t)0xF8FFB80CU;
sahilmgandhi 18:6a4db94011d3 185 #else
sahilmgandhi 18:6a4db94011d3 186 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
sahilmgandhi 18:6a4db94011d3 187 RCC->CFGR &= (uint32_t)0x08FFB80CU;
sahilmgandhi 18:6a4db94011d3 188 #endif /* STM32F051x8 or STM32F058x8 */
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 /* Reset HSEON, CSSON and PLLON bits */
sahilmgandhi 18:6a4db94011d3 191 RCC->CR &= (uint32_t)0xFEF6FFFFU;
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /* Reset HSEBYP bit */
sahilmgandhi 18:6a4db94011d3 194 RCC->CR &= (uint32_t)0xFFFBFFFFU;
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
sahilmgandhi 18:6a4db94011d3 197 RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /* Reset PREDIV[3:0] bits */
sahilmgandhi 18:6a4db94011d3 200 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 #if defined (STM32F072xB) || defined (STM32F078xx)
sahilmgandhi 18:6a4db94011d3 203 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
sahilmgandhi 18:6a4db94011d3 204 RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
sahilmgandhi 18:6a4db94011d3 205 #elif defined (STM32F071xB)
sahilmgandhi 18:6a4db94011d3 206 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
sahilmgandhi 18:6a4db94011d3 207 RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
sahilmgandhi 18:6a4db94011d3 208 #elif defined (STM32F091xC) || defined (STM32F098xx)
sahilmgandhi 18:6a4db94011d3 209 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
sahilmgandhi 18:6a4db94011d3 210 RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
sahilmgandhi 18:6a4db94011d3 211 #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
sahilmgandhi 18:6a4db94011d3 212 /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
sahilmgandhi 18:6a4db94011d3 213 RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
sahilmgandhi 18:6a4db94011d3 214 #elif defined (STM32F051x8) || defined (STM32F058xx)
sahilmgandhi 18:6a4db94011d3 215 /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
sahilmgandhi 18:6a4db94011d3 216 RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
sahilmgandhi 18:6a4db94011d3 217 #elif defined (STM32F042x6) || defined (STM32F048xx)
sahilmgandhi 18:6a4db94011d3 218 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
sahilmgandhi 18:6a4db94011d3 219 RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
sahilmgandhi 18:6a4db94011d3 220 #elif defined (STM32F070x6) || defined (STM32F070xB)
sahilmgandhi 18:6a4db94011d3 221 /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
sahilmgandhi 18:6a4db94011d3 222 RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
sahilmgandhi 18:6a4db94011d3 223 /* Set default USB clock to PLLCLK, since there is no HSI48 */
sahilmgandhi 18:6a4db94011d3 224 RCC->CFGR3 |= (uint32_t)0x00000080U;
sahilmgandhi 18:6a4db94011d3 225 #else
sahilmgandhi 18:6a4db94011d3 226 #warning "No target selected"
sahilmgandhi 18:6a4db94011d3 227 #endif
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 /* Reset HSI14 bit */
sahilmgandhi 18:6a4db94011d3 230 RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /* Disable all interrupts */
sahilmgandhi 18:6a4db94011d3 233 RCC->CIR = 0x00000000U;
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
sahilmgandhi 18:6a4db94011d3 236 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /* Configure the Cube driver */
sahilmgandhi 18:6a4db94011d3 239 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
sahilmgandhi 18:6a4db94011d3 240 HAL_Init();
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 /* Configure the System clock source, PLL Multiplier and Divider factors,
sahilmgandhi 18:6a4db94011d3 243 AHB/APBx prescalers and Flash settings */
sahilmgandhi 18:6a4db94011d3 244 SetSysClock();
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 /* Reset the timer to avoid issues after the RAM initialization */
sahilmgandhi 18:6a4db94011d3 247 TIM_MST_RESET_ON;
sahilmgandhi 18:6a4db94011d3 248 TIM_MST_RESET_OFF;
sahilmgandhi 18:6a4db94011d3 249 }
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /**
sahilmgandhi 18:6a4db94011d3 252 * @brief Update SystemCoreClock variable according to Clock Register Values.
sahilmgandhi 18:6a4db94011d3 253 * The SystemCoreClock variable contains the core clock (HCLK), it can
sahilmgandhi 18:6a4db94011d3 254 * be used by the user application to setup the SysTick timer or configure
sahilmgandhi 18:6a4db94011d3 255 * other parameters.
sahilmgandhi 18:6a4db94011d3 256 *
sahilmgandhi 18:6a4db94011d3 257 * @note Each time the core clock (HCLK) changes, this function must be called
sahilmgandhi 18:6a4db94011d3 258 * to update SystemCoreClock variable value. Otherwise, any configuration
sahilmgandhi 18:6a4db94011d3 259 * based on this variable will be incorrect.
sahilmgandhi 18:6a4db94011d3 260 *
sahilmgandhi 18:6a4db94011d3 261 * @note - The system frequency computed by this function is not the real
sahilmgandhi 18:6a4db94011d3 262 * frequency in the chip. It is calculated based on the predefined
sahilmgandhi 18:6a4db94011d3 263 * constant and the selected clock source:
sahilmgandhi 18:6a4db94011d3 264 *
sahilmgandhi 18:6a4db94011d3 265 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
sahilmgandhi 18:6a4db94011d3 266 *
sahilmgandhi 18:6a4db94011d3 267 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
sahilmgandhi 18:6a4db94011d3 268 *
sahilmgandhi 18:6a4db94011d3 269 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
sahilmgandhi 18:6a4db94011d3 270 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
sahilmgandhi 18:6a4db94011d3 271 *
sahilmgandhi 18:6a4db94011d3 272 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
sahilmgandhi 18:6a4db94011d3 273 * 8 MHz) but the real value may vary depending on the variations
sahilmgandhi 18:6a4db94011d3 274 * in voltage and temperature.
sahilmgandhi 18:6a4db94011d3 275 *
sahilmgandhi 18:6a4db94011d3 276 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
sahilmgandhi 18:6a4db94011d3 277 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
sahilmgandhi 18:6a4db94011d3 278 * frequency of the crystal used. Otherwise, this function may
sahilmgandhi 18:6a4db94011d3 279 * have wrong result.
sahilmgandhi 18:6a4db94011d3 280 *
sahilmgandhi 18:6a4db94011d3 281 * - The result of this function could be not correct when using fractional
sahilmgandhi 18:6a4db94011d3 282 * value for HSE crystal.
sahilmgandhi 18:6a4db94011d3 283 *
sahilmgandhi 18:6a4db94011d3 284 * @param None
sahilmgandhi 18:6a4db94011d3 285 * @retval None
sahilmgandhi 18:6a4db94011d3 286 */
sahilmgandhi 18:6a4db94011d3 287 void SystemCoreClockUpdate (void)
sahilmgandhi 18:6a4db94011d3 288 {
sahilmgandhi 18:6a4db94011d3 289 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /* Get SYSCLK source -------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 292 tmp = RCC->CFGR & RCC_CFGR_SWS;
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 switch (tmp)
sahilmgandhi 18:6a4db94011d3 295 {
sahilmgandhi 18:6a4db94011d3 296 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
sahilmgandhi 18:6a4db94011d3 297 SystemCoreClock = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 298 break;
sahilmgandhi 18:6a4db94011d3 299 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
sahilmgandhi 18:6a4db94011d3 300 SystemCoreClock = HSE_VALUE;
sahilmgandhi 18:6a4db94011d3 301 break;
sahilmgandhi 18:6a4db94011d3 302 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
sahilmgandhi 18:6a4db94011d3 303 /* Get PLL clock source and multiplication factor ----------------------*/
sahilmgandhi 18:6a4db94011d3 304 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
sahilmgandhi 18:6a4db94011d3 305 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
sahilmgandhi 18:6a4db94011d3 306 pllmull = ( pllmull >> 18) + 2;
sahilmgandhi 18:6a4db94011d3 307 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
sahilmgandhi 18:6a4db94011d3 310 {
sahilmgandhi 18:6a4db94011d3 311 /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
sahilmgandhi 18:6a4db94011d3 312 SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
sahilmgandhi 18:6a4db94011d3 313 }
sahilmgandhi 18:6a4db94011d3 314 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
sahilmgandhi 18:6a4db94011d3 315 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
sahilmgandhi 18:6a4db94011d3 316 {
sahilmgandhi 18:6a4db94011d3 317 /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
sahilmgandhi 18:6a4db94011d3 318 SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
sahilmgandhi 18:6a4db94011d3 319 }
sahilmgandhi 18:6a4db94011d3 320 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
sahilmgandhi 18:6a4db94011d3 321 else
sahilmgandhi 18:6a4db94011d3 322 {
sahilmgandhi 18:6a4db94011d3 323 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
sahilmgandhi 18:6a4db94011d3 324 || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
sahilmgandhi 18:6a4db94011d3 325 || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
sahilmgandhi 18:6a4db94011d3 326 /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
sahilmgandhi 18:6a4db94011d3 327 SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
sahilmgandhi 18:6a4db94011d3 328 #else
sahilmgandhi 18:6a4db94011d3 329 /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
sahilmgandhi 18:6a4db94011d3 330 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
sahilmgandhi 18:6a4db94011d3 331 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
sahilmgandhi 18:6a4db94011d3 332 STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
sahilmgandhi 18:6a4db94011d3 333 STM32F091xC || STM32F098xx || STM32F030xC */
sahilmgandhi 18:6a4db94011d3 334 }
sahilmgandhi 18:6a4db94011d3 335 break;
sahilmgandhi 18:6a4db94011d3 336 default: /* HSI used as system clock */
sahilmgandhi 18:6a4db94011d3 337 SystemCoreClock = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 338 break;
sahilmgandhi 18:6a4db94011d3 339 }
sahilmgandhi 18:6a4db94011d3 340 /* Compute HCLK clock frequency ----------------*/
sahilmgandhi 18:6a4db94011d3 341 /* Get HCLK prescaler */
sahilmgandhi 18:6a4db94011d3 342 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
sahilmgandhi 18:6a4db94011d3 343 /* HCLK clock frequency */
sahilmgandhi 18:6a4db94011d3 344 SystemCoreClock >>= tmp;
sahilmgandhi 18:6a4db94011d3 345 }
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 /**
sahilmgandhi 18:6a4db94011d3 348 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
sahilmgandhi 18:6a4db94011d3 349 * AHB/APBx prescalers and Flash settings
sahilmgandhi 18:6a4db94011d3 350 * @note This function should be called only once the RCC clock configuration
sahilmgandhi 18:6a4db94011d3 351 * is reset to the default reset state (done in SystemInit() function).
sahilmgandhi 18:6a4db94011d3 352 * @param None
sahilmgandhi 18:6a4db94011d3 353 * @retval None
sahilmgandhi 18:6a4db94011d3 354 */
sahilmgandhi 18:6a4db94011d3 355 void SetSysClock(void)
sahilmgandhi 18:6a4db94011d3 356 {
sahilmgandhi 18:6a4db94011d3 357 /* 1- Try to start with HSE and external clock */
sahilmgandhi 18:6a4db94011d3 358 #if USE_PLL_HSE_EXTC != 0
sahilmgandhi 18:6a4db94011d3 359 if (SetSysClock_PLL_HSE(1) == 0)
sahilmgandhi 18:6a4db94011d3 360 #endif
sahilmgandhi 18:6a4db94011d3 361 {
sahilmgandhi 18:6a4db94011d3 362 /* 2- If fail try to start with HSE and external xtal */
sahilmgandhi 18:6a4db94011d3 363 #if USE_PLL_HSE_XTAL != 0
sahilmgandhi 18:6a4db94011d3 364 if (SetSysClock_PLL_HSE(0) == 0)
sahilmgandhi 18:6a4db94011d3 365 #endif
sahilmgandhi 18:6a4db94011d3 366 {
sahilmgandhi 18:6a4db94011d3 367 /* 3- If fail start with HSI clock */
sahilmgandhi 18:6a4db94011d3 368 if (SetSysClock_PLL_HSI() == 0)
sahilmgandhi 18:6a4db94011d3 369 {
sahilmgandhi 18:6a4db94011d3 370 while(1)
sahilmgandhi 18:6a4db94011d3 371 {
sahilmgandhi 18:6a4db94011d3 372 // [TODO] Put something here to tell the user that a problem occured...
sahilmgandhi 18:6a4db94011d3 373 }
sahilmgandhi 18:6a4db94011d3 374 }
sahilmgandhi 18:6a4db94011d3 375 }
sahilmgandhi 18:6a4db94011d3 376 }
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 // Output clock on MCO pin(PA8) for debugging purpose
sahilmgandhi 18:6a4db94011d3 379 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
sahilmgandhi 18:6a4db94011d3 380 }
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
sahilmgandhi 18:6a4db94011d3 383 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 384 /* PLL (clocked by HSE) used as System clock source */
sahilmgandhi 18:6a4db94011d3 385 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 386 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
sahilmgandhi 18:6a4db94011d3 387 {
sahilmgandhi 18:6a4db94011d3 388 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
sahilmgandhi 18:6a4db94011d3 389 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
sahilmgandhi 18:6a4db94011d3 390 //Select HSI as system clock source to allow modification of the PLL configuration
sahilmgandhi 18:6a4db94011d3 391 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
sahilmgandhi 18:6a4db94011d3 392 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
sahilmgandhi 18:6a4db94011d3 393 if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 394 {
sahilmgandhi 18:6a4db94011d3 395 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 396 }
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398
sahilmgandhi 18:6a4db94011d3 399 // Select HSE oscillator as PLL source
sahilmgandhi 18:6a4db94011d3 400 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
sahilmgandhi 18:6a4db94011d3 401 if (bypass == 0) {
sahilmgandhi 18:6a4db94011d3 402 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
sahilmgandhi 18:6a4db94011d3 403 } else {
sahilmgandhi 18:6a4db94011d3 404 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
sahilmgandhi 18:6a4db94011d3 407 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
sahilmgandhi 18:6a4db94011d3 408 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
sahilmgandhi 18:6a4db94011d3 409 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
sahilmgandhi 18:6a4db94011d3 410 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
sahilmgandhi 18:6a4db94011d3 411 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 412 }
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
sahilmgandhi 18:6a4db94011d3 415 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
sahilmgandhi 18:6a4db94011d3 416 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
sahilmgandhi 18:6a4db94011d3 417 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
sahilmgandhi 18:6a4db94011d3 418 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
sahilmgandhi 18:6a4db94011d3 419 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
sahilmgandhi 18:6a4db94011d3 420 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 421 }
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 return 1; // OK
sahilmgandhi 18:6a4db94011d3 426 }
sahilmgandhi 18:6a4db94011d3 427 #endif
sahilmgandhi 18:6a4db94011d3 428
sahilmgandhi 18:6a4db94011d3 429 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 430 /* PLL (clocked by HSI) used as System clock source */
sahilmgandhi 18:6a4db94011d3 431 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 432 uint8_t SetSysClock_PLL_HSI(void)
sahilmgandhi 18:6a4db94011d3 433 {
sahilmgandhi 18:6a4db94011d3 434 RCC_ClkInitTypeDef RCC_ClkInitStruct;
sahilmgandhi 18:6a4db94011d3 435 RCC_OscInitTypeDef RCC_OscInitStruct;
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
sahilmgandhi 18:6a4db94011d3 438 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
sahilmgandhi 18:6a4db94011d3 439 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
sahilmgandhi 18:6a4db94011d3 440 RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
sahilmgandhi 18:6a4db94011d3 441 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
sahilmgandhi 18:6a4db94011d3 442 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
sahilmgandhi 18:6a4db94011d3 443 RCC_OscInitStruct.HSI14State = RCC_HSI_OFF;
sahilmgandhi 18:6a4db94011d3 444 RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
sahilmgandhi 18:6a4db94011d3 445 RCC_OscInitStruct.HSI48State = RCC_HSI_ON;
sahilmgandhi 18:6a4db94011d3 446 RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
sahilmgandhi 18:6a4db94011d3 447 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
sahilmgandhi 18:6a4db94011d3 448 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
sahilmgandhi 18:6a4db94011d3 449 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
sahilmgandhi 18:6a4db94011d3 450 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
sahilmgandhi 18:6a4db94011d3 451 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
sahilmgandhi 18:6a4db94011d3 452 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 453 }
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
sahilmgandhi 18:6a4db94011d3 456 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
sahilmgandhi 18:6a4db94011d3 457 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
sahilmgandhi 18:6a4db94011d3 458 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
sahilmgandhi 18:6a4db94011d3 459 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
sahilmgandhi 18:6a4db94011d3 460 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
sahilmgandhi 18:6a4db94011d3 461 return 0; // FAIL
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 return 1; // OK
sahilmgandhi 18:6a4db94011d3 467 }
sahilmgandhi 18:6a4db94011d3 468
sahilmgandhi 18:6a4db94011d3 469 /**
sahilmgandhi 18:6a4db94011d3 470 * @}
sahilmgandhi 18:6a4db94011d3 471 */
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 /**
sahilmgandhi 18:6a4db94011d3 474 * @}
sahilmgandhi 18:6a4db94011d3 475 */
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /**
sahilmgandhi 18:6a4db94011d3 478 * @}
sahilmgandhi 18:6a4db94011d3 479 */
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
sahilmgandhi 18:6a4db94011d3 482