MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f051x8.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V2.3.1
sahilmgandhi 18:6a4db94011d3 6 * @date 04-November-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
sahilmgandhi 18:6a4db94011d3 8 * This file contains all the peripheral register's definitions, bits
sahilmgandhi 18:6a4db94011d3 9 * definitions and memory mapping for STM32F0xx devices.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * This file contains:
sahilmgandhi 18:6a4db94011d3 12 * - Data structures and the address mapping for all peripherals
sahilmgandhi 18:6a4db94011d3 13 * - Peripheral's registers declarations and bits definition
sahilmgandhi 18:6a4db94011d3 14 * - Macros to access peripheral’s registers hardware
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 17 * @attention
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 22 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 23 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 24 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 26 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 27 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 29 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 30 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 31 *
sahilmgandhi 18:6a4db94011d3 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 44 */
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /** @addtogroup CMSIS
sahilmgandhi 18:6a4db94011d3 47 * @{
sahilmgandhi 18:6a4db94011d3 48 */
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /** @addtogroup stm32f051x8
sahilmgandhi 18:6a4db94011d3 51 * @{
sahilmgandhi 18:6a4db94011d3 52 */
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 #ifndef __STM32F051x8_H
sahilmgandhi 18:6a4db94011d3 55 #define __STM32F051x8_H
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 58 extern "C" {
sahilmgandhi 18:6a4db94011d3 59 #endif /* __cplusplus */
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 /** @addtogroup Configuration_section_for_CMSIS
sahilmgandhi 18:6a4db94011d3 62 * @{
sahilmgandhi 18:6a4db94011d3 63 */
sahilmgandhi 18:6a4db94011d3 64 /**
sahilmgandhi 18:6a4db94011d3 65 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67 #define __CM0_REV 0 /*!< Core Revision r0p0 */
sahilmgandhi 18:6a4db94011d3 68 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
sahilmgandhi 18:6a4db94011d3 69 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
sahilmgandhi 18:6a4db94011d3 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 /**
sahilmgandhi 18:6a4db94011d3 73 * @}
sahilmgandhi 18:6a4db94011d3 74 */
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 /** @addtogroup Peripheral_interrupt_number_definition
sahilmgandhi 18:6a4db94011d3 77 * @{
sahilmgandhi 18:6a4db94011d3 78 */
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 /**
sahilmgandhi 18:6a4db94011d3 81 * @brief STM32F0xx Interrupt Number Definition, according to the selected device
sahilmgandhi 18:6a4db94011d3 82 * in @ref Library_configuration_section
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /*!< Interrupt Number Definition */
sahilmgandhi 18:6a4db94011d3 86 typedef enum
sahilmgandhi 18:6a4db94011d3 87 {
sahilmgandhi 18:6a4db94011d3 88 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
sahilmgandhi 18:6a4db94011d3 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 90 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 91 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 92 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 93 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /****** STM32F0 specific Interrupt Numbers ******************************************************************/
sahilmgandhi 18:6a4db94011d3 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
sahilmgandhi 18:6a4db94011d3 97 PVD_IRQn = 1, /*!< PVD Interrupt through EXTI Lines 16 */
sahilmgandhi 18:6a4db94011d3 98 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
sahilmgandhi 18:6a4db94011d3 99 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
sahilmgandhi 18:6a4db94011d3 100 RCC_IRQn = 4, /*!< RCC global Interrupt */
sahilmgandhi 18:6a4db94011d3 101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */
sahilmgandhi 18:6a4db94011d3 103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */
sahilmgandhi 18:6a4db94011d3 104 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
sahilmgandhi 18:6a4db94011d3 105 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 106 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */
sahilmgandhi 18:6a4db94011d3 107 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */
sahilmgandhi 18:6a4db94011d3 108 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
sahilmgandhi 18:6a4db94011d3 109 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */
sahilmgandhi 18:6a4db94011d3 110 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
sahilmgandhi 18:6a4db94011d3 111 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 112 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 113 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupt */
sahilmgandhi 18:6a4db94011d3 114 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
sahilmgandhi 18:6a4db94011d3 115 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
sahilmgandhi 18:6a4db94011d3 116 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
sahilmgandhi 18:6a4db94011d3 117 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
sahilmgandhi 18:6a4db94011d3 118 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
sahilmgandhi 18:6a4db94011d3 119 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
sahilmgandhi 18:6a4db94011d3 120 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 121 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 122 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
sahilmgandhi 18:6a4db94011d3 123 USART2_IRQn = 28, /*!< USART2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 124 CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
sahilmgandhi 18:6a4db94011d3 125 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 /**
sahilmgandhi 18:6a4db94011d3 128 * @}
sahilmgandhi 18:6a4db94011d3 129 */
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 132 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
sahilmgandhi 18:6a4db94011d3 133 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 /** @addtogroup Peripheral_registers_structures
sahilmgandhi 18:6a4db94011d3 136 * @{
sahilmgandhi 18:6a4db94011d3 137 */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /**
sahilmgandhi 18:6a4db94011d3 140 * @brief Analog to Digital Converter
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 typedef struct
sahilmgandhi 18:6a4db94011d3 144 {
sahilmgandhi 18:6a4db94011d3 145 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 146 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 147 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 148 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 149 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 150 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 151 uint32_t RESERVED1; /*!< Reserved, 0x18 */
sahilmgandhi 18:6a4db94011d3 152 uint32_t RESERVED2; /*!< Reserved, 0x1C */
sahilmgandhi 18:6a4db94011d3 153 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 154 uint32_t RESERVED3; /*!< Reserved, 0x24 */
sahilmgandhi 18:6a4db94011d3 155 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 156 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
sahilmgandhi 18:6a4db94011d3 157 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 158 } ADC_TypeDef;
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 typedef struct
sahilmgandhi 18:6a4db94011d3 161 {
sahilmgandhi 18:6a4db94011d3 162 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
sahilmgandhi 18:6a4db94011d3 163 } ADC_Common_TypeDef;
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /**
sahilmgandhi 18:6a4db94011d3 166 * @brief HDMI-CEC
sahilmgandhi 18:6a4db94011d3 167 */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 typedef struct
sahilmgandhi 18:6a4db94011d3 170 {
sahilmgandhi 18:6a4db94011d3 171 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
sahilmgandhi 18:6a4db94011d3 172 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
sahilmgandhi 18:6a4db94011d3 173 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
sahilmgandhi 18:6a4db94011d3 174 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
sahilmgandhi 18:6a4db94011d3 175 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
sahilmgandhi 18:6a4db94011d3 176 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
sahilmgandhi 18:6a4db94011d3 177 }CEC_TypeDef;
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /**
sahilmgandhi 18:6a4db94011d3 180 * @brief Comparator
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 typedef struct
sahilmgandhi 18:6a4db94011d3 184 {
sahilmgandhi 18:6a4db94011d3 185 __IO uint16_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 186 } COMP_TypeDef;
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 typedef struct
sahilmgandhi 18:6a4db94011d3 189 {
sahilmgandhi 18:6a4db94011d3 190 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 191 } COMP_Common_TypeDef;
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 194 typedef struct
sahilmgandhi 18:6a4db94011d3 195 {
sahilmgandhi 18:6a4db94011d3 196 __IO uint32_t CSR; /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */
sahilmgandhi 18:6a4db94011d3 197 }COMP1_2_TypeDef;
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /**
sahilmgandhi 18:6a4db94011d3 200 * @brief CRC calculation unit
sahilmgandhi 18:6a4db94011d3 201 */
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 typedef struct
sahilmgandhi 18:6a4db94011d3 204 {
sahilmgandhi 18:6a4db94011d3 205 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 206 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 207 uint8_t RESERVED0; /*!< Reserved, 0x05 */
sahilmgandhi 18:6a4db94011d3 208 uint16_t RESERVED1; /*!< Reserved, 0x06 */
sahilmgandhi 18:6a4db94011d3 209 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 210 uint32_t RESERVED2; /*!< Reserved, 0x0C */
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 212 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */
sahilmgandhi 18:6a4db94011d3 213 } CRC_TypeDef;
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 /**
sahilmgandhi 18:6a4db94011d3 216 * @brief Digital to Analog Converter
sahilmgandhi 18:6a4db94011d3 217 */
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 typedef struct
sahilmgandhi 18:6a4db94011d3 220 {
sahilmgandhi 18:6a4db94011d3 221 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 222 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 223 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 224 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 226 uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x14 to 0x28 */
sahilmgandhi 18:6a4db94011d3 227 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 228 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 229 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 230 } DAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /**
sahilmgandhi 18:6a4db94011d3 233 * @brief Debug MCU
sahilmgandhi 18:6a4db94011d3 234 */
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 typedef struct
sahilmgandhi 18:6a4db94011d3 237 {
sahilmgandhi 18:6a4db94011d3 238 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 239 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 240 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 241 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 242 }DBGMCU_TypeDef;
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /**
sahilmgandhi 18:6a4db94011d3 245 * @brief DMA Controller
sahilmgandhi 18:6a4db94011d3 246 */
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 typedef struct
sahilmgandhi 18:6a4db94011d3 249 {
sahilmgandhi 18:6a4db94011d3 250 __IO uint32_t CCR; /*!< DMA channel x configuration register */
sahilmgandhi 18:6a4db94011d3 251 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
sahilmgandhi 18:6a4db94011d3 252 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
sahilmgandhi 18:6a4db94011d3 253 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
sahilmgandhi 18:6a4db94011d3 254 } DMA_Channel_TypeDef;
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 typedef struct
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 259 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 260 } DMA_TypeDef;
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /**
sahilmgandhi 18:6a4db94011d3 263 * @brief External Interrupt/Event Controller
sahilmgandhi 18:6a4db94011d3 264 */
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 typedef struct
sahilmgandhi 18:6a4db94011d3 267 {
sahilmgandhi 18:6a4db94011d3 268 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 269 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 270 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 271 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 272 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 273 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 274 } EXTI_TypeDef;
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 /**
sahilmgandhi 18:6a4db94011d3 277 * @brief FLASH Registers
sahilmgandhi 18:6a4db94011d3 278 */
sahilmgandhi 18:6a4db94011d3 279 typedef struct
sahilmgandhi 18:6a4db94011d3 280 {
sahilmgandhi 18:6a4db94011d3 281 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 282 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 283 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 284 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 285 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 286 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 287 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
sahilmgandhi 18:6a4db94011d3 288 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 289 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 290 } FLASH_TypeDef;
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 /**
sahilmgandhi 18:6a4db94011d3 293 * @brief Option Bytes Registers
sahilmgandhi 18:6a4db94011d3 294 */
sahilmgandhi 18:6a4db94011d3 295 typedef struct
sahilmgandhi 18:6a4db94011d3 296 {
sahilmgandhi 18:6a4db94011d3 297 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 298 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
sahilmgandhi 18:6a4db94011d3 299 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 300 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
sahilmgandhi 18:6a4db94011d3 301 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 302 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
sahilmgandhi 18:6a4db94011d3 303 } OB_TypeDef;
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /**
sahilmgandhi 18:6a4db94011d3 306 * @brief General Purpose I/O
sahilmgandhi 18:6a4db94011d3 307 */
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 typedef struct
sahilmgandhi 18:6a4db94011d3 310 {
sahilmgandhi 18:6a4db94011d3 311 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 312 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 313 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 314 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 315 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 316 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 317 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
sahilmgandhi 18:6a4db94011d3 318 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 319 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
sahilmgandhi 18:6a4db94011d3 320 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 321 } GPIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 /**
sahilmgandhi 18:6a4db94011d3 324 * @brief SysTem Configuration
sahilmgandhi 18:6a4db94011d3 325 */
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 typedef struct
sahilmgandhi 18:6a4db94011d3 328 {
sahilmgandhi 18:6a4db94011d3 329 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 330 uint32_t RESERVED; /*!< Reserved, 0x04 */
sahilmgandhi 18:6a4db94011d3 331 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
sahilmgandhi 18:6a4db94011d3 332 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 333 } SYSCFG_TypeDef;
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 /**
sahilmgandhi 18:6a4db94011d3 336 * @brief Inter-integrated Circuit Interface
sahilmgandhi 18:6a4db94011d3 337 */
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 typedef struct
sahilmgandhi 18:6a4db94011d3 340 {
sahilmgandhi 18:6a4db94011d3 341 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 342 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 343 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 344 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 345 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 346 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 347 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 348 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 349 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 350 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 351 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 352 } I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 /**
sahilmgandhi 18:6a4db94011d3 355 * @brief Independent WATCHDOG
sahilmgandhi 18:6a4db94011d3 356 */
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 typedef struct
sahilmgandhi 18:6a4db94011d3 359 {
sahilmgandhi 18:6a4db94011d3 360 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 364 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 365 } IWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 /**
sahilmgandhi 18:6a4db94011d3 368 * @brief Power Control
sahilmgandhi 18:6a4db94011d3 369 */
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 typedef struct
sahilmgandhi 18:6a4db94011d3 372 {
sahilmgandhi 18:6a4db94011d3 373 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 374 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 375 } PWR_TypeDef;
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 /**
sahilmgandhi 18:6a4db94011d3 378 * @brief Reset and Clock Control
sahilmgandhi 18:6a4db94011d3 379 */
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 typedef struct
sahilmgandhi 18:6a4db94011d3 382 {
sahilmgandhi 18:6a4db94011d3 383 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 384 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 385 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 386 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 387 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 388 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 389 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 390 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 391 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 392 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 393 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 394 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 395 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 396 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 397 } RCC_TypeDef;
sahilmgandhi 18:6a4db94011d3 398
sahilmgandhi 18:6a4db94011d3 399 /**
sahilmgandhi 18:6a4db94011d3 400 * @brief Real-Time Clock
sahilmgandhi 18:6a4db94011d3 401 */
sahilmgandhi 18:6a4db94011d3 402 typedef struct
sahilmgandhi 18:6a4db94011d3 403 {
sahilmgandhi 18:6a4db94011d3 404 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 405 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 406 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 407 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 408 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 409 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 410 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 411 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 412 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 414 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 415 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 416 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 417 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 418 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 419 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 420 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 421 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 422 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 423 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 424 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 425 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 426 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 427 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
sahilmgandhi 18:6a4db94011d3 428 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 429 } RTC_TypeDef;
sahilmgandhi 18:6a4db94011d3 430
sahilmgandhi 18:6a4db94011d3 431 /**
sahilmgandhi 18:6a4db94011d3 432 * @brief Serial Peripheral Interface
sahilmgandhi 18:6a4db94011d3 433 */
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 typedef struct
sahilmgandhi 18:6a4db94011d3 436 {
sahilmgandhi 18:6a4db94011d3 437 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 438 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 439 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 440 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 441 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 442 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 443 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 444 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 445 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 446 } SPI_TypeDef;
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /**
sahilmgandhi 18:6a4db94011d3 449 * @brief TIM
sahilmgandhi 18:6a4db94011d3 450 */
sahilmgandhi 18:6a4db94011d3 451 typedef struct
sahilmgandhi 18:6a4db94011d3 452 {
sahilmgandhi 18:6a4db94011d3 453 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 454 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 455 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 456 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 457 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 458 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 459 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 460 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 461 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 462 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 463 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 464 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 465 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 466 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 467 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 468 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 469 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 470 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 471 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 472 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 473 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 474 } TIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 /**
sahilmgandhi 18:6a4db94011d3 477 * @brief Touch Sensing Controller (TSC)
sahilmgandhi 18:6a4db94011d3 478 */
sahilmgandhi 18:6a4db94011d3 479 typedef struct
sahilmgandhi 18:6a4db94011d3 480 {
sahilmgandhi 18:6a4db94011d3 481 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 482 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 483 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 485 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 486 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 487 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 488 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 489 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 490 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 491 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 492 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 493 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
sahilmgandhi 18:6a4db94011d3 495 }TSC_TypeDef;
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 /**
sahilmgandhi 18:6a4db94011d3 498 * @brief Universal Synchronous Asynchronous Receiver Transmitter
sahilmgandhi 18:6a4db94011d3 499 */
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 typedef struct
sahilmgandhi 18:6a4db94011d3 502 {
sahilmgandhi 18:6a4db94011d3 503 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 504 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 505 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 506 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 507 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 508 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 509 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 510 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 511 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 512 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 513 uint16_t RESERVED1; /*!< Reserved, 0x26 */
sahilmgandhi 18:6a4db94011d3 514 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 515 uint16_t RESERVED2; /*!< Reserved, 0x2A */
sahilmgandhi 18:6a4db94011d3 516 } USART_TypeDef;
sahilmgandhi 18:6a4db94011d3 517
sahilmgandhi 18:6a4db94011d3 518 /**
sahilmgandhi 18:6a4db94011d3 519 * @brief Window WATCHDOG
sahilmgandhi 18:6a4db94011d3 520 */
sahilmgandhi 18:6a4db94011d3 521 typedef struct
sahilmgandhi 18:6a4db94011d3 522 {
sahilmgandhi 18:6a4db94011d3 523 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 524 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 525 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 526 } WWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 527
sahilmgandhi 18:6a4db94011d3 528 /**
sahilmgandhi 18:6a4db94011d3 529 * @}
sahilmgandhi 18:6a4db94011d3 530 */
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 /** @addtogroup Peripheral_memory_map
sahilmgandhi 18:6a4db94011d3 533 * @{
sahilmgandhi 18:6a4db94011d3 534 */
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
sahilmgandhi 18:6a4db94011d3 537 #define FLASH_BANK1_END ((uint32_t)0x0800FFFFU) /*!< FLASH END address of bank1 */
sahilmgandhi 18:6a4db94011d3 538 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
sahilmgandhi 18:6a4db94011d3 539 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 /*!< Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 542 #define APBPERIPH_BASE PERIPH_BASE
sahilmgandhi 18:6a4db94011d3 543 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
sahilmgandhi 18:6a4db94011d3 544 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 /*!< APB peripherals */
sahilmgandhi 18:6a4db94011d3 547 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
sahilmgandhi 18:6a4db94011d3 548 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
sahilmgandhi 18:6a4db94011d3 549 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
sahilmgandhi 18:6a4db94011d3 550 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
sahilmgandhi 18:6a4db94011d3 551 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
sahilmgandhi 18:6a4db94011d3 552 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
sahilmgandhi 18:6a4db94011d3 553 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
sahilmgandhi 18:6a4db94011d3 554 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
sahilmgandhi 18:6a4db94011d3 555 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
sahilmgandhi 18:6a4db94011d3 556 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
sahilmgandhi 18:6a4db94011d3 557 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
sahilmgandhi 18:6a4db94011d3 558 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
sahilmgandhi 18:6a4db94011d3 559 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
sahilmgandhi 18:6a4db94011d3 564 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
sahilmgandhi 18:6a4db94011d3 565 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
sahilmgandhi 18:6a4db94011d3 566 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
sahilmgandhi 18:6a4db94011d3 567 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
sahilmgandhi 18:6a4db94011d3 568 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
sahilmgandhi 18:6a4db94011d3 569 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
sahilmgandhi 18:6a4db94011d3 570 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
sahilmgandhi 18:6a4db94011d3 571 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
sahilmgandhi 18:6a4db94011d3 572 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
sahilmgandhi 18:6a4db94011d3 573 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
sahilmgandhi 18:6a4db94011d3 574 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 /*!< AHB peripherals */
sahilmgandhi 18:6a4db94011d3 577 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
sahilmgandhi 18:6a4db94011d3 578 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
sahilmgandhi 18:6a4db94011d3 579 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
sahilmgandhi 18:6a4db94011d3 580 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
sahilmgandhi 18:6a4db94011d3 581 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
sahilmgandhi 18:6a4db94011d3 582 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
sahilmgandhi 18:6a4db94011d3 585 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
sahilmgandhi 18:6a4db94011d3 586 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< FLASH Option Bytes base address */
sahilmgandhi 18:6a4db94011d3 587 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
sahilmgandhi 18:6a4db94011d3 588 #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
sahilmgandhi 18:6a4db94011d3 589 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
sahilmgandhi 18:6a4db94011d3 590 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
sahilmgandhi 18:6a4db94011d3 591
sahilmgandhi 18:6a4db94011d3 592 /*!< AHB2 peripherals */
sahilmgandhi 18:6a4db94011d3 593 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
sahilmgandhi 18:6a4db94011d3 594 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
sahilmgandhi 18:6a4db94011d3 595 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
sahilmgandhi 18:6a4db94011d3 596 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
sahilmgandhi 18:6a4db94011d3 597 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 /**
sahilmgandhi 18:6a4db94011d3 600 * @}
sahilmgandhi 18:6a4db94011d3 601 */
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 /** @addtogroup Peripheral_declaration
sahilmgandhi 18:6a4db94011d3 604 * @{
sahilmgandhi 18:6a4db94011d3 605 */
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
sahilmgandhi 18:6a4db94011d3 608 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
sahilmgandhi 18:6a4db94011d3 609 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
sahilmgandhi 18:6a4db94011d3 610 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
sahilmgandhi 18:6a4db94011d3 611 #define RTC ((RTC_TypeDef *) RTC_BASE)
sahilmgandhi 18:6a4db94011d3 612 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
sahilmgandhi 18:6a4db94011d3 613 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
sahilmgandhi 18:6a4db94011d3 614 #define USART2 ((USART_TypeDef *) USART2_BASE)
sahilmgandhi 18:6a4db94011d3 615 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 616 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
sahilmgandhi 18:6a4db94011d3 617 #define PWR ((PWR_TypeDef *) PWR_BASE)
sahilmgandhi 18:6a4db94011d3 618 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
sahilmgandhi 18:6a4db94011d3 619 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
sahilmgandhi 18:6a4db94011d3 620 #define CEC ((CEC_TypeDef *) CEC_BASE)
sahilmgandhi 18:6a4db94011d3 621 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
sahilmgandhi 18:6a4db94011d3 622 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
sahilmgandhi 18:6a4db94011d3 623 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
sahilmgandhi 18:6a4db94011d3 624 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE)
sahilmgandhi 18:6a4db94011d3 625 #define COMP ((COMP1_2_TypeDef *) COMP_BASE) /* Kept for legacy purpose */
sahilmgandhi 18:6a4db94011d3 626 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
sahilmgandhi 18:6a4db94011d3 627 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
sahilmgandhi 18:6a4db94011d3 628 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
sahilmgandhi 18:6a4db94011d3 629 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
sahilmgandhi 18:6a4db94011d3 630 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
sahilmgandhi 18:6a4db94011d3 631 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 632 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
sahilmgandhi 18:6a4db94011d3 633 #define USART1 ((USART_TypeDef *) USART1_BASE)
sahilmgandhi 18:6a4db94011d3 634 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
sahilmgandhi 18:6a4db94011d3 635 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
sahilmgandhi 18:6a4db94011d3 636 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
sahilmgandhi 18:6a4db94011d3 637 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
sahilmgandhi 18:6a4db94011d3 638 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
sahilmgandhi 18:6a4db94011d3 639 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
sahilmgandhi 18:6a4db94011d3 640 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
sahilmgandhi 18:6a4db94011d3 641 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
sahilmgandhi 18:6a4db94011d3 642 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
sahilmgandhi 18:6a4db94011d3 643 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
sahilmgandhi 18:6a4db94011d3 644 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
sahilmgandhi 18:6a4db94011d3 645 #define OB ((OB_TypeDef *) OB_BASE)
sahilmgandhi 18:6a4db94011d3 646 #define RCC ((RCC_TypeDef *) RCC_BASE)
sahilmgandhi 18:6a4db94011d3 647 #define CRC ((CRC_TypeDef *) CRC_BASE)
sahilmgandhi 18:6a4db94011d3 648 #define TSC ((TSC_TypeDef *) TSC_BASE)
sahilmgandhi 18:6a4db94011d3 649 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
sahilmgandhi 18:6a4db94011d3 650 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
sahilmgandhi 18:6a4db94011d3 651 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
sahilmgandhi 18:6a4db94011d3 652 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
sahilmgandhi 18:6a4db94011d3 653 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
sahilmgandhi 18:6a4db94011d3 654 /**
sahilmgandhi 18:6a4db94011d3 655 * @}
sahilmgandhi 18:6a4db94011d3 656 */
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 /** @addtogroup Exported_constants
sahilmgandhi 18:6a4db94011d3 659 * @{
sahilmgandhi 18:6a4db94011d3 660 */
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 /** @addtogroup Peripheral_Registers_Bits_Definition
sahilmgandhi 18:6a4db94011d3 663 * @{
sahilmgandhi 18:6a4db94011d3 664 */
sahilmgandhi 18:6a4db94011d3 665
sahilmgandhi 18:6a4db94011d3 666 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 667 /* Peripheral Registers Bits Definition */
sahilmgandhi 18:6a4db94011d3 668 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 671 /* */
sahilmgandhi 18:6a4db94011d3 672 /* Analog to Digital Converter (ADC) */
sahilmgandhi 18:6a4db94011d3 673 /* */
sahilmgandhi 18:6a4db94011d3 674 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 /*
sahilmgandhi 18:6a4db94011d3 677 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
sahilmgandhi 18:6a4db94011d3 678 */
sahilmgandhi 18:6a4db94011d3 679 #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */
sahilmgandhi 18:6a4db94011d3 680
sahilmgandhi 18:6a4db94011d3 681 /******************** Bits definition for ADC_ISR register ******************/
sahilmgandhi 18:6a4db94011d3 682 #define ADC_ISR_ADRDY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 683 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 684 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
sahilmgandhi 18:6a4db94011d3 685 #define ADC_ISR_EOSMP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 686 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 687 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
sahilmgandhi 18:6a4db94011d3 688 #define ADC_ISR_EOC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 689 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 690 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
sahilmgandhi 18:6a4db94011d3 691 #define ADC_ISR_EOS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 692 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 693 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
sahilmgandhi 18:6a4db94011d3 694 #define ADC_ISR_OVR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 695 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 696 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
sahilmgandhi 18:6a4db94011d3 697 #define ADC_ISR_AWD1_Pos (7U)
sahilmgandhi 18:6a4db94011d3 698 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 699 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
sahilmgandhi 18:6a4db94011d3 700
sahilmgandhi 18:6a4db94011d3 701 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 702 #define ADC_ISR_AWD (ADC_ISR_AWD1)
sahilmgandhi 18:6a4db94011d3 703 #define ADC_ISR_EOSEQ (ADC_ISR_EOS)
sahilmgandhi 18:6a4db94011d3 704
sahilmgandhi 18:6a4db94011d3 705 /******************** Bits definition for ADC_IER register ******************/
sahilmgandhi 18:6a4db94011d3 706 #define ADC_IER_ADRDYIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 707 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 708 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
sahilmgandhi 18:6a4db94011d3 709 #define ADC_IER_EOSMPIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 710 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 711 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
sahilmgandhi 18:6a4db94011d3 712 #define ADC_IER_EOCIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 713 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 714 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
sahilmgandhi 18:6a4db94011d3 715 #define ADC_IER_EOSIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 716 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 717 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
sahilmgandhi 18:6a4db94011d3 718 #define ADC_IER_OVRIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 719 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 720 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
sahilmgandhi 18:6a4db94011d3 721 #define ADC_IER_AWD1IE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 722 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 723 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
sahilmgandhi 18:6a4db94011d3 724
sahilmgandhi 18:6a4db94011d3 725 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 726 #define ADC_IER_AWDIE (ADC_IER_AWD1IE)
sahilmgandhi 18:6a4db94011d3 727 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
sahilmgandhi 18:6a4db94011d3 728
sahilmgandhi 18:6a4db94011d3 729 /******************** Bits definition for ADC_CR register *******************/
sahilmgandhi 18:6a4db94011d3 730 #define ADC_CR_ADEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 731 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 732 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
sahilmgandhi 18:6a4db94011d3 733 #define ADC_CR_ADDIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 734 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 735 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
sahilmgandhi 18:6a4db94011d3 736 #define ADC_CR_ADSTART_Pos (2U)
sahilmgandhi 18:6a4db94011d3 737 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 738 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
sahilmgandhi 18:6a4db94011d3 739 #define ADC_CR_ADSTP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 740 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 741 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
sahilmgandhi 18:6a4db94011d3 742 #define ADC_CR_ADCAL_Pos (31U)
sahilmgandhi 18:6a4db94011d3 743 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 744 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 /******************* Bits definition for ADC_CFGR1 register *****************/
sahilmgandhi 18:6a4db94011d3 747 #define ADC_CFGR1_DMAEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 748 #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 749 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
sahilmgandhi 18:6a4db94011d3 750 #define ADC_CFGR1_DMACFG_Pos (1U)
sahilmgandhi 18:6a4db94011d3 751 #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 752 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
sahilmgandhi 18:6a4db94011d3 753 #define ADC_CFGR1_SCANDIR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 754 #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 755 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
sahilmgandhi 18:6a4db94011d3 756
sahilmgandhi 18:6a4db94011d3 757 #define ADC_CFGR1_RES_Pos (3U)
sahilmgandhi 18:6a4db94011d3 758 #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
sahilmgandhi 18:6a4db94011d3 759 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
sahilmgandhi 18:6a4db94011d3 760 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 761 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 #define ADC_CFGR1_ALIGN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 764 #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 765 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
sahilmgandhi 18:6a4db94011d3 766
sahilmgandhi 18:6a4db94011d3 767 #define ADC_CFGR1_EXTSEL_Pos (6U)
sahilmgandhi 18:6a4db94011d3 768 #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
sahilmgandhi 18:6a4db94011d3 769 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
sahilmgandhi 18:6a4db94011d3 770 #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 771 #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 772 #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 #define ADC_CFGR1_EXTEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 775 #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 776 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
sahilmgandhi 18:6a4db94011d3 777 #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 778 #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 779
sahilmgandhi 18:6a4db94011d3 780 #define ADC_CFGR1_OVRMOD_Pos (12U)
sahilmgandhi 18:6a4db94011d3 781 #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 782 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
sahilmgandhi 18:6a4db94011d3 783 #define ADC_CFGR1_CONT_Pos (13U)
sahilmgandhi 18:6a4db94011d3 784 #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 785 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
sahilmgandhi 18:6a4db94011d3 786 #define ADC_CFGR1_WAIT_Pos (14U)
sahilmgandhi 18:6a4db94011d3 787 #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 788 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
sahilmgandhi 18:6a4db94011d3 789 #define ADC_CFGR1_AUTOFF_Pos (15U)
sahilmgandhi 18:6a4db94011d3 790 #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 791 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
sahilmgandhi 18:6a4db94011d3 792 #define ADC_CFGR1_DISCEN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 793 #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 794 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796 #define ADC_CFGR1_AWD1SGL_Pos (22U)
sahilmgandhi 18:6a4db94011d3 797 #define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 798 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
sahilmgandhi 18:6a4db94011d3 799 #define ADC_CFGR1_AWD1EN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 800 #define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 801 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
sahilmgandhi 18:6a4db94011d3 802
sahilmgandhi 18:6a4db94011d3 803 #define ADC_CFGR1_AWD1CH_Pos (26U)
sahilmgandhi 18:6a4db94011d3 804 #define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
sahilmgandhi 18:6a4db94011d3 805 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
sahilmgandhi 18:6a4db94011d3 806 #define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 807 #define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 808 #define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 809 #define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 810 #define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 811
sahilmgandhi 18:6a4db94011d3 812 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 813 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
sahilmgandhi 18:6a4db94011d3 814 #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL)
sahilmgandhi 18:6a4db94011d3 815 #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN)
sahilmgandhi 18:6a4db94011d3 816 #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH)
sahilmgandhi 18:6a4db94011d3 817 #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0)
sahilmgandhi 18:6a4db94011d3 818 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)
sahilmgandhi 18:6a4db94011d3 819 #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2)
sahilmgandhi 18:6a4db94011d3 820 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3)
sahilmgandhi 18:6a4db94011d3 821 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4)
sahilmgandhi 18:6a4db94011d3 822
sahilmgandhi 18:6a4db94011d3 823 /******************* Bits definition for ADC_CFGR2 register *****************/
sahilmgandhi 18:6a4db94011d3 824 #define ADC_CFGR2_CKMODE_Pos (30U)
sahilmgandhi 18:6a4db94011d3 825 #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 826 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
sahilmgandhi 18:6a4db94011d3 827 #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 828 #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 829
sahilmgandhi 18:6a4db94011d3 830 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 831 #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */
sahilmgandhi 18:6a4db94011d3 832 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
sahilmgandhi 18:6a4db94011d3 833
sahilmgandhi 18:6a4db94011d3 834 /****************** Bit definition for ADC_SMPR register ********************/
sahilmgandhi 18:6a4db94011d3 835 #define ADC_SMPR_SMP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 836 #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 837 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */
sahilmgandhi 18:6a4db94011d3 838 #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 839 #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 840 #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 843 #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */
sahilmgandhi 18:6a4db94011d3 844 #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */
sahilmgandhi 18:6a4db94011d3 845 #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */
sahilmgandhi 18:6a4db94011d3 846 #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 /******************* Bit definition for ADC_TR register ********************/
sahilmgandhi 18:6a4db94011d3 849 #define ADC_TR1_LT1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 850 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 851 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
sahilmgandhi 18:6a4db94011d3 852 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 853 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 854 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 855 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 856 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 857 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 858 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 859 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 860 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 861 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 862 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 863 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 864
sahilmgandhi 18:6a4db94011d3 865 #define ADC_TR1_HT1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 866 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
sahilmgandhi 18:6a4db94011d3 867 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
sahilmgandhi 18:6a4db94011d3 868 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 869 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 870 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 871 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 872 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 873 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 874 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 875 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 876 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 877 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 878 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 879 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 880
sahilmgandhi 18:6a4db94011d3 881 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 882 #define ADC_TR_HT (ADC_TR1_HT1)
sahilmgandhi 18:6a4db94011d3 883 #define ADC_TR_LT (ADC_TR1_LT1)
sahilmgandhi 18:6a4db94011d3 884 #define ADC_HTR_HT (ADC_TR1_HT1)
sahilmgandhi 18:6a4db94011d3 885 #define ADC_LTR_LT (ADC_TR1_LT1)
sahilmgandhi 18:6a4db94011d3 886
sahilmgandhi 18:6a4db94011d3 887 /****************** Bit definition for ADC_CHSELR register ******************/
sahilmgandhi 18:6a4db94011d3 888 #define ADC_CHSELR_CHSEL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 889 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
sahilmgandhi 18:6a4db94011d3 890 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 891 #define ADC_CHSELR_CHSEL18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 892 #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 893 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 894 #define ADC_CHSELR_CHSEL17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 895 #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 896 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 897 #define ADC_CHSELR_CHSEL16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 898 #define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 899 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 900 #define ADC_CHSELR_CHSEL15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 901 #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 902 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 903 #define ADC_CHSELR_CHSEL14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 904 #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 905 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 906 #define ADC_CHSELR_CHSEL13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 907 #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 908 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 909 #define ADC_CHSELR_CHSEL12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 910 #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 911 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 912 #define ADC_CHSELR_CHSEL11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 913 #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 914 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 915 #define ADC_CHSELR_CHSEL10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 916 #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 917 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 918 #define ADC_CHSELR_CHSEL9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 919 #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 920 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 921 #define ADC_CHSELR_CHSEL8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 922 #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 923 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 924 #define ADC_CHSELR_CHSEL7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 925 #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 926 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 927 #define ADC_CHSELR_CHSEL6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 928 #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 929 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 930 #define ADC_CHSELR_CHSEL5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 931 #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 932 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 933 #define ADC_CHSELR_CHSEL4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 934 #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 935 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 936 #define ADC_CHSELR_CHSEL3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 937 #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 938 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 939 #define ADC_CHSELR_CHSEL2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 940 #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 941 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 942 #define ADC_CHSELR_CHSEL1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 943 #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 944 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 945 #define ADC_CHSELR_CHSEL0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 946 #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 947 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
sahilmgandhi 18:6a4db94011d3 948
sahilmgandhi 18:6a4db94011d3 949 /******************** Bit definition for ADC_DR register ********************/
sahilmgandhi 18:6a4db94011d3 950 #define ADC_DR_DATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 951 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 952 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
sahilmgandhi 18:6a4db94011d3 953 #define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 954 #define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 955 #define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 956 #define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 957 #define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 958 #define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 959 #define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 960 #define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 961 #define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 962 #define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 963 #define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 964 #define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 965 #define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 966 #define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 967 #define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 968 #define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 969
sahilmgandhi 18:6a4db94011d3 970 /************************* ADC Common registers *****************************/
sahilmgandhi 18:6a4db94011d3 971 /******************* Bit definition for ADC_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 972 #define ADC_CCR_VREFEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 973 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 974 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
sahilmgandhi 18:6a4db94011d3 975 #define ADC_CCR_TSEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 976 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 977 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
sahilmgandhi 18:6a4db94011d3 978
sahilmgandhi 18:6a4db94011d3 979 #define ADC_CCR_VBATEN_Pos (24U)
sahilmgandhi 18:6a4db94011d3 980 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 981 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
sahilmgandhi 18:6a4db94011d3 982
sahilmgandhi 18:6a4db94011d3 983 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 984 /* */
sahilmgandhi 18:6a4db94011d3 985 /* HDMI-CEC (CEC) */
sahilmgandhi 18:6a4db94011d3 986 /* */
sahilmgandhi 18:6a4db94011d3 987 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 988
sahilmgandhi 18:6a4db94011d3 989 /******************* Bit definition for CEC_CR register *********************/
sahilmgandhi 18:6a4db94011d3 990 #define CEC_CR_CECEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 991 #define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 992 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
sahilmgandhi 18:6a4db94011d3 993 #define CEC_CR_TXSOM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 994 #define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 995 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
sahilmgandhi 18:6a4db94011d3 996 #define CEC_CR_TXEOM_Pos (2U)
sahilmgandhi 18:6a4db94011d3 997 #define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 998 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 /******************* Bit definition for CEC_CFGR register *******************/
sahilmgandhi 18:6a4db94011d3 1001 #define CEC_CFGR_SFT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1002 #define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 1003 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
sahilmgandhi 18:6a4db94011d3 1004 #define CEC_CFGR_RXTOL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1005 #define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1006 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
sahilmgandhi 18:6a4db94011d3 1007 #define CEC_CFGR_BRESTP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1008 #define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1009 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
sahilmgandhi 18:6a4db94011d3 1010 #define CEC_CFGR_BREGEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1011 #define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1012 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
sahilmgandhi 18:6a4db94011d3 1013 #define CEC_CFGR_LBPEGEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1014 #define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1015 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */
sahilmgandhi 18:6a4db94011d3 1016 #define CEC_CFGR_BRDNOGEN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1017 #define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1018 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */
sahilmgandhi 18:6a4db94011d3 1019 #define CEC_CFGR_SFTOPT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1020 #define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1021 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
sahilmgandhi 18:6a4db94011d3 1022 #define CEC_CFGR_OAR_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1023 #define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
sahilmgandhi 18:6a4db94011d3 1024 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
sahilmgandhi 18:6a4db94011d3 1025 #define CEC_CFGR_LSTN_Pos (31U)
sahilmgandhi 18:6a4db94011d3 1026 #define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 1027 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
sahilmgandhi 18:6a4db94011d3 1028
sahilmgandhi 18:6a4db94011d3 1029 /******************* Bit definition for CEC_TXDR register *******************/
sahilmgandhi 18:6a4db94011d3 1030 #define CEC_TXDR_TXD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1031 #define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 1032 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
sahilmgandhi 18:6a4db94011d3 1033
sahilmgandhi 18:6a4db94011d3 1034 /******************* Bit definition for CEC_RXDR register *******************/
sahilmgandhi 18:6a4db94011d3 1035 #define CEC_TXDR_RXD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1036 #define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 1037 #define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
sahilmgandhi 18:6a4db94011d3 1038
sahilmgandhi 18:6a4db94011d3 1039 /******************* Bit definition for CEC_ISR register ********************/
sahilmgandhi 18:6a4db94011d3 1040 #define CEC_ISR_RXBR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1041 #define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1042 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
sahilmgandhi 18:6a4db94011d3 1043 #define CEC_ISR_RXEND_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1044 #define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1045 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
sahilmgandhi 18:6a4db94011d3 1046 #define CEC_ISR_RXOVR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1047 #define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1048 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
sahilmgandhi 18:6a4db94011d3 1049 #define CEC_ISR_BRE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1050 #define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1051 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
sahilmgandhi 18:6a4db94011d3 1052 #define CEC_ISR_SBPE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1053 #define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1054 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
sahilmgandhi 18:6a4db94011d3 1055 #define CEC_ISR_LBPE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1056 #define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1057 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
sahilmgandhi 18:6a4db94011d3 1058 #define CEC_ISR_RXACKE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1059 #define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1060 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
sahilmgandhi 18:6a4db94011d3 1061 #define CEC_ISR_ARBLST_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1062 #define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1063 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
sahilmgandhi 18:6a4db94011d3 1064 #define CEC_ISR_TXBR_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1065 #define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1066 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
sahilmgandhi 18:6a4db94011d3 1067 #define CEC_ISR_TXEND_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1068 #define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1069 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
sahilmgandhi 18:6a4db94011d3 1070 #define CEC_ISR_TXUDR_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1071 #define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1072 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
sahilmgandhi 18:6a4db94011d3 1073 #define CEC_ISR_TXERR_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1074 #define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1075 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
sahilmgandhi 18:6a4db94011d3 1076 #define CEC_ISR_TXACKE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1077 #define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1078 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 /******************* Bit definition for CEC_IER register ********************/
sahilmgandhi 18:6a4db94011d3 1081 #define CEC_IER_RXBRIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1082 #define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1083 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
sahilmgandhi 18:6a4db94011d3 1084 #define CEC_IER_RXENDIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1085 #define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1086 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
sahilmgandhi 18:6a4db94011d3 1087 #define CEC_IER_RXOVRIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1088 #define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1089 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
sahilmgandhi 18:6a4db94011d3 1090 #define CEC_IER_BREIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1091 #define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1092 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
sahilmgandhi 18:6a4db94011d3 1093 #define CEC_IER_SBPEIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1094 #define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1095 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
sahilmgandhi 18:6a4db94011d3 1096 #define CEC_IER_LBPEIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1097 #define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1098 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
sahilmgandhi 18:6a4db94011d3 1099 #define CEC_IER_RXACKEIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1100 #define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1101 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
sahilmgandhi 18:6a4db94011d3 1102 #define CEC_IER_ARBLSTIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1103 #define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1104 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
sahilmgandhi 18:6a4db94011d3 1105 #define CEC_IER_TXBRIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1106 #define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1107 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
sahilmgandhi 18:6a4db94011d3 1108 #define CEC_IER_TXENDIE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1109 #define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1110 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
sahilmgandhi 18:6a4db94011d3 1111 #define CEC_IER_TXUDRIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1112 #define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1113 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
sahilmgandhi 18:6a4db94011d3 1114 #define CEC_IER_TXERRIE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1115 #define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1116 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
sahilmgandhi 18:6a4db94011d3 1117 #define CEC_IER_TXACKEIE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1118 #define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1119 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
sahilmgandhi 18:6a4db94011d3 1120
sahilmgandhi 18:6a4db94011d3 1121 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1122 /* */
sahilmgandhi 18:6a4db94011d3 1123 /* Analog Comparators (COMP) */
sahilmgandhi 18:6a4db94011d3 1124 /* */
sahilmgandhi 18:6a4db94011d3 1125 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1126 /*********************** Bit definition for COMP_CSR register ***************/
sahilmgandhi 18:6a4db94011d3 1127 /* COMP1 bits definition */
sahilmgandhi 18:6a4db94011d3 1128 #define COMP_CSR_COMP1EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1129 #define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1130 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
sahilmgandhi 18:6a4db94011d3 1131 #define COMP_CSR_COMP1SW1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1132 #define COMP_CSR_COMP1SW1_Msk (0x1U << COMP_CSR_COMP1SW1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1133 #define COMP_CSR_COMP1SW1 COMP_CSR_COMP1SW1_Msk /*!< COMP1 SW1 switch control */
sahilmgandhi 18:6a4db94011d3 1134 #define COMP_CSR_COMP1MODE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1135 #define COMP_CSR_COMP1MODE_Msk (0x3U << COMP_CSR_COMP1MODE_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 1136 #define COMP_CSR_COMP1MODE COMP_CSR_COMP1MODE_Msk /*!< COMP1 power mode */
sahilmgandhi 18:6a4db94011d3 1137 #define COMP_CSR_COMP1MODE_0 (0x1U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1138 #define COMP_CSR_COMP1MODE_1 (0x2U << COMP_CSR_COMP1MODE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1139 #define COMP_CSR_COMP1INSEL_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1140 #define COMP_CSR_COMP1INSEL_Msk (0x7U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 1141 #define COMP_CSR_COMP1INSEL COMP_CSR_COMP1INSEL_Msk /*!< COMP1 inverting input select */
sahilmgandhi 18:6a4db94011d3 1142 #define COMP_CSR_COMP1INSEL_0 (0x1U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1143 #define COMP_CSR_COMP1INSEL_1 (0x2U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1144 #define COMP_CSR_COMP1INSEL_2 (0x4U << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1145 #define COMP_CSR_COMP1OUTSEL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1146 #define COMP_CSR_COMP1OUTSEL_Msk (0x7U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 1147 #define COMP_CSR_COMP1OUTSEL COMP_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */
sahilmgandhi 18:6a4db94011d3 1148 #define COMP_CSR_COMP1OUTSEL_0 (0x1U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1149 #define COMP_CSR_COMP1OUTSEL_1 (0x2U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1150 #define COMP_CSR_COMP1OUTSEL_2 (0x4U << COMP_CSR_COMP1OUTSEL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1151 #define COMP_CSR_COMP1POL_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1152 #define COMP_CSR_COMP1POL_Msk (0x1U << COMP_CSR_COMP1POL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1153 #define COMP_CSR_COMP1POL COMP_CSR_COMP1POL_Msk /*!< COMP1 output polarity */
sahilmgandhi 18:6a4db94011d3 1154 #define COMP_CSR_COMP1HYST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1155 #define COMP_CSR_COMP1HYST_Msk (0x3U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 1156 #define COMP_CSR_COMP1HYST COMP_CSR_COMP1HYST_Msk /*!< COMP1 hysteresis */
sahilmgandhi 18:6a4db94011d3 1157 #define COMP_CSR_COMP1HYST_0 (0x1U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1158 #define COMP_CSR_COMP1HYST_1 (0x2U << COMP_CSR_COMP1HYST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1159 #define COMP_CSR_COMP1OUT_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1160 #define COMP_CSR_COMP1OUT_Msk (0x1U << COMP_CSR_COMP1OUT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1161 #define COMP_CSR_COMP1OUT COMP_CSR_COMP1OUT_Msk /*!< COMP1 output level */
sahilmgandhi 18:6a4db94011d3 1162 #define COMP_CSR_COMP1LOCK_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1163 #define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1164 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
sahilmgandhi 18:6a4db94011d3 1165 /* COMP2 bits definition */
sahilmgandhi 18:6a4db94011d3 1166 #define COMP_CSR_COMP2EN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1167 #define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1168 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
sahilmgandhi 18:6a4db94011d3 1169 #define COMP_CSR_COMP2MODE_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1170 #define COMP_CSR_COMP2MODE_Msk (0x3U << COMP_CSR_COMP2MODE_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 1171 #define COMP_CSR_COMP2MODE COMP_CSR_COMP2MODE_Msk /*!< COMP2 power mode */
sahilmgandhi 18:6a4db94011d3 1172 #define COMP_CSR_COMP2MODE_0 (0x1U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1173 #define COMP_CSR_COMP2MODE_1 (0x2U << COMP_CSR_COMP2MODE_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1174 #define COMP_CSR_COMP2INSEL_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1175 #define COMP_CSR_COMP2INSEL_Msk (0x7U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00700000 */
sahilmgandhi 18:6a4db94011d3 1176 #define COMP_CSR_COMP2INSEL COMP_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
sahilmgandhi 18:6a4db94011d3 1177 #define COMP_CSR_COMP2INSEL_0 (0x1U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1178 #define COMP_CSR_COMP2INSEL_1 (0x2U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1179 #define COMP_CSR_COMP2INSEL_2 (0x4U << COMP_CSR_COMP2INSEL_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1180 #define COMP_CSR_WNDWEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1181 #define COMP_CSR_WNDWEN_Msk (0x1U << COMP_CSR_WNDWEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1182 #define COMP_CSR_WNDWEN COMP_CSR_WNDWEN_Msk /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
sahilmgandhi 18:6a4db94011d3 1183 #define COMP_CSR_COMP2OUTSEL_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1184 #define COMP_CSR_COMP2OUTSEL_Msk (0x7U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x07000000 */
sahilmgandhi 18:6a4db94011d3 1185 #define COMP_CSR_COMP2OUTSEL COMP_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
sahilmgandhi 18:6a4db94011d3 1186 #define COMP_CSR_COMP2OUTSEL_0 (0x1U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1187 #define COMP_CSR_COMP2OUTSEL_1 (0x2U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1188 #define COMP_CSR_COMP2OUTSEL_2 (0x4U << COMP_CSR_COMP2OUTSEL_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1189 #define COMP_CSR_COMP2POL_Pos (27U)
sahilmgandhi 18:6a4db94011d3 1190 #define COMP_CSR_COMP2POL_Msk (0x1U << COMP_CSR_COMP2POL_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1191 #define COMP_CSR_COMP2POL COMP_CSR_COMP2POL_Msk /*!< COMP2 output polarity */
sahilmgandhi 18:6a4db94011d3 1192 #define COMP_CSR_COMP2HYST_Pos (28U)
sahilmgandhi 18:6a4db94011d3 1193 #define COMP_CSR_COMP2HYST_Msk (0x3U << COMP_CSR_COMP2HYST_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 1194 #define COMP_CSR_COMP2HYST COMP_CSR_COMP2HYST_Msk /*!< COMP2 hysteresis */
sahilmgandhi 18:6a4db94011d3 1195 #define COMP_CSR_COMP2HYST_0 (0x1U << COMP_CSR_COMP2HYST_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1196 #define COMP_CSR_COMP2HYST_1 (0x2U << COMP_CSR_COMP2HYST_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1197 #define COMP_CSR_COMP2OUT_Pos (30U)
sahilmgandhi 18:6a4db94011d3 1198 #define COMP_CSR_COMP2OUT_Msk (0x1U << COMP_CSR_COMP2OUT_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 1199 #define COMP_CSR_COMP2OUT COMP_CSR_COMP2OUT_Msk /*!< COMP2 output level */
sahilmgandhi 18:6a4db94011d3 1200 #define COMP_CSR_COMP2LOCK_Pos (31U)
sahilmgandhi 18:6a4db94011d3 1201 #define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 1202 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
sahilmgandhi 18:6a4db94011d3 1203 /* COMPx bits definition */
sahilmgandhi 18:6a4db94011d3 1204 #define COMP_CSR_COMPxEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1205 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1206 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
sahilmgandhi 18:6a4db94011d3 1207 #define COMP_CSR_COMPxMODE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1208 #define COMP_CSR_COMPxMODE_Msk (0x3U << COMP_CSR_COMPxMODE_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 1209 #define COMP_CSR_COMPxMODE COMP_CSR_COMPxMODE_Msk /*!< COMPx power mode */
sahilmgandhi 18:6a4db94011d3 1210 #define COMP_CSR_COMPxMODE_0 (0x1U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1211 #define COMP_CSR_COMPxMODE_1 (0x2U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1212 #define COMP_CSR_COMPxINSEL_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1213 #define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 1214 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
sahilmgandhi 18:6a4db94011d3 1215 #define COMP_CSR_COMPxINSEL_0 (0x1U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1216 #define COMP_CSR_COMPxINSEL_1 (0x2U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1217 #define COMP_CSR_COMPxINSEL_2 (0x4U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1218 #define COMP_CSR_COMPxOUTSEL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1219 #define COMP_CSR_COMPxOUTSEL_Msk (0x7U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 1220 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
sahilmgandhi 18:6a4db94011d3 1221 #define COMP_CSR_COMPxOUTSEL_0 (0x1U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1222 #define COMP_CSR_COMPxOUTSEL_1 (0x2U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1223 #define COMP_CSR_COMPxOUTSEL_2 (0x4U << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1224 #define COMP_CSR_COMPxPOL_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1225 #define COMP_CSR_COMPxPOL_Msk (0x1U << COMP_CSR_COMPxPOL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1226 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */
sahilmgandhi 18:6a4db94011d3 1227 #define COMP_CSR_COMPxHYST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1228 #define COMP_CSR_COMPxHYST_Msk (0x3U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 1229 #define COMP_CSR_COMPxHYST COMP_CSR_COMPxHYST_Msk /*!< COMPx hysteresis */
sahilmgandhi 18:6a4db94011d3 1230 #define COMP_CSR_COMPxHYST_0 (0x1U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1231 #define COMP_CSR_COMPxHYST_1 (0x2U << COMP_CSR_COMPxHYST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1232 #define COMP_CSR_COMPxOUT_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1233 #define COMP_CSR_COMPxOUT_Msk (0x1U << COMP_CSR_COMPxOUT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1234 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */
sahilmgandhi 18:6a4db94011d3 1235 #define COMP_CSR_COMPxLOCK_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1236 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1237 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
sahilmgandhi 18:6a4db94011d3 1238
sahilmgandhi 18:6a4db94011d3 1239 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1240 /* */
sahilmgandhi 18:6a4db94011d3 1241 /* CRC calculation unit (CRC) */
sahilmgandhi 18:6a4db94011d3 1242 /* */
sahilmgandhi 18:6a4db94011d3 1243 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1244 /******************* Bit definition for CRC_DR register *********************/
sahilmgandhi 18:6a4db94011d3 1245 #define CRC_DR_DR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1246 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 1247 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
sahilmgandhi 18:6a4db94011d3 1248
sahilmgandhi 18:6a4db94011d3 1249 /******************* Bit definition for CRC_IDR register ********************/
sahilmgandhi 18:6a4db94011d3 1250 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
sahilmgandhi 18:6a4db94011d3 1251
sahilmgandhi 18:6a4db94011d3 1252 /******************** Bit definition for CRC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 1253 #define CRC_CR_RESET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1254 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1255 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
sahilmgandhi 18:6a4db94011d3 1256 #define CRC_CR_REV_IN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1257 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
sahilmgandhi 18:6a4db94011d3 1258 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
sahilmgandhi 18:6a4db94011d3 1259 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1260 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1261 #define CRC_CR_REV_OUT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1262 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1263 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
sahilmgandhi 18:6a4db94011d3 1264
sahilmgandhi 18:6a4db94011d3 1265 /******************* Bit definition for CRC_INIT register *******************/
sahilmgandhi 18:6a4db94011d3 1266 #define CRC_INIT_INIT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1267 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 1268 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
sahilmgandhi 18:6a4db94011d3 1269
sahilmgandhi 18:6a4db94011d3 1270 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1271 /* */
sahilmgandhi 18:6a4db94011d3 1272 /* Digital to Analog Converter (DAC) */
sahilmgandhi 18:6a4db94011d3 1273 /* */
sahilmgandhi 18:6a4db94011d3 1274 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1275
sahilmgandhi 18:6a4db94011d3 1276 /*
sahilmgandhi 18:6a4db94011d3 1277 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
sahilmgandhi 18:6a4db94011d3 1278 */
sahilmgandhi 18:6a4db94011d3 1279 /* Note: No specific macro feature on this device */
sahilmgandhi 18:6a4db94011d3 1280
sahilmgandhi 18:6a4db94011d3 1281 /******************** Bit definition for DAC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 1282 #define DAC_CR_EN1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1283 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1284 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
sahilmgandhi 18:6a4db94011d3 1285 #define DAC_CR_BOFF1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1286 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1287 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
sahilmgandhi 18:6a4db94011d3 1288 #define DAC_CR_TEN1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1289 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1290 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
sahilmgandhi 18:6a4db94011d3 1291
sahilmgandhi 18:6a4db94011d3 1292 #define DAC_CR_TSEL1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1293 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 1294 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
sahilmgandhi 18:6a4db94011d3 1295 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1296 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1297 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1298
sahilmgandhi 18:6a4db94011d3 1299 #define DAC_CR_DMAEN1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1300 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1301 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
sahilmgandhi 18:6a4db94011d3 1302 #define DAC_CR_DMAUDRIE1_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1303 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1304 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun Interrupt enable */
sahilmgandhi 18:6a4db94011d3 1305
sahilmgandhi 18:6a4db94011d3 1306
sahilmgandhi 18:6a4db94011d3 1307 /***************** Bit definition for DAC_SWTRIGR register ******************/
sahilmgandhi 18:6a4db94011d3 1308 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1309 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1310 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
sahilmgandhi 18:6a4db94011d3 1311
sahilmgandhi 18:6a4db94011d3 1312 /***************** Bit definition for DAC_DHR12R1 register ******************/
sahilmgandhi 18:6a4db94011d3 1313 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1314 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1315 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1316
sahilmgandhi 18:6a4db94011d3 1317 /***************** Bit definition for DAC_DHR12L1 register ******************/
sahilmgandhi 18:6a4db94011d3 1318 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1319 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 1320 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 1321
sahilmgandhi 18:6a4db94011d3 1322 /****************** Bit definition for DAC_DHR8R1 register ******************/
sahilmgandhi 18:6a4db94011d3 1323 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1324 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 1325 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 1326
sahilmgandhi 18:6a4db94011d3 1327 /******************* Bit definition for DAC_DOR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1328 #define DAC_DOR1_DACC1DOR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1329 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1330 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
sahilmgandhi 18:6a4db94011d3 1331
sahilmgandhi 18:6a4db94011d3 1332 /******************** Bit definition for DAC_SR register ********************/
sahilmgandhi 18:6a4db94011d3 1333 #define DAC_SR_DMAUDR1_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1334 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1335 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
sahilmgandhi 18:6a4db94011d3 1336 #define DAC_SR_DMAUDR2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 1337 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1338 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
sahilmgandhi 18:6a4db94011d3 1339
sahilmgandhi 18:6a4db94011d3 1340 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1341 /* */
sahilmgandhi 18:6a4db94011d3 1342 /* Debug MCU (DBGMCU) */
sahilmgandhi 18:6a4db94011d3 1343 /* */
sahilmgandhi 18:6a4db94011d3 1344 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1345
sahilmgandhi 18:6a4db94011d3 1346 /**************** Bit definition for DBGMCU_IDCODE register *****************/
sahilmgandhi 18:6a4db94011d3 1347 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1348 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1349 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
sahilmgandhi 18:6a4db94011d3 1350
sahilmgandhi 18:6a4db94011d3 1351 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1352 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 1353 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
sahilmgandhi 18:6a4db94011d3 1354 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1355 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1356 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1357 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1358 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1359 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1360 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1361 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1362 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1363 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1364 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1365 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1366 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1367 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1368 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 1369 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 1370
sahilmgandhi 18:6a4db94011d3 1371 /****************** Bit definition for DBGMCU_CR register *******************/
sahilmgandhi 18:6a4db94011d3 1372 #define DBGMCU_CR_DBG_STOP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1373 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1374 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
sahilmgandhi 18:6a4db94011d3 1375 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1376 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1377 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
sahilmgandhi 18:6a4db94011d3 1378
sahilmgandhi 18:6a4db94011d3 1379 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
sahilmgandhi 18:6a4db94011d3 1380 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1381 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1382 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1383 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1384 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1385 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1386 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1387 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1388 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1389 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1390 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1391 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1392 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1393 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1394 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
sahilmgandhi 18:6a4db94011d3 1395 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1396 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1397 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
sahilmgandhi 18:6a4db94011d3 1398 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1399 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1400 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
sahilmgandhi 18:6a4db94011d3 1401 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1402 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1403 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
sahilmgandhi 18:6a4db94011d3 1404
sahilmgandhi 18:6a4db94011d3 1405 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
sahilmgandhi 18:6a4db94011d3 1406 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1407 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1408 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1409 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1410 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1411 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1412 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1413 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1414 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1415 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1416 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1417 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
sahilmgandhi 18:6a4db94011d3 1418
sahilmgandhi 18:6a4db94011d3 1419 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1420 /* */
sahilmgandhi 18:6a4db94011d3 1421 /* DMA Controller (DMA) */
sahilmgandhi 18:6a4db94011d3 1422 /* */
sahilmgandhi 18:6a4db94011d3 1423 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1424 /******************* Bit definition for DMA_ISR register ********************/
sahilmgandhi 18:6a4db94011d3 1425 #define DMA_ISR_GIF1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1426 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1427 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1428 #define DMA_ISR_TCIF1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1429 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1430 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1431 #define DMA_ISR_HTIF1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1432 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1433 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1434 #define DMA_ISR_TEIF1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1435 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1436 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1437 #define DMA_ISR_GIF2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1438 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1439 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1440 #define DMA_ISR_TCIF2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1441 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1442 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1443 #define DMA_ISR_HTIF2_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1444 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1445 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1446 #define DMA_ISR_TEIF2_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1447 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1448 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1449 #define DMA_ISR_GIF3_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1450 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1451 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1452 #define DMA_ISR_TCIF3_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1453 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1454 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1455 #define DMA_ISR_HTIF3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1456 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1457 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1458 #define DMA_ISR_TEIF3_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1459 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1460 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1461 #define DMA_ISR_GIF4_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1462 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1463 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1464 #define DMA_ISR_TCIF4_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1465 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1466 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1467 #define DMA_ISR_HTIF4_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1468 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1469 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1470 #define DMA_ISR_TEIF4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1471 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1472 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1473 #define DMA_ISR_GIF5_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1474 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1475 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
sahilmgandhi 18:6a4db94011d3 1476 #define DMA_ISR_TCIF5_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1477 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1478 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 1479 #define DMA_ISR_HTIF5_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1480 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1481 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
sahilmgandhi 18:6a4db94011d3 1482 #define DMA_ISR_TEIF5_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1483 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1484 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
sahilmgandhi 18:6a4db94011d3 1485
sahilmgandhi 18:6a4db94011d3 1486 /******************* Bit definition for DMA_IFCR register *******************/
sahilmgandhi 18:6a4db94011d3 1487 #define DMA_IFCR_CGIF1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1488 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1489 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1490 #define DMA_IFCR_CTCIF1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1491 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1492 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1493 #define DMA_IFCR_CHTIF1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1494 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1495 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1496 #define DMA_IFCR_CTEIF1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1497 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1498 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1499 #define DMA_IFCR_CGIF2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1500 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1501 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1502 #define DMA_IFCR_CTCIF2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1503 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1504 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1505 #define DMA_IFCR_CHTIF2_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1506 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1507 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1508 #define DMA_IFCR_CTEIF2_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1509 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1510 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1511 #define DMA_IFCR_CGIF3_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1512 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1513 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1514 #define DMA_IFCR_CTCIF3_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1515 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1516 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1517 #define DMA_IFCR_CHTIF3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1518 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1519 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1520 #define DMA_IFCR_CTEIF3_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1521 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1522 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1523 #define DMA_IFCR_CGIF4_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1524 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1525 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1526 #define DMA_IFCR_CTCIF4_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1527 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1528 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1529 #define DMA_IFCR_CHTIF4_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1530 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1531 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1532 #define DMA_IFCR_CTEIF4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1533 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1534 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1535 #define DMA_IFCR_CGIF5_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1536 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1537 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
sahilmgandhi 18:6a4db94011d3 1538 #define DMA_IFCR_CTCIF5_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1539 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1540 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
sahilmgandhi 18:6a4db94011d3 1541 #define DMA_IFCR_CHTIF5_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1542 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1543 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
sahilmgandhi 18:6a4db94011d3 1544 #define DMA_IFCR_CTEIF5_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1545 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1546 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
sahilmgandhi 18:6a4db94011d3 1547
sahilmgandhi 18:6a4db94011d3 1548 /******************* Bit definition for DMA_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 1549 #define DMA_CCR_EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1550 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1551 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
sahilmgandhi 18:6a4db94011d3 1552 #define DMA_CCR_TCIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1553 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1554 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
sahilmgandhi 18:6a4db94011d3 1555 #define DMA_CCR_HTIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1556 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1557 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
sahilmgandhi 18:6a4db94011d3 1558 #define DMA_CCR_TEIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1559 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1560 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
sahilmgandhi 18:6a4db94011d3 1561 #define DMA_CCR_DIR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1562 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1563 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
sahilmgandhi 18:6a4db94011d3 1564 #define DMA_CCR_CIRC_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1565 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1566 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
sahilmgandhi 18:6a4db94011d3 1567 #define DMA_CCR_PINC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1568 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1569 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
sahilmgandhi 18:6a4db94011d3 1570 #define DMA_CCR_MINC_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1571 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1572 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
sahilmgandhi 18:6a4db94011d3 1573
sahilmgandhi 18:6a4db94011d3 1574 #define DMA_CCR_PSIZE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1575 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 1576 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
sahilmgandhi 18:6a4db94011d3 1577 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1578 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1579
sahilmgandhi 18:6a4db94011d3 1580 #define DMA_CCR_MSIZE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1581 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 1582 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
sahilmgandhi 18:6a4db94011d3 1583 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1584 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1585
sahilmgandhi 18:6a4db94011d3 1586 #define DMA_CCR_PL_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1587 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 1588 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
sahilmgandhi 18:6a4db94011d3 1589 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1590 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1591
sahilmgandhi 18:6a4db94011d3 1592 #define DMA_CCR_MEM2MEM_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1593 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1594 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
sahilmgandhi 18:6a4db94011d3 1595
sahilmgandhi 18:6a4db94011d3 1596 /****************** Bit definition for DMA_CNDTR register *******************/
sahilmgandhi 18:6a4db94011d3 1597 #define DMA_CNDTR_NDT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1598 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1599 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
sahilmgandhi 18:6a4db94011d3 1600
sahilmgandhi 18:6a4db94011d3 1601 /****************** Bit definition for DMA_CPAR register ********************/
sahilmgandhi 18:6a4db94011d3 1602 #define DMA_CPAR_PA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1603 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 1604 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
sahilmgandhi 18:6a4db94011d3 1605
sahilmgandhi 18:6a4db94011d3 1606 /****************** Bit definition for DMA_CMAR register ********************/
sahilmgandhi 18:6a4db94011d3 1607 #define DMA_CMAR_MA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1608 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 1609 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
sahilmgandhi 18:6a4db94011d3 1610
sahilmgandhi 18:6a4db94011d3 1611 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1612 /* */
sahilmgandhi 18:6a4db94011d3 1613 /* External Interrupt/Event Controller (EXTI) */
sahilmgandhi 18:6a4db94011d3 1614 /* */
sahilmgandhi 18:6a4db94011d3 1615 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1616 /******************* Bit definition for EXTI_IMR register *******************/
sahilmgandhi 18:6a4db94011d3 1617 #define EXTI_IMR_MR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1618 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1619 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 1620 #define EXTI_IMR_MR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1621 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1622 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 1623 #define EXTI_IMR_MR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1624 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1625 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 1626 #define EXTI_IMR_MR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1627 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1628 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 1629 #define EXTI_IMR_MR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1630 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1631 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 1632 #define EXTI_IMR_MR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1633 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1634 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 1635 #define EXTI_IMR_MR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1636 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1637 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 1638 #define EXTI_IMR_MR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1639 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1640 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 1641 #define EXTI_IMR_MR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1642 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1643 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 1644 #define EXTI_IMR_MR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1645 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1646 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 1647 #define EXTI_IMR_MR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1648 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1649 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 1650 #define EXTI_IMR_MR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1651 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1652 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 1653 #define EXTI_IMR_MR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1654 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1655 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 1656 #define EXTI_IMR_MR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1657 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1658 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 1659 #define EXTI_IMR_MR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1660 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1661 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 1662 #define EXTI_IMR_MR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1663 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1664 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 1665 #define EXTI_IMR_MR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1666 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1667 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 1668 #define EXTI_IMR_MR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1669 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1670 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 1671 #define EXTI_IMR_MR18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1672 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1673 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 1674 #define EXTI_IMR_MR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1675 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1676 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 1677 #define EXTI_IMR_MR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1678 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1679 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 1680 #define EXTI_IMR_MR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1681 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1682 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 1683 #define EXTI_IMR_MR23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1684 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1685 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
sahilmgandhi 18:6a4db94011d3 1686 #define EXTI_IMR_MR25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 1687 #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1688 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
sahilmgandhi 18:6a4db94011d3 1689 #define EXTI_IMR_MR27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 1690 #define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1691 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
sahilmgandhi 18:6a4db94011d3 1692
sahilmgandhi 18:6a4db94011d3 1693 /* References Defines */
sahilmgandhi 18:6a4db94011d3 1694 #define EXTI_IMR_IM0 EXTI_IMR_MR0
sahilmgandhi 18:6a4db94011d3 1695 #define EXTI_IMR_IM1 EXTI_IMR_MR1
sahilmgandhi 18:6a4db94011d3 1696 #define EXTI_IMR_IM2 EXTI_IMR_MR2
sahilmgandhi 18:6a4db94011d3 1697 #define EXTI_IMR_IM3 EXTI_IMR_MR3
sahilmgandhi 18:6a4db94011d3 1698 #define EXTI_IMR_IM4 EXTI_IMR_MR4
sahilmgandhi 18:6a4db94011d3 1699 #define EXTI_IMR_IM5 EXTI_IMR_MR5
sahilmgandhi 18:6a4db94011d3 1700 #define EXTI_IMR_IM6 EXTI_IMR_MR6
sahilmgandhi 18:6a4db94011d3 1701 #define EXTI_IMR_IM7 EXTI_IMR_MR7
sahilmgandhi 18:6a4db94011d3 1702 #define EXTI_IMR_IM8 EXTI_IMR_MR8
sahilmgandhi 18:6a4db94011d3 1703 #define EXTI_IMR_IM9 EXTI_IMR_MR9
sahilmgandhi 18:6a4db94011d3 1704 #define EXTI_IMR_IM10 EXTI_IMR_MR10
sahilmgandhi 18:6a4db94011d3 1705 #define EXTI_IMR_IM11 EXTI_IMR_MR11
sahilmgandhi 18:6a4db94011d3 1706 #define EXTI_IMR_IM12 EXTI_IMR_MR12
sahilmgandhi 18:6a4db94011d3 1707 #define EXTI_IMR_IM13 EXTI_IMR_MR13
sahilmgandhi 18:6a4db94011d3 1708 #define EXTI_IMR_IM14 EXTI_IMR_MR14
sahilmgandhi 18:6a4db94011d3 1709 #define EXTI_IMR_IM15 EXTI_IMR_MR15
sahilmgandhi 18:6a4db94011d3 1710 #define EXTI_IMR_IM16 EXTI_IMR_MR16
sahilmgandhi 18:6a4db94011d3 1711 #define EXTI_IMR_IM17 EXTI_IMR_MR17
sahilmgandhi 18:6a4db94011d3 1712 #define EXTI_IMR_IM18 EXTI_IMR_MR18
sahilmgandhi 18:6a4db94011d3 1713 #define EXTI_IMR_IM19 EXTI_IMR_MR19
sahilmgandhi 18:6a4db94011d3 1714 #define EXTI_IMR_IM21 EXTI_IMR_MR21
sahilmgandhi 18:6a4db94011d3 1715 #define EXTI_IMR_IM22 EXTI_IMR_MR22
sahilmgandhi 18:6a4db94011d3 1716 #define EXTI_IMR_IM23 EXTI_IMR_MR23
sahilmgandhi 18:6a4db94011d3 1717 #define EXTI_IMR_IM25 EXTI_IMR_MR25
sahilmgandhi 18:6a4db94011d3 1718 #define EXTI_IMR_IM27 EXTI_IMR_MR27
sahilmgandhi 18:6a4db94011d3 1719
sahilmgandhi 18:6a4db94011d3 1720 #define EXTI_IMR_IM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1721 #define EXTI_IMR_IM_Msk (0xAEFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x0AEFFFFF */
sahilmgandhi 18:6a4db94011d3 1722 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
sahilmgandhi 18:6a4db94011d3 1723
sahilmgandhi 18:6a4db94011d3 1724
sahilmgandhi 18:6a4db94011d3 1725 /****************** Bit definition for EXTI_EMR register ********************/
sahilmgandhi 18:6a4db94011d3 1726 #define EXTI_EMR_MR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1727 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1728 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 1729 #define EXTI_EMR_MR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1730 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1731 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 1732 #define EXTI_EMR_MR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1733 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1734 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 1735 #define EXTI_EMR_MR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1736 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1737 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 1738 #define EXTI_EMR_MR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1739 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1740 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 1741 #define EXTI_EMR_MR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1742 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1743 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 1744 #define EXTI_EMR_MR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1745 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1746 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 1747 #define EXTI_EMR_MR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1748 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1749 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 1750 #define EXTI_EMR_MR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1751 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1752 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 1753 #define EXTI_EMR_MR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1754 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1755 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 1756 #define EXTI_EMR_MR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1757 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1758 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 1759 #define EXTI_EMR_MR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1760 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1761 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 1762 #define EXTI_EMR_MR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1763 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1764 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 1765 #define EXTI_EMR_MR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1766 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1767 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 1768 #define EXTI_EMR_MR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1769 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1770 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 1771 #define EXTI_EMR_MR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1772 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1773 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 1774 #define EXTI_EMR_MR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1775 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1776 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 1777 #define EXTI_EMR_MR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1778 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1779 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 1780 #define EXTI_EMR_MR18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1781 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1782 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 1783 #define EXTI_EMR_MR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1784 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1785 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 1786 #define EXTI_EMR_MR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1787 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1788 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 1789 #define EXTI_EMR_MR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1790 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1791 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 1792 #define EXTI_EMR_MR23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1793 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1794 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
sahilmgandhi 18:6a4db94011d3 1795 #define EXTI_EMR_MR25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 1796 #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1797 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
sahilmgandhi 18:6a4db94011d3 1798 #define EXTI_EMR_MR27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 1799 #define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1800 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
sahilmgandhi 18:6a4db94011d3 1801
sahilmgandhi 18:6a4db94011d3 1802 /* References Defines */
sahilmgandhi 18:6a4db94011d3 1803 #define EXTI_EMR_EM0 EXTI_EMR_MR0
sahilmgandhi 18:6a4db94011d3 1804 #define EXTI_EMR_EM1 EXTI_EMR_MR1
sahilmgandhi 18:6a4db94011d3 1805 #define EXTI_EMR_EM2 EXTI_EMR_MR2
sahilmgandhi 18:6a4db94011d3 1806 #define EXTI_EMR_EM3 EXTI_EMR_MR3
sahilmgandhi 18:6a4db94011d3 1807 #define EXTI_EMR_EM4 EXTI_EMR_MR4
sahilmgandhi 18:6a4db94011d3 1808 #define EXTI_EMR_EM5 EXTI_EMR_MR5
sahilmgandhi 18:6a4db94011d3 1809 #define EXTI_EMR_EM6 EXTI_EMR_MR6
sahilmgandhi 18:6a4db94011d3 1810 #define EXTI_EMR_EM7 EXTI_EMR_MR7
sahilmgandhi 18:6a4db94011d3 1811 #define EXTI_EMR_EM8 EXTI_EMR_MR8
sahilmgandhi 18:6a4db94011d3 1812 #define EXTI_EMR_EM9 EXTI_EMR_MR9
sahilmgandhi 18:6a4db94011d3 1813 #define EXTI_EMR_EM10 EXTI_EMR_MR10
sahilmgandhi 18:6a4db94011d3 1814 #define EXTI_EMR_EM11 EXTI_EMR_MR11
sahilmgandhi 18:6a4db94011d3 1815 #define EXTI_EMR_EM12 EXTI_EMR_MR12
sahilmgandhi 18:6a4db94011d3 1816 #define EXTI_EMR_EM13 EXTI_EMR_MR13
sahilmgandhi 18:6a4db94011d3 1817 #define EXTI_EMR_EM14 EXTI_EMR_MR14
sahilmgandhi 18:6a4db94011d3 1818 #define EXTI_EMR_EM15 EXTI_EMR_MR15
sahilmgandhi 18:6a4db94011d3 1819 #define EXTI_EMR_EM16 EXTI_EMR_MR16
sahilmgandhi 18:6a4db94011d3 1820 #define EXTI_EMR_EM17 EXTI_EMR_MR17
sahilmgandhi 18:6a4db94011d3 1821 #define EXTI_EMR_EM18 EXTI_EMR_MR18
sahilmgandhi 18:6a4db94011d3 1822 #define EXTI_EMR_EM19 EXTI_EMR_MR19
sahilmgandhi 18:6a4db94011d3 1823 #define EXTI_EMR_EM21 EXTI_EMR_MR21
sahilmgandhi 18:6a4db94011d3 1824 #define EXTI_EMR_EM22 EXTI_EMR_MR22
sahilmgandhi 18:6a4db94011d3 1825 #define EXTI_EMR_EM23 EXTI_EMR_MR23
sahilmgandhi 18:6a4db94011d3 1826 #define EXTI_EMR_EM25 EXTI_EMR_MR25
sahilmgandhi 18:6a4db94011d3 1827 #define EXTI_EMR_EM27 EXTI_EMR_MR27
sahilmgandhi 18:6a4db94011d3 1828
sahilmgandhi 18:6a4db94011d3 1829 /******************* Bit definition for EXTI_RTSR register ******************/
sahilmgandhi 18:6a4db94011d3 1830 #define EXTI_RTSR_TR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1831 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1832 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 1833 #define EXTI_RTSR_TR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1834 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1835 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 1836 #define EXTI_RTSR_TR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1837 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1838 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 1839 #define EXTI_RTSR_TR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1840 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1841 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 1842 #define EXTI_RTSR_TR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1843 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1844 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 1845 #define EXTI_RTSR_TR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1846 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1847 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 1848 #define EXTI_RTSR_TR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1849 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1850 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 1851 #define EXTI_RTSR_TR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1852 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1853 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 1854 #define EXTI_RTSR_TR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1855 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1856 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 1857 #define EXTI_RTSR_TR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1858 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1859 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 1860 #define EXTI_RTSR_TR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1861 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1862 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 1863 #define EXTI_RTSR_TR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1864 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1865 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 1866 #define EXTI_RTSR_TR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1867 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1868 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 1869 #define EXTI_RTSR_TR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1870 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1871 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 1872 #define EXTI_RTSR_TR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1873 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1874 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 1875 #define EXTI_RTSR_TR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1876 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1877 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 1878 #define EXTI_RTSR_TR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1879 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1880 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 1881 #define EXTI_RTSR_TR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1882 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1883 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 1884 #define EXTI_RTSR_TR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1885 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1886 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 1887 #define EXTI_RTSR_TR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1888 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1889 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 1890 #define EXTI_RTSR_TR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1891 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1892 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 1893
sahilmgandhi 18:6a4db94011d3 1894 /* References Defines */
sahilmgandhi 18:6a4db94011d3 1895 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
sahilmgandhi 18:6a4db94011d3 1896 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
sahilmgandhi 18:6a4db94011d3 1897 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
sahilmgandhi 18:6a4db94011d3 1898 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
sahilmgandhi 18:6a4db94011d3 1899 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
sahilmgandhi 18:6a4db94011d3 1900 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
sahilmgandhi 18:6a4db94011d3 1901 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
sahilmgandhi 18:6a4db94011d3 1902 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
sahilmgandhi 18:6a4db94011d3 1903 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
sahilmgandhi 18:6a4db94011d3 1904 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
sahilmgandhi 18:6a4db94011d3 1905 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
sahilmgandhi 18:6a4db94011d3 1906 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
sahilmgandhi 18:6a4db94011d3 1907 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
sahilmgandhi 18:6a4db94011d3 1908 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
sahilmgandhi 18:6a4db94011d3 1909 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
sahilmgandhi 18:6a4db94011d3 1910 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
sahilmgandhi 18:6a4db94011d3 1911 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
sahilmgandhi 18:6a4db94011d3 1912 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
sahilmgandhi 18:6a4db94011d3 1913 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
sahilmgandhi 18:6a4db94011d3 1914 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
sahilmgandhi 18:6a4db94011d3 1915 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
sahilmgandhi 18:6a4db94011d3 1916
sahilmgandhi 18:6a4db94011d3 1917 /******************* Bit definition for EXTI_FTSR register *******************/
sahilmgandhi 18:6a4db94011d3 1918 #define EXTI_FTSR_TR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1919 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1920 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 1921 #define EXTI_FTSR_TR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1922 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1923 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 1924 #define EXTI_FTSR_TR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1925 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1926 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 1927 #define EXTI_FTSR_TR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1928 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1929 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 1930 #define EXTI_FTSR_TR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1931 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1932 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 1933 #define EXTI_FTSR_TR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1934 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1935 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 1936 #define EXTI_FTSR_TR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1937 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1938 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 1939 #define EXTI_FTSR_TR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1940 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1941 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 1942 #define EXTI_FTSR_TR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1943 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1944 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 1945 #define EXTI_FTSR_TR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1946 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1947 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 1948 #define EXTI_FTSR_TR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1949 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1950 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 1951 #define EXTI_FTSR_TR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1952 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1953 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 1954 #define EXTI_FTSR_TR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1955 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1956 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 1957 #define EXTI_FTSR_TR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1958 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1959 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 1960 #define EXTI_FTSR_TR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1961 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1962 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 1963 #define EXTI_FTSR_TR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1964 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1965 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 1966 #define EXTI_FTSR_TR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1967 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1968 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 1969 #define EXTI_FTSR_TR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1970 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1971 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 1972 #define EXTI_FTSR_TR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1973 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1974 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 1975 #define EXTI_FTSR_TR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1976 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1977 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 1978 #define EXTI_FTSR_TR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1979 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1980 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 1981
sahilmgandhi 18:6a4db94011d3 1982 /* References Defines */
sahilmgandhi 18:6a4db94011d3 1983 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
sahilmgandhi 18:6a4db94011d3 1984 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
sahilmgandhi 18:6a4db94011d3 1985 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
sahilmgandhi 18:6a4db94011d3 1986 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
sahilmgandhi 18:6a4db94011d3 1987 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
sahilmgandhi 18:6a4db94011d3 1988 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
sahilmgandhi 18:6a4db94011d3 1989 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
sahilmgandhi 18:6a4db94011d3 1990 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
sahilmgandhi 18:6a4db94011d3 1991 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
sahilmgandhi 18:6a4db94011d3 1992 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
sahilmgandhi 18:6a4db94011d3 1993 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
sahilmgandhi 18:6a4db94011d3 1994 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
sahilmgandhi 18:6a4db94011d3 1995 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
sahilmgandhi 18:6a4db94011d3 1996 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
sahilmgandhi 18:6a4db94011d3 1997 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
sahilmgandhi 18:6a4db94011d3 1998 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
sahilmgandhi 18:6a4db94011d3 1999 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
sahilmgandhi 18:6a4db94011d3 2000 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
sahilmgandhi 18:6a4db94011d3 2001 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
sahilmgandhi 18:6a4db94011d3 2002 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
sahilmgandhi 18:6a4db94011d3 2003 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
sahilmgandhi 18:6a4db94011d3 2004
sahilmgandhi 18:6a4db94011d3 2005 /******************* Bit definition for EXTI_SWIER register *******************/
sahilmgandhi 18:6a4db94011d3 2006 #define EXTI_SWIER_SWIER0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2007 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2008 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
sahilmgandhi 18:6a4db94011d3 2009 #define EXTI_SWIER_SWIER1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2010 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2011 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
sahilmgandhi 18:6a4db94011d3 2012 #define EXTI_SWIER_SWIER2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2013 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2014 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
sahilmgandhi 18:6a4db94011d3 2015 #define EXTI_SWIER_SWIER3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2016 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2017 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
sahilmgandhi 18:6a4db94011d3 2018 #define EXTI_SWIER_SWIER4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2019 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2020 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
sahilmgandhi 18:6a4db94011d3 2021 #define EXTI_SWIER_SWIER5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2022 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2023 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
sahilmgandhi 18:6a4db94011d3 2024 #define EXTI_SWIER_SWIER6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2025 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2026 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
sahilmgandhi 18:6a4db94011d3 2027 #define EXTI_SWIER_SWIER7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2028 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2029 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
sahilmgandhi 18:6a4db94011d3 2030 #define EXTI_SWIER_SWIER8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2031 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2032 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
sahilmgandhi 18:6a4db94011d3 2033 #define EXTI_SWIER_SWIER9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2034 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2035 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
sahilmgandhi 18:6a4db94011d3 2036 #define EXTI_SWIER_SWIER10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2037 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2038 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
sahilmgandhi 18:6a4db94011d3 2039 #define EXTI_SWIER_SWIER11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2040 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2041 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
sahilmgandhi 18:6a4db94011d3 2042 #define EXTI_SWIER_SWIER12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2043 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2044 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
sahilmgandhi 18:6a4db94011d3 2045 #define EXTI_SWIER_SWIER13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2046 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2047 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
sahilmgandhi 18:6a4db94011d3 2048 #define EXTI_SWIER_SWIER14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2049 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2050 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
sahilmgandhi 18:6a4db94011d3 2051 #define EXTI_SWIER_SWIER15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2052 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2053 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
sahilmgandhi 18:6a4db94011d3 2054 #define EXTI_SWIER_SWIER16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2055 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2056 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
sahilmgandhi 18:6a4db94011d3 2057 #define EXTI_SWIER_SWIER17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2058 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2059 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
sahilmgandhi 18:6a4db94011d3 2060 #define EXTI_SWIER_SWIER19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2061 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2062 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
sahilmgandhi 18:6a4db94011d3 2063 #define EXTI_SWIER_SWIER21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2064 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2065 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
sahilmgandhi 18:6a4db94011d3 2066 #define EXTI_SWIER_SWIER22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2067 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2068 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
sahilmgandhi 18:6a4db94011d3 2069
sahilmgandhi 18:6a4db94011d3 2070 /* References Defines */
sahilmgandhi 18:6a4db94011d3 2071 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
sahilmgandhi 18:6a4db94011d3 2072 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
sahilmgandhi 18:6a4db94011d3 2073 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
sahilmgandhi 18:6a4db94011d3 2074 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
sahilmgandhi 18:6a4db94011d3 2075 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
sahilmgandhi 18:6a4db94011d3 2076 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
sahilmgandhi 18:6a4db94011d3 2077 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
sahilmgandhi 18:6a4db94011d3 2078 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
sahilmgandhi 18:6a4db94011d3 2079 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
sahilmgandhi 18:6a4db94011d3 2080 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
sahilmgandhi 18:6a4db94011d3 2081 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
sahilmgandhi 18:6a4db94011d3 2082 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
sahilmgandhi 18:6a4db94011d3 2083 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
sahilmgandhi 18:6a4db94011d3 2084 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
sahilmgandhi 18:6a4db94011d3 2085 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
sahilmgandhi 18:6a4db94011d3 2086 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
sahilmgandhi 18:6a4db94011d3 2087 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
sahilmgandhi 18:6a4db94011d3 2088 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
sahilmgandhi 18:6a4db94011d3 2089 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
sahilmgandhi 18:6a4db94011d3 2090 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
sahilmgandhi 18:6a4db94011d3 2091 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
sahilmgandhi 18:6a4db94011d3 2092
sahilmgandhi 18:6a4db94011d3 2093 /****************** Bit definition for EXTI_PR register *********************/
sahilmgandhi 18:6a4db94011d3 2094 #define EXTI_PR_PR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2095 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2096 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */
sahilmgandhi 18:6a4db94011d3 2097 #define EXTI_PR_PR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2098 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2099 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */
sahilmgandhi 18:6a4db94011d3 2100 #define EXTI_PR_PR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2101 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2102 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */
sahilmgandhi 18:6a4db94011d3 2103 #define EXTI_PR_PR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2104 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2105 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */
sahilmgandhi 18:6a4db94011d3 2106 #define EXTI_PR_PR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2107 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2108 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */
sahilmgandhi 18:6a4db94011d3 2109 #define EXTI_PR_PR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2110 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2111 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */
sahilmgandhi 18:6a4db94011d3 2112 #define EXTI_PR_PR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2113 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2114 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */
sahilmgandhi 18:6a4db94011d3 2115 #define EXTI_PR_PR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2116 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2117 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */
sahilmgandhi 18:6a4db94011d3 2118 #define EXTI_PR_PR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2119 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2120 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */
sahilmgandhi 18:6a4db94011d3 2121 #define EXTI_PR_PR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2122 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2123 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */
sahilmgandhi 18:6a4db94011d3 2124 #define EXTI_PR_PR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2125 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2126 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */
sahilmgandhi 18:6a4db94011d3 2127 #define EXTI_PR_PR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2128 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2129 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */
sahilmgandhi 18:6a4db94011d3 2130 #define EXTI_PR_PR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2131 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2132 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */
sahilmgandhi 18:6a4db94011d3 2133 #define EXTI_PR_PR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2134 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2135 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */
sahilmgandhi 18:6a4db94011d3 2136 #define EXTI_PR_PR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2137 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2138 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */
sahilmgandhi 18:6a4db94011d3 2139 #define EXTI_PR_PR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2140 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2141 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */
sahilmgandhi 18:6a4db94011d3 2142 #define EXTI_PR_PR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2143 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2144 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */
sahilmgandhi 18:6a4db94011d3 2145 #define EXTI_PR_PR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2146 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2147 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */
sahilmgandhi 18:6a4db94011d3 2148 #define EXTI_PR_PR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2149 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2150 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */
sahilmgandhi 18:6a4db94011d3 2151 #define EXTI_PR_PR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2152 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2153 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit 21 */
sahilmgandhi 18:6a4db94011d3 2154 #define EXTI_PR_PR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2155 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2156 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit 22 */
sahilmgandhi 18:6a4db94011d3 2157
sahilmgandhi 18:6a4db94011d3 2158 /* References Defines */
sahilmgandhi 18:6a4db94011d3 2159 #define EXTI_PR_PIF0 EXTI_PR_PR0
sahilmgandhi 18:6a4db94011d3 2160 #define EXTI_PR_PIF1 EXTI_PR_PR1
sahilmgandhi 18:6a4db94011d3 2161 #define EXTI_PR_PIF2 EXTI_PR_PR2
sahilmgandhi 18:6a4db94011d3 2162 #define EXTI_PR_PIF3 EXTI_PR_PR3
sahilmgandhi 18:6a4db94011d3 2163 #define EXTI_PR_PIF4 EXTI_PR_PR4
sahilmgandhi 18:6a4db94011d3 2164 #define EXTI_PR_PIF5 EXTI_PR_PR5
sahilmgandhi 18:6a4db94011d3 2165 #define EXTI_PR_PIF6 EXTI_PR_PR6
sahilmgandhi 18:6a4db94011d3 2166 #define EXTI_PR_PIF7 EXTI_PR_PR7
sahilmgandhi 18:6a4db94011d3 2167 #define EXTI_PR_PIF8 EXTI_PR_PR8
sahilmgandhi 18:6a4db94011d3 2168 #define EXTI_PR_PIF9 EXTI_PR_PR9
sahilmgandhi 18:6a4db94011d3 2169 #define EXTI_PR_PIF10 EXTI_PR_PR10
sahilmgandhi 18:6a4db94011d3 2170 #define EXTI_PR_PIF11 EXTI_PR_PR11
sahilmgandhi 18:6a4db94011d3 2171 #define EXTI_PR_PIF12 EXTI_PR_PR12
sahilmgandhi 18:6a4db94011d3 2172 #define EXTI_PR_PIF13 EXTI_PR_PR13
sahilmgandhi 18:6a4db94011d3 2173 #define EXTI_PR_PIF14 EXTI_PR_PR14
sahilmgandhi 18:6a4db94011d3 2174 #define EXTI_PR_PIF15 EXTI_PR_PR15
sahilmgandhi 18:6a4db94011d3 2175 #define EXTI_PR_PIF16 EXTI_PR_PR16
sahilmgandhi 18:6a4db94011d3 2176 #define EXTI_PR_PIF17 EXTI_PR_PR17
sahilmgandhi 18:6a4db94011d3 2177 #define EXTI_PR_PIF19 EXTI_PR_PR19
sahilmgandhi 18:6a4db94011d3 2178 #define EXTI_PR_PIF21 EXTI_PR_PR21
sahilmgandhi 18:6a4db94011d3 2179 #define EXTI_PR_PIF22 EXTI_PR_PR22
sahilmgandhi 18:6a4db94011d3 2180
sahilmgandhi 18:6a4db94011d3 2181 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2182 /* */
sahilmgandhi 18:6a4db94011d3 2183 /* FLASH and Option Bytes Registers */
sahilmgandhi 18:6a4db94011d3 2184 /* */
sahilmgandhi 18:6a4db94011d3 2185 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2186
sahilmgandhi 18:6a4db94011d3 2187 /******************* Bit definition for FLASH_ACR register ******************/
sahilmgandhi 18:6a4db94011d3 2188 #define FLASH_ACR_LATENCY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2189 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2190 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
sahilmgandhi 18:6a4db94011d3 2191
sahilmgandhi 18:6a4db94011d3 2192 #define FLASH_ACR_PRFTBE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2193 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2194 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
sahilmgandhi 18:6a4db94011d3 2195 #define FLASH_ACR_PRFTBS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2196 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2197 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
sahilmgandhi 18:6a4db94011d3 2198
sahilmgandhi 18:6a4db94011d3 2199 /****************** Bit definition for FLASH_KEYR register ******************/
sahilmgandhi 18:6a4db94011d3 2200 #define FLASH_KEYR_FKEYR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2201 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 2202 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
sahilmgandhi 18:6a4db94011d3 2203
sahilmgandhi 18:6a4db94011d3 2204 /***************** Bit definition for FLASH_OPTKEYR register ****************/
sahilmgandhi 18:6a4db94011d3 2205 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2206 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 2207 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
sahilmgandhi 18:6a4db94011d3 2208
sahilmgandhi 18:6a4db94011d3 2209 /****************** FLASH Keys **********************************************/
sahilmgandhi 18:6a4db94011d3 2210 #define FLASH_KEY1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2211 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
sahilmgandhi 18:6a4db94011d3 2212 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */
sahilmgandhi 18:6a4db94011d3 2213 #define FLASH_KEY2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2214 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
sahilmgandhi 18:6a4db94011d3 2215 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1
sahilmgandhi 18:6a4db94011d3 2216 to unlock the write access to the FPEC. */
sahilmgandhi 18:6a4db94011d3 2217
sahilmgandhi 18:6a4db94011d3 2218 #define FLASH_OPTKEY1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2219 #define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */
sahilmgandhi 18:6a4db94011d3 2220 #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */
sahilmgandhi 18:6a4db94011d3 2221 #define FLASH_OPTKEY2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2222 #define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */
sahilmgandhi 18:6a4db94011d3 2223 #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to
sahilmgandhi 18:6a4db94011d3 2224 unlock the write access to the option byte block */
sahilmgandhi 18:6a4db94011d3 2225
sahilmgandhi 18:6a4db94011d3 2226 /****************** Bit definition for FLASH_SR register *******************/
sahilmgandhi 18:6a4db94011d3 2227 #define FLASH_SR_BSY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2228 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2229 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
sahilmgandhi 18:6a4db94011d3 2230 #define FLASH_SR_PGERR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2231 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2232 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
sahilmgandhi 18:6a4db94011d3 2233 #define FLASH_SR_WRPRTERR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2234 #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2235 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
sahilmgandhi 18:6a4db94011d3 2236 #define FLASH_SR_EOP_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2237 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2238 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
sahilmgandhi 18:6a4db94011d3 2239 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
sahilmgandhi 18:6a4db94011d3 2240
sahilmgandhi 18:6a4db94011d3 2241 /******************* Bit definition for FLASH_CR register *******************/
sahilmgandhi 18:6a4db94011d3 2242 #define FLASH_CR_PG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2243 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2244 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
sahilmgandhi 18:6a4db94011d3 2245 #define FLASH_CR_PER_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2246 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2247 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
sahilmgandhi 18:6a4db94011d3 2248 #define FLASH_CR_MER_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2249 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2250 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
sahilmgandhi 18:6a4db94011d3 2251 #define FLASH_CR_OPTPG_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2252 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2253 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
sahilmgandhi 18:6a4db94011d3 2254 #define FLASH_CR_OPTER_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2255 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2256 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
sahilmgandhi 18:6a4db94011d3 2257 #define FLASH_CR_STRT_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2258 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2259 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
sahilmgandhi 18:6a4db94011d3 2260 #define FLASH_CR_LOCK_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2261 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2262 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
sahilmgandhi 18:6a4db94011d3 2263 #define FLASH_CR_OPTWRE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2264 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2265 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
sahilmgandhi 18:6a4db94011d3 2266 #define FLASH_CR_ERRIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2267 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2268 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2269 #define FLASH_CR_EOPIE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2270 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2271 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
sahilmgandhi 18:6a4db94011d3 2272 #define FLASH_CR_OBL_LAUNCH_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2273 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2274 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */
sahilmgandhi 18:6a4db94011d3 2275
sahilmgandhi 18:6a4db94011d3 2276 /******************* Bit definition for FLASH_AR register *******************/
sahilmgandhi 18:6a4db94011d3 2277 #define FLASH_AR_FAR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2278 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 2279 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
sahilmgandhi 18:6a4db94011d3 2280
sahilmgandhi 18:6a4db94011d3 2281 /****************** Bit definition for FLASH_OBR register *******************/
sahilmgandhi 18:6a4db94011d3 2282 #define FLASH_OBR_OPTERR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2283 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2284 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
sahilmgandhi 18:6a4db94011d3 2285 #define FLASH_OBR_RDPRT1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2286 #define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2287 #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */
sahilmgandhi 18:6a4db94011d3 2288 #define FLASH_OBR_RDPRT2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2289 #define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2290 #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */
sahilmgandhi 18:6a4db94011d3 2291
sahilmgandhi 18:6a4db94011d3 2292 #define FLASH_OBR_USER_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2293 #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
sahilmgandhi 18:6a4db94011d3 2294 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
sahilmgandhi 18:6a4db94011d3 2295 #define FLASH_OBR_IWDG_SW_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2296 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2297 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
sahilmgandhi 18:6a4db94011d3 2298 #define FLASH_OBR_nRST_STOP_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2299 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2300 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
sahilmgandhi 18:6a4db94011d3 2301 #define FLASH_OBR_nRST_STDBY_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2302 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2303 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
sahilmgandhi 18:6a4db94011d3 2304 #define FLASH_OBR_nBOOT1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2305 #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2306 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
sahilmgandhi 18:6a4db94011d3 2307 #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2308 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2309 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */
sahilmgandhi 18:6a4db94011d3 2310 #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2311 #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2312 #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */
sahilmgandhi 18:6a4db94011d3 2313 #define FLASH_OBR_DATA0_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2314 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2315 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
sahilmgandhi 18:6a4db94011d3 2316 #define FLASH_OBR_DATA1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2317 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2318 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
sahilmgandhi 18:6a4db94011d3 2319
sahilmgandhi 18:6a4db94011d3 2320 /* Old BOOT1 bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 2321 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
sahilmgandhi 18:6a4db94011d3 2322
sahilmgandhi 18:6a4db94011d3 2323 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 2324 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
sahilmgandhi 18:6a4db94011d3 2325
sahilmgandhi 18:6a4db94011d3 2326 /****************** Bit definition for FLASH_WRPR register ******************/
sahilmgandhi 18:6a4db94011d3 2327 #define FLASH_WRPR_WRP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2328 #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 2329 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
sahilmgandhi 18:6a4db94011d3 2330
sahilmgandhi 18:6a4db94011d3 2331 /*----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 2332
sahilmgandhi 18:6a4db94011d3 2333 /****************** Bit definition for OB_RDP register **********************/
sahilmgandhi 18:6a4db94011d3 2334 #define OB_RDP_RDP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2335 #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2336 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
sahilmgandhi 18:6a4db94011d3 2337 #define OB_RDP_nRDP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2338 #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2339 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
sahilmgandhi 18:6a4db94011d3 2340
sahilmgandhi 18:6a4db94011d3 2341 /****************** Bit definition for OB_USER register *********************/
sahilmgandhi 18:6a4db94011d3 2342 #define OB_USER_USER_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2343 #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2344 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
sahilmgandhi 18:6a4db94011d3 2345 #define OB_USER_nUSER_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2346 #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2347 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
sahilmgandhi 18:6a4db94011d3 2348
sahilmgandhi 18:6a4db94011d3 2349 /****************** Bit definition for OB_WRP0 register *********************/
sahilmgandhi 18:6a4db94011d3 2350 #define OB_WRP0_WRP0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2351 #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2352 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
sahilmgandhi 18:6a4db94011d3 2353 #define OB_WRP0_nWRP0_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2354 #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2355 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
sahilmgandhi 18:6a4db94011d3 2356
sahilmgandhi 18:6a4db94011d3 2357 /****************** Bit definition for OB_WRP1 register *********************/
sahilmgandhi 18:6a4db94011d3 2358 #define OB_WRP1_WRP1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2359 #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2360 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
sahilmgandhi 18:6a4db94011d3 2361 #define OB_WRP1_nWRP1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2362 #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2363 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
sahilmgandhi 18:6a4db94011d3 2364
sahilmgandhi 18:6a4db94011d3 2365 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2366 /* */
sahilmgandhi 18:6a4db94011d3 2367 /* General Purpose IOs (GPIO) */
sahilmgandhi 18:6a4db94011d3 2368 /* */
sahilmgandhi 18:6a4db94011d3 2369 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2370 /******************* Bit definition for GPIO_MODER register *****************/
sahilmgandhi 18:6a4db94011d3 2371 #define GPIO_MODER_MODER0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2372 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 2373 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
sahilmgandhi 18:6a4db94011d3 2374 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2375 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2376 #define GPIO_MODER_MODER1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2377 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 2378 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
sahilmgandhi 18:6a4db94011d3 2379 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2380 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2381 #define GPIO_MODER_MODER2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2382 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 2383 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
sahilmgandhi 18:6a4db94011d3 2384 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2385 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2386 #define GPIO_MODER_MODER3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2387 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 2388 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
sahilmgandhi 18:6a4db94011d3 2389 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2390 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2391 #define GPIO_MODER_MODER4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2392 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 2393 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
sahilmgandhi 18:6a4db94011d3 2394 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2395 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2396 #define GPIO_MODER_MODER5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2397 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 2398 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
sahilmgandhi 18:6a4db94011d3 2399 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2400 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2401 #define GPIO_MODER_MODER6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2402 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 2403 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
sahilmgandhi 18:6a4db94011d3 2404 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2405 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2406 #define GPIO_MODER_MODER7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2407 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 2408 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
sahilmgandhi 18:6a4db94011d3 2409 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2410 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2411 #define GPIO_MODER_MODER8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2412 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 2413 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
sahilmgandhi 18:6a4db94011d3 2414 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2415 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2416 #define GPIO_MODER_MODER9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2417 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 2418 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
sahilmgandhi 18:6a4db94011d3 2419 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2420 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2421 #define GPIO_MODER_MODER10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2422 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 2423 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
sahilmgandhi 18:6a4db94011d3 2424 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2425 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2426 #define GPIO_MODER_MODER11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2427 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 2428 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
sahilmgandhi 18:6a4db94011d3 2429 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2430 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2431 #define GPIO_MODER_MODER12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2432 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 2433 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
sahilmgandhi 18:6a4db94011d3 2434 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2435 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2436 #define GPIO_MODER_MODER13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2437 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 2438 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
sahilmgandhi 18:6a4db94011d3 2439 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2440 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2441 #define GPIO_MODER_MODER14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2442 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 2443 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
sahilmgandhi 18:6a4db94011d3 2444 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 2445 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 2446 #define GPIO_MODER_MODER15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 2447 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 2448 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
sahilmgandhi 18:6a4db94011d3 2449 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 2450 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2451
sahilmgandhi 18:6a4db94011d3 2452 /****************** Bit definition for GPIO_OTYPER register *****************/
sahilmgandhi 18:6a4db94011d3 2453 #define GPIO_OTYPER_OT_0 (0x00000001U)
sahilmgandhi 18:6a4db94011d3 2454 #define GPIO_OTYPER_OT_1 (0x00000002U)
sahilmgandhi 18:6a4db94011d3 2455 #define GPIO_OTYPER_OT_2 (0x00000004U)
sahilmgandhi 18:6a4db94011d3 2456 #define GPIO_OTYPER_OT_3 (0x00000008U)
sahilmgandhi 18:6a4db94011d3 2457 #define GPIO_OTYPER_OT_4 (0x00000010U)
sahilmgandhi 18:6a4db94011d3 2458 #define GPIO_OTYPER_OT_5 (0x00000020U)
sahilmgandhi 18:6a4db94011d3 2459 #define GPIO_OTYPER_OT_6 (0x00000040U)
sahilmgandhi 18:6a4db94011d3 2460 #define GPIO_OTYPER_OT_7 (0x00000080U)
sahilmgandhi 18:6a4db94011d3 2461 #define GPIO_OTYPER_OT_8 (0x00000100U)
sahilmgandhi 18:6a4db94011d3 2462 #define GPIO_OTYPER_OT_9 (0x00000200U)
sahilmgandhi 18:6a4db94011d3 2463 #define GPIO_OTYPER_OT_10 (0x00000400U)
sahilmgandhi 18:6a4db94011d3 2464 #define GPIO_OTYPER_OT_11 (0x00000800U)
sahilmgandhi 18:6a4db94011d3 2465 #define GPIO_OTYPER_OT_12 (0x00001000U)
sahilmgandhi 18:6a4db94011d3 2466 #define GPIO_OTYPER_OT_13 (0x00002000U)
sahilmgandhi 18:6a4db94011d3 2467 #define GPIO_OTYPER_OT_14 (0x00004000U)
sahilmgandhi 18:6a4db94011d3 2468 #define GPIO_OTYPER_OT_15 (0x00008000U)
sahilmgandhi 18:6a4db94011d3 2469
sahilmgandhi 18:6a4db94011d3 2470 /**************** Bit definition for GPIO_OSPEEDR register ******************/
sahilmgandhi 18:6a4db94011d3 2471 #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2472 #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 2473 #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
sahilmgandhi 18:6a4db94011d3 2474 #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2475 #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2476 #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2477 #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 2478 #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
sahilmgandhi 18:6a4db94011d3 2479 #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2480 #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2481 #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2482 #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 2483 #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
sahilmgandhi 18:6a4db94011d3 2484 #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2485 #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2486 #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2487 #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 2488 #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
sahilmgandhi 18:6a4db94011d3 2489 #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2490 #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2491 #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2492 #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 2493 #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
sahilmgandhi 18:6a4db94011d3 2494 #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2495 #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2496 #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2497 #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 2498 #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
sahilmgandhi 18:6a4db94011d3 2499 #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2500 #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2501 #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2502 #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 2503 #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
sahilmgandhi 18:6a4db94011d3 2504 #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2505 #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2506 #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2507 #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 2508 #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
sahilmgandhi 18:6a4db94011d3 2509 #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2510 #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2511 #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2512 #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 2513 #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
sahilmgandhi 18:6a4db94011d3 2514 #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2515 #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2516 #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2517 #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 2518 #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
sahilmgandhi 18:6a4db94011d3 2519 #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2520 #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2521 #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2522 #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 2523 #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
sahilmgandhi 18:6a4db94011d3 2524 #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2525 #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2526 #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2527 #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 2528 #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
sahilmgandhi 18:6a4db94011d3 2529 #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2530 #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2531 #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2532 #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 2533 #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
sahilmgandhi 18:6a4db94011d3 2534 #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2535 #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2536 #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2537 #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 2538 #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
sahilmgandhi 18:6a4db94011d3 2539 #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2540 #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2541 #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2542 #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 2543 #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
sahilmgandhi 18:6a4db94011d3 2544 #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 2545 #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 2546 #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 2547 #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 2548 #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
sahilmgandhi 18:6a4db94011d3 2549 #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 2550 #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2551
sahilmgandhi 18:6a4db94011d3 2552 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 2553 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
sahilmgandhi 18:6a4db94011d3 2554 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
sahilmgandhi 18:6a4db94011d3 2555 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
sahilmgandhi 18:6a4db94011d3 2556 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
sahilmgandhi 18:6a4db94011d3 2557 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
sahilmgandhi 18:6a4db94011d3 2558 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
sahilmgandhi 18:6a4db94011d3 2559 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
sahilmgandhi 18:6a4db94011d3 2560 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
sahilmgandhi 18:6a4db94011d3 2561 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
sahilmgandhi 18:6a4db94011d3 2562 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
sahilmgandhi 18:6a4db94011d3 2563 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
sahilmgandhi 18:6a4db94011d3 2564 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
sahilmgandhi 18:6a4db94011d3 2565 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
sahilmgandhi 18:6a4db94011d3 2566 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
sahilmgandhi 18:6a4db94011d3 2567 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
sahilmgandhi 18:6a4db94011d3 2568 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
sahilmgandhi 18:6a4db94011d3 2569 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
sahilmgandhi 18:6a4db94011d3 2570 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
sahilmgandhi 18:6a4db94011d3 2571 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
sahilmgandhi 18:6a4db94011d3 2572 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
sahilmgandhi 18:6a4db94011d3 2573 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
sahilmgandhi 18:6a4db94011d3 2574 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
sahilmgandhi 18:6a4db94011d3 2575 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
sahilmgandhi 18:6a4db94011d3 2576 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
sahilmgandhi 18:6a4db94011d3 2577 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
sahilmgandhi 18:6a4db94011d3 2578 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
sahilmgandhi 18:6a4db94011d3 2579 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
sahilmgandhi 18:6a4db94011d3 2580 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
sahilmgandhi 18:6a4db94011d3 2581 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
sahilmgandhi 18:6a4db94011d3 2582 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
sahilmgandhi 18:6a4db94011d3 2583 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
sahilmgandhi 18:6a4db94011d3 2584 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
sahilmgandhi 18:6a4db94011d3 2585 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
sahilmgandhi 18:6a4db94011d3 2586 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
sahilmgandhi 18:6a4db94011d3 2587 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
sahilmgandhi 18:6a4db94011d3 2588 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
sahilmgandhi 18:6a4db94011d3 2589 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
sahilmgandhi 18:6a4db94011d3 2590 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
sahilmgandhi 18:6a4db94011d3 2591 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
sahilmgandhi 18:6a4db94011d3 2592 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
sahilmgandhi 18:6a4db94011d3 2593 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
sahilmgandhi 18:6a4db94011d3 2594 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
sahilmgandhi 18:6a4db94011d3 2595 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
sahilmgandhi 18:6a4db94011d3 2596 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
sahilmgandhi 18:6a4db94011d3 2597 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
sahilmgandhi 18:6a4db94011d3 2598 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
sahilmgandhi 18:6a4db94011d3 2599 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
sahilmgandhi 18:6a4db94011d3 2600 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
sahilmgandhi 18:6a4db94011d3 2601
sahilmgandhi 18:6a4db94011d3 2602 /******************* Bit definition for GPIO_PUPDR register ******************/
sahilmgandhi 18:6a4db94011d3 2603 #define GPIO_PUPDR_PUPDR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2604 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 2605 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
sahilmgandhi 18:6a4db94011d3 2606 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2607 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2608 #define GPIO_PUPDR_PUPDR1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2609 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 2610 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
sahilmgandhi 18:6a4db94011d3 2611 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2612 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2613 #define GPIO_PUPDR_PUPDR2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2614 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 2615 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
sahilmgandhi 18:6a4db94011d3 2616 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2617 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2618 #define GPIO_PUPDR_PUPDR3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2619 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 2620 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
sahilmgandhi 18:6a4db94011d3 2621 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2622 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2623 #define GPIO_PUPDR_PUPDR4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2624 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 2625 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
sahilmgandhi 18:6a4db94011d3 2626 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2627 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2628 #define GPIO_PUPDR_PUPDR5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2629 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 2630 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
sahilmgandhi 18:6a4db94011d3 2631 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2632 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2633 #define GPIO_PUPDR_PUPDR6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2634 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 2635 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
sahilmgandhi 18:6a4db94011d3 2636 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2637 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2638 #define GPIO_PUPDR_PUPDR7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2639 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 2640 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
sahilmgandhi 18:6a4db94011d3 2641 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2642 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2643 #define GPIO_PUPDR_PUPDR8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2644 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 2645 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
sahilmgandhi 18:6a4db94011d3 2646 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2647 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2648 #define GPIO_PUPDR_PUPDR9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2649 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 2650 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
sahilmgandhi 18:6a4db94011d3 2651 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2652 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2653 #define GPIO_PUPDR_PUPDR10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2654 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 2655 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
sahilmgandhi 18:6a4db94011d3 2656 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2657 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2658 #define GPIO_PUPDR_PUPDR11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2659 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 2660 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
sahilmgandhi 18:6a4db94011d3 2661 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2662 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2663 #define GPIO_PUPDR_PUPDR12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2664 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 2665 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
sahilmgandhi 18:6a4db94011d3 2666 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2667 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2668 #define GPIO_PUPDR_PUPDR13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2669 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 2670 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
sahilmgandhi 18:6a4db94011d3 2671 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2672 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2673 #define GPIO_PUPDR_PUPDR14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2674 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 2675 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
sahilmgandhi 18:6a4db94011d3 2676 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 2677 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 2678 #define GPIO_PUPDR_PUPDR15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 2679 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 2680 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
sahilmgandhi 18:6a4db94011d3 2681 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 2682 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2683
sahilmgandhi 18:6a4db94011d3 2684 /******************* Bit definition for GPIO_IDR register *******************/
sahilmgandhi 18:6a4db94011d3 2685 #define GPIO_IDR_0 (0x00000001U)
sahilmgandhi 18:6a4db94011d3 2686 #define GPIO_IDR_1 (0x00000002U)
sahilmgandhi 18:6a4db94011d3 2687 #define GPIO_IDR_2 (0x00000004U)
sahilmgandhi 18:6a4db94011d3 2688 #define GPIO_IDR_3 (0x00000008U)
sahilmgandhi 18:6a4db94011d3 2689 #define GPIO_IDR_4 (0x00000010U)
sahilmgandhi 18:6a4db94011d3 2690 #define GPIO_IDR_5 (0x00000020U)
sahilmgandhi 18:6a4db94011d3 2691 #define GPIO_IDR_6 (0x00000040U)
sahilmgandhi 18:6a4db94011d3 2692 #define GPIO_IDR_7 (0x00000080U)
sahilmgandhi 18:6a4db94011d3 2693 #define GPIO_IDR_8 (0x00000100U)
sahilmgandhi 18:6a4db94011d3 2694 #define GPIO_IDR_9 (0x00000200U)
sahilmgandhi 18:6a4db94011d3 2695 #define GPIO_IDR_10 (0x00000400U)
sahilmgandhi 18:6a4db94011d3 2696 #define GPIO_IDR_11 (0x00000800U)
sahilmgandhi 18:6a4db94011d3 2697 #define GPIO_IDR_12 (0x00001000U)
sahilmgandhi 18:6a4db94011d3 2698 #define GPIO_IDR_13 (0x00002000U)
sahilmgandhi 18:6a4db94011d3 2699 #define GPIO_IDR_14 (0x00004000U)
sahilmgandhi 18:6a4db94011d3 2700 #define GPIO_IDR_15 (0x00008000U)
sahilmgandhi 18:6a4db94011d3 2701
sahilmgandhi 18:6a4db94011d3 2702 /****************** Bit definition for GPIO_ODR register ********************/
sahilmgandhi 18:6a4db94011d3 2703 #define GPIO_ODR_0 (0x00000001U)
sahilmgandhi 18:6a4db94011d3 2704 #define GPIO_ODR_1 (0x00000002U)
sahilmgandhi 18:6a4db94011d3 2705 #define GPIO_ODR_2 (0x00000004U)
sahilmgandhi 18:6a4db94011d3 2706 #define GPIO_ODR_3 (0x00000008U)
sahilmgandhi 18:6a4db94011d3 2707 #define GPIO_ODR_4 (0x00000010U)
sahilmgandhi 18:6a4db94011d3 2708 #define GPIO_ODR_5 (0x00000020U)
sahilmgandhi 18:6a4db94011d3 2709 #define GPIO_ODR_6 (0x00000040U)
sahilmgandhi 18:6a4db94011d3 2710 #define GPIO_ODR_7 (0x00000080U)
sahilmgandhi 18:6a4db94011d3 2711 #define GPIO_ODR_8 (0x00000100U)
sahilmgandhi 18:6a4db94011d3 2712 #define GPIO_ODR_9 (0x00000200U)
sahilmgandhi 18:6a4db94011d3 2713 #define GPIO_ODR_10 (0x00000400U)
sahilmgandhi 18:6a4db94011d3 2714 #define GPIO_ODR_11 (0x00000800U)
sahilmgandhi 18:6a4db94011d3 2715 #define GPIO_ODR_12 (0x00001000U)
sahilmgandhi 18:6a4db94011d3 2716 #define GPIO_ODR_13 (0x00002000U)
sahilmgandhi 18:6a4db94011d3 2717 #define GPIO_ODR_14 (0x00004000U)
sahilmgandhi 18:6a4db94011d3 2718 #define GPIO_ODR_15 (0x00008000U)
sahilmgandhi 18:6a4db94011d3 2719
sahilmgandhi 18:6a4db94011d3 2720 /****************** Bit definition for GPIO_BSRR register ********************/
sahilmgandhi 18:6a4db94011d3 2721 #define GPIO_BSRR_BS_0 (0x00000001U)
sahilmgandhi 18:6a4db94011d3 2722 #define GPIO_BSRR_BS_1 (0x00000002U)
sahilmgandhi 18:6a4db94011d3 2723 #define GPIO_BSRR_BS_2 (0x00000004U)
sahilmgandhi 18:6a4db94011d3 2724 #define GPIO_BSRR_BS_3 (0x00000008U)
sahilmgandhi 18:6a4db94011d3 2725 #define GPIO_BSRR_BS_4 (0x00000010U)
sahilmgandhi 18:6a4db94011d3 2726 #define GPIO_BSRR_BS_5 (0x00000020U)
sahilmgandhi 18:6a4db94011d3 2727 #define GPIO_BSRR_BS_6 (0x00000040U)
sahilmgandhi 18:6a4db94011d3 2728 #define GPIO_BSRR_BS_7 (0x00000080U)
sahilmgandhi 18:6a4db94011d3 2729 #define GPIO_BSRR_BS_8 (0x00000100U)
sahilmgandhi 18:6a4db94011d3 2730 #define GPIO_BSRR_BS_9 (0x00000200U)
sahilmgandhi 18:6a4db94011d3 2731 #define GPIO_BSRR_BS_10 (0x00000400U)
sahilmgandhi 18:6a4db94011d3 2732 #define GPIO_BSRR_BS_11 (0x00000800U)
sahilmgandhi 18:6a4db94011d3 2733 #define GPIO_BSRR_BS_12 (0x00001000U)
sahilmgandhi 18:6a4db94011d3 2734 #define GPIO_BSRR_BS_13 (0x00002000U)
sahilmgandhi 18:6a4db94011d3 2735 #define GPIO_BSRR_BS_14 (0x00004000U)
sahilmgandhi 18:6a4db94011d3 2736 #define GPIO_BSRR_BS_15 (0x00008000U)
sahilmgandhi 18:6a4db94011d3 2737 #define GPIO_BSRR_BR_0 (0x00010000U)
sahilmgandhi 18:6a4db94011d3 2738 #define GPIO_BSRR_BR_1 (0x00020000U)
sahilmgandhi 18:6a4db94011d3 2739 #define GPIO_BSRR_BR_2 (0x00040000U)
sahilmgandhi 18:6a4db94011d3 2740 #define GPIO_BSRR_BR_3 (0x00080000U)
sahilmgandhi 18:6a4db94011d3 2741 #define GPIO_BSRR_BR_4 (0x00100000U)
sahilmgandhi 18:6a4db94011d3 2742 #define GPIO_BSRR_BR_5 (0x00200000U)
sahilmgandhi 18:6a4db94011d3 2743 #define GPIO_BSRR_BR_6 (0x00400000U)
sahilmgandhi 18:6a4db94011d3 2744 #define GPIO_BSRR_BR_7 (0x00800000U)
sahilmgandhi 18:6a4db94011d3 2745 #define GPIO_BSRR_BR_8 (0x01000000U)
sahilmgandhi 18:6a4db94011d3 2746 #define GPIO_BSRR_BR_9 (0x02000000U)
sahilmgandhi 18:6a4db94011d3 2747 #define GPIO_BSRR_BR_10 (0x04000000U)
sahilmgandhi 18:6a4db94011d3 2748 #define GPIO_BSRR_BR_11 (0x08000000U)
sahilmgandhi 18:6a4db94011d3 2749 #define GPIO_BSRR_BR_12 (0x10000000U)
sahilmgandhi 18:6a4db94011d3 2750 #define GPIO_BSRR_BR_13 (0x20000000U)
sahilmgandhi 18:6a4db94011d3 2751 #define GPIO_BSRR_BR_14 (0x40000000U)
sahilmgandhi 18:6a4db94011d3 2752 #define GPIO_BSRR_BR_15 (0x80000000U)
sahilmgandhi 18:6a4db94011d3 2753
sahilmgandhi 18:6a4db94011d3 2754 /****************** Bit definition for GPIO_LCKR register ********************/
sahilmgandhi 18:6a4db94011d3 2755 #define GPIO_LCKR_LCK0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2756 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2757 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
sahilmgandhi 18:6a4db94011d3 2758 #define GPIO_LCKR_LCK1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2759 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2760 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
sahilmgandhi 18:6a4db94011d3 2761 #define GPIO_LCKR_LCK2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2762 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2763 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
sahilmgandhi 18:6a4db94011d3 2764 #define GPIO_LCKR_LCK3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2765 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2766 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
sahilmgandhi 18:6a4db94011d3 2767 #define GPIO_LCKR_LCK4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2768 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2769 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
sahilmgandhi 18:6a4db94011d3 2770 #define GPIO_LCKR_LCK5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2771 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2772 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
sahilmgandhi 18:6a4db94011d3 2773 #define GPIO_LCKR_LCK6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2774 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2775 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
sahilmgandhi 18:6a4db94011d3 2776 #define GPIO_LCKR_LCK7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2777 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2778 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
sahilmgandhi 18:6a4db94011d3 2779 #define GPIO_LCKR_LCK8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2780 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2781 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
sahilmgandhi 18:6a4db94011d3 2782 #define GPIO_LCKR_LCK9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2783 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2784 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
sahilmgandhi 18:6a4db94011d3 2785 #define GPIO_LCKR_LCK10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2786 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2787 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
sahilmgandhi 18:6a4db94011d3 2788 #define GPIO_LCKR_LCK11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2789 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2790 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
sahilmgandhi 18:6a4db94011d3 2791 #define GPIO_LCKR_LCK12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2792 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2793 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
sahilmgandhi 18:6a4db94011d3 2794 #define GPIO_LCKR_LCK13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2795 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2796 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
sahilmgandhi 18:6a4db94011d3 2797 #define GPIO_LCKR_LCK14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2798 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2799 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
sahilmgandhi 18:6a4db94011d3 2800 #define GPIO_LCKR_LCK15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2801 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2802 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
sahilmgandhi 18:6a4db94011d3 2803 #define GPIO_LCKR_LCKK_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2804 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2805 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
sahilmgandhi 18:6a4db94011d3 2806
sahilmgandhi 18:6a4db94011d3 2807 /****************** Bit definition for GPIO_AFRL register ********************/
sahilmgandhi 18:6a4db94011d3 2808 #define GPIO_AFRL_AFRL0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2809 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 2810 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
sahilmgandhi 18:6a4db94011d3 2811 #define GPIO_AFRL_AFRL1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2812 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 2813 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
sahilmgandhi 18:6a4db94011d3 2814 #define GPIO_AFRL_AFRL2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2815 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 2816 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
sahilmgandhi 18:6a4db94011d3 2817 #define GPIO_AFRL_AFRL3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2818 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 2819 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
sahilmgandhi 18:6a4db94011d3 2820 #define GPIO_AFRL_AFRL4_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2821 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 2822 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
sahilmgandhi 18:6a4db94011d3 2823 #define GPIO_AFRL_AFRL5_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2824 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 2825 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
sahilmgandhi 18:6a4db94011d3 2826 #define GPIO_AFRL_AFRL6_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2827 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 2828 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
sahilmgandhi 18:6a4db94011d3 2829 #define GPIO_AFRL_AFRL7_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2830 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 2831 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
sahilmgandhi 18:6a4db94011d3 2832
sahilmgandhi 18:6a4db94011d3 2833 /****************** Bit definition for GPIO_AFRH register ********************/
sahilmgandhi 18:6a4db94011d3 2834 #define GPIO_AFRH_AFRH0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2835 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 2836 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
sahilmgandhi 18:6a4db94011d3 2837 #define GPIO_AFRH_AFRH1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2838 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 2839 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
sahilmgandhi 18:6a4db94011d3 2840 #define GPIO_AFRH_AFRH2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2841 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 2842 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
sahilmgandhi 18:6a4db94011d3 2843 #define GPIO_AFRH_AFRH3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2844 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 2845 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
sahilmgandhi 18:6a4db94011d3 2846 #define GPIO_AFRH_AFRH4_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2847 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 2848 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
sahilmgandhi 18:6a4db94011d3 2849 #define GPIO_AFRH_AFRH5_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2850 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 2851 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
sahilmgandhi 18:6a4db94011d3 2852 #define GPIO_AFRH_AFRH6_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2853 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 2854 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
sahilmgandhi 18:6a4db94011d3 2855 #define GPIO_AFRH_AFRH7_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2856 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 2857 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
sahilmgandhi 18:6a4db94011d3 2858
sahilmgandhi 18:6a4db94011d3 2859 /****************** Bit definition for GPIO_BRR register *********************/
sahilmgandhi 18:6a4db94011d3 2860 #define GPIO_BRR_BR_0 (0x00000001U)
sahilmgandhi 18:6a4db94011d3 2861 #define GPIO_BRR_BR_1 (0x00000002U)
sahilmgandhi 18:6a4db94011d3 2862 #define GPIO_BRR_BR_2 (0x00000004U)
sahilmgandhi 18:6a4db94011d3 2863 #define GPIO_BRR_BR_3 (0x00000008U)
sahilmgandhi 18:6a4db94011d3 2864 #define GPIO_BRR_BR_4 (0x00000010U)
sahilmgandhi 18:6a4db94011d3 2865 #define GPIO_BRR_BR_5 (0x00000020U)
sahilmgandhi 18:6a4db94011d3 2866 #define GPIO_BRR_BR_6 (0x00000040U)
sahilmgandhi 18:6a4db94011d3 2867 #define GPIO_BRR_BR_7 (0x00000080U)
sahilmgandhi 18:6a4db94011d3 2868 #define GPIO_BRR_BR_8 (0x00000100U)
sahilmgandhi 18:6a4db94011d3 2869 #define GPIO_BRR_BR_9 (0x00000200U)
sahilmgandhi 18:6a4db94011d3 2870 #define GPIO_BRR_BR_10 (0x00000400U)
sahilmgandhi 18:6a4db94011d3 2871 #define GPIO_BRR_BR_11 (0x00000800U)
sahilmgandhi 18:6a4db94011d3 2872 #define GPIO_BRR_BR_12 (0x00001000U)
sahilmgandhi 18:6a4db94011d3 2873 #define GPIO_BRR_BR_13 (0x00002000U)
sahilmgandhi 18:6a4db94011d3 2874 #define GPIO_BRR_BR_14 (0x00004000U)
sahilmgandhi 18:6a4db94011d3 2875 #define GPIO_BRR_BR_15 (0x00008000U)
sahilmgandhi 18:6a4db94011d3 2876
sahilmgandhi 18:6a4db94011d3 2877 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2878 /* */
sahilmgandhi 18:6a4db94011d3 2879 /* Inter-integrated Circuit Interface (I2C) */
sahilmgandhi 18:6a4db94011d3 2880 /* */
sahilmgandhi 18:6a4db94011d3 2881 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 2882
sahilmgandhi 18:6a4db94011d3 2883 /******************* Bit definition for I2C_CR1 register *******************/
sahilmgandhi 18:6a4db94011d3 2884 #define I2C_CR1_PE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2885 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2886 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
sahilmgandhi 18:6a4db94011d3 2887 #define I2C_CR1_TXIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2888 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2889 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
sahilmgandhi 18:6a4db94011d3 2890 #define I2C_CR1_RXIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2891 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2892 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
sahilmgandhi 18:6a4db94011d3 2893 #define I2C_CR1_ADDRIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2894 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2895 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
sahilmgandhi 18:6a4db94011d3 2896 #define I2C_CR1_NACKIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2897 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2898 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
sahilmgandhi 18:6a4db94011d3 2899 #define I2C_CR1_STOPIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2900 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2901 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
sahilmgandhi 18:6a4db94011d3 2902 #define I2C_CR1_TCIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2903 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2904 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
sahilmgandhi 18:6a4db94011d3 2905 #define I2C_CR1_ERRIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2906 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2907 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
sahilmgandhi 18:6a4db94011d3 2908 #define I2C_CR1_DNF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2909 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 2910 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
sahilmgandhi 18:6a4db94011d3 2911 #define I2C_CR1_ANFOFF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2912 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2913 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
sahilmgandhi 18:6a4db94011d3 2914 #define I2C_CR1_SWRST_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2915 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2916 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
sahilmgandhi 18:6a4db94011d3 2917 #define I2C_CR1_TXDMAEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2918 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2919 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
sahilmgandhi 18:6a4db94011d3 2920 #define I2C_CR1_RXDMAEN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2921 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2922 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
sahilmgandhi 18:6a4db94011d3 2923 #define I2C_CR1_SBC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2924 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2925 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
sahilmgandhi 18:6a4db94011d3 2926 #define I2C_CR1_NOSTRETCH_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2927 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2928 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
sahilmgandhi 18:6a4db94011d3 2929 #define I2C_CR1_WUPEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2930 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2931 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
sahilmgandhi 18:6a4db94011d3 2932 #define I2C_CR1_GCEN_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2933 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2934 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
sahilmgandhi 18:6a4db94011d3 2935 #define I2C_CR1_SMBHEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2936 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2937 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
sahilmgandhi 18:6a4db94011d3 2938 #define I2C_CR1_SMBDEN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2939 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2940 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
sahilmgandhi 18:6a4db94011d3 2941 #define I2C_CR1_ALERTEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2942 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2943 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
sahilmgandhi 18:6a4db94011d3 2944 #define I2C_CR1_PECEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 2945 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2946 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
sahilmgandhi 18:6a4db94011d3 2947
sahilmgandhi 18:6a4db94011d3 2948 /****************** Bit definition for I2C_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 2949 #define I2C_CR2_SADD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2950 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
sahilmgandhi 18:6a4db94011d3 2951 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
sahilmgandhi 18:6a4db94011d3 2952 #define I2C_CR2_RD_WRN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2953 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2954 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
sahilmgandhi 18:6a4db94011d3 2955 #define I2C_CR2_ADD10_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2956 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2957 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
sahilmgandhi 18:6a4db94011d3 2958 #define I2C_CR2_HEAD10R_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2959 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2960 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
sahilmgandhi 18:6a4db94011d3 2961 #define I2C_CR2_START_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2962 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2963 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
sahilmgandhi 18:6a4db94011d3 2964 #define I2C_CR2_STOP_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2965 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2966 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
sahilmgandhi 18:6a4db94011d3 2967 #define I2C_CR2_NACK_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2968 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2969 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
sahilmgandhi 18:6a4db94011d3 2970 #define I2C_CR2_NBYTES_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2971 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2972 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
sahilmgandhi 18:6a4db94011d3 2973 #define I2C_CR2_RELOAD_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2974 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2975 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
sahilmgandhi 18:6a4db94011d3 2976 #define I2C_CR2_AUTOEND_Pos (25U)
sahilmgandhi 18:6a4db94011d3 2977 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2978 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
sahilmgandhi 18:6a4db94011d3 2979 #define I2C_CR2_PECBYTE_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2980 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2981 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
sahilmgandhi 18:6a4db94011d3 2982
sahilmgandhi 18:6a4db94011d3 2983 /******************* Bit definition for I2C_OAR1 register ******************/
sahilmgandhi 18:6a4db94011d3 2984 #define I2C_OAR1_OA1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2985 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
sahilmgandhi 18:6a4db94011d3 2986 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
sahilmgandhi 18:6a4db94011d3 2987 #define I2C_OAR1_OA1MODE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2988 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2989 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
sahilmgandhi 18:6a4db94011d3 2990 #define I2C_OAR1_OA1EN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2991 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2992 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
sahilmgandhi 18:6a4db94011d3 2993
sahilmgandhi 18:6a4db94011d3 2994 /******************* Bit definition for I2C_OAR2 register ******************/
sahilmgandhi 18:6a4db94011d3 2995 #define I2C_OAR2_OA2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2996 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
sahilmgandhi 18:6a4db94011d3 2997 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
sahilmgandhi 18:6a4db94011d3 2998 #define I2C_OAR2_OA2MSK_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2999 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 3000 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
sahilmgandhi 18:6a4db94011d3 3001 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
sahilmgandhi 18:6a4db94011d3 3002 #define I2C_OAR2_OA2MASK01_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3003 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3004 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
sahilmgandhi 18:6a4db94011d3 3005 #define I2C_OAR2_OA2MASK02_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3006 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3007 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
sahilmgandhi 18:6a4db94011d3 3008 #define I2C_OAR2_OA2MASK03_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3009 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 3010 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
sahilmgandhi 18:6a4db94011d3 3011 #define I2C_OAR2_OA2MASK04_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3012 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3013 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
sahilmgandhi 18:6a4db94011d3 3014 #define I2C_OAR2_OA2MASK05_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3015 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
sahilmgandhi 18:6a4db94011d3 3016 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
sahilmgandhi 18:6a4db94011d3 3017 #define I2C_OAR2_OA2MASK06_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3018 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
sahilmgandhi 18:6a4db94011d3 3019 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
sahilmgandhi 18:6a4db94011d3 3020 #define I2C_OAR2_OA2MASK07_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3021 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 3022 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
sahilmgandhi 18:6a4db94011d3 3023 #define I2C_OAR2_OA2EN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3024 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3025 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
sahilmgandhi 18:6a4db94011d3 3026
sahilmgandhi 18:6a4db94011d3 3027 /******************* Bit definition for I2C_TIMINGR register ****************/
sahilmgandhi 18:6a4db94011d3 3028 #define I2C_TIMINGR_SCLL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3029 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 3030 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
sahilmgandhi 18:6a4db94011d3 3031 #define I2C_TIMINGR_SCLH_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3032 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 3033 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
sahilmgandhi 18:6a4db94011d3 3034 #define I2C_TIMINGR_SDADEL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3035 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 3036 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
sahilmgandhi 18:6a4db94011d3 3037 #define I2C_TIMINGR_SCLDEL_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3038 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 3039 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
sahilmgandhi 18:6a4db94011d3 3040 #define I2C_TIMINGR_PRESC_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3041 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 3042 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
sahilmgandhi 18:6a4db94011d3 3043
sahilmgandhi 18:6a4db94011d3 3044 /******************* Bit definition for I2C_TIMEOUTR register ****************/
sahilmgandhi 18:6a4db94011d3 3045 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3046 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 3047 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
sahilmgandhi 18:6a4db94011d3 3048 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3049 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3050 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
sahilmgandhi 18:6a4db94011d3 3051 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3052 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3053 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
sahilmgandhi 18:6a4db94011d3 3054 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3055 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
sahilmgandhi 18:6a4db94011d3 3056 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
sahilmgandhi 18:6a4db94011d3 3057 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3058 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3059 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
sahilmgandhi 18:6a4db94011d3 3060
sahilmgandhi 18:6a4db94011d3 3061 /****************** Bit definition for I2C_ISR register ********************/
sahilmgandhi 18:6a4db94011d3 3062 #define I2C_ISR_TXE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3063 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3064 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
sahilmgandhi 18:6a4db94011d3 3065 #define I2C_ISR_TXIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3066 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3067 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
sahilmgandhi 18:6a4db94011d3 3068 #define I2C_ISR_RXNE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3069 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3070 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
sahilmgandhi 18:6a4db94011d3 3071 #define I2C_ISR_ADDR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3072 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3073 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
sahilmgandhi 18:6a4db94011d3 3074 #define I2C_ISR_NACKF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3075 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3076 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
sahilmgandhi 18:6a4db94011d3 3077 #define I2C_ISR_STOPF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3078 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3079 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
sahilmgandhi 18:6a4db94011d3 3080 #define I2C_ISR_TC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3081 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3082 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
sahilmgandhi 18:6a4db94011d3 3083 #define I2C_ISR_TCR_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3084 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3085 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
sahilmgandhi 18:6a4db94011d3 3086 #define I2C_ISR_BERR_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3087 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3088 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
sahilmgandhi 18:6a4db94011d3 3089 #define I2C_ISR_ARLO_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3090 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3091 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
sahilmgandhi 18:6a4db94011d3 3092 #define I2C_ISR_OVR_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3093 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3094 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
sahilmgandhi 18:6a4db94011d3 3095 #define I2C_ISR_PECERR_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3096 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3097 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
sahilmgandhi 18:6a4db94011d3 3098 #define I2C_ISR_TIMEOUT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3099 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3100 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
sahilmgandhi 18:6a4db94011d3 3101 #define I2C_ISR_ALERT_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3102 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3103 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
sahilmgandhi 18:6a4db94011d3 3104 #define I2C_ISR_BUSY_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3105 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3106 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
sahilmgandhi 18:6a4db94011d3 3107 #define I2C_ISR_DIR_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3108 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3109 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
sahilmgandhi 18:6a4db94011d3 3110 #define I2C_ISR_ADDCODE_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3111 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
sahilmgandhi 18:6a4db94011d3 3112 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
sahilmgandhi 18:6a4db94011d3 3113
sahilmgandhi 18:6a4db94011d3 3114 /****************** Bit definition for I2C_ICR register ********************/
sahilmgandhi 18:6a4db94011d3 3115 #define I2C_ICR_ADDRCF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3116 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3117 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
sahilmgandhi 18:6a4db94011d3 3118 #define I2C_ICR_NACKCF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3119 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3120 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
sahilmgandhi 18:6a4db94011d3 3121 #define I2C_ICR_STOPCF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3122 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3123 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
sahilmgandhi 18:6a4db94011d3 3124 #define I2C_ICR_BERRCF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3125 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3126 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
sahilmgandhi 18:6a4db94011d3 3127 #define I2C_ICR_ARLOCF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3128 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3129 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
sahilmgandhi 18:6a4db94011d3 3130 #define I2C_ICR_OVRCF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3131 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3132 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
sahilmgandhi 18:6a4db94011d3 3133 #define I2C_ICR_PECCF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3134 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3135 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
sahilmgandhi 18:6a4db94011d3 3136 #define I2C_ICR_TIMOUTCF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3137 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3138 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
sahilmgandhi 18:6a4db94011d3 3139 #define I2C_ICR_ALERTCF_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3140 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3141 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
sahilmgandhi 18:6a4db94011d3 3142
sahilmgandhi 18:6a4db94011d3 3143 /****************** Bit definition for I2C_PECR register *******************/
sahilmgandhi 18:6a4db94011d3 3144 #define I2C_PECR_PEC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3145 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 3146 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
sahilmgandhi 18:6a4db94011d3 3147
sahilmgandhi 18:6a4db94011d3 3148 /****************** Bit definition for I2C_RXDR register *********************/
sahilmgandhi 18:6a4db94011d3 3149 #define I2C_RXDR_RXDATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3150 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 3151 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
sahilmgandhi 18:6a4db94011d3 3152
sahilmgandhi 18:6a4db94011d3 3153 /****************** Bit definition for I2C_TXDR register *******************/
sahilmgandhi 18:6a4db94011d3 3154 #define I2C_TXDR_TXDATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3155 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 3156 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
sahilmgandhi 18:6a4db94011d3 3157
sahilmgandhi 18:6a4db94011d3 3158 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 3159 /* */
sahilmgandhi 18:6a4db94011d3 3160 /* Independent WATCHDOG (IWDG) */
sahilmgandhi 18:6a4db94011d3 3161 /* */
sahilmgandhi 18:6a4db94011d3 3162 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 3163 /******************* Bit definition for IWDG_KR register *******************/
sahilmgandhi 18:6a4db94011d3 3164 #define IWDG_KR_KEY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3165 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 3166 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
sahilmgandhi 18:6a4db94011d3 3167
sahilmgandhi 18:6a4db94011d3 3168 /******************* Bit definition for IWDG_PR register *******************/
sahilmgandhi 18:6a4db94011d3 3169 #define IWDG_PR_PR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3170 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 3171 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
sahilmgandhi 18:6a4db94011d3 3172 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
sahilmgandhi 18:6a4db94011d3 3173 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
sahilmgandhi 18:6a4db94011d3 3174 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
sahilmgandhi 18:6a4db94011d3 3175
sahilmgandhi 18:6a4db94011d3 3176 /******************* Bit definition for IWDG_RLR register ******************/
sahilmgandhi 18:6a4db94011d3 3177 #define IWDG_RLR_RL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3178 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 3179 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
sahilmgandhi 18:6a4db94011d3 3180
sahilmgandhi 18:6a4db94011d3 3181 /******************* Bit definition for IWDG_SR register *******************/
sahilmgandhi 18:6a4db94011d3 3182 #define IWDG_SR_PVU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3183 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3184 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
sahilmgandhi 18:6a4db94011d3 3185 #define IWDG_SR_RVU_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3186 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3187 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
sahilmgandhi 18:6a4db94011d3 3188 #define IWDG_SR_WVU_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3189 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3190 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
sahilmgandhi 18:6a4db94011d3 3191
sahilmgandhi 18:6a4db94011d3 3192 /******************* Bit definition for IWDG_KR register *******************/
sahilmgandhi 18:6a4db94011d3 3193 #define IWDG_WINR_WIN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3194 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 3195 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
sahilmgandhi 18:6a4db94011d3 3196
sahilmgandhi 18:6a4db94011d3 3197 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 3198 /* */
sahilmgandhi 18:6a4db94011d3 3199 /* Power Control (PWR) */
sahilmgandhi 18:6a4db94011d3 3200 /* */
sahilmgandhi 18:6a4db94011d3 3201 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 3202
sahilmgandhi 18:6a4db94011d3 3203 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
sahilmgandhi 18:6a4db94011d3 3204
sahilmgandhi 18:6a4db94011d3 3205
sahilmgandhi 18:6a4db94011d3 3206 /******************** Bit definition for PWR_CR register *******************/
sahilmgandhi 18:6a4db94011d3 3207 #define PWR_CR_LPDS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3208 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3209 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
sahilmgandhi 18:6a4db94011d3 3210 #define PWR_CR_PDDS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3211 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3212 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
sahilmgandhi 18:6a4db94011d3 3213 #define PWR_CR_CWUF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3214 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3215 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 3216 #define PWR_CR_CSBF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3217 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3218 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
sahilmgandhi 18:6a4db94011d3 3219 #define PWR_CR_PVDE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3220 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3221 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
sahilmgandhi 18:6a4db94011d3 3222
sahilmgandhi 18:6a4db94011d3 3223 #define PWR_CR_PLS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3224 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
sahilmgandhi 18:6a4db94011d3 3225 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
sahilmgandhi 18:6a4db94011d3 3226 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3227 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3228 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3229
sahilmgandhi 18:6a4db94011d3 3230 /*!< PVD level configuration */
sahilmgandhi 18:6a4db94011d3 3231 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
sahilmgandhi 18:6a4db94011d3 3232 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
sahilmgandhi 18:6a4db94011d3 3233 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
sahilmgandhi 18:6a4db94011d3 3234 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
sahilmgandhi 18:6a4db94011d3 3235 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
sahilmgandhi 18:6a4db94011d3 3236 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
sahilmgandhi 18:6a4db94011d3 3237 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
sahilmgandhi 18:6a4db94011d3 3238 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
sahilmgandhi 18:6a4db94011d3 3239
sahilmgandhi 18:6a4db94011d3 3240 #define PWR_CR_DBP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3241 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3242 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
sahilmgandhi 18:6a4db94011d3 3243
sahilmgandhi 18:6a4db94011d3 3244 /******************* Bit definition for PWR_CSR register *******************/
sahilmgandhi 18:6a4db94011d3 3245 #define PWR_CSR_WUF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3246 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3247 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 3248 #define PWR_CSR_SBF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3249 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3250 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
sahilmgandhi 18:6a4db94011d3 3251 #define PWR_CSR_PVDO_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3252 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3253 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
sahilmgandhi 18:6a4db94011d3 3254 #define PWR_CSR_VREFINTRDYF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3255 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3256 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
sahilmgandhi 18:6a4db94011d3 3257
sahilmgandhi 18:6a4db94011d3 3258 #define PWR_CSR_EWUP1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3259 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3260 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
sahilmgandhi 18:6a4db94011d3 3261 #define PWR_CSR_EWUP2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3262 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3263 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
sahilmgandhi 18:6a4db94011d3 3264
sahilmgandhi 18:6a4db94011d3 3265 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 3266 /* */
sahilmgandhi 18:6a4db94011d3 3267 /* Reset and Clock Control */
sahilmgandhi 18:6a4db94011d3 3268 /* */
sahilmgandhi 18:6a4db94011d3 3269 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 3270 /*
sahilmgandhi 18:6a4db94011d3 3271 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
sahilmgandhi 18:6a4db94011d3 3272 */
sahilmgandhi 18:6a4db94011d3 3273
sahilmgandhi 18:6a4db94011d3 3274 /******************** Bit definition for RCC_CR register *******************/
sahilmgandhi 18:6a4db94011d3 3275 #define RCC_CR_HSION_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3276 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3277 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
sahilmgandhi 18:6a4db94011d3 3278 #define RCC_CR_HSIRDY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3279 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3280 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
sahilmgandhi 18:6a4db94011d3 3281
sahilmgandhi 18:6a4db94011d3 3282 #define RCC_CR_HSITRIM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3283 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
sahilmgandhi 18:6a4db94011d3 3284 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
sahilmgandhi 18:6a4db94011d3 3285 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3286 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3287 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3288 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3289 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3290
sahilmgandhi 18:6a4db94011d3 3291 #define RCC_CR_HSICAL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3292 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 3293 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
sahilmgandhi 18:6a4db94011d3 3294 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3295 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3296 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3297 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3298 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3299 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3300 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3301 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3302
sahilmgandhi 18:6a4db94011d3 3303 #define RCC_CR_HSEON_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3304 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3305 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
sahilmgandhi 18:6a4db94011d3 3306 #define RCC_CR_HSERDY_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3307 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3308 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
sahilmgandhi 18:6a4db94011d3 3309 #define RCC_CR_HSEBYP_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3310 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3311 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
sahilmgandhi 18:6a4db94011d3 3312 #define RCC_CR_CSSON_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3313 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3314 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
sahilmgandhi 18:6a4db94011d3 3315 #define RCC_CR_PLLON_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3316 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3317 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
sahilmgandhi 18:6a4db94011d3 3318 #define RCC_CR_PLLRDY_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3319 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3320 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
sahilmgandhi 18:6a4db94011d3 3321
sahilmgandhi 18:6a4db94011d3 3322 /******************** Bit definition for RCC_CFGR register *****************/
sahilmgandhi 18:6a4db94011d3 3323 /*!< SW configuration */
sahilmgandhi 18:6a4db94011d3 3324 #define RCC_CFGR_SW_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3325 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 3326 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
sahilmgandhi 18:6a4db94011d3 3327 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3328 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3329
sahilmgandhi 18:6a4db94011d3 3330 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
sahilmgandhi 18:6a4db94011d3 3331 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
sahilmgandhi 18:6a4db94011d3 3332 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
sahilmgandhi 18:6a4db94011d3 3333
sahilmgandhi 18:6a4db94011d3 3334 /*!< SWS configuration */
sahilmgandhi 18:6a4db94011d3 3335 #define RCC_CFGR_SWS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3336 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 3337 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
sahilmgandhi 18:6a4db94011d3 3338 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3339 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3340
sahilmgandhi 18:6a4db94011d3 3341 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 3342 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 3343 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
sahilmgandhi 18:6a4db94011d3 3344
sahilmgandhi 18:6a4db94011d3 3345 /*!< HPRE configuration */
sahilmgandhi 18:6a4db94011d3 3346 #define RCC_CFGR_HPRE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3347 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 3348 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
sahilmgandhi 18:6a4db94011d3 3349 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3350 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3351 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3352 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3353
sahilmgandhi 18:6a4db94011d3 3354 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
sahilmgandhi 18:6a4db94011d3 3355 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 3356 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 3357 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 3358 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 3359 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
sahilmgandhi 18:6a4db94011d3 3360 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
sahilmgandhi 18:6a4db94011d3 3361 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
sahilmgandhi 18:6a4db94011d3 3362 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
sahilmgandhi 18:6a4db94011d3 3363
sahilmgandhi 18:6a4db94011d3 3364 /*!< PPRE configuration */
sahilmgandhi 18:6a4db94011d3 3365 #define RCC_CFGR_PPRE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3366 #define RCC_CFGR_PPRE_Msk (0x7U << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 3367 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */
sahilmgandhi 18:6a4db94011d3 3368 #define RCC_CFGR_PPRE_0 (0x1U << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3369 #define RCC_CFGR_PPRE_1 (0x2U << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3370 #define RCC_CFGR_PPRE_2 (0x4U << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3371
sahilmgandhi 18:6a4db94011d3 3372 #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */
sahilmgandhi 18:6a4db94011d3 3373 #define RCC_CFGR_PPRE_DIV2_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3374 #define RCC_CFGR_PPRE_DIV2_Msk (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3375 #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 3376 #define RCC_CFGR_PPRE_DIV4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3377 #define RCC_CFGR_PPRE_DIV4_Msk (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
sahilmgandhi 18:6a4db94011d3 3378 #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 3379 #define RCC_CFGR_PPRE_DIV8_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3380 #define RCC_CFGR_PPRE_DIV8_Msk (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
sahilmgandhi 18:6a4db94011d3 3381 #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 3382 #define RCC_CFGR_PPRE_DIV16_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3383 #define RCC_CFGR_PPRE_DIV16_Msk (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 3384 #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 3385
sahilmgandhi 18:6a4db94011d3 3386 /*!< ADCPPRE configuration */
sahilmgandhi 18:6a4db94011d3 3387 #define RCC_CFGR_ADCPRE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3388 #define RCC_CFGR_ADCPRE_Msk (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3389 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */
sahilmgandhi 18:6a4db94011d3 3390
sahilmgandhi 18:6a4db94011d3 3391 #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 3392 #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 3393
sahilmgandhi 18:6a4db94011d3 3394 #define RCC_CFGR_PLLSRC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3395 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3396 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
sahilmgandhi 18:6a4db94011d3 3397 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
sahilmgandhi 18:6a4db94011d3 3398 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
sahilmgandhi 18:6a4db94011d3 3399
sahilmgandhi 18:6a4db94011d3 3400 #define RCC_CFGR_PLLXTPRE_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3401 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3402 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
sahilmgandhi 18:6a4db94011d3 3403 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
sahilmgandhi 18:6a4db94011d3 3404 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
sahilmgandhi 18:6a4db94011d3 3405
sahilmgandhi 18:6a4db94011d3 3406 /*!< PLLMUL configuration */
sahilmgandhi 18:6a4db94011d3 3407 #define RCC_CFGR_PLLMUL_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3408 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
sahilmgandhi 18:6a4db94011d3 3409 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
sahilmgandhi 18:6a4db94011d3 3410 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3411 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3412 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3413 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3414
sahilmgandhi 18:6a4db94011d3 3415 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
sahilmgandhi 18:6a4db94011d3 3416 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
sahilmgandhi 18:6a4db94011d3 3417 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
sahilmgandhi 18:6a4db94011d3 3418 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
sahilmgandhi 18:6a4db94011d3 3419 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
sahilmgandhi 18:6a4db94011d3 3420 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
sahilmgandhi 18:6a4db94011d3 3421 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
sahilmgandhi 18:6a4db94011d3 3422 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
sahilmgandhi 18:6a4db94011d3 3423 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
sahilmgandhi 18:6a4db94011d3 3424 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
sahilmgandhi 18:6a4db94011d3 3425 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
sahilmgandhi 18:6a4db94011d3 3426 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
sahilmgandhi 18:6a4db94011d3 3427 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
sahilmgandhi 18:6a4db94011d3 3428 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
sahilmgandhi 18:6a4db94011d3 3429 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
sahilmgandhi 18:6a4db94011d3 3430
sahilmgandhi 18:6a4db94011d3 3431 /*!< MCO configuration */
sahilmgandhi 18:6a4db94011d3 3432 #define RCC_CFGR_MCO_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3433 #define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 3434 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
sahilmgandhi 18:6a4db94011d3 3435 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3436 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3437 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3438
sahilmgandhi 18:6a4db94011d3 3439 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
sahilmgandhi 18:6a4db94011d3 3440 #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */
sahilmgandhi 18:6a4db94011d3 3441 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
sahilmgandhi 18:6a4db94011d3 3442 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
sahilmgandhi 18:6a4db94011d3 3443 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
sahilmgandhi 18:6a4db94011d3 3444 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
sahilmgandhi 18:6a4db94011d3 3445 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
sahilmgandhi 18:6a4db94011d3 3446 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
sahilmgandhi 18:6a4db94011d3 3447
sahilmgandhi 18:6a4db94011d3 3448 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 3449 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
sahilmgandhi 18:6a4db94011d3 3450 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
sahilmgandhi 18:6a4db94011d3 3451 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
sahilmgandhi 18:6a4db94011d3 3452 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
sahilmgandhi 18:6a4db94011d3 3453 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
sahilmgandhi 18:6a4db94011d3 3454 #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14
sahilmgandhi 18:6a4db94011d3 3455 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
sahilmgandhi 18:6a4db94011d3 3456 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
sahilmgandhi 18:6a4db94011d3 3457 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
sahilmgandhi 18:6a4db94011d3 3458 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
sahilmgandhi 18:6a4db94011d3 3459 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
sahilmgandhi 18:6a4db94011d3 3460 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
sahilmgandhi 18:6a4db94011d3 3461
sahilmgandhi 18:6a4db94011d3 3462 /*!<****************** Bit definition for RCC_CIR register *****************/
sahilmgandhi 18:6a4db94011d3 3463 #define RCC_CIR_LSIRDYF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3464 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3465 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 3466 #define RCC_CIR_LSERDYF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3467 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3468 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 3469 #define RCC_CIR_HSIRDYF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3470 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3471 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 3472 #define RCC_CIR_HSERDYF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3473 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3474 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 3475 #define RCC_CIR_PLLRDYF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3476 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3477 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 3478 #define RCC_CIR_HSI14RDYF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3479 #define RCC_CIR_HSI14RDYF_Msk (0x1U << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3480 #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */
sahilmgandhi 18:6a4db94011d3 3481 #define RCC_CIR_CSSF_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3482 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3483 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
sahilmgandhi 18:6a4db94011d3 3484 #define RCC_CIR_LSIRDYIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3485 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3486 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3487 #define RCC_CIR_LSERDYIE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3488 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3489 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3490 #define RCC_CIR_HSIRDYIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3491 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3492 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3493 #define RCC_CIR_HSERDYIE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3494 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3495 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3496 #define RCC_CIR_PLLRDYIE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3497 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3498 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3499 #define RCC_CIR_HSI14RDYIE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3500 #define RCC_CIR_HSI14RDYIE_Msk (0x1U << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3501 #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 3502 #define RCC_CIR_LSIRDYC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3503 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3504 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 3505 #define RCC_CIR_LSERDYC_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3506 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3507 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 3508 #define RCC_CIR_HSIRDYC_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3509 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3510 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 3511 #define RCC_CIR_HSERDYC_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3512 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3513 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 3514 #define RCC_CIR_PLLRDYC_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3515 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3516 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 3517 #define RCC_CIR_HSI14RDYC_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3518 #define RCC_CIR_HSI14RDYC_Msk (0x1U << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3519 #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 3520 #define RCC_CIR_CSSC_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3521 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3522 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
sahilmgandhi 18:6a4db94011d3 3523
sahilmgandhi 18:6a4db94011d3 3524 /***************** Bit definition for RCC_APB2RSTR register ****************/
sahilmgandhi 18:6a4db94011d3 3525 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3526 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3527 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */
sahilmgandhi 18:6a4db94011d3 3528 #define RCC_APB2RSTR_ADCRST_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3529 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3530 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */
sahilmgandhi 18:6a4db94011d3 3531 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3532 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3533 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */
sahilmgandhi 18:6a4db94011d3 3534 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3535 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3536 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */
sahilmgandhi 18:6a4db94011d3 3537 #define RCC_APB2RSTR_USART1RST_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3538 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3539 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */
sahilmgandhi 18:6a4db94011d3 3540 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3541 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3542 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */
sahilmgandhi 18:6a4db94011d3 3543 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3544 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3545 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */
sahilmgandhi 18:6a4db94011d3 3546 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3547 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3548 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */
sahilmgandhi 18:6a4db94011d3 3549 #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3550 #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3551 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */
sahilmgandhi 18:6a4db94011d3 3552
sahilmgandhi 18:6a4db94011d3 3553 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 3554 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
sahilmgandhi 18:6a4db94011d3 3555
sahilmgandhi 18:6a4db94011d3 3556 /***************** Bit definition for RCC_APB1RSTR register ****************/
sahilmgandhi 18:6a4db94011d3 3557 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3558 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3559 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */
sahilmgandhi 18:6a4db94011d3 3560 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3561 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3562 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */
sahilmgandhi 18:6a4db94011d3 3563 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3564 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3565 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */
sahilmgandhi 18:6a4db94011d3 3566 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3567 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3568 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */
sahilmgandhi 18:6a4db94011d3 3569 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3570 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3571 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */
sahilmgandhi 18:6a4db94011d3 3572 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3573 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3574 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */
sahilmgandhi 18:6a4db94011d3 3575 #define RCC_APB1RSTR_USART2RST_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3576 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3577 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */
sahilmgandhi 18:6a4db94011d3 3578 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3579 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3580 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */
sahilmgandhi 18:6a4db94011d3 3581 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3582 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3583 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */
sahilmgandhi 18:6a4db94011d3 3584 #define RCC_APB1RSTR_PWRRST_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3585 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3586 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */
sahilmgandhi 18:6a4db94011d3 3587 #define RCC_APB1RSTR_DACRST_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3588 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3589 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */
sahilmgandhi 18:6a4db94011d3 3590 #define RCC_APB1RSTR_CECRST_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3591 #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3592 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC clock reset */
sahilmgandhi 18:6a4db94011d3 3593
sahilmgandhi 18:6a4db94011d3 3594 /****************** Bit definition for RCC_AHBENR register *****************/
sahilmgandhi 18:6a4db94011d3 3595 #define RCC_AHBENR_DMAEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3596 #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3597 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
sahilmgandhi 18:6a4db94011d3 3598 #define RCC_AHBENR_SRAMEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3599 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3600 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
sahilmgandhi 18:6a4db94011d3 3601 #define RCC_AHBENR_FLITFEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3602 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3603 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
sahilmgandhi 18:6a4db94011d3 3604 #define RCC_AHBENR_CRCEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3605 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3606 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
sahilmgandhi 18:6a4db94011d3 3607 #define RCC_AHBENR_GPIOAEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3608 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3609 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
sahilmgandhi 18:6a4db94011d3 3610 #define RCC_AHBENR_GPIOBEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3611 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3612 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
sahilmgandhi 18:6a4db94011d3 3613 #define RCC_AHBENR_GPIOCEN_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3614 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3615 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
sahilmgandhi 18:6a4db94011d3 3616 #define RCC_AHBENR_GPIODEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3617 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3618 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
sahilmgandhi 18:6a4db94011d3 3619 #define RCC_AHBENR_GPIOFEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3620 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3621 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
sahilmgandhi 18:6a4db94011d3 3622 #define RCC_AHBENR_TSCEN_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3623 #define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3624 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller clock enable */
sahilmgandhi 18:6a4db94011d3 3625
sahilmgandhi 18:6a4db94011d3 3626 /* Old Bit definition maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 3627 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
sahilmgandhi 18:6a4db94011d3 3628 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
sahilmgandhi 18:6a4db94011d3 3629
sahilmgandhi 18:6a4db94011d3 3630 /***************** Bit definition for RCC_APB2ENR register *****************/
sahilmgandhi 18:6a4db94011d3 3631 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3632 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3633 #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */
sahilmgandhi 18:6a4db94011d3 3634 #define RCC_APB2ENR_ADCEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3635 #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3636 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
sahilmgandhi 18:6a4db94011d3 3637 #define RCC_APB2ENR_TIM1EN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3638 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3639 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
sahilmgandhi 18:6a4db94011d3 3640 #define RCC_APB2ENR_SPI1EN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3641 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3642 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
sahilmgandhi 18:6a4db94011d3 3643 #define RCC_APB2ENR_USART1EN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3644 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3645 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
sahilmgandhi 18:6a4db94011d3 3646 #define RCC_APB2ENR_TIM15EN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3647 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3648 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */
sahilmgandhi 18:6a4db94011d3 3649 #define RCC_APB2ENR_TIM16EN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3650 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3651 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
sahilmgandhi 18:6a4db94011d3 3652 #define RCC_APB2ENR_TIM17EN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3653 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3654 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
sahilmgandhi 18:6a4db94011d3 3655 #define RCC_APB2ENR_DBGMCUEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3656 #define RCC_APB2ENR_DBGMCUEN_Msk (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3657 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */
sahilmgandhi 18:6a4db94011d3 3658
sahilmgandhi 18:6a4db94011d3 3659 /* Old Bit definition maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 3660 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
sahilmgandhi 18:6a4db94011d3 3661 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
sahilmgandhi 18:6a4db94011d3 3662
sahilmgandhi 18:6a4db94011d3 3663 /***************** Bit definition for RCC_APB1ENR register *****************/
sahilmgandhi 18:6a4db94011d3 3664 #define RCC_APB1ENR_TIM2EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3665 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3666 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
sahilmgandhi 18:6a4db94011d3 3667 #define RCC_APB1ENR_TIM3EN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3668 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3669 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
sahilmgandhi 18:6a4db94011d3 3670 #define RCC_APB1ENR_TIM6EN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3671 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3672 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
sahilmgandhi 18:6a4db94011d3 3673 #define RCC_APB1ENR_TIM14EN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3674 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3675 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */
sahilmgandhi 18:6a4db94011d3 3676 #define RCC_APB1ENR_WWDGEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3677 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3678 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
sahilmgandhi 18:6a4db94011d3 3679 #define RCC_APB1ENR_SPI2EN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3680 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3681 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
sahilmgandhi 18:6a4db94011d3 3682 #define RCC_APB1ENR_USART2EN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3683 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3684 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
sahilmgandhi 18:6a4db94011d3 3685 #define RCC_APB1ENR_I2C1EN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3686 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3687 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
sahilmgandhi 18:6a4db94011d3 3688 #define RCC_APB1ENR_I2C2EN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3689 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3690 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
sahilmgandhi 18:6a4db94011d3 3691 #define RCC_APB1ENR_PWREN_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3692 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3693 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
sahilmgandhi 18:6a4db94011d3 3694 #define RCC_APB1ENR_DACEN_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3695 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3696 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
sahilmgandhi 18:6a4db94011d3 3697 #define RCC_APB1ENR_CECEN_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3698 #define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3699 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enable */
sahilmgandhi 18:6a4db94011d3 3700
sahilmgandhi 18:6a4db94011d3 3701 /******************* Bit definition for RCC_BDCR register ******************/
sahilmgandhi 18:6a4db94011d3 3702 #define RCC_BDCR_LSEON_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3703 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3704 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
sahilmgandhi 18:6a4db94011d3 3705 #define RCC_BDCR_LSERDY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3706 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3707 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
sahilmgandhi 18:6a4db94011d3 3708 #define RCC_BDCR_LSEBYP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3709 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3710 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
sahilmgandhi 18:6a4db94011d3 3711
sahilmgandhi 18:6a4db94011d3 3712 #define RCC_BDCR_LSEDRV_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3713 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
sahilmgandhi 18:6a4db94011d3 3714 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
sahilmgandhi 18:6a4db94011d3 3715 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3716 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3717
sahilmgandhi 18:6a4db94011d3 3718 #define RCC_BDCR_RTCSEL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3719 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 3720 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
sahilmgandhi 18:6a4db94011d3 3721 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3722 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3723
sahilmgandhi 18:6a4db94011d3 3724 /*!< RTC configuration */
sahilmgandhi 18:6a4db94011d3 3725 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
sahilmgandhi 18:6a4db94011d3 3726 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
sahilmgandhi 18:6a4db94011d3 3727 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
sahilmgandhi 18:6a4db94011d3 3728 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */
sahilmgandhi 18:6a4db94011d3 3729
sahilmgandhi 18:6a4db94011d3 3730 #define RCC_BDCR_RTCEN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3731 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3732 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
sahilmgandhi 18:6a4db94011d3 3733 #define RCC_BDCR_BDRST_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3734 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3735 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
sahilmgandhi 18:6a4db94011d3 3736
sahilmgandhi 18:6a4db94011d3 3737 /******************* Bit definition for RCC_CSR register *******************/
sahilmgandhi 18:6a4db94011d3 3738 #define RCC_CSR_LSION_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3739 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3740 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
sahilmgandhi 18:6a4db94011d3 3741 #define RCC_CSR_LSIRDY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3742 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3743 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
sahilmgandhi 18:6a4db94011d3 3744 #define RCC_CSR_V18PWRRSTF_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3745 #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3746 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
sahilmgandhi 18:6a4db94011d3 3747 #define RCC_CSR_RMVF_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3748 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3749 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
sahilmgandhi 18:6a4db94011d3 3750 #define RCC_CSR_OBLRSTF_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3751 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3752 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
sahilmgandhi 18:6a4db94011d3 3753 #define RCC_CSR_PINRSTF_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3754 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3755 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
sahilmgandhi 18:6a4db94011d3 3756 #define RCC_CSR_PORRSTF_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3757 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3758 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
sahilmgandhi 18:6a4db94011d3 3759 #define RCC_CSR_SFTRSTF_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3760 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3761 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
sahilmgandhi 18:6a4db94011d3 3762 #define RCC_CSR_IWDGRSTF_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3763 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3764 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
sahilmgandhi 18:6a4db94011d3 3765 #define RCC_CSR_WWDGRSTF_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3766 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3767 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
sahilmgandhi 18:6a4db94011d3 3768 #define RCC_CSR_LPWRRSTF_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3769 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3770 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
sahilmgandhi 18:6a4db94011d3 3771
sahilmgandhi 18:6a4db94011d3 3772 /* Old Bit definition maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 3773 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
sahilmgandhi 18:6a4db94011d3 3774
sahilmgandhi 18:6a4db94011d3 3775 /******************* Bit definition for RCC_AHBRSTR register ***************/
sahilmgandhi 18:6a4db94011d3 3776 #define RCC_AHBRSTR_GPIOARST_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3777 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3778 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */
sahilmgandhi 18:6a4db94011d3 3779 #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3780 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3781 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */
sahilmgandhi 18:6a4db94011d3 3782 #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3783 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3784 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */
sahilmgandhi 18:6a4db94011d3 3785 #define RCC_AHBRSTR_GPIODRST_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3786 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3787 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */
sahilmgandhi 18:6a4db94011d3 3788 #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3789 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3790 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */
sahilmgandhi 18:6a4db94011d3 3791 #define RCC_AHBRSTR_TSCRST_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3792 #define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3793 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TS clock reset */
sahilmgandhi 18:6a4db94011d3 3794
sahilmgandhi 18:6a4db94011d3 3795 /* Old Bit definition maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 3796 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
sahilmgandhi 18:6a4db94011d3 3797
sahilmgandhi 18:6a4db94011d3 3798 /******************* Bit definition for RCC_CFGR2 register *****************/
sahilmgandhi 18:6a4db94011d3 3799 /*!< PREDIV configuration */
sahilmgandhi 18:6a4db94011d3 3800 #define RCC_CFGR2_PREDIV_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3801 #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 3802 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
sahilmgandhi 18:6a4db94011d3 3803 #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3804 #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3805 #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3806 #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3807
sahilmgandhi 18:6a4db94011d3 3808 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
sahilmgandhi 18:6a4db94011d3 3809 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
sahilmgandhi 18:6a4db94011d3 3810 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
sahilmgandhi 18:6a4db94011d3 3811 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
sahilmgandhi 18:6a4db94011d3 3812 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
sahilmgandhi 18:6a4db94011d3 3813 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
sahilmgandhi 18:6a4db94011d3 3814 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
sahilmgandhi 18:6a4db94011d3 3815 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
sahilmgandhi 18:6a4db94011d3 3816 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
sahilmgandhi 18:6a4db94011d3 3817 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
sahilmgandhi 18:6a4db94011d3 3818 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
sahilmgandhi 18:6a4db94011d3 3819 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
sahilmgandhi 18:6a4db94011d3 3820 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
sahilmgandhi 18:6a4db94011d3 3821 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
sahilmgandhi 18:6a4db94011d3 3822 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
sahilmgandhi 18:6a4db94011d3 3823 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
sahilmgandhi 18:6a4db94011d3 3824
sahilmgandhi 18:6a4db94011d3 3825 /******************* Bit definition for RCC_CFGR3 register *****************/
sahilmgandhi 18:6a4db94011d3 3826 /*!< USART1 Clock source selection */
sahilmgandhi 18:6a4db94011d3 3827 #define RCC_CFGR3_USART1SW_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3828 #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 3829 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
sahilmgandhi 18:6a4db94011d3 3830 #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3831 #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3832
sahilmgandhi 18:6a4db94011d3 3833 #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */
sahilmgandhi 18:6a4db94011d3 3834 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
sahilmgandhi 18:6a4db94011d3 3835 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
sahilmgandhi 18:6a4db94011d3 3836 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
sahilmgandhi 18:6a4db94011d3 3837
sahilmgandhi 18:6a4db94011d3 3838 /*!< I2C1 Clock source selection */
sahilmgandhi 18:6a4db94011d3 3839 #define RCC_CFGR3_I2C1SW_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3840 #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3841 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
sahilmgandhi 18:6a4db94011d3 3842
sahilmgandhi 18:6a4db94011d3 3843 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
sahilmgandhi 18:6a4db94011d3 3844 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3845 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3846 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
sahilmgandhi 18:6a4db94011d3 3847
sahilmgandhi 18:6a4db94011d3 3848 /*!< CEC Clock source selection */
sahilmgandhi 18:6a4db94011d3 3849 #define RCC_CFGR3_CECSW_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3850 #define RCC_CFGR3_CECSW_Msk (0x1U << RCC_CFGR3_CECSW_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3851 #define RCC_CFGR3_CECSW RCC_CFGR3_CECSW_Msk /*!< CECSW bits */
sahilmgandhi 18:6a4db94011d3 3852
sahilmgandhi 18:6a4db94011d3 3853 #define RCC_CFGR3_CECSW_HSI_DIV244 (0x00000000U) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
sahilmgandhi 18:6a4db94011d3 3854 #define RCC_CFGR3_CECSW_LSE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3855 #define RCC_CFGR3_CECSW_LSE_Msk (0x1U << RCC_CFGR3_CECSW_LSE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3856 #define RCC_CFGR3_CECSW_LSE RCC_CFGR3_CECSW_LSE_Msk /*!< LSE clock selected as HDMI CEC entry clock source */
sahilmgandhi 18:6a4db94011d3 3857
sahilmgandhi 18:6a4db94011d3 3858 /******************* Bit definition for RCC_CR2 register *******************/
sahilmgandhi 18:6a4db94011d3 3859 #define RCC_CR2_HSI14ON_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3860 #define RCC_CR2_HSI14ON_Msk (0x1U << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3861 #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */
sahilmgandhi 18:6a4db94011d3 3862 #define RCC_CR2_HSI14RDY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3863 #define RCC_CR2_HSI14RDY_Msk (0x1U << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3864 #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */
sahilmgandhi 18:6a4db94011d3 3865 #define RCC_CR2_HSI14DIS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3866 #define RCC_CR2_HSI14DIS_Msk (0x1U << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3867 #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */
sahilmgandhi 18:6a4db94011d3 3868 #define RCC_CR2_HSI14TRIM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3869 #define RCC_CR2_HSI14TRIM_Msk (0x1FU << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
sahilmgandhi 18:6a4db94011d3 3870 #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */
sahilmgandhi 18:6a4db94011d3 3871 #define RCC_CR2_HSI14CAL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3872 #define RCC_CR2_HSI14CAL_Msk (0xFFU << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 3873 #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */
sahilmgandhi 18:6a4db94011d3 3874
sahilmgandhi 18:6a4db94011d3 3875 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 3876 /* */
sahilmgandhi 18:6a4db94011d3 3877 /* Real-Time Clock (RTC) */
sahilmgandhi 18:6a4db94011d3 3878 /* */
sahilmgandhi 18:6a4db94011d3 3879 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 3880 /*
sahilmgandhi 18:6a4db94011d3 3881 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
sahilmgandhi 18:6a4db94011d3 3882 */
sahilmgandhi 18:6a4db94011d3 3883 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
sahilmgandhi 18:6a4db94011d3 3884 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
sahilmgandhi 18:6a4db94011d3 3885 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
sahilmgandhi 18:6a4db94011d3 3886
sahilmgandhi 18:6a4db94011d3 3887 /******************** Bits definition for RTC_TR register ******************/
sahilmgandhi 18:6a4db94011d3 3888 #define RTC_TR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3889 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3890 #define RTC_TR_PM RTC_TR_PM_Msk
sahilmgandhi 18:6a4db94011d3 3891 #define RTC_TR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3892 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 3893 #define RTC_TR_HT RTC_TR_HT_Msk
sahilmgandhi 18:6a4db94011d3 3894 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3895 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3896 #define RTC_TR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3897 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 3898 #define RTC_TR_HU RTC_TR_HU_Msk
sahilmgandhi 18:6a4db94011d3 3899 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3900 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3901 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3902 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3903 #define RTC_TR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3904 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 3905 #define RTC_TR_MNT RTC_TR_MNT_Msk
sahilmgandhi 18:6a4db94011d3 3906 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3907 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3908 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3909 #define RTC_TR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3910 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 3911 #define RTC_TR_MNU RTC_TR_MNU_Msk
sahilmgandhi 18:6a4db94011d3 3912 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3913 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3914 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3915 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3916 #define RTC_TR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3917 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 3918 #define RTC_TR_ST RTC_TR_ST_Msk
sahilmgandhi 18:6a4db94011d3 3919 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3920 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3921 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3922 #define RTC_TR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3923 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 3924 #define RTC_TR_SU RTC_TR_SU_Msk
sahilmgandhi 18:6a4db94011d3 3925 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3926 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3927 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3928 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3929
sahilmgandhi 18:6a4db94011d3 3930 /******************** Bits definition for RTC_DR register ******************/
sahilmgandhi 18:6a4db94011d3 3931 #define RTC_DR_YT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3932 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 3933 #define RTC_DR_YT RTC_DR_YT_Msk
sahilmgandhi 18:6a4db94011d3 3934 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3935 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3936 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3937 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3938 #define RTC_DR_YU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3939 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 3940 #define RTC_DR_YU RTC_DR_YU_Msk
sahilmgandhi 18:6a4db94011d3 3941 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3942 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3943 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3944 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3945 #define RTC_DR_WDU_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3946 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 3947 #define RTC_DR_WDU RTC_DR_WDU_Msk
sahilmgandhi 18:6a4db94011d3 3948 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3949 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3950 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3951 #define RTC_DR_MT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3952 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3953 #define RTC_DR_MT RTC_DR_MT_Msk
sahilmgandhi 18:6a4db94011d3 3954 #define RTC_DR_MU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3955 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 3956 #define RTC_DR_MU RTC_DR_MU_Msk
sahilmgandhi 18:6a4db94011d3 3957 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3958 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3959 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3960 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3961 #define RTC_DR_DT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3962 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 3963 #define RTC_DR_DT RTC_DR_DT_Msk
sahilmgandhi 18:6a4db94011d3 3964 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3965 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3966 #define RTC_DR_DU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3967 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 3968 #define RTC_DR_DU RTC_DR_DU_Msk
sahilmgandhi 18:6a4db94011d3 3969 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3970 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3971 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3972 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3973
sahilmgandhi 18:6a4db94011d3 3974 /******************** Bits definition for RTC_CR register ******************/
sahilmgandhi 18:6a4db94011d3 3975 #define RTC_CR_COE_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3976 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3977 #define RTC_CR_COE RTC_CR_COE_Msk
sahilmgandhi 18:6a4db94011d3 3978 #define RTC_CR_OSEL_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3979 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
sahilmgandhi 18:6a4db94011d3 3980 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
sahilmgandhi 18:6a4db94011d3 3981 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3982 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3983 #define RTC_CR_POL_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3984 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3985 #define RTC_CR_POL RTC_CR_POL_Msk
sahilmgandhi 18:6a4db94011d3 3986 #define RTC_CR_COSEL_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3987 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3988 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
sahilmgandhi 18:6a4db94011d3 3989 #define RTC_CR_BCK_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3990 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3991 #define RTC_CR_BCK RTC_CR_BCK_Msk
sahilmgandhi 18:6a4db94011d3 3992 #define RTC_CR_SUB1H_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3993 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3994 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
sahilmgandhi 18:6a4db94011d3 3995 #define RTC_CR_ADD1H_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3996 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3997 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
sahilmgandhi 18:6a4db94011d3 3998 #define RTC_CR_TSIE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3999 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4000 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
sahilmgandhi 18:6a4db94011d3 4001 #define RTC_CR_ALRAIE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4002 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4003 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
sahilmgandhi 18:6a4db94011d3 4004 #define RTC_CR_TSE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4005 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4006 #define RTC_CR_TSE RTC_CR_TSE_Msk
sahilmgandhi 18:6a4db94011d3 4007 #define RTC_CR_ALRAE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4008 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4009 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
sahilmgandhi 18:6a4db94011d3 4010 #define RTC_CR_FMT_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4011 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4012 #define RTC_CR_FMT RTC_CR_FMT_Msk
sahilmgandhi 18:6a4db94011d3 4013 #define RTC_CR_BYPSHAD_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4014 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4015 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
sahilmgandhi 18:6a4db94011d3 4016 #define RTC_CR_REFCKON_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4017 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4018 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
sahilmgandhi 18:6a4db94011d3 4019 #define RTC_CR_TSEDGE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4020 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4021 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
sahilmgandhi 18:6a4db94011d3 4022
sahilmgandhi 18:6a4db94011d3 4023 /******************** Bits definition for RTC_ISR register *****************/
sahilmgandhi 18:6a4db94011d3 4024 #define RTC_ISR_RECALPF_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4025 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4026 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
sahilmgandhi 18:6a4db94011d3 4027 #define RTC_ISR_TAMP2F_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4028 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4029 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
sahilmgandhi 18:6a4db94011d3 4030 #define RTC_ISR_TAMP1F_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4031 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4032 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
sahilmgandhi 18:6a4db94011d3 4033 #define RTC_ISR_TSOVF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4034 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4035 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
sahilmgandhi 18:6a4db94011d3 4036 #define RTC_ISR_TSF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4037 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4038 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
sahilmgandhi 18:6a4db94011d3 4039 #define RTC_ISR_ALRAF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4040 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4041 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
sahilmgandhi 18:6a4db94011d3 4042 #define RTC_ISR_INIT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4043 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4044 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
sahilmgandhi 18:6a4db94011d3 4045 #define RTC_ISR_INITF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4046 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4047 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
sahilmgandhi 18:6a4db94011d3 4048 #define RTC_ISR_RSF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4049 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4050 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
sahilmgandhi 18:6a4db94011d3 4051 #define RTC_ISR_INITS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4052 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4053 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
sahilmgandhi 18:6a4db94011d3 4054 #define RTC_ISR_SHPF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4055 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4056 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
sahilmgandhi 18:6a4db94011d3 4057 #define RTC_ISR_ALRAWF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4058 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4059 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
sahilmgandhi 18:6a4db94011d3 4060
sahilmgandhi 18:6a4db94011d3 4061 /******************** Bits definition for RTC_PRER register ****************/
sahilmgandhi 18:6a4db94011d3 4062 #define RTC_PRER_PREDIV_A_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4063 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
sahilmgandhi 18:6a4db94011d3 4064 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
sahilmgandhi 18:6a4db94011d3 4065 #define RTC_PRER_PREDIV_S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4066 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 4067 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
sahilmgandhi 18:6a4db94011d3 4068
sahilmgandhi 18:6a4db94011d3 4069 /******************** Bits definition for RTC_ALRMAR register **************/
sahilmgandhi 18:6a4db94011d3 4070 #define RTC_ALRMAR_MSK4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4071 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4072 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
sahilmgandhi 18:6a4db94011d3 4073 #define RTC_ALRMAR_WDSEL_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4074 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4075 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
sahilmgandhi 18:6a4db94011d3 4076 #define RTC_ALRMAR_DT_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4077 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 4078 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
sahilmgandhi 18:6a4db94011d3 4079 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4080 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4081 #define RTC_ALRMAR_DU_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4082 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 4083 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
sahilmgandhi 18:6a4db94011d3 4084 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4085 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4086 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4087 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4088 #define RTC_ALRMAR_MSK3_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4089 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4090 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
sahilmgandhi 18:6a4db94011d3 4091 #define RTC_ALRMAR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4092 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4093 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
sahilmgandhi 18:6a4db94011d3 4094 #define RTC_ALRMAR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4095 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 4096 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
sahilmgandhi 18:6a4db94011d3 4097 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4098 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4099 #define RTC_ALRMAR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4100 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 4101 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
sahilmgandhi 18:6a4db94011d3 4102 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4103 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4104 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4105 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4106 #define RTC_ALRMAR_MSK2_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4107 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4108 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
sahilmgandhi 18:6a4db94011d3 4109 #define RTC_ALRMAR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4110 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 4111 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
sahilmgandhi 18:6a4db94011d3 4112 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4113 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4114 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4115 #define RTC_ALRMAR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4116 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4117 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
sahilmgandhi 18:6a4db94011d3 4118 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4119 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4120 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4121 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4122 #define RTC_ALRMAR_MSK1_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4123 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4124 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
sahilmgandhi 18:6a4db94011d3 4125 #define RTC_ALRMAR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4126 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 4127 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
sahilmgandhi 18:6a4db94011d3 4128 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4129 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4130 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4131 #define RTC_ALRMAR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4132 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 4133 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
sahilmgandhi 18:6a4db94011d3 4134 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4135 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4136 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4137 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4138
sahilmgandhi 18:6a4db94011d3 4139 /******************** Bits definition for RTC_WPR register *****************/
sahilmgandhi 18:6a4db94011d3 4140 #define RTC_WPR_KEY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4141 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 4142 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
sahilmgandhi 18:6a4db94011d3 4143
sahilmgandhi 18:6a4db94011d3 4144 /******************** Bits definition for RTC_SSR register *****************/
sahilmgandhi 18:6a4db94011d3 4145 #define RTC_SSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4146 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 4147 #define RTC_SSR_SS RTC_SSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 4148
sahilmgandhi 18:6a4db94011d3 4149 /******************** Bits definition for RTC_SHIFTR register **************/
sahilmgandhi 18:6a4db94011d3 4150 #define RTC_SHIFTR_SUBFS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4151 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 4152 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
sahilmgandhi 18:6a4db94011d3 4153 #define RTC_SHIFTR_ADD1S_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4154 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4155 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
sahilmgandhi 18:6a4db94011d3 4156
sahilmgandhi 18:6a4db94011d3 4157 /******************** Bits definition for RTC_TSTR register ****************/
sahilmgandhi 18:6a4db94011d3 4158 #define RTC_TSTR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4159 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4160 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
sahilmgandhi 18:6a4db94011d3 4161 #define RTC_TSTR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4162 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 4163 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
sahilmgandhi 18:6a4db94011d3 4164 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4165 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4166 #define RTC_TSTR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4167 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 4168 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
sahilmgandhi 18:6a4db94011d3 4169 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4170 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4171 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4172 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4173 #define RTC_TSTR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4174 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 4175 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
sahilmgandhi 18:6a4db94011d3 4176 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4177 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4178 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4179 #define RTC_TSTR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4180 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4181 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
sahilmgandhi 18:6a4db94011d3 4182 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4183 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4184 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4185 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4186 #define RTC_TSTR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4187 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 4188 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
sahilmgandhi 18:6a4db94011d3 4189 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4190 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4191 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4192 #define RTC_TSTR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4193 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 4194 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
sahilmgandhi 18:6a4db94011d3 4195 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4196 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4197 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4198 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4199
sahilmgandhi 18:6a4db94011d3 4200 /******************** Bits definition for RTC_TSDR register ****************/
sahilmgandhi 18:6a4db94011d3 4201 #define RTC_TSDR_WDU_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4202 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 4203 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
sahilmgandhi 18:6a4db94011d3 4204 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4205 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4206 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4207 #define RTC_TSDR_MT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4208 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4209 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
sahilmgandhi 18:6a4db94011d3 4210 #define RTC_TSDR_MU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4211 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4212 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
sahilmgandhi 18:6a4db94011d3 4213 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4214 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4215 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4216 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4217 #define RTC_TSDR_DT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4218 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 4219 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
sahilmgandhi 18:6a4db94011d3 4220 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4221 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4222 #define RTC_TSDR_DU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4223 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 4224 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
sahilmgandhi 18:6a4db94011d3 4225 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4226 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4227 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4228 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4229
sahilmgandhi 18:6a4db94011d3 4230 /******************** Bits definition for RTC_TSSSR register ***************/
sahilmgandhi 18:6a4db94011d3 4231 #define RTC_TSSSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4232 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 4233 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 4234
sahilmgandhi 18:6a4db94011d3 4235 /******************** Bits definition for RTC_CALR register ****************/
sahilmgandhi 18:6a4db94011d3 4236 #define RTC_CALR_CALP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4237 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4238 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
sahilmgandhi 18:6a4db94011d3 4239 #define RTC_CALR_CALW8_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4240 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4241 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
sahilmgandhi 18:6a4db94011d3 4242 #define RTC_CALR_CALW16_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4243 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4244 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
sahilmgandhi 18:6a4db94011d3 4245 #define RTC_CALR_CALM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4246 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
sahilmgandhi 18:6a4db94011d3 4247 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
sahilmgandhi 18:6a4db94011d3 4248 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4249 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4250 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4251 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4252 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4253 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4254 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4255 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4256 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4257
sahilmgandhi 18:6a4db94011d3 4258 /******************** Bits definition for RTC_TAFCR register ***************/
sahilmgandhi 18:6a4db94011d3 4259 #define RTC_TAFCR_PC15MODE_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4260 #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4261 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
sahilmgandhi 18:6a4db94011d3 4262 #define RTC_TAFCR_PC15VALUE_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4263 #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4264 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
sahilmgandhi 18:6a4db94011d3 4265 #define RTC_TAFCR_PC14MODE_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4266 #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4267 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
sahilmgandhi 18:6a4db94011d3 4268 #define RTC_TAFCR_PC14VALUE_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4269 #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4270 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
sahilmgandhi 18:6a4db94011d3 4271 #define RTC_TAFCR_PC13MODE_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4272 #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4273 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
sahilmgandhi 18:6a4db94011d3 4274 #define RTC_TAFCR_PC13VALUE_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4275 #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4276 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
sahilmgandhi 18:6a4db94011d3 4277 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4278 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4279 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
sahilmgandhi 18:6a4db94011d3 4280 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4281 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
sahilmgandhi 18:6a4db94011d3 4282 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
sahilmgandhi 18:6a4db94011d3 4283 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4284 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4285 #define RTC_TAFCR_TAMPFLT_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4286 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
sahilmgandhi 18:6a4db94011d3 4287 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
sahilmgandhi 18:6a4db94011d3 4288 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4289 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4290 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4291 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 4292 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
sahilmgandhi 18:6a4db94011d3 4293 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4294 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4295 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4296 #define RTC_TAFCR_TAMPTS_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4297 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4298 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
sahilmgandhi 18:6a4db94011d3 4299 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4300 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4301 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
sahilmgandhi 18:6a4db94011d3 4302 #define RTC_TAFCR_TAMP2E_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4303 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4304 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
sahilmgandhi 18:6a4db94011d3 4305 #define RTC_TAFCR_TAMPIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4306 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4307 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
sahilmgandhi 18:6a4db94011d3 4308 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4309 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4310 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
sahilmgandhi 18:6a4db94011d3 4311 #define RTC_TAFCR_TAMP1E_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4312 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4313 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
sahilmgandhi 18:6a4db94011d3 4314
sahilmgandhi 18:6a4db94011d3 4315 /* Reference defines */
sahilmgandhi 18:6a4db94011d3 4316 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
sahilmgandhi 18:6a4db94011d3 4317
sahilmgandhi 18:6a4db94011d3 4318 /******************** Bits definition for RTC_ALRMASSR register ************/
sahilmgandhi 18:6a4db94011d3 4319 #define RTC_ALRMASSR_MASKSS_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4320 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 4321 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
sahilmgandhi 18:6a4db94011d3 4322 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4323 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4324 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4325 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4326 #define RTC_ALRMASSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4327 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 4328 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 4329
sahilmgandhi 18:6a4db94011d3 4330 /******************** Bits definition for RTC_BKP0R register ***************/
sahilmgandhi 18:6a4db94011d3 4331 #define RTC_BKP0R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4332 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 4333 #define RTC_BKP0R RTC_BKP0R_Msk
sahilmgandhi 18:6a4db94011d3 4334
sahilmgandhi 18:6a4db94011d3 4335 /******************** Bits definition for RTC_BKP1R register ***************/
sahilmgandhi 18:6a4db94011d3 4336 #define RTC_BKP1R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4337 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 4338 #define RTC_BKP1R RTC_BKP1R_Msk
sahilmgandhi 18:6a4db94011d3 4339
sahilmgandhi 18:6a4db94011d3 4340 /******************** Bits definition for RTC_BKP2R register ***************/
sahilmgandhi 18:6a4db94011d3 4341 #define RTC_BKP2R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4342 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 4343 #define RTC_BKP2R RTC_BKP2R_Msk
sahilmgandhi 18:6a4db94011d3 4344
sahilmgandhi 18:6a4db94011d3 4345 /******************** Bits definition for RTC_BKP3R register ***************/
sahilmgandhi 18:6a4db94011d3 4346 #define RTC_BKP3R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4347 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 4348 #define RTC_BKP3R RTC_BKP3R_Msk
sahilmgandhi 18:6a4db94011d3 4349
sahilmgandhi 18:6a4db94011d3 4350 /******************** Bits definition for RTC_BKP4R register ***************/
sahilmgandhi 18:6a4db94011d3 4351 #define RTC_BKP4R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4352 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 4353 #define RTC_BKP4R RTC_BKP4R_Msk
sahilmgandhi 18:6a4db94011d3 4354
sahilmgandhi 18:6a4db94011d3 4355 /******************** Number of backup registers ******************************/
sahilmgandhi 18:6a4db94011d3 4356 #define RTC_BKP_NUMBER 0x00000005U
sahilmgandhi 18:6a4db94011d3 4357
sahilmgandhi 18:6a4db94011d3 4358 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 4359 /* */
sahilmgandhi 18:6a4db94011d3 4360 /* Serial Peripheral Interface (SPI) */
sahilmgandhi 18:6a4db94011d3 4361 /* */
sahilmgandhi 18:6a4db94011d3 4362 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 4363
sahilmgandhi 18:6a4db94011d3 4364 /*
sahilmgandhi 18:6a4db94011d3 4365 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
sahilmgandhi 18:6a4db94011d3 4366 */
sahilmgandhi 18:6a4db94011d3 4367 #define SPI_I2S_SUPPORT /*!< I2S support */
sahilmgandhi 18:6a4db94011d3 4368
sahilmgandhi 18:6a4db94011d3 4369 /******************* Bit definition for SPI_CR1 register *******************/
sahilmgandhi 18:6a4db94011d3 4370 #define SPI_CR1_CPHA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4371 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4372 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
sahilmgandhi 18:6a4db94011d3 4373 #define SPI_CR1_CPOL_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4374 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4375 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
sahilmgandhi 18:6a4db94011d3 4376 #define SPI_CR1_MSTR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4377 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4378 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
sahilmgandhi 18:6a4db94011d3 4379 #define SPI_CR1_BR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4380 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 4381 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
sahilmgandhi 18:6a4db94011d3 4382 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4383 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4384 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4385 #define SPI_CR1_SPE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4386 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4387 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
sahilmgandhi 18:6a4db94011d3 4388 #define SPI_CR1_LSBFIRST_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4389 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4390 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
sahilmgandhi 18:6a4db94011d3 4391 #define SPI_CR1_SSI_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4392 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4393 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
sahilmgandhi 18:6a4db94011d3 4394 #define SPI_CR1_SSM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4395 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4396 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
sahilmgandhi 18:6a4db94011d3 4397 #define SPI_CR1_RXONLY_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4398 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4399 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
sahilmgandhi 18:6a4db94011d3 4400 #define SPI_CR1_CRCL_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4401 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4402 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
sahilmgandhi 18:6a4db94011d3 4403 #define SPI_CR1_CRCNEXT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4404 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4405 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
sahilmgandhi 18:6a4db94011d3 4406 #define SPI_CR1_CRCEN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4407 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4408 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
sahilmgandhi 18:6a4db94011d3 4409 #define SPI_CR1_BIDIOE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4410 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4411 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
sahilmgandhi 18:6a4db94011d3 4412 #define SPI_CR1_BIDIMODE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4413 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4414 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
sahilmgandhi 18:6a4db94011d3 4415
sahilmgandhi 18:6a4db94011d3 4416 /******************* Bit definition for SPI_CR2 register *******************/
sahilmgandhi 18:6a4db94011d3 4417 #define SPI_CR2_RXDMAEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4418 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4419 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 4420 #define SPI_CR2_TXDMAEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4421 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4422 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 4423 #define SPI_CR2_SSOE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4424 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4425 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
sahilmgandhi 18:6a4db94011d3 4426 #define SPI_CR2_NSSP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4427 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4428 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
sahilmgandhi 18:6a4db94011d3 4429 #define SPI_CR2_FRF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4430 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4431 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
sahilmgandhi 18:6a4db94011d3 4432 #define SPI_CR2_ERRIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4433 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4434 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4435 #define SPI_CR2_RXNEIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4436 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4437 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4438 #define SPI_CR2_TXEIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4439 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4440 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 4441 #define SPI_CR2_DS_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4442 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4443 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
sahilmgandhi 18:6a4db94011d3 4444 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4445 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4446 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4447 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4448 #define SPI_CR2_FRXTH_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4449 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4450 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
sahilmgandhi 18:6a4db94011d3 4451 #define SPI_CR2_LDMARX_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4452 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4453 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
sahilmgandhi 18:6a4db94011d3 4454 #define SPI_CR2_LDMATX_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4455 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4456 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
sahilmgandhi 18:6a4db94011d3 4457
sahilmgandhi 18:6a4db94011d3 4458 /******************** Bit definition for SPI_SR register *******************/
sahilmgandhi 18:6a4db94011d3 4459 #define SPI_SR_RXNE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4460 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4461 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
sahilmgandhi 18:6a4db94011d3 4462 #define SPI_SR_TXE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4463 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4464 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
sahilmgandhi 18:6a4db94011d3 4465 #define SPI_SR_CHSIDE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4466 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4467 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
sahilmgandhi 18:6a4db94011d3 4468 #define SPI_SR_UDR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4469 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4470 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
sahilmgandhi 18:6a4db94011d3 4471 #define SPI_SR_CRCERR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4472 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4473 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
sahilmgandhi 18:6a4db94011d3 4474 #define SPI_SR_MODF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4475 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4476 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
sahilmgandhi 18:6a4db94011d3 4477 #define SPI_SR_OVR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4478 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4479 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
sahilmgandhi 18:6a4db94011d3 4480 #define SPI_SR_BSY_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4481 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4482 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
sahilmgandhi 18:6a4db94011d3 4483 #define SPI_SR_FRE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4484 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4485 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
sahilmgandhi 18:6a4db94011d3 4486 #define SPI_SR_FRLVL_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4487 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
sahilmgandhi 18:6a4db94011d3 4488 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
sahilmgandhi 18:6a4db94011d3 4489 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4490 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4491 #define SPI_SR_FTLVL_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4492 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
sahilmgandhi 18:6a4db94011d3 4493 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
sahilmgandhi 18:6a4db94011d3 4494 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4495 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4496
sahilmgandhi 18:6a4db94011d3 4497 /******************** Bit definition for SPI_DR register *******************/
sahilmgandhi 18:6a4db94011d3 4498 #define SPI_DR_DR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4499 #define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 4500 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
sahilmgandhi 18:6a4db94011d3 4501
sahilmgandhi 18:6a4db94011d3 4502 /******************* Bit definition for SPI_CRCPR register *****************/
sahilmgandhi 18:6a4db94011d3 4503 #define SPI_CRCPR_CRCPOLY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4504 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 4505 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
sahilmgandhi 18:6a4db94011d3 4506
sahilmgandhi 18:6a4db94011d3 4507 /****************** Bit definition for SPI_RXCRCR register *****************/
sahilmgandhi 18:6a4db94011d3 4508 #define SPI_RXCRCR_RXCRC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4509 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 4510 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
sahilmgandhi 18:6a4db94011d3 4511
sahilmgandhi 18:6a4db94011d3 4512 /****************** Bit definition for SPI_TXCRCR register *****************/
sahilmgandhi 18:6a4db94011d3 4513 #define SPI_TXCRCR_TXCRC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4514 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 4515 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
sahilmgandhi 18:6a4db94011d3 4516
sahilmgandhi 18:6a4db94011d3 4517 /****************** Bit definition for SPI_I2SCFGR register ****************/
sahilmgandhi 18:6a4db94011d3 4518 #define SPI_I2SCFGR_CHLEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4519 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4520 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
sahilmgandhi 18:6a4db94011d3 4521 #define SPI_I2SCFGR_DATLEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4522 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
sahilmgandhi 18:6a4db94011d3 4523 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
sahilmgandhi 18:6a4db94011d3 4524 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4525 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4526 #define SPI_I2SCFGR_CKPOL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4527 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4528 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
sahilmgandhi 18:6a4db94011d3 4529 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4530 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 4531 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
sahilmgandhi 18:6a4db94011d3 4532 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4533 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4534 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4535 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4536 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
sahilmgandhi 18:6a4db94011d3 4537 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4538 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 4539 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
sahilmgandhi 18:6a4db94011d3 4540 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4541 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4542 #define SPI_I2SCFGR_I2SE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4543 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4544 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
sahilmgandhi 18:6a4db94011d3 4545 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4546 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4547 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
sahilmgandhi 18:6a4db94011d3 4548
sahilmgandhi 18:6a4db94011d3 4549 /****************** Bit definition for SPI_I2SPR register ******************/
sahilmgandhi 18:6a4db94011d3 4550 #define SPI_I2SPR_I2SDIV_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4551 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 4552 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
sahilmgandhi 18:6a4db94011d3 4553 #define SPI_I2SPR_ODD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4554 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4555 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
sahilmgandhi 18:6a4db94011d3 4556 #define SPI_I2SPR_MCKOE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4557 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4558 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
sahilmgandhi 18:6a4db94011d3 4559
sahilmgandhi 18:6a4db94011d3 4560 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 4561 /* */
sahilmgandhi 18:6a4db94011d3 4562 /* System Configuration (SYSCFG) */
sahilmgandhi 18:6a4db94011d3 4563 /* */
sahilmgandhi 18:6a4db94011d3 4564 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 4565 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
sahilmgandhi 18:6a4db94011d3 4566 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4567 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 4568 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
sahilmgandhi 18:6a4db94011d3 4569 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4570 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4571
sahilmgandhi 18:6a4db94011d3 4572 #define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4573 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00001F00 */
sahilmgandhi 18:6a4db94011d3 4574 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
sahilmgandhi 18:6a4db94011d3 4575 #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4576 #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4577 #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */
sahilmgandhi 18:6a4db94011d3 4578 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4579 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4580 #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */
sahilmgandhi 18:6a4db94011d3 4581 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4582 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4583 #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */
sahilmgandhi 18:6a4db94011d3 4584 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4585 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4586 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
sahilmgandhi 18:6a4db94011d3 4587 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4588 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4589 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
sahilmgandhi 18:6a4db94011d3 4590
sahilmgandhi 18:6a4db94011d3 4591 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4592 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4593 #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 4594 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4595 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4596 #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 4597 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4598 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4599 #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 4600 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4601 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4602 #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */
sahilmgandhi 18:6a4db94011d3 4603
sahilmgandhi 18:6a4db94011d3 4604 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
sahilmgandhi 18:6a4db94011d3 4605 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4606 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 4607 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
sahilmgandhi 18:6a4db94011d3 4608 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4609 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 4610 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
sahilmgandhi 18:6a4db94011d3 4611 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4612 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4613 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
sahilmgandhi 18:6a4db94011d3 4614 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4615 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 4616 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
sahilmgandhi 18:6a4db94011d3 4617
sahilmgandhi 18:6a4db94011d3 4618 /**
sahilmgandhi 18:6a4db94011d3 4619 * @brief EXTI0 configuration
sahilmgandhi 18:6a4db94011d3 4620 */
sahilmgandhi 18:6a4db94011d3 4621 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
sahilmgandhi 18:6a4db94011d3 4622 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
sahilmgandhi 18:6a4db94011d3 4623 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
sahilmgandhi 18:6a4db94011d3 4624 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
sahilmgandhi 18:6a4db94011d3 4625 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
sahilmgandhi 18:6a4db94011d3 4626
sahilmgandhi 18:6a4db94011d3 4627 /**
sahilmgandhi 18:6a4db94011d3 4628 * @brief EXTI1 configuration
sahilmgandhi 18:6a4db94011d3 4629 */
sahilmgandhi 18:6a4db94011d3 4630 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
sahilmgandhi 18:6a4db94011d3 4631 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
sahilmgandhi 18:6a4db94011d3 4632 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
sahilmgandhi 18:6a4db94011d3 4633 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
sahilmgandhi 18:6a4db94011d3 4634 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
sahilmgandhi 18:6a4db94011d3 4635
sahilmgandhi 18:6a4db94011d3 4636 /**
sahilmgandhi 18:6a4db94011d3 4637 * @brief EXTI2 configuration
sahilmgandhi 18:6a4db94011d3 4638 */
sahilmgandhi 18:6a4db94011d3 4639 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
sahilmgandhi 18:6a4db94011d3 4640 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
sahilmgandhi 18:6a4db94011d3 4641 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
sahilmgandhi 18:6a4db94011d3 4642 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
sahilmgandhi 18:6a4db94011d3 4643 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
sahilmgandhi 18:6a4db94011d3 4644
sahilmgandhi 18:6a4db94011d3 4645 /**
sahilmgandhi 18:6a4db94011d3 4646 * @brief EXTI3 configuration
sahilmgandhi 18:6a4db94011d3 4647 */
sahilmgandhi 18:6a4db94011d3 4648 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
sahilmgandhi 18:6a4db94011d3 4649 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
sahilmgandhi 18:6a4db94011d3 4650 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
sahilmgandhi 18:6a4db94011d3 4651 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
sahilmgandhi 18:6a4db94011d3 4652 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */
sahilmgandhi 18:6a4db94011d3 4653
sahilmgandhi 18:6a4db94011d3 4654 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
sahilmgandhi 18:6a4db94011d3 4655 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4656 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 4657 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
sahilmgandhi 18:6a4db94011d3 4658 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4659 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 4660 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
sahilmgandhi 18:6a4db94011d3 4661 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4662 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4663 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
sahilmgandhi 18:6a4db94011d3 4664 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4665 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 4666 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
sahilmgandhi 18:6a4db94011d3 4667
sahilmgandhi 18:6a4db94011d3 4668 /**
sahilmgandhi 18:6a4db94011d3 4669 * @brief EXTI4 configuration
sahilmgandhi 18:6a4db94011d3 4670 */
sahilmgandhi 18:6a4db94011d3 4671 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
sahilmgandhi 18:6a4db94011d3 4672 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
sahilmgandhi 18:6a4db94011d3 4673 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
sahilmgandhi 18:6a4db94011d3 4674 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
sahilmgandhi 18:6a4db94011d3 4675 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
sahilmgandhi 18:6a4db94011d3 4676
sahilmgandhi 18:6a4db94011d3 4677 /**
sahilmgandhi 18:6a4db94011d3 4678 * @brief EXTI5 configuration
sahilmgandhi 18:6a4db94011d3 4679 */
sahilmgandhi 18:6a4db94011d3 4680 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
sahilmgandhi 18:6a4db94011d3 4681 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
sahilmgandhi 18:6a4db94011d3 4682 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
sahilmgandhi 18:6a4db94011d3 4683 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
sahilmgandhi 18:6a4db94011d3 4684 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
sahilmgandhi 18:6a4db94011d3 4685
sahilmgandhi 18:6a4db94011d3 4686 /**
sahilmgandhi 18:6a4db94011d3 4687 * @brief EXTI6 configuration
sahilmgandhi 18:6a4db94011d3 4688 */
sahilmgandhi 18:6a4db94011d3 4689 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
sahilmgandhi 18:6a4db94011d3 4690 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
sahilmgandhi 18:6a4db94011d3 4691 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
sahilmgandhi 18:6a4db94011d3 4692 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
sahilmgandhi 18:6a4db94011d3 4693 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
sahilmgandhi 18:6a4db94011d3 4694
sahilmgandhi 18:6a4db94011d3 4695 /**
sahilmgandhi 18:6a4db94011d3 4696 * @brief EXTI7 configuration
sahilmgandhi 18:6a4db94011d3 4697 */
sahilmgandhi 18:6a4db94011d3 4698 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
sahilmgandhi 18:6a4db94011d3 4699 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
sahilmgandhi 18:6a4db94011d3 4700 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
sahilmgandhi 18:6a4db94011d3 4701 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
sahilmgandhi 18:6a4db94011d3 4702 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */
sahilmgandhi 18:6a4db94011d3 4703
sahilmgandhi 18:6a4db94011d3 4704 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
sahilmgandhi 18:6a4db94011d3 4705 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4706 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 4707 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
sahilmgandhi 18:6a4db94011d3 4708 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4709 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 4710 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
sahilmgandhi 18:6a4db94011d3 4711 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4712 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4713 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
sahilmgandhi 18:6a4db94011d3 4714 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4715 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 4716 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
sahilmgandhi 18:6a4db94011d3 4717
sahilmgandhi 18:6a4db94011d3 4718 /**
sahilmgandhi 18:6a4db94011d3 4719 * @brief EXTI8 configuration
sahilmgandhi 18:6a4db94011d3 4720 */
sahilmgandhi 18:6a4db94011d3 4721 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
sahilmgandhi 18:6a4db94011d3 4722 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
sahilmgandhi 18:6a4db94011d3 4723 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
sahilmgandhi 18:6a4db94011d3 4724 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
sahilmgandhi 18:6a4db94011d3 4725 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */
sahilmgandhi 18:6a4db94011d3 4726
sahilmgandhi 18:6a4db94011d3 4727
sahilmgandhi 18:6a4db94011d3 4728 /**
sahilmgandhi 18:6a4db94011d3 4729 * @brief EXTI9 configuration
sahilmgandhi 18:6a4db94011d3 4730 */
sahilmgandhi 18:6a4db94011d3 4731 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
sahilmgandhi 18:6a4db94011d3 4732 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
sahilmgandhi 18:6a4db94011d3 4733 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
sahilmgandhi 18:6a4db94011d3 4734 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
sahilmgandhi 18:6a4db94011d3 4735 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
sahilmgandhi 18:6a4db94011d3 4736
sahilmgandhi 18:6a4db94011d3 4737 /**
sahilmgandhi 18:6a4db94011d3 4738 * @brief EXTI10 configuration
sahilmgandhi 18:6a4db94011d3 4739 */
sahilmgandhi 18:6a4db94011d3 4740 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
sahilmgandhi 18:6a4db94011d3 4741 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
sahilmgandhi 18:6a4db94011d3 4742 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
sahilmgandhi 18:6a4db94011d3 4743 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
sahilmgandhi 18:6a4db94011d3 4744 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
sahilmgandhi 18:6a4db94011d3 4745
sahilmgandhi 18:6a4db94011d3 4746 /**
sahilmgandhi 18:6a4db94011d3 4747 * @brief EXTI11 configuration
sahilmgandhi 18:6a4db94011d3 4748 */
sahilmgandhi 18:6a4db94011d3 4749 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
sahilmgandhi 18:6a4db94011d3 4750 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
sahilmgandhi 18:6a4db94011d3 4751 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
sahilmgandhi 18:6a4db94011d3 4752 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
sahilmgandhi 18:6a4db94011d3 4753 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */
sahilmgandhi 18:6a4db94011d3 4754
sahilmgandhi 18:6a4db94011d3 4755 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
sahilmgandhi 18:6a4db94011d3 4756 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4757 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 4758 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
sahilmgandhi 18:6a4db94011d3 4759 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4760 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 4761 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
sahilmgandhi 18:6a4db94011d3 4762 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4763 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4764 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
sahilmgandhi 18:6a4db94011d3 4765 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4766 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 4767 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
sahilmgandhi 18:6a4db94011d3 4768
sahilmgandhi 18:6a4db94011d3 4769 /**
sahilmgandhi 18:6a4db94011d3 4770 * @brief EXTI12 configuration
sahilmgandhi 18:6a4db94011d3 4771 */
sahilmgandhi 18:6a4db94011d3 4772 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
sahilmgandhi 18:6a4db94011d3 4773 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
sahilmgandhi 18:6a4db94011d3 4774 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
sahilmgandhi 18:6a4db94011d3 4775 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
sahilmgandhi 18:6a4db94011d3 4776 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */
sahilmgandhi 18:6a4db94011d3 4777
sahilmgandhi 18:6a4db94011d3 4778 /**
sahilmgandhi 18:6a4db94011d3 4779 * @brief EXTI13 configuration
sahilmgandhi 18:6a4db94011d3 4780 */
sahilmgandhi 18:6a4db94011d3 4781 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
sahilmgandhi 18:6a4db94011d3 4782 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
sahilmgandhi 18:6a4db94011d3 4783 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
sahilmgandhi 18:6a4db94011d3 4784 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
sahilmgandhi 18:6a4db94011d3 4785 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */
sahilmgandhi 18:6a4db94011d3 4786
sahilmgandhi 18:6a4db94011d3 4787 /**
sahilmgandhi 18:6a4db94011d3 4788 * @brief EXTI14 configuration
sahilmgandhi 18:6a4db94011d3 4789 */
sahilmgandhi 18:6a4db94011d3 4790 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
sahilmgandhi 18:6a4db94011d3 4791 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
sahilmgandhi 18:6a4db94011d3 4792 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
sahilmgandhi 18:6a4db94011d3 4793 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
sahilmgandhi 18:6a4db94011d3 4794 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */
sahilmgandhi 18:6a4db94011d3 4795
sahilmgandhi 18:6a4db94011d3 4796 /**
sahilmgandhi 18:6a4db94011d3 4797 * @brief EXTI15 configuration
sahilmgandhi 18:6a4db94011d3 4798 */
sahilmgandhi 18:6a4db94011d3 4799 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
sahilmgandhi 18:6a4db94011d3 4800 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
sahilmgandhi 18:6a4db94011d3 4801 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
sahilmgandhi 18:6a4db94011d3 4802 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
sahilmgandhi 18:6a4db94011d3 4803 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */
sahilmgandhi 18:6a4db94011d3 4804
sahilmgandhi 18:6a4db94011d3 4805 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
sahilmgandhi 18:6a4db94011d3 4806 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4807 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4808 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
sahilmgandhi 18:6a4db94011d3 4809 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4810 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4811 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
sahilmgandhi 18:6a4db94011d3 4812 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4813 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4814 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
sahilmgandhi 18:6a4db94011d3 4815 #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4816 #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4817 #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */
sahilmgandhi 18:6a4db94011d3 4818 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
sahilmgandhi 18:6a4db94011d3 4819
sahilmgandhi 18:6a4db94011d3 4820 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 4821 /* */
sahilmgandhi 18:6a4db94011d3 4822 /* Timers (TIM) */
sahilmgandhi 18:6a4db94011d3 4823 /* */
sahilmgandhi 18:6a4db94011d3 4824 /*****************************************************************************/
sahilmgandhi 18:6a4db94011d3 4825 /******************* Bit definition for TIM_CR1 register *******************/
sahilmgandhi 18:6a4db94011d3 4826 #define TIM_CR1_CEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4827 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4828 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
sahilmgandhi 18:6a4db94011d3 4829 #define TIM_CR1_UDIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4830 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4831 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
sahilmgandhi 18:6a4db94011d3 4832 #define TIM_CR1_URS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4833 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4834 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
sahilmgandhi 18:6a4db94011d3 4835 #define TIM_CR1_OPM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4836 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4837 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
sahilmgandhi 18:6a4db94011d3 4838 #define TIM_CR1_DIR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4839 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4840 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
sahilmgandhi 18:6a4db94011d3 4841
sahilmgandhi 18:6a4db94011d3 4842 #define TIM_CR1_CMS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4843 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
sahilmgandhi 18:6a4db94011d3 4844 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
sahilmgandhi 18:6a4db94011d3 4845 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4846 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4847
sahilmgandhi 18:6a4db94011d3 4848 #define TIM_CR1_ARPE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4849 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4850 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
sahilmgandhi 18:6a4db94011d3 4851
sahilmgandhi 18:6a4db94011d3 4852 #define TIM_CR1_CKD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4853 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 4854 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
sahilmgandhi 18:6a4db94011d3 4855 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4856 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4857
sahilmgandhi 18:6a4db94011d3 4858 /******************* Bit definition for TIM_CR2 register *******************/
sahilmgandhi 18:6a4db94011d3 4859 #define TIM_CR2_CCPC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4860 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4861 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
sahilmgandhi 18:6a4db94011d3 4862 #define TIM_CR2_CCUS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4863 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4864 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
sahilmgandhi 18:6a4db94011d3 4865 #define TIM_CR2_CCDS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4866 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4867 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
sahilmgandhi 18:6a4db94011d3 4868
sahilmgandhi 18:6a4db94011d3 4869 #define TIM_CR2_MMS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4870 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 4871 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
sahilmgandhi 18:6a4db94011d3 4872 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4873 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4874 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4875
sahilmgandhi 18:6a4db94011d3 4876 #define TIM_CR2_TI1S_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4877 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4878 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
sahilmgandhi 18:6a4db94011d3 4879 #define TIM_CR2_OIS1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4880 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4881 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
sahilmgandhi 18:6a4db94011d3 4882 #define TIM_CR2_OIS1N_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4883 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4884 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
sahilmgandhi 18:6a4db94011d3 4885 #define TIM_CR2_OIS2_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4886 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4887 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
sahilmgandhi 18:6a4db94011d3 4888 #define TIM_CR2_OIS2N_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4889 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4890 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
sahilmgandhi 18:6a4db94011d3 4891 #define TIM_CR2_OIS3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4892 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4893 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
sahilmgandhi 18:6a4db94011d3 4894 #define TIM_CR2_OIS3N_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4895 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4896 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
sahilmgandhi 18:6a4db94011d3 4897 #define TIM_CR2_OIS4_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4898 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4899 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
sahilmgandhi 18:6a4db94011d3 4900
sahilmgandhi 18:6a4db94011d3 4901 /******************* Bit definition for TIM_SMCR register ******************/
sahilmgandhi 18:6a4db94011d3 4902 #define TIM_SMCR_SMS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4903 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 4904 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
sahilmgandhi 18:6a4db94011d3 4905 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4906 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4907 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4908
sahilmgandhi 18:6a4db94011d3 4909 #define TIM_SMCR_OCCS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4910 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4911 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
sahilmgandhi 18:6a4db94011d3 4912
sahilmgandhi 18:6a4db94011d3 4913 #define TIM_SMCR_TS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4914 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 4915 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
sahilmgandhi 18:6a4db94011d3 4916 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4917 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4918 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4919
sahilmgandhi 18:6a4db94011d3 4920 #define TIM_SMCR_MSM_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4921 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4922 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
sahilmgandhi 18:6a4db94011d3 4923
sahilmgandhi 18:6a4db94011d3 4924 #define TIM_SMCR_ETF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4925 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 4926 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
sahilmgandhi 18:6a4db94011d3 4927 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4928 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4929 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4930 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4931
sahilmgandhi 18:6a4db94011d3 4932 #define TIM_SMCR_ETPS_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4933 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 4934 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
sahilmgandhi 18:6a4db94011d3 4935 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4936 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4937
sahilmgandhi 18:6a4db94011d3 4938 #define TIM_SMCR_ECE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4939 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4940 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
sahilmgandhi 18:6a4db94011d3 4941 #define TIM_SMCR_ETP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4942 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4943 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
sahilmgandhi 18:6a4db94011d3 4944
sahilmgandhi 18:6a4db94011d3 4945 /******************* Bit definition for TIM_DIER register ******************/
sahilmgandhi 18:6a4db94011d3 4946 #define TIM_DIER_UIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4947 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4948 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
sahilmgandhi 18:6a4db94011d3 4949 #define TIM_DIER_CC1IE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4950 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4951 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
sahilmgandhi 18:6a4db94011d3 4952 #define TIM_DIER_CC2IE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4953 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4954 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
sahilmgandhi 18:6a4db94011d3 4955 #define TIM_DIER_CC3IE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4956 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4957 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
sahilmgandhi 18:6a4db94011d3 4958 #define TIM_DIER_CC4IE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4959 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4960 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
sahilmgandhi 18:6a4db94011d3 4961 #define TIM_DIER_COMIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4962 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4963 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
sahilmgandhi 18:6a4db94011d3 4964 #define TIM_DIER_TIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4965 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4966 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
sahilmgandhi 18:6a4db94011d3 4967 #define TIM_DIER_BIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4968 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4969 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
sahilmgandhi 18:6a4db94011d3 4970 #define TIM_DIER_UDE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4971 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4972 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
sahilmgandhi 18:6a4db94011d3 4973 #define TIM_DIER_CC1DE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4974 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4975 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
sahilmgandhi 18:6a4db94011d3 4976 #define TIM_DIER_CC2DE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4977 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4978 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
sahilmgandhi 18:6a4db94011d3 4979 #define TIM_DIER_CC3DE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4980 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4981 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
sahilmgandhi 18:6a4db94011d3 4982 #define TIM_DIER_CC4DE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4983 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4984 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
sahilmgandhi 18:6a4db94011d3 4985 #define TIM_DIER_COMDE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4986 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4987 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
sahilmgandhi 18:6a4db94011d3 4988 #define TIM_DIER_TDE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4989 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4990 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
sahilmgandhi 18:6a4db94011d3 4991
sahilmgandhi 18:6a4db94011d3 4992 /******************** Bit definition for TIM_SR register *******************/
sahilmgandhi 18:6a4db94011d3 4993 #define TIM_SR_UIF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4994 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4995 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
sahilmgandhi 18:6a4db94011d3 4996 #define TIM_SR_CC1IF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4997 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4998 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 4999 #define TIM_SR_CC2IF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5000 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5001 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 5002 #define TIM_SR_CC3IF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5003 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5004 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 5005 #define TIM_SR_CC4IF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5006 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5007 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 5008 #define TIM_SR_COMIF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5009 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5010 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
sahilmgandhi 18:6a4db94011d3 5011 #define TIM_SR_TIF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5012 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5013 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
sahilmgandhi 18:6a4db94011d3 5014 #define TIM_SR_BIF_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5015 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5016 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
sahilmgandhi 18:6a4db94011d3 5017 #define TIM_SR_CC1OF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5018 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5019 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 5020 #define TIM_SR_CC2OF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5021 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5022 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 5023 #define TIM_SR_CC3OF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5024 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5025 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 5026 #define TIM_SR_CC4OF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5027 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5028 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 5029
sahilmgandhi 18:6a4db94011d3 5030 /******************* Bit definition for TIM_EGR register *******************/
sahilmgandhi 18:6a4db94011d3 5031 #define TIM_EGR_UG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5032 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5033 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
sahilmgandhi 18:6a4db94011d3 5034 #define TIM_EGR_CC1G_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5035 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5036 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
sahilmgandhi 18:6a4db94011d3 5037 #define TIM_EGR_CC2G_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5038 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5039 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
sahilmgandhi 18:6a4db94011d3 5040 #define TIM_EGR_CC3G_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5041 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5042 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
sahilmgandhi 18:6a4db94011d3 5043 #define TIM_EGR_CC4G_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5044 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5045 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
sahilmgandhi 18:6a4db94011d3 5046 #define TIM_EGR_COMG_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5047 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5048 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
sahilmgandhi 18:6a4db94011d3 5049 #define TIM_EGR_TG_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5050 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5051 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
sahilmgandhi 18:6a4db94011d3 5052 #define TIM_EGR_BG_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5053 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5054 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
sahilmgandhi 18:6a4db94011d3 5055
sahilmgandhi 18:6a4db94011d3 5056 /****************** Bit definition for TIM_CCMR1 register ******************/
sahilmgandhi 18:6a4db94011d3 5057 #define TIM_CCMR1_CC1S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5058 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 5059 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
sahilmgandhi 18:6a4db94011d3 5060 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5061 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5062
sahilmgandhi 18:6a4db94011d3 5063 #define TIM_CCMR1_OC1FE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5064 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5065 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
sahilmgandhi 18:6a4db94011d3 5066 #define TIM_CCMR1_OC1PE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5067 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5068 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
sahilmgandhi 18:6a4db94011d3 5069
sahilmgandhi 18:6a4db94011d3 5070 #define TIM_CCMR1_OC1M_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5071 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 5072 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
sahilmgandhi 18:6a4db94011d3 5073 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5074 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5075 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5076
sahilmgandhi 18:6a4db94011d3 5077 #define TIM_CCMR1_OC1CE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5078 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5079 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
sahilmgandhi 18:6a4db94011d3 5080
sahilmgandhi 18:6a4db94011d3 5081 #define TIM_CCMR1_CC2S_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5082 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 5083 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
sahilmgandhi 18:6a4db94011d3 5084 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5085 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5086
sahilmgandhi 18:6a4db94011d3 5087 #define TIM_CCMR1_OC2FE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5088 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5089 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
sahilmgandhi 18:6a4db94011d3 5090 #define TIM_CCMR1_OC2PE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5091 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5092 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
sahilmgandhi 18:6a4db94011d3 5093
sahilmgandhi 18:6a4db94011d3 5094 #define TIM_CCMR1_OC2M_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5095 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 5096 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
sahilmgandhi 18:6a4db94011d3 5097 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5098 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5099 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5100
sahilmgandhi 18:6a4db94011d3 5101 #define TIM_CCMR1_OC2CE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5102 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5103 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
sahilmgandhi 18:6a4db94011d3 5104
sahilmgandhi 18:6a4db94011d3 5105 /*---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 5106
sahilmgandhi 18:6a4db94011d3 5107 #define TIM_CCMR1_IC1PSC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5108 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 5109 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
sahilmgandhi 18:6a4db94011d3 5110 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5111 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5112
sahilmgandhi 18:6a4db94011d3 5113 #define TIM_CCMR1_IC1F_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5114 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 5115 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
sahilmgandhi 18:6a4db94011d3 5116 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5117 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5118 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5119 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5120
sahilmgandhi 18:6a4db94011d3 5121 #define TIM_CCMR1_IC2PSC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5122 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 5123 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
sahilmgandhi 18:6a4db94011d3 5124 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5125 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5126
sahilmgandhi 18:6a4db94011d3 5127 #define TIM_CCMR1_IC2F_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5128 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 5129 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
sahilmgandhi 18:6a4db94011d3 5130 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5131 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5132 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5133 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5134
sahilmgandhi 18:6a4db94011d3 5135 /****************** Bit definition for TIM_CCMR2 register ******************/
sahilmgandhi 18:6a4db94011d3 5136 #define TIM_CCMR2_CC3S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5137 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 5138 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
sahilmgandhi 18:6a4db94011d3 5139 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5140 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5141
sahilmgandhi 18:6a4db94011d3 5142 #define TIM_CCMR2_OC3FE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5143 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5144 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
sahilmgandhi 18:6a4db94011d3 5145 #define TIM_CCMR2_OC3PE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5146 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5147 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
sahilmgandhi 18:6a4db94011d3 5148
sahilmgandhi 18:6a4db94011d3 5149 #define TIM_CCMR2_OC3M_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5150 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 5151 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
sahilmgandhi 18:6a4db94011d3 5152 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5153 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5154 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5155
sahilmgandhi 18:6a4db94011d3 5156 #define TIM_CCMR2_OC3CE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5157 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5158 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
sahilmgandhi 18:6a4db94011d3 5159
sahilmgandhi 18:6a4db94011d3 5160 #define TIM_CCMR2_CC4S_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5161 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 5162 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
sahilmgandhi 18:6a4db94011d3 5163 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5164 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5165
sahilmgandhi 18:6a4db94011d3 5166 #define TIM_CCMR2_OC4FE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5167 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5168 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
sahilmgandhi 18:6a4db94011d3 5169 #define TIM_CCMR2_OC4PE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5170 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5171 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
sahilmgandhi 18:6a4db94011d3 5172
sahilmgandhi 18:6a4db94011d3 5173 #define TIM_CCMR2_OC4M_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5174 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 5175 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
sahilmgandhi 18:6a4db94011d3 5176 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5177 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5178 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5179
sahilmgandhi 18:6a4db94011d3 5180 #define TIM_CCMR2_OC4CE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5181 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5182 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
sahilmgandhi 18:6a4db94011d3 5183
sahilmgandhi 18:6a4db94011d3 5184 /*---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 5185
sahilmgandhi 18:6a4db94011d3 5186 #define TIM_CCMR2_IC3PSC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5187 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 5188 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
sahilmgandhi 18:6a4db94011d3 5189 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5190 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5191
sahilmgandhi 18:6a4db94011d3 5192 #define TIM_CCMR2_IC3F_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5193 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 5194 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
sahilmgandhi 18:6a4db94011d3 5195 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5196 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5197 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5198 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5199
sahilmgandhi 18:6a4db94011d3 5200 #define TIM_CCMR2_IC4PSC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5201 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 5202 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
sahilmgandhi 18:6a4db94011d3 5203 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5204 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5205
sahilmgandhi 18:6a4db94011d3 5206 #define TIM_CCMR2_IC4F_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5207 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 5208 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
sahilmgandhi 18:6a4db94011d3 5209 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5210 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5211 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5212 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5213
sahilmgandhi 18:6a4db94011d3 5214 /******************* Bit definition for TIM_CCER register ******************/
sahilmgandhi 18:6a4db94011d3 5215 #define TIM_CCER_CC1E_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5216 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5217 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
sahilmgandhi 18:6a4db94011d3 5218 #define TIM_CCER_CC1P_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5219 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5220 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
sahilmgandhi 18:6a4db94011d3 5221 #define TIM_CCER_CC1NE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5222 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5223 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 5224 #define TIM_CCER_CC1NP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5225 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5226 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 5227 #define TIM_CCER_CC2E_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5228 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5229 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
sahilmgandhi 18:6a4db94011d3 5230 #define TIM_CCER_CC2P_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5231 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5232 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
sahilmgandhi 18:6a4db94011d3 5233 #define TIM_CCER_CC2NE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5234 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5235 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 5236 #define TIM_CCER_CC2NP_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5237 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5238 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 5239 #define TIM_CCER_CC3E_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5240 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5241 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
sahilmgandhi 18:6a4db94011d3 5242 #define TIM_CCER_CC3P_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5243 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5244 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
sahilmgandhi 18:6a4db94011d3 5245 #define TIM_CCER_CC3NE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5246 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5247 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 5248 #define TIM_CCER_CC3NP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5249 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5250 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 5251 #define TIM_CCER_CC4E_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5252 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5253 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
sahilmgandhi 18:6a4db94011d3 5254 #define TIM_CCER_CC4P_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5255 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5256 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
sahilmgandhi 18:6a4db94011d3 5257 #define TIM_CCER_CC4NP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5258 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5259 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 5260
sahilmgandhi 18:6a4db94011d3 5261 /******************* Bit definition for TIM_CNT register *******************/
sahilmgandhi 18:6a4db94011d3 5262 #define TIM_CNT_CNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5263 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 5264 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
sahilmgandhi 18:6a4db94011d3 5265
sahilmgandhi 18:6a4db94011d3 5266 /******************* Bit definition for TIM_PSC register *******************/
sahilmgandhi 18:6a4db94011d3 5267 #define TIM_PSC_PSC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5268 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5269 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
sahilmgandhi 18:6a4db94011d3 5270
sahilmgandhi 18:6a4db94011d3 5271 /******************* Bit definition for TIM_ARR register *******************/
sahilmgandhi 18:6a4db94011d3 5272 #define TIM_ARR_ARR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5273 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 5274 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
sahilmgandhi 18:6a4db94011d3 5275
sahilmgandhi 18:6a4db94011d3 5276 /******************* Bit definition for TIM_RCR register *******************/
sahilmgandhi 18:6a4db94011d3 5277 #define TIM_RCR_REP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5278 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 5279 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
sahilmgandhi 18:6a4db94011d3 5280
sahilmgandhi 18:6a4db94011d3 5281 /******************* Bit definition for TIM_CCR1 register ******************/
sahilmgandhi 18:6a4db94011d3 5282 #define TIM_CCR1_CCR1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5283 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5284 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
sahilmgandhi 18:6a4db94011d3 5285
sahilmgandhi 18:6a4db94011d3 5286 /******************* Bit definition for TIM_CCR2 register ******************/
sahilmgandhi 18:6a4db94011d3 5287 #define TIM_CCR2_CCR2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5288 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5289 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
sahilmgandhi 18:6a4db94011d3 5290
sahilmgandhi 18:6a4db94011d3 5291 /******************* Bit definition for TIM_CCR3 register ******************/
sahilmgandhi 18:6a4db94011d3 5292 #define TIM_CCR3_CCR3_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5293 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5294 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
sahilmgandhi 18:6a4db94011d3 5295
sahilmgandhi 18:6a4db94011d3 5296 /******************* Bit definition for TIM_CCR4 register ******************/
sahilmgandhi 18:6a4db94011d3 5297 #define TIM_CCR4_CCR4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5298 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5299 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
sahilmgandhi 18:6a4db94011d3 5300
sahilmgandhi 18:6a4db94011d3 5301 /******************* Bit definition for TIM_BDTR register ******************/
sahilmgandhi 18:6a4db94011d3 5302 #define TIM_BDTR_DTG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5303 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 5304 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
sahilmgandhi 18:6a4db94011d3 5305 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5306 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5307 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5308 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5309 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5310 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5311 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5312 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5313
sahilmgandhi 18:6a4db94011d3 5314 #define TIM_BDTR_LOCK_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5315 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 5316 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
sahilmgandhi 18:6a4db94011d3 5317 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5318 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5319
sahilmgandhi 18:6a4db94011d3 5320 #define TIM_BDTR_OSSI_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5321 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5322 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
sahilmgandhi 18:6a4db94011d3 5323 #define TIM_BDTR_OSSR_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5324 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5325 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
sahilmgandhi 18:6a4db94011d3 5326 #define TIM_BDTR_BKE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5327 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5328 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
sahilmgandhi 18:6a4db94011d3 5329 #define TIM_BDTR_BKP_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5330 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5331 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
sahilmgandhi 18:6a4db94011d3 5332 #define TIM_BDTR_AOE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5333 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5334 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
sahilmgandhi 18:6a4db94011d3 5335 #define TIM_BDTR_MOE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5336 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5337 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
sahilmgandhi 18:6a4db94011d3 5338
sahilmgandhi 18:6a4db94011d3 5339 /******************* Bit definition for TIM_DCR register *******************/
sahilmgandhi 18:6a4db94011d3 5340 #define TIM_DCR_DBA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5341 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 5342 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
sahilmgandhi 18:6a4db94011d3 5343 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5344 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5345 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5346 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5347 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5348
sahilmgandhi 18:6a4db94011d3 5349 #define TIM_DCR_DBL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5350 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
sahilmgandhi 18:6a4db94011d3 5351 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
sahilmgandhi 18:6a4db94011d3 5352 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5353 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5354 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5355 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5356 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5357
sahilmgandhi 18:6a4db94011d3 5358 /******************* Bit definition for TIM_DMAR register ******************/
sahilmgandhi 18:6a4db94011d3 5359 #define TIM_DMAR_DMAB_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5360 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 5361 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
sahilmgandhi 18:6a4db94011d3 5362
sahilmgandhi 18:6a4db94011d3 5363 /******************* Bit definition for TIM14_OR register ********************/
sahilmgandhi 18:6a4db94011d3 5364 #define TIM14_OR_TI1_RMP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5365 #define TIM14_OR_TI1_RMP_Msk (0x3U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 5366 #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
sahilmgandhi 18:6a4db94011d3 5367 #define TIM14_OR_TI1_RMP_0 (0x1U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5368 #define TIM14_OR_TI1_RMP_1 (0x2U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5369
sahilmgandhi 18:6a4db94011d3 5370 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5371 /* */
sahilmgandhi 18:6a4db94011d3 5372 /* Touch Sensing Controller (TSC) */
sahilmgandhi 18:6a4db94011d3 5373 /* */
sahilmgandhi 18:6a4db94011d3 5374 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5375 /******************* Bit definition for TSC_CR register *********************/
sahilmgandhi 18:6a4db94011d3 5376 #define TSC_CR_TSCE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5377 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5378 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
sahilmgandhi 18:6a4db94011d3 5379 #define TSC_CR_START_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5380 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5381 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
sahilmgandhi 18:6a4db94011d3 5382 #define TSC_CR_AM_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5383 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5384 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
sahilmgandhi 18:6a4db94011d3 5385 #define TSC_CR_SYNCPOL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5386 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5387 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
sahilmgandhi 18:6a4db94011d3 5388 #define TSC_CR_IODEF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5389 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5390 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
sahilmgandhi 18:6a4db94011d3 5391
sahilmgandhi 18:6a4db94011d3 5392 #define TSC_CR_MCV_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5393 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
sahilmgandhi 18:6a4db94011d3 5394 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
sahilmgandhi 18:6a4db94011d3 5395 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5396 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5397 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5398
sahilmgandhi 18:6a4db94011d3 5399 #define TSC_CR_PGPSC_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5400 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 5401 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
sahilmgandhi 18:6a4db94011d3 5402 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5403 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5404 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5405
sahilmgandhi 18:6a4db94011d3 5406 #define TSC_CR_SSPSC_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5407 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5408 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
sahilmgandhi 18:6a4db94011d3 5409 #define TSC_CR_SSE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5410 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5411 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
sahilmgandhi 18:6a4db94011d3 5412
sahilmgandhi 18:6a4db94011d3 5413 #define TSC_CR_SSD_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5414 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
sahilmgandhi 18:6a4db94011d3 5415 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
sahilmgandhi 18:6a4db94011d3 5416 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5417 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5418 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5419 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5420 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5421 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5422 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5423
sahilmgandhi 18:6a4db94011d3 5424 #define TSC_CR_CTPL_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5425 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 5426 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
sahilmgandhi 18:6a4db94011d3 5427 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5428 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5429 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5430 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5431
sahilmgandhi 18:6a4db94011d3 5432 #define TSC_CR_CTPH_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5433 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 5434 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
sahilmgandhi 18:6a4db94011d3 5435 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5436 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5437 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5438 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5439
sahilmgandhi 18:6a4db94011d3 5440 /******************* Bit definition for TSC_IER register ********************/
sahilmgandhi 18:6a4db94011d3 5441 #define TSC_IER_EOAIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5442 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5443 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
sahilmgandhi 18:6a4db94011d3 5444 #define TSC_IER_MCEIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5445 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5446 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
sahilmgandhi 18:6a4db94011d3 5447
sahilmgandhi 18:6a4db94011d3 5448 /******************* Bit definition for TSC_ICR register ********************/
sahilmgandhi 18:6a4db94011d3 5449 #define TSC_ICR_EOAIC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5450 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5451 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
sahilmgandhi 18:6a4db94011d3 5452 #define TSC_ICR_MCEIC_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5453 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5454 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
sahilmgandhi 18:6a4db94011d3 5455
sahilmgandhi 18:6a4db94011d3 5456 /******************* Bit definition for TSC_ISR register ********************/
sahilmgandhi 18:6a4db94011d3 5457 #define TSC_ISR_EOAF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5458 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5459 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
sahilmgandhi 18:6a4db94011d3 5460 #define TSC_ISR_MCEF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5461 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5462 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
sahilmgandhi 18:6a4db94011d3 5463
sahilmgandhi 18:6a4db94011d3 5464 /******************* Bit definition for TSC_IOHCR register ******************/
sahilmgandhi 18:6a4db94011d3 5465 #define TSC_IOHCR_G1_IO1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5466 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5467 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5468 #define TSC_IOHCR_G1_IO2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5469 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5470 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5471 #define TSC_IOHCR_G1_IO3_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5472 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5473 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5474 #define TSC_IOHCR_G1_IO4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5475 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5476 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5477 #define TSC_IOHCR_G2_IO1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5478 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5479 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5480 #define TSC_IOHCR_G2_IO2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5481 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5482 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5483 #define TSC_IOHCR_G2_IO3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5484 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5485 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5486 #define TSC_IOHCR_G2_IO4_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5487 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5488 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5489 #define TSC_IOHCR_G3_IO1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5490 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5491 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5492 #define TSC_IOHCR_G3_IO2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5493 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5494 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5495 #define TSC_IOHCR_G3_IO3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5496 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5497 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5498 #define TSC_IOHCR_G3_IO4_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5499 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5500 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5501 #define TSC_IOHCR_G4_IO1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5502 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5503 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5504 #define TSC_IOHCR_G4_IO2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5505 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5506 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5507 #define TSC_IOHCR_G4_IO3_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5508 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5509 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5510 #define TSC_IOHCR_G4_IO4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5511 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5512 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5513 #define TSC_IOHCR_G5_IO1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5514 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5515 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5516 #define TSC_IOHCR_G5_IO2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5517 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5518 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5519 #define TSC_IOHCR_G5_IO3_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5520 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5521 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5522 #define TSC_IOHCR_G5_IO4_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5523 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5524 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5525 #define TSC_IOHCR_G6_IO1_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5526 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5527 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5528 #define TSC_IOHCR_G6_IO2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5529 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5530 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5531 #define TSC_IOHCR_G6_IO3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5532 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5533 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5534 #define TSC_IOHCR_G6_IO4_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5535 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5536 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5537 #define TSC_IOHCR_G7_IO1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5538 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5539 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5540 #define TSC_IOHCR_G7_IO2_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5541 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5542 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5543 #define TSC_IOHCR_G7_IO3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5544 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5545 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5546 #define TSC_IOHCR_G7_IO4_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5547 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5548 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5549 #define TSC_IOHCR_G8_IO1_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5550 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5551 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5552 #define TSC_IOHCR_G8_IO2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5553 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5554 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5555 #define TSC_IOHCR_G8_IO3_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5556 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5557 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5558 #define TSC_IOHCR_G8_IO4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5559 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5560 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
sahilmgandhi 18:6a4db94011d3 5561
sahilmgandhi 18:6a4db94011d3 5562 /******************* Bit definition for TSC_IOASCR register *****************/
sahilmgandhi 18:6a4db94011d3 5563 #define TSC_IOASCR_G1_IO1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5564 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5565 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5566 #define TSC_IOASCR_G1_IO2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5567 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5568 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5569 #define TSC_IOASCR_G1_IO3_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5570 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5571 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5572 #define TSC_IOASCR_G1_IO4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5573 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5574 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5575 #define TSC_IOASCR_G2_IO1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5576 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5577 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5578 #define TSC_IOASCR_G2_IO2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5579 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5580 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5581 #define TSC_IOASCR_G2_IO3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5582 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5583 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5584 #define TSC_IOASCR_G2_IO4_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5585 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5586 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5587 #define TSC_IOASCR_G3_IO1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5588 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5589 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5590 #define TSC_IOASCR_G3_IO2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5591 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5592 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5593 #define TSC_IOASCR_G3_IO3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5594 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5595 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5596 #define TSC_IOASCR_G3_IO4_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5597 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5598 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5599 #define TSC_IOASCR_G4_IO1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5600 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5601 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5602 #define TSC_IOASCR_G4_IO2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5603 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5604 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5605 #define TSC_IOASCR_G4_IO3_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5606 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5607 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5608 #define TSC_IOASCR_G4_IO4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5609 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5610 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5611 #define TSC_IOASCR_G5_IO1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5612 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5613 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5614 #define TSC_IOASCR_G5_IO2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5615 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5616 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5617 #define TSC_IOASCR_G5_IO3_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5618 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5619 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5620 #define TSC_IOASCR_G5_IO4_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5621 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5622 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5623 #define TSC_IOASCR_G6_IO1_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5624 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5625 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5626 #define TSC_IOASCR_G6_IO2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5627 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5628 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5629 #define TSC_IOASCR_G6_IO3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5630 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5631 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5632 #define TSC_IOASCR_G6_IO4_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5633 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5634 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5635 #define TSC_IOASCR_G7_IO1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5636 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5637 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5638 #define TSC_IOASCR_G7_IO2_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5639 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5640 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5641 #define TSC_IOASCR_G7_IO3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5642 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5643 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5644 #define TSC_IOASCR_G7_IO4_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5645 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5646 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5647 #define TSC_IOASCR_G8_IO1_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5648 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5649 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5650 #define TSC_IOASCR_G8_IO2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5651 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5652 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5653 #define TSC_IOASCR_G8_IO3_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5654 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5655 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5656 #define TSC_IOASCR_G8_IO4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5657 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5658 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
sahilmgandhi 18:6a4db94011d3 5659
sahilmgandhi 18:6a4db94011d3 5660 /******************* Bit definition for TSC_IOSCR register ******************/
sahilmgandhi 18:6a4db94011d3 5661 #define TSC_IOSCR_G1_IO1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5662 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5663 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 5664 #define TSC_IOSCR_G1_IO2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5665 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5666 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 5667 #define TSC_IOSCR_G1_IO3_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5668 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5669 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 5670 #define TSC_IOSCR_G1_IO4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5671 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5672 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 5673 #define TSC_IOSCR_G2_IO1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5674 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5675 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 5676 #define TSC_IOSCR_G2_IO2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5677 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5678 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 5679 #define TSC_IOSCR_G2_IO3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5680 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5681 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 5682 #define TSC_IOSCR_G2_IO4_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5683 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5684 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 5685 #define TSC_IOSCR_G3_IO1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5686 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5687 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 5688 #define TSC_IOSCR_G3_IO2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5689 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5690 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 5691 #define TSC_IOSCR_G3_IO3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5692 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5693 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 5694 #define TSC_IOSCR_G3_IO4_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5695 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5696 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 5697 #define TSC_IOSCR_G4_IO1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5698 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5699 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 5700 #define TSC_IOSCR_G4_IO2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5701 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5702 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 5703 #define TSC_IOSCR_G4_IO3_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5704 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5705 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 5706 #define TSC_IOSCR_G4_IO4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5707 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5708 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 5709 #define TSC_IOSCR_G5_IO1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5710 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5711 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 5712 #define TSC_IOSCR_G5_IO2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5713 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5714 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 5715 #define TSC_IOSCR_G5_IO3_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5716 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5717 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 5718 #define TSC_IOSCR_G5_IO4_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5719 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5720 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 5721 #define TSC_IOSCR_G6_IO1_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5722 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5723 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 5724 #define TSC_IOSCR_G6_IO2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5725 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5726 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 5727 #define TSC_IOSCR_G6_IO3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5728 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5729 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 5730 #define TSC_IOSCR_G6_IO4_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5731 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5732 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 5733 #define TSC_IOSCR_G7_IO1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5734 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5735 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 5736 #define TSC_IOSCR_G7_IO2_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5737 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5738 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 5739 #define TSC_IOSCR_G7_IO3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5740 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5741 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 5742 #define TSC_IOSCR_G7_IO4_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5743 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5744 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 5745 #define TSC_IOSCR_G8_IO1_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5746 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5747 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
sahilmgandhi 18:6a4db94011d3 5748 #define TSC_IOSCR_G8_IO2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5749 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5750 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
sahilmgandhi 18:6a4db94011d3 5751 #define TSC_IOSCR_G8_IO3_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5752 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5753 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
sahilmgandhi 18:6a4db94011d3 5754 #define TSC_IOSCR_G8_IO4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5755 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5756 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
sahilmgandhi 18:6a4db94011d3 5757
sahilmgandhi 18:6a4db94011d3 5758 /******************* Bit definition for TSC_IOCCR register ******************/
sahilmgandhi 18:6a4db94011d3 5759 #define TSC_IOCCR_G1_IO1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5760 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5761 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 5762 #define TSC_IOCCR_G1_IO2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5763 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5764 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 5765 #define TSC_IOCCR_G1_IO3_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5766 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5767 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 5768 #define TSC_IOCCR_G1_IO4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5769 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5770 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 5771 #define TSC_IOCCR_G2_IO1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5772 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5773 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 5774 #define TSC_IOCCR_G2_IO2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5775 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5776 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 5777 #define TSC_IOCCR_G2_IO3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5778 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5779 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 5780 #define TSC_IOCCR_G2_IO4_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5781 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5782 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 5783 #define TSC_IOCCR_G3_IO1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5784 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5785 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 5786 #define TSC_IOCCR_G3_IO2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5787 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5788 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 5789 #define TSC_IOCCR_G3_IO3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5790 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5791 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 5792 #define TSC_IOCCR_G3_IO4_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5793 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5794 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 5795 #define TSC_IOCCR_G4_IO1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5796 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5797 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 5798 #define TSC_IOCCR_G4_IO2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5799 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5800 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 5801 #define TSC_IOCCR_G4_IO3_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5802 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5803 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 5804 #define TSC_IOCCR_G4_IO4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5805 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5806 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 5807 #define TSC_IOCCR_G5_IO1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5808 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5809 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 5810 #define TSC_IOCCR_G5_IO2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5811 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5812 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 5813 #define TSC_IOCCR_G5_IO3_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5814 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5815 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 5816 #define TSC_IOCCR_G5_IO4_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5817 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5818 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 5819 #define TSC_IOCCR_G6_IO1_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5820 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5821 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 5822 #define TSC_IOCCR_G6_IO2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5823 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5824 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 5825 #define TSC_IOCCR_G6_IO3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5826 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5827 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 5828 #define TSC_IOCCR_G6_IO4_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5829 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5830 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 5831 #define TSC_IOCCR_G7_IO1_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5832 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5833 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 5834 #define TSC_IOCCR_G7_IO2_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5835 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5836 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 5837 #define TSC_IOCCR_G7_IO3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5838 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5839 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 5840 #define TSC_IOCCR_G7_IO4_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5841 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5842 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 5843 #define TSC_IOCCR_G8_IO1_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5844 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5845 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
sahilmgandhi 18:6a4db94011d3 5846 #define TSC_IOCCR_G8_IO2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5847 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5848 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
sahilmgandhi 18:6a4db94011d3 5849 #define TSC_IOCCR_G8_IO3_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5850 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5851 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
sahilmgandhi 18:6a4db94011d3 5852 #define TSC_IOCCR_G8_IO4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5853 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5854 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
sahilmgandhi 18:6a4db94011d3 5855
sahilmgandhi 18:6a4db94011d3 5856 /******************* Bit definition for TSC_IOGCSR register *****************/
sahilmgandhi 18:6a4db94011d3 5857 #define TSC_IOGCSR_G1E_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5858 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5859 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
sahilmgandhi 18:6a4db94011d3 5860 #define TSC_IOGCSR_G2E_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5861 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5862 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
sahilmgandhi 18:6a4db94011d3 5863 #define TSC_IOGCSR_G3E_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5864 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5865 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
sahilmgandhi 18:6a4db94011d3 5866 #define TSC_IOGCSR_G4E_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5867 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5868 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
sahilmgandhi 18:6a4db94011d3 5869 #define TSC_IOGCSR_G5E_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5870 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5871 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
sahilmgandhi 18:6a4db94011d3 5872 #define TSC_IOGCSR_G6E_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5873 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5874 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
sahilmgandhi 18:6a4db94011d3 5875 #define TSC_IOGCSR_G7E_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5876 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5877 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
sahilmgandhi 18:6a4db94011d3 5878 #define TSC_IOGCSR_G8E_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5879 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5880 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
sahilmgandhi 18:6a4db94011d3 5881 #define TSC_IOGCSR_G1S_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5882 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5883 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
sahilmgandhi 18:6a4db94011d3 5884 #define TSC_IOGCSR_G2S_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5885 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5886 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
sahilmgandhi 18:6a4db94011d3 5887 #define TSC_IOGCSR_G3S_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5888 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5889 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
sahilmgandhi 18:6a4db94011d3 5890 #define TSC_IOGCSR_G4S_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5891 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5892 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
sahilmgandhi 18:6a4db94011d3 5893 #define TSC_IOGCSR_G5S_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5894 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5895 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
sahilmgandhi 18:6a4db94011d3 5896 #define TSC_IOGCSR_G6S_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5897 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5898 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
sahilmgandhi 18:6a4db94011d3 5899 #define TSC_IOGCSR_G7S_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5900 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5901 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
sahilmgandhi 18:6a4db94011d3 5902 #define TSC_IOGCSR_G8S_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5903 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5904 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
sahilmgandhi 18:6a4db94011d3 5905
sahilmgandhi 18:6a4db94011d3 5906 /******************* Bit definition for TSC_IOGXCR register *****************/
sahilmgandhi 18:6a4db94011d3 5907 #define TSC_IOGXCR_CNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5908 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
sahilmgandhi 18:6a4db94011d3 5909 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
sahilmgandhi 18:6a4db94011d3 5910
sahilmgandhi 18:6a4db94011d3 5911 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5912 /* */
sahilmgandhi 18:6a4db94011d3 5913 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
sahilmgandhi 18:6a4db94011d3 5914 /* */
sahilmgandhi 18:6a4db94011d3 5915 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5916
sahilmgandhi 18:6a4db94011d3 5917 /*
sahilmgandhi 18:6a4db94011d3 5918 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
sahilmgandhi 18:6a4db94011d3 5919 */
sahilmgandhi 18:6a4db94011d3 5920
sahilmgandhi 18:6a4db94011d3 5921 /* Support of LIN feature */
sahilmgandhi 18:6a4db94011d3 5922 #define USART_LIN_SUPPORT
sahilmgandhi 18:6a4db94011d3 5923
sahilmgandhi 18:6a4db94011d3 5924 /* Support of Smartcard feature */
sahilmgandhi 18:6a4db94011d3 5925 #define USART_SMARTCARD_SUPPORT
sahilmgandhi 18:6a4db94011d3 5926
sahilmgandhi 18:6a4db94011d3 5927 /* Support of Irda feature */
sahilmgandhi 18:6a4db94011d3 5928 #define USART_IRDA_SUPPORT
sahilmgandhi 18:6a4db94011d3 5929
sahilmgandhi 18:6a4db94011d3 5930 /* Support of Wake Up from Stop Mode feature */
sahilmgandhi 18:6a4db94011d3 5931 #define USART_WUSM_SUPPORT
sahilmgandhi 18:6a4db94011d3 5932
sahilmgandhi 18:6a4db94011d3 5933 /****************** Bit definition for USART_CR1 register *******************/
sahilmgandhi 18:6a4db94011d3 5934 #define USART_CR1_UE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5935 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5936 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
sahilmgandhi 18:6a4db94011d3 5937 #define USART_CR1_UESM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5938 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5939 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
sahilmgandhi 18:6a4db94011d3 5940 #define USART_CR1_RE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5941 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5942 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
sahilmgandhi 18:6a4db94011d3 5943 #define USART_CR1_TE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5944 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5945 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
sahilmgandhi 18:6a4db94011d3 5946 #define USART_CR1_IDLEIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5947 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5948 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5949 #define USART_CR1_RXNEIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5950 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5951 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5952 #define USART_CR1_TCIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5953 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5954 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5955 #define USART_CR1_TXEIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5956 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5957 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5958 #define USART_CR1_PEIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5959 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5960 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 5961 #define USART_CR1_PS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5962 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5963 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
sahilmgandhi 18:6a4db94011d3 5964 #define USART_CR1_PCE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5965 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5966 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
sahilmgandhi 18:6a4db94011d3 5967 #define USART_CR1_WAKE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5968 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5969 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
sahilmgandhi 18:6a4db94011d3 5970 #define USART_CR1_M_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5971 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5972 #define USART_CR1_M USART_CR1_M_Msk /*!< Word Length */
sahilmgandhi 18:6a4db94011d3 5973 #define USART_CR1_MME_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5974 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5975 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
sahilmgandhi 18:6a4db94011d3 5976 #define USART_CR1_CMIE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5977 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5978 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
sahilmgandhi 18:6a4db94011d3 5979 #define USART_CR1_OVER8_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5980 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5981 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
sahilmgandhi 18:6a4db94011d3 5982 #define USART_CR1_DEDT_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5983 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
sahilmgandhi 18:6a4db94011d3 5984 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
sahilmgandhi 18:6a4db94011d3 5985 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5986 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5987 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5988 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5989 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5990 #define USART_CR1_DEAT_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5991 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
sahilmgandhi 18:6a4db94011d3 5992 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
sahilmgandhi 18:6a4db94011d3 5993 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5994 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5995 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5996 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5997 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5998 #define USART_CR1_RTOIE_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5999 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6000 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
sahilmgandhi 18:6a4db94011d3 6001 #define USART_CR1_EOBIE_Pos (27U)
sahilmgandhi 18:6a4db94011d3 6002 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6003 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
sahilmgandhi 18:6a4db94011d3 6004
sahilmgandhi 18:6a4db94011d3 6005 /****************** Bit definition for USART_CR2 register *******************/
sahilmgandhi 18:6a4db94011d3 6006 #define USART_CR2_ADDM7_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6007 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6008 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
sahilmgandhi 18:6a4db94011d3 6009 #define USART_CR2_LBDL_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6010 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6011 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
sahilmgandhi 18:6a4db94011d3 6012 #define USART_CR2_LBDIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6013 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6014 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6015 #define USART_CR2_LBCL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6016 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6017 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
sahilmgandhi 18:6a4db94011d3 6018 #define USART_CR2_CPHA_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6019 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6020 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
sahilmgandhi 18:6a4db94011d3 6021 #define USART_CR2_CPOL_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6022 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6023 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
sahilmgandhi 18:6a4db94011d3 6024 #define USART_CR2_CLKEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6025 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6026 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
sahilmgandhi 18:6a4db94011d3 6027 #define USART_CR2_STOP_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6028 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 6029 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
sahilmgandhi 18:6a4db94011d3 6030 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6031 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6032 #define USART_CR2_LINEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6033 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6034 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
sahilmgandhi 18:6a4db94011d3 6035 #define USART_CR2_SWAP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6036 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6037 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
sahilmgandhi 18:6a4db94011d3 6038 #define USART_CR2_RXINV_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6039 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6040 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
sahilmgandhi 18:6a4db94011d3 6041 #define USART_CR2_TXINV_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6042 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6043 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
sahilmgandhi 18:6a4db94011d3 6044 #define USART_CR2_DATAINV_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6045 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6046 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
sahilmgandhi 18:6a4db94011d3 6047 #define USART_CR2_MSBFIRST_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6048 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6049 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
sahilmgandhi 18:6a4db94011d3 6050 #define USART_CR2_ABREN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6051 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6052 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
sahilmgandhi 18:6a4db94011d3 6053 #define USART_CR2_ABRMODE_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6054 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
sahilmgandhi 18:6a4db94011d3 6055 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
sahilmgandhi 18:6a4db94011d3 6056 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6057 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6058 #define USART_CR2_RTOEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 6059 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 6060 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
sahilmgandhi 18:6a4db94011d3 6061 #define USART_CR2_ADD_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6062 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 6063 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
sahilmgandhi 18:6a4db94011d3 6064
sahilmgandhi 18:6a4db94011d3 6065 /****************** Bit definition for USART_CR3 register *******************/
sahilmgandhi 18:6a4db94011d3 6066 #define USART_CR3_EIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6067 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6068 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6069 #define USART_CR3_IREN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6070 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6071 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
sahilmgandhi 18:6a4db94011d3 6072 #define USART_CR3_IRLP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6073 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6074 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
sahilmgandhi 18:6a4db94011d3 6075 #define USART_CR3_HDSEL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6076 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6077 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
sahilmgandhi 18:6a4db94011d3 6078 #define USART_CR3_NACK_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6079 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6080 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
sahilmgandhi 18:6a4db94011d3 6081 #define USART_CR3_SCEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6082 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6083 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
sahilmgandhi 18:6a4db94011d3 6084 #define USART_CR3_DMAR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6085 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6086 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
sahilmgandhi 18:6a4db94011d3 6087 #define USART_CR3_DMAT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6088 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6089 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
sahilmgandhi 18:6a4db94011d3 6090 #define USART_CR3_RTSE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6091 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6092 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
sahilmgandhi 18:6a4db94011d3 6093 #define USART_CR3_CTSE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6094 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6095 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
sahilmgandhi 18:6a4db94011d3 6096 #define USART_CR3_CTSIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6097 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6098 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6099 #define USART_CR3_ONEBIT_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6100 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6101 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
sahilmgandhi 18:6a4db94011d3 6102 #define USART_CR3_OVRDIS_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6103 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6104 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
sahilmgandhi 18:6a4db94011d3 6105 #define USART_CR3_DDRE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6106 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6107 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
sahilmgandhi 18:6a4db94011d3 6108 #define USART_CR3_DEM_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6109 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6110 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
sahilmgandhi 18:6a4db94011d3 6111 #define USART_CR3_DEP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6112 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6113 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
sahilmgandhi 18:6a4db94011d3 6114 #define USART_CR3_SCARCNT_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6115 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
sahilmgandhi 18:6a4db94011d3 6116 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
sahilmgandhi 18:6a4db94011d3 6117 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6118 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6119 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6120 #define USART_CR3_WUS_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6121 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 6122 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
sahilmgandhi 18:6a4db94011d3 6123 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6124 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6125 #define USART_CR3_WUFIE_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6126 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6127 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6128
sahilmgandhi 18:6a4db94011d3 6129 /****************** Bit definition for USART_BRR register *******************/
sahilmgandhi 18:6a4db94011d3 6130 #define USART_BRR_DIV_FRACTION_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6131 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 6132 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
sahilmgandhi 18:6a4db94011d3 6133 #define USART_BRR_DIV_MANTISSA_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6134 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 6135 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
sahilmgandhi 18:6a4db94011d3 6136
sahilmgandhi 18:6a4db94011d3 6137 /****************** Bit definition for USART_GTPR register ******************/
sahilmgandhi 18:6a4db94011d3 6138 #define USART_GTPR_PSC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6139 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 6140 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
sahilmgandhi 18:6a4db94011d3 6141 #define USART_GTPR_GT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6142 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 6143 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
sahilmgandhi 18:6a4db94011d3 6144
sahilmgandhi 18:6a4db94011d3 6145
sahilmgandhi 18:6a4db94011d3 6146 /******************* Bit definition for USART_RTOR register *****************/
sahilmgandhi 18:6a4db94011d3 6147 #define USART_RTOR_RTO_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6148 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
sahilmgandhi 18:6a4db94011d3 6149 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
sahilmgandhi 18:6a4db94011d3 6150 #define USART_RTOR_BLEN_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6151 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 6152 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
sahilmgandhi 18:6a4db94011d3 6153
sahilmgandhi 18:6a4db94011d3 6154 /******************* Bit definition for USART_RQR register ******************/
sahilmgandhi 18:6a4db94011d3 6155 #define USART_RQR_ABRRQ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6156 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6157 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
sahilmgandhi 18:6a4db94011d3 6158 #define USART_RQR_SBKRQ_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6159 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6160 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
sahilmgandhi 18:6a4db94011d3 6161 #define USART_RQR_MMRQ_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6162 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6163 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
sahilmgandhi 18:6a4db94011d3 6164 #define USART_RQR_RXFRQ_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6165 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6166 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
sahilmgandhi 18:6a4db94011d3 6167 #define USART_RQR_TXFRQ_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6168 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6169 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
sahilmgandhi 18:6a4db94011d3 6170
sahilmgandhi 18:6a4db94011d3 6171 /******************* Bit definition for USART_ISR register ******************/
sahilmgandhi 18:6a4db94011d3 6172 #define USART_ISR_PE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6173 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6174 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
sahilmgandhi 18:6a4db94011d3 6175 #define USART_ISR_FE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6176 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6177 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
sahilmgandhi 18:6a4db94011d3 6178 #define USART_ISR_NE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6179 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6180 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
sahilmgandhi 18:6a4db94011d3 6181 #define USART_ISR_ORE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6182 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6183 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
sahilmgandhi 18:6a4db94011d3 6184 #define USART_ISR_IDLE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6185 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6186 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
sahilmgandhi 18:6a4db94011d3 6187 #define USART_ISR_RXNE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6188 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6189 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
sahilmgandhi 18:6a4db94011d3 6190 #define USART_ISR_TC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6191 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6192 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
sahilmgandhi 18:6a4db94011d3 6193 #define USART_ISR_TXE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6194 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6195 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
sahilmgandhi 18:6a4db94011d3 6196 #define USART_ISR_LBDF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6197 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6198 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
sahilmgandhi 18:6a4db94011d3 6199 #define USART_ISR_CTSIF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6200 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6201 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
sahilmgandhi 18:6a4db94011d3 6202 #define USART_ISR_CTS_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6203 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6204 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
sahilmgandhi 18:6a4db94011d3 6205 #define USART_ISR_RTOF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6206 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6207 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
sahilmgandhi 18:6a4db94011d3 6208 #define USART_ISR_EOBF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6209 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6210 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
sahilmgandhi 18:6a4db94011d3 6211 #define USART_ISR_ABRE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6212 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6213 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
sahilmgandhi 18:6a4db94011d3 6214 #define USART_ISR_ABRF_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6215 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6216 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
sahilmgandhi 18:6a4db94011d3 6217 #define USART_ISR_BUSY_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6218 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6219 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
sahilmgandhi 18:6a4db94011d3 6220 #define USART_ISR_CMF_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6221 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6222 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
sahilmgandhi 18:6a4db94011d3 6223 #define USART_ISR_SBKF_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6224 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6225 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
sahilmgandhi 18:6a4db94011d3 6226 #define USART_ISR_RWU_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6227 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6228 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
sahilmgandhi 18:6a4db94011d3 6229 #define USART_ISR_WUF_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6230 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6231 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
sahilmgandhi 18:6a4db94011d3 6232 #define USART_ISR_TEACK_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6233 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6234 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
sahilmgandhi 18:6a4db94011d3 6235 #define USART_ISR_REACK_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6236 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6237 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
sahilmgandhi 18:6a4db94011d3 6238
sahilmgandhi 18:6a4db94011d3 6239 /******************* Bit definition for USART_ICR register ******************/
sahilmgandhi 18:6a4db94011d3 6240 #define USART_ICR_PECF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6241 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6242 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
sahilmgandhi 18:6a4db94011d3 6243 #define USART_ICR_FECF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6244 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6245 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
sahilmgandhi 18:6a4db94011d3 6246 #define USART_ICR_NCF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6247 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6248 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
sahilmgandhi 18:6a4db94011d3 6249 #define USART_ICR_ORECF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6250 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6251 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
sahilmgandhi 18:6a4db94011d3 6252 #define USART_ICR_IDLECF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6253 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6254 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
sahilmgandhi 18:6a4db94011d3 6255 #define USART_ICR_TCCF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6256 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6257 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
sahilmgandhi 18:6a4db94011d3 6258 #define USART_ICR_LBDCF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6259 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6260 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
sahilmgandhi 18:6a4db94011d3 6261 #define USART_ICR_CTSCF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6262 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6263 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
sahilmgandhi 18:6a4db94011d3 6264 #define USART_ICR_RTOCF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6265 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6266 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
sahilmgandhi 18:6a4db94011d3 6267 #define USART_ICR_EOBCF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6268 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6269 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
sahilmgandhi 18:6a4db94011d3 6270 #define USART_ICR_CMCF_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6271 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6272 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
sahilmgandhi 18:6a4db94011d3 6273 #define USART_ICR_WUCF_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6274 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6275 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
sahilmgandhi 18:6a4db94011d3 6276
sahilmgandhi 18:6a4db94011d3 6277 /******************* Bit definition for USART_RDR register ******************/
sahilmgandhi 18:6a4db94011d3 6278 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
sahilmgandhi 18:6a4db94011d3 6279
sahilmgandhi 18:6a4db94011d3 6280 /******************* Bit definition for USART_TDR register ******************/
sahilmgandhi 18:6a4db94011d3 6281 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
sahilmgandhi 18:6a4db94011d3 6282
sahilmgandhi 18:6a4db94011d3 6283 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6284 /* */
sahilmgandhi 18:6a4db94011d3 6285 /* Window WATCHDOG (WWDG) */
sahilmgandhi 18:6a4db94011d3 6286 /* */
sahilmgandhi 18:6a4db94011d3 6287 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6288
sahilmgandhi 18:6a4db94011d3 6289 /******************* Bit definition for WWDG_CR register ********************/
sahilmgandhi 18:6a4db94011d3 6290 #define WWDG_CR_T_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6291 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
sahilmgandhi 18:6a4db94011d3 6292 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
sahilmgandhi 18:6a4db94011d3 6293 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6294 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6295 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6296 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6297 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6298 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6299 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6300
sahilmgandhi 18:6a4db94011d3 6301 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6302 #define WWDG_CR_T0 WWDG_CR_T_0
sahilmgandhi 18:6a4db94011d3 6303 #define WWDG_CR_T1 WWDG_CR_T_1
sahilmgandhi 18:6a4db94011d3 6304 #define WWDG_CR_T2 WWDG_CR_T_2
sahilmgandhi 18:6a4db94011d3 6305 #define WWDG_CR_T3 WWDG_CR_T_3
sahilmgandhi 18:6a4db94011d3 6306 #define WWDG_CR_T4 WWDG_CR_T_4
sahilmgandhi 18:6a4db94011d3 6307 #define WWDG_CR_T5 WWDG_CR_T_5
sahilmgandhi 18:6a4db94011d3 6308 #define WWDG_CR_T6 WWDG_CR_T_6
sahilmgandhi 18:6a4db94011d3 6309
sahilmgandhi 18:6a4db94011d3 6310 #define WWDG_CR_WDGA_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6311 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6312 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
sahilmgandhi 18:6a4db94011d3 6313
sahilmgandhi 18:6a4db94011d3 6314 /******************* Bit definition for WWDG_CFR register *******************/
sahilmgandhi 18:6a4db94011d3 6315 #define WWDG_CFR_W_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6316 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
sahilmgandhi 18:6a4db94011d3 6317 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
sahilmgandhi 18:6a4db94011d3 6318 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6319 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6320 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6321 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6322 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6323 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6324 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6325
sahilmgandhi 18:6a4db94011d3 6326 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6327 #define WWDG_CFR_W0 WWDG_CFR_W_0
sahilmgandhi 18:6a4db94011d3 6328 #define WWDG_CFR_W1 WWDG_CFR_W_1
sahilmgandhi 18:6a4db94011d3 6329 #define WWDG_CFR_W2 WWDG_CFR_W_2
sahilmgandhi 18:6a4db94011d3 6330 #define WWDG_CFR_W3 WWDG_CFR_W_3
sahilmgandhi 18:6a4db94011d3 6331 #define WWDG_CFR_W4 WWDG_CFR_W_4
sahilmgandhi 18:6a4db94011d3 6332 #define WWDG_CFR_W5 WWDG_CFR_W_5
sahilmgandhi 18:6a4db94011d3 6333 #define WWDG_CFR_W6 WWDG_CFR_W_6
sahilmgandhi 18:6a4db94011d3 6334
sahilmgandhi 18:6a4db94011d3 6335 #define WWDG_CFR_WDGTB_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6336 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
sahilmgandhi 18:6a4db94011d3 6337 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
sahilmgandhi 18:6a4db94011d3 6338 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6339 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6340
sahilmgandhi 18:6a4db94011d3 6341 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6342 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
sahilmgandhi 18:6a4db94011d3 6343 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
sahilmgandhi 18:6a4db94011d3 6344
sahilmgandhi 18:6a4db94011d3 6345 #define WWDG_CFR_EWI_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6346 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6347 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
sahilmgandhi 18:6a4db94011d3 6348
sahilmgandhi 18:6a4db94011d3 6349 /******************* Bit definition for WWDG_SR register ********************/
sahilmgandhi 18:6a4db94011d3 6350 #define WWDG_SR_EWIF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6351 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6352 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6353
sahilmgandhi 18:6a4db94011d3 6354 /**
sahilmgandhi 18:6a4db94011d3 6355 * @}
sahilmgandhi 18:6a4db94011d3 6356 */
sahilmgandhi 18:6a4db94011d3 6357
sahilmgandhi 18:6a4db94011d3 6358 /**
sahilmgandhi 18:6a4db94011d3 6359 * @}
sahilmgandhi 18:6a4db94011d3 6360 */
sahilmgandhi 18:6a4db94011d3 6361
sahilmgandhi 18:6a4db94011d3 6362
sahilmgandhi 18:6a4db94011d3 6363 /** @addtogroup Exported_macro
sahilmgandhi 18:6a4db94011d3 6364 * @{
sahilmgandhi 18:6a4db94011d3 6365 */
sahilmgandhi 18:6a4db94011d3 6366
sahilmgandhi 18:6a4db94011d3 6367 /****************************** ADC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6368 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
sahilmgandhi 18:6a4db94011d3 6369
sahilmgandhi 18:6a4db94011d3 6370 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
sahilmgandhi 18:6a4db94011d3 6371
sahilmgandhi 18:6a4db94011d3 6372 /****************************** COMP Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6373 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
sahilmgandhi 18:6a4db94011d3 6374 ((INSTANCE) == COMP2))
sahilmgandhi 18:6a4db94011d3 6375
sahilmgandhi 18:6a4db94011d3 6376 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
sahilmgandhi 18:6a4db94011d3 6377
sahilmgandhi 18:6a4db94011d3 6378 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
sahilmgandhi 18:6a4db94011d3 6379
sahilmgandhi 18:6a4db94011d3 6380 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
sahilmgandhi 18:6a4db94011d3 6381
sahilmgandhi 18:6a4db94011d3 6382 /****************************** CEC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6383 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
sahilmgandhi 18:6a4db94011d3 6384
sahilmgandhi 18:6a4db94011d3 6385 /****************************** CRC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6386 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
sahilmgandhi 18:6a4db94011d3 6387
sahilmgandhi 18:6a4db94011d3 6388 /******************************* DAC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 6389 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
sahilmgandhi 18:6a4db94011d3 6390
sahilmgandhi 18:6a4db94011d3 6391 /******************************* DMA Instances ********************************/
sahilmgandhi 18:6a4db94011d3 6392 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
sahilmgandhi 18:6a4db94011d3 6393 ((INSTANCE) == DMA1_Channel2) || \
sahilmgandhi 18:6a4db94011d3 6394 ((INSTANCE) == DMA1_Channel3) || \
sahilmgandhi 18:6a4db94011d3 6395 ((INSTANCE) == DMA1_Channel4) || \
sahilmgandhi 18:6a4db94011d3 6396 ((INSTANCE) == DMA1_Channel5))
sahilmgandhi 18:6a4db94011d3 6397
sahilmgandhi 18:6a4db94011d3 6398 /****************************** GPIO Instances ********************************/
sahilmgandhi 18:6a4db94011d3 6399 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
sahilmgandhi 18:6a4db94011d3 6400 ((INSTANCE) == GPIOB) || \
sahilmgandhi 18:6a4db94011d3 6401 ((INSTANCE) == GPIOC) || \
sahilmgandhi 18:6a4db94011d3 6402 ((INSTANCE) == GPIOD) || \
sahilmgandhi 18:6a4db94011d3 6403 ((INSTANCE) == GPIOF))
sahilmgandhi 18:6a4db94011d3 6404
sahilmgandhi 18:6a4db94011d3 6405 /**************************** GPIO Alternate Function Instances ***************/
sahilmgandhi 18:6a4db94011d3 6406 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
sahilmgandhi 18:6a4db94011d3 6407 ((INSTANCE) == GPIOB))
sahilmgandhi 18:6a4db94011d3 6408
sahilmgandhi 18:6a4db94011d3 6409 /****************************** GPIO Lock Instances ***************************/
sahilmgandhi 18:6a4db94011d3 6410 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
sahilmgandhi 18:6a4db94011d3 6411 ((INSTANCE) == GPIOB))
sahilmgandhi 18:6a4db94011d3 6412
sahilmgandhi 18:6a4db94011d3 6413 /****************************** I2C Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6414 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
sahilmgandhi 18:6a4db94011d3 6415 ((INSTANCE) == I2C2))
sahilmgandhi 18:6a4db94011d3 6416
sahilmgandhi 18:6a4db94011d3 6417 /****************** I2C Instances : wakeup capability from stop modes *********/
sahilmgandhi 18:6a4db94011d3 6418 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
sahilmgandhi 18:6a4db94011d3 6419
sahilmgandhi 18:6a4db94011d3 6420 /****************************** I2S Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6421 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
sahilmgandhi 18:6a4db94011d3 6422 ((INSTANCE) == SPI2))
sahilmgandhi 18:6a4db94011d3 6423
sahilmgandhi 18:6a4db94011d3 6424 /****************************** IWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 6425 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
sahilmgandhi 18:6a4db94011d3 6426
sahilmgandhi 18:6a4db94011d3 6427 /****************************** RTC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6428 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
sahilmgandhi 18:6a4db94011d3 6429
sahilmgandhi 18:6a4db94011d3 6430 /****************************** SMBUS Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6431 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
sahilmgandhi 18:6a4db94011d3 6432
sahilmgandhi 18:6a4db94011d3 6433 /****************************** SPI Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6434 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
sahilmgandhi 18:6a4db94011d3 6435 ((INSTANCE) == SPI2))
sahilmgandhi 18:6a4db94011d3 6436
sahilmgandhi 18:6a4db94011d3 6437 /****************************** TIM Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6438 #define IS_TIM_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6439 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6440 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6441 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6442 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 6443 ((INSTANCE) == TIM14) || \
sahilmgandhi 18:6a4db94011d3 6444 ((INSTANCE) == TIM15) || \
sahilmgandhi 18:6a4db94011d3 6445 ((INSTANCE) == TIM16) || \
sahilmgandhi 18:6a4db94011d3 6446 ((INSTANCE) == TIM17))
sahilmgandhi 18:6a4db94011d3 6447
sahilmgandhi 18:6a4db94011d3 6448 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6449 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6450 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6451 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6452 ((INSTANCE) == TIM14) || \
sahilmgandhi 18:6a4db94011d3 6453 ((INSTANCE) == TIM15) || \
sahilmgandhi 18:6a4db94011d3 6454 ((INSTANCE) == TIM16) || \
sahilmgandhi 18:6a4db94011d3 6455 ((INSTANCE) == TIM17))
sahilmgandhi 18:6a4db94011d3 6456
sahilmgandhi 18:6a4db94011d3 6457 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6458 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6459 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6460 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6461 ((INSTANCE) == TIM15))
sahilmgandhi 18:6a4db94011d3 6462
sahilmgandhi 18:6a4db94011d3 6463 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6464 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6465 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6466 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 6467
sahilmgandhi 18:6a4db94011d3 6468 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6469 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6470 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6471 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 6472
sahilmgandhi 18:6a4db94011d3 6473 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6474 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6475 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6476 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 6477
sahilmgandhi 18:6a4db94011d3 6478 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6479 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6480 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6481 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 6482
sahilmgandhi 18:6a4db94011d3 6483 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6484 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6485 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6486 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6487 ((INSTANCE) == TIM15))
sahilmgandhi 18:6a4db94011d3 6488
sahilmgandhi 18:6a4db94011d3 6489 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6490 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6491 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6492 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6493 ((INSTANCE) == TIM15))
sahilmgandhi 18:6a4db94011d3 6494
sahilmgandhi 18:6a4db94011d3 6495 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6496 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6497 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6498 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 6499
sahilmgandhi 18:6a4db94011d3 6500 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6501 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6502 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6503 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 6504
sahilmgandhi 18:6a4db94011d3 6505 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6506 (((INSTANCE) == TIM1))
sahilmgandhi 18:6a4db94011d3 6507
sahilmgandhi 18:6a4db94011d3 6508 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6509 (((INSTANCE) == TIM1))
sahilmgandhi 18:6a4db94011d3 6510
sahilmgandhi 18:6a4db94011d3 6511 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6512 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6513 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6514 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 6515
sahilmgandhi 18:6a4db94011d3 6516 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6517 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6518 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6519 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6520 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 6521 ((INSTANCE) == TIM15))
sahilmgandhi 18:6a4db94011d3 6522
sahilmgandhi 18:6a4db94011d3 6523 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6524 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6525 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6526 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6527 ((INSTANCE) == TIM15))
sahilmgandhi 18:6a4db94011d3 6528
sahilmgandhi 18:6a4db94011d3 6529 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6530 ((INSTANCE) == TIM2)
sahilmgandhi 18:6a4db94011d3 6531
sahilmgandhi 18:6a4db94011d3 6532 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6533 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6534 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6535 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6536 ((INSTANCE) == TIM15) || \
sahilmgandhi 18:6a4db94011d3 6537 ((INSTANCE) == TIM16) || \
sahilmgandhi 18:6a4db94011d3 6538 ((INSTANCE) == TIM17))
sahilmgandhi 18:6a4db94011d3 6539
sahilmgandhi 18:6a4db94011d3 6540 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6541 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6542 ((INSTANCE) == TIM15) || \
sahilmgandhi 18:6a4db94011d3 6543 ((INSTANCE) == TIM16) || \
sahilmgandhi 18:6a4db94011d3 6544 ((INSTANCE) == TIM17))
sahilmgandhi 18:6a4db94011d3 6545
sahilmgandhi 18:6a4db94011d3 6546 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
sahilmgandhi 18:6a4db94011d3 6547 ((((INSTANCE) == TIM1) && \
sahilmgandhi 18:6a4db94011d3 6548 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 6549 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 6550 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 6551 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 6552 || \
sahilmgandhi 18:6a4db94011d3 6553 (((INSTANCE) == TIM2) && \
sahilmgandhi 18:6a4db94011d3 6554 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 6555 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 6556 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 6557 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 6558 || \
sahilmgandhi 18:6a4db94011d3 6559 (((INSTANCE) == TIM3) && \
sahilmgandhi 18:6a4db94011d3 6560 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 6561 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 6562 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 6563 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 6564 || \
sahilmgandhi 18:6a4db94011d3 6565 (((INSTANCE) == TIM14) && \
sahilmgandhi 18:6a4db94011d3 6566 (((CHANNEL) == TIM_CHANNEL_1))) \
sahilmgandhi 18:6a4db94011d3 6567 || \
sahilmgandhi 18:6a4db94011d3 6568 (((INSTANCE) == TIM15) && \
sahilmgandhi 18:6a4db94011d3 6569 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 6570 ((CHANNEL) == TIM_CHANNEL_2))) \
sahilmgandhi 18:6a4db94011d3 6571 || \
sahilmgandhi 18:6a4db94011d3 6572 (((INSTANCE) == TIM16) && \
sahilmgandhi 18:6a4db94011d3 6573 (((CHANNEL) == TIM_CHANNEL_1))) \
sahilmgandhi 18:6a4db94011d3 6574 || \
sahilmgandhi 18:6a4db94011d3 6575 (((INSTANCE) == TIM17) && \
sahilmgandhi 18:6a4db94011d3 6576 (((CHANNEL) == TIM_CHANNEL_1))))
sahilmgandhi 18:6a4db94011d3 6577
sahilmgandhi 18:6a4db94011d3 6578 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
sahilmgandhi 18:6a4db94011d3 6579 ((((INSTANCE) == TIM1) && \
sahilmgandhi 18:6a4db94011d3 6580 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 6581 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 6582 ((CHANNEL) == TIM_CHANNEL_3))) \
sahilmgandhi 18:6a4db94011d3 6583 || \
sahilmgandhi 18:6a4db94011d3 6584 (((INSTANCE) == TIM15) && \
sahilmgandhi 18:6a4db94011d3 6585 ((CHANNEL) == TIM_CHANNEL_1)) \
sahilmgandhi 18:6a4db94011d3 6586 || \
sahilmgandhi 18:6a4db94011d3 6587 (((INSTANCE) == TIM16) && \
sahilmgandhi 18:6a4db94011d3 6588 ((CHANNEL) == TIM_CHANNEL_1)) \
sahilmgandhi 18:6a4db94011d3 6589 || \
sahilmgandhi 18:6a4db94011d3 6590 (((INSTANCE) == TIM17) && \
sahilmgandhi 18:6a4db94011d3 6591 ((CHANNEL) == TIM_CHANNEL_1)))
sahilmgandhi 18:6a4db94011d3 6592
sahilmgandhi 18:6a4db94011d3 6593 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6594 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6595 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6596 ((INSTANCE) == TIM3))
sahilmgandhi 18:6a4db94011d3 6597
sahilmgandhi 18:6a4db94011d3 6598 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6599 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6600 ((INSTANCE) == TIM15) || \
sahilmgandhi 18:6a4db94011d3 6601 ((INSTANCE) == TIM16) || \
sahilmgandhi 18:6a4db94011d3 6602 ((INSTANCE) == TIM17))
sahilmgandhi 18:6a4db94011d3 6603
sahilmgandhi 18:6a4db94011d3 6604 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6605 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6606 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6607 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6608 ((INSTANCE) == TIM14) || \
sahilmgandhi 18:6a4db94011d3 6609 ((INSTANCE) == TIM15) || \
sahilmgandhi 18:6a4db94011d3 6610 ((INSTANCE) == TIM16) || \
sahilmgandhi 18:6a4db94011d3 6611 ((INSTANCE) == TIM17))
sahilmgandhi 18:6a4db94011d3 6612
sahilmgandhi 18:6a4db94011d3 6613 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6614 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6615 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6616 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6617 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 6618 ((INSTANCE) == TIM15) || \
sahilmgandhi 18:6a4db94011d3 6619 ((INSTANCE) == TIM16) || \
sahilmgandhi 18:6a4db94011d3 6620 ((INSTANCE) == TIM17))
sahilmgandhi 18:6a4db94011d3 6621
sahilmgandhi 18:6a4db94011d3 6622 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6623 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6624 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 6625 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 6626 ((INSTANCE) == TIM15) || \
sahilmgandhi 18:6a4db94011d3 6627 ((INSTANCE) == TIM16) || \
sahilmgandhi 18:6a4db94011d3 6628 ((INSTANCE) == TIM17))
sahilmgandhi 18:6a4db94011d3 6629
sahilmgandhi 18:6a4db94011d3 6630 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6631 (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 6632 ((INSTANCE) == TIM15) || \
sahilmgandhi 18:6a4db94011d3 6633 ((INSTANCE) == TIM16) || \
sahilmgandhi 18:6a4db94011d3 6634 ((INSTANCE) == TIM17))
sahilmgandhi 18:6a4db94011d3 6635
sahilmgandhi 18:6a4db94011d3 6636 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
sahilmgandhi 18:6a4db94011d3 6637 ((INSTANCE) == TIM14)
sahilmgandhi 18:6a4db94011d3 6638
sahilmgandhi 18:6a4db94011d3 6639 /****************************** TSC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 6640 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
sahilmgandhi 18:6a4db94011d3 6641
sahilmgandhi 18:6a4db94011d3 6642 /*********************** UART Instances : IRDA mode ***************************/
sahilmgandhi 18:6a4db94011d3 6643 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
sahilmgandhi 18:6a4db94011d3 6644
sahilmgandhi 18:6a4db94011d3 6645 /********************* UART Instances : Smard card mode ***********************/
sahilmgandhi 18:6a4db94011d3 6646 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
sahilmgandhi 18:6a4db94011d3 6647
sahilmgandhi 18:6a4db94011d3 6648 /******************** USART Instances : Synchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 6649 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 6650 ((INSTANCE) == USART2))
sahilmgandhi 18:6a4db94011d3 6651
sahilmgandhi 18:6a4db94011d3 6652 /******************** USART Instances : auto Baud rate detection **************/
sahilmgandhi 18:6a4db94011d3 6653 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
sahilmgandhi 18:6a4db94011d3 6654
sahilmgandhi 18:6a4db94011d3 6655 /******************** UART Instances : Asynchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 6656 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 6657 ((INSTANCE) == USART2))
sahilmgandhi 18:6a4db94011d3 6658
sahilmgandhi 18:6a4db94011d3 6659 /******************** UART Instances : Half-Duplex mode **********************/
sahilmgandhi 18:6a4db94011d3 6660 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 6661 ((INSTANCE) == USART2))
sahilmgandhi 18:6a4db94011d3 6662
sahilmgandhi 18:6a4db94011d3 6663 /****************** UART Instances : Hardware Flow control ********************/
sahilmgandhi 18:6a4db94011d3 6664 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 6665 ((INSTANCE) == USART2))
sahilmgandhi 18:6a4db94011d3 6666
sahilmgandhi 18:6a4db94011d3 6667 /****************** UART Instances : LIN mode ********************/
sahilmgandhi 18:6a4db94011d3 6668 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
sahilmgandhi 18:6a4db94011d3 6669
sahilmgandhi 18:6a4db94011d3 6670 /****************** UART Instances : wakeup from stop mode ********************/
sahilmgandhi 18:6a4db94011d3 6671 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
sahilmgandhi 18:6a4db94011d3 6672 /* Old macro definition maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 6673 #define IS_UART_WAKEUP_INSTANCE IS_UART_WAKEUP_FROMSTOP_INSTANCE
sahilmgandhi 18:6a4db94011d3 6674
sahilmgandhi 18:6a4db94011d3 6675 /****************** UART Instances : Driver enable detection ********************/
sahilmgandhi 18:6a4db94011d3 6676 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 6677 ((INSTANCE) == USART2))
sahilmgandhi 18:6a4db94011d3 6678
sahilmgandhi 18:6a4db94011d3 6679 /****************************** WWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 6680 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
sahilmgandhi 18:6a4db94011d3 6681
sahilmgandhi 18:6a4db94011d3 6682 /**
sahilmgandhi 18:6a4db94011d3 6683 * @}
sahilmgandhi 18:6a4db94011d3 6684 */
sahilmgandhi 18:6a4db94011d3 6685
sahilmgandhi 18:6a4db94011d3 6686
sahilmgandhi 18:6a4db94011d3 6687 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6688 /* For a painless codes migration between the STM32F0xx device product */
sahilmgandhi 18:6a4db94011d3 6689 /* lines, the aliases defined below are put in place to overcome the */
sahilmgandhi 18:6a4db94011d3 6690 /* differences in the interrupt handlers and IRQn definitions. */
sahilmgandhi 18:6a4db94011d3 6691 /* No need to update developed interrupt code when moving across */
sahilmgandhi 18:6a4db94011d3 6692 /* product lines within the same STM32F0 Family */
sahilmgandhi 18:6a4db94011d3 6693 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6694
sahilmgandhi 18:6a4db94011d3 6695 /* Aliases for __IRQn */
sahilmgandhi 18:6a4db94011d3 6696 #define ADC1_IRQn ADC1_COMP_IRQn
sahilmgandhi 18:6a4db94011d3 6697 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
sahilmgandhi 18:6a4db94011d3 6698 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
sahilmgandhi 18:6a4db94011d3 6699 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
sahilmgandhi 18:6a4db94011d3 6700 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
sahilmgandhi 18:6a4db94011d3 6701 #define VDDIO2_IRQn PVD_IRQn
sahilmgandhi 18:6a4db94011d3 6702 #define PVD_VDDIO2_IRQn PVD_IRQn
sahilmgandhi 18:6a4db94011d3 6703 #define RCC_CRS_IRQn RCC_IRQn
sahilmgandhi 18:6a4db94011d3 6704 #define TIM6_IRQn TIM6_DAC_IRQn
sahilmgandhi 18:6a4db94011d3 6705
sahilmgandhi 18:6a4db94011d3 6706
sahilmgandhi 18:6a4db94011d3 6707 /* Aliases for __IRQHandler */
sahilmgandhi 18:6a4db94011d3 6708 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
sahilmgandhi 18:6a4db94011d3 6709 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
sahilmgandhi 18:6a4db94011d3 6710 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
sahilmgandhi 18:6a4db94011d3 6711 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
sahilmgandhi 18:6a4db94011d3 6712 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
sahilmgandhi 18:6a4db94011d3 6713 #define VDDIO2_IRQHandler PVD_IRQHandler
sahilmgandhi 18:6a4db94011d3 6714 #define PVD_VDDIO2_IRQHandler PVD_IRQHandler
sahilmgandhi 18:6a4db94011d3 6715 #define RCC_CRS_IRQHandler RCC_IRQHandler
sahilmgandhi 18:6a4db94011d3 6716 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
sahilmgandhi 18:6a4db94011d3 6717
sahilmgandhi 18:6a4db94011d3 6718
sahilmgandhi 18:6a4db94011d3 6719 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 6720 }
sahilmgandhi 18:6a4db94011d3 6721 #endif /* __cplusplus */
sahilmgandhi 18:6a4db94011d3 6722
sahilmgandhi 18:6a4db94011d3 6723 #endif /* __STM32F051x8_H */
sahilmgandhi 18:6a4db94011d3 6724
sahilmgandhi 18:6a4db94011d3 6725 /**
sahilmgandhi 18:6a4db94011d3 6726 * @}
sahilmgandhi 18:6a4db94011d3 6727 */
sahilmgandhi 18:6a4db94011d3 6728
sahilmgandhi 18:6a4db94011d3 6729 /**
sahilmgandhi 18:6a4db94011d3 6730 * @}
sahilmgandhi 18:6a4db94011d3 6731 */
sahilmgandhi 18:6a4db94011d3 6732
sahilmgandhi 18:6a4db94011d3 6733 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/