Mouse code for the MacroRat
mbed-dev/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/vfp_neon_push_pop.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | #ifndef __VFP_NEON_PUSH_POP_H__ |
sahilmgandhi | 18:6a4db94011d3 | 2 | #define __VFP_NEON_PUSH_POP_H__ |
sahilmgandhi | 18:6a4db94011d3 | 3 | |
sahilmgandhi | 18:6a4db94011d3 | 4 | |
sahilmgandhi | 18:6a4db94011d3 | 5 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 6 | /* ARM armcc specific functions */ |
sahilmgandhi | 18:6a4db94011d3 | 7 | #pragma push |
sahilmgandhi | 18:6a4db94011d3 | 8 | #pragma arm |
sahilmgandhi | 18:6a4db94011d3 | 9 | __STATIC_ASM void __vfp_neon_push(void) { |
sahilmgandhi | 18:6a4db94011d3 | 10 | ARM |
sahilmgandhi | 18:6a4db94011d3 | 11 | |
sahilmgandhi | 18:6a4db94011d3 | 12 | VMRS R2,FPSCR |
sahilmgandhi | 18:6a4db94011d3 | 13 | STMDB SP!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment |
sahilmgandhi | 18:6a4db94011d3 | 14 | VSTMDB SP!,{D0-D15} |
sahilmgandhi | 18:6a4db94011d3 | 15 | VSTMDB SP!,{D16-D31} |
sahilmgandhi | 18:6a4db94011d3 | 16 | BX LR |
sahilmgandhi | 18:6a4db94011d3 | 17 | } |
sahilmgandhi | 18:6a4db94011d3 | 18 | #pragma pop |
sahilmgandhi | 18:6a4db94011d3 | 19 | |
sahilmgandhi | 18:6a4db94011d3 | 20 | #pragma push |
sahilmgandhi | 18:6a4db94011d3 | 21 | #pragma arm |
sahilmgandhi | 18:6a4db94011d3 | 22 | __STATIC_ASM void __vfp_neon_pop(void) { |
sahilmgandhi | 18:6a4db94011d3 | 23 | ARM |
sahilmgandhi | 18:6a4db94011d3 | 24 | |
sahilmgandhi | 18:6a4db94011d3 | 25 | VLDMIA SP!,{D16-D31} |
sahilmgandhi | 18:6a4db94011d3 | 26 | VLDMIA SP!,{D0-D15} |
sahilmgandhi | 18:6a4db94011d3 | 27 | LDR R2,[SP] |
sahilmgandhi | 18:6a4db94011d3 | 28 | VMSR FPSCR,R2 |
sahilmgandhi | 18:6a4db94011d3 | 29 | ADD SP,SP,#8 |
sahilmgandhi | 18:6a4db94011d3 | 30 | BX LR |
sahilmgandhi | 18:6a4db94011d3 | 31 | } |
sahilmgandhi | 18:6a4db94011d3 | 32 | #pragma pop |
sahilmgandhi | 18:6a4db94011d3 | 33 | |
sahilmgandhi | 18:6a4db94011d3 | 34 | |
sahilmgandhi | 18:6a4db94011d3 | 35 | #pragma push |
sahilmgandhi | 18:6a4db94011d3 | 36 | #pragma arm |
sahilmgandhi | 18:6a4db94011d3 | 37 | __STATIC_ASM void __vfp_push(void) { |
sahilmgandhi | 18:6a4db94011d3 | 38 | ARM |
sahilmgandhi | 18:6a4db94011d3 | 39 | |
sahilmgandhi | 18:6a4db94011d3 | 40 | VMRS R2,FPSCR |
sahilmgandhi | 18:6a4db94011d3 | 41 | STMDB SP!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment |
sahilmgandhi | 18:6a4db94011d3 | 42 | VSTMDB SP!,{D0-D15} |
sahilmgandhi | 18:6a4db94011d3 | 43 | BX LR |
sahilmgandhi | 18:6a4db94011d3 | 44 | } |
sahilmgandhi | 18:6a4db94011d3 | 45 | #pragma pop |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | #pragma push |
sahilmgandhi | 18:6a4db94011d3 | 48 | #pragma arm |
sahilmgandhi | 18:6a4db94011d3 | 49 | __STATIC_ASM void __vfp_pop(void) { |
sahilmgandhi | 18:6a4db94011d3 | 50 | ARM |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | VLDMIA SP!,{D0-D15} |
sahilmgandhi | 18:6a4db94011d3 | 53 | LDR R2,[SP] |
sahilmgandhi | 18:6a4db94011d3 | 54 | VMSR FPSCR,R2 |
sahilmgandhi | 18:6a4db94011d3 | 55 | ADD SP,SP,#8 |
sahilmgandhi | 18:6a4db94011d3 | 56 | BX LR |
sahilmgandhi | 18:6a4db94011d3 | 57 | } |
sahilmgandhi | 18:6a4db94011d3 | 58 | #pragma pop |
sahilmgandhi | 18:6a4db94011d3 | 59 | |
sahilmgandhi | 18:6a4db94011d3 | 60 | #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 61 | |
sahilmgandhi | 18:6a4db94011d3 | 62 | __arm static inline void __vfp_neon_push(void) { |
sahilmgandhi | 18:6a4db94011d3 | 63 | __asm( |
sahilmgandhi | 18:6a4db94011d3 | 64 | "ARM \n" |
sahilmgandhi | 18:6a4db94011d3 | 65 | "VMRS R2,FPSCR \n" |
sahilmgandhi | 18:6a4db94011d3 | 66 | "STMDB SP!,{R2,R4} \n" // Push FPSCR, maintain 8-byte alignment |
sahilmgandhi | 18:6a4db94011d3 | 67 | "VSTMDB SP!,{D0-D15} \n" |
sahilmgandhi | 18:6a4db94011d3 | 68 | "VSTMDB SP!,{D16-D31} \n" |
sahilmgandhi | 18:6a4db94011d3 | 69 | "BX lr \n" ); |
sahilmgandhi | 18:6a4db94011d3 | 70 | } |
sahilmgandhi | 18:6a4db94011d3 | 71 | |
sahilmgandhi | 18:6a4db94011d3 | 72 | __arm static inline void __vfp_neon_pop(void) { |
sahilmgandhi | 18:6a4db94011d3 | 73 | __asm( |
sahilmgandhi | 18:6a4db94011d3 | 74 | "ARM \n" |
sahilmgandhi | 18:6a4db94011d3 | 75 | "VLDMIA SP!,{D16-D31} \n" |
sahilmgandhi | 18:6a4db94011d3 | 76 | "VLDMIA SP!,{D0-D15} \n" |
sahilmgandhi | 18:6a4db94011d3 | 77 | "LDR R2,[SP] \n" |
sahilmgandhi | 18:6a4db94011d3 | 78 | "VMSR FPSCR,R2 \n" |
sahilmgandhi | 18:6a4db94011d3 | 79 | "ADD SP,SP,#8 \n" |
sahilmgandhi | 18:6a4db94011d3 | 80 | "BX lr \n" ); |
sahilmgandhi | 18:6a4db94011d3 | 81 | } |
sahilmgandhi | 18:6a4db94011d3 | 82 | |
sahilmgandhi | 18:6a4db94011d3 | 83 | __arm static inline void __vfp_push(void) { |
sahilmgandhi | 18:6a4db94011d3 | 84 | __asm( |
sahilmgandhi | 18:6a4db94011d3 | 85 | "ARM \n" |
sahilmgandhi | 18:6a4db94011d3 | 86 | "VMRS R2,FPSCR \n" |
sahilmgandhi | 18:6a4db94011d3 | 87 | "STMDB SP!,{R2,R4} \n" // Push FPSCR, maintain 8-byte alignment |
sahilmgandhi | 18:6a4db94011d3 | 88 | "VSTMDB SP!,{D0-D15} \n" |
sahilmgandhi | 18:6a4db94011d3 | 89 | "BX lr \n" ); |
sahilmgandhi | 18:6a4db94011d3 | 90 | } |
sahilmgandhi | 18:6a4db94011d3 | 91 | |
sahilmgandhi | 18:6a4db94011d3 | 92 | __arm static inline void __vfp_pop(void) { |
sahilmgandhi | 18:6a4db94011d3 | 93 | __asm( |
sahilmgandhi | 18:6a4db94011d3 | 94 | "ARM \n" |
sahilmgandhi | 18:6a4db94011d3 | 95 | "VLDMIA SP!,{D0-D15} \n" |
sahilmgandhi | 18:6a4db94011d3 | 96 | "LDR R2,[SP] \n" |
sahilmgandhi | 18:6a4db94011d3 | 97 | "VMSR FPSCR,R2 \n" |
sahilmgandhi | 18:6a4db94011d3 | 98 | "ADD SP,SP,#8 \n" |
sahilmgandhi | 18:6a4db94011d3 | 99 | "BX lr \n" ); |
sahilmgandhi | 18:6a4db94011d3 | 100 | } |
sahilmgandhi | 18:6a4db94011d3 | 101 | |
sahilmgandhi | 18:6a4db94011d3 | 102 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 103 | |
sahilmgandhi | 18:6a4db94011d3 | 104 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_push(void) |
sahilmgandhi | 18:6a4db94011d3 | 105 | { |
sahilmgandhi | 18:6a4db94011d3 | 106 | __asm__ volatile ( |
sahilmgandhi | 18:6a4db94011d3 | 107 | ".ARM;" |
sahilmgandhi | 18:6a4db94011d3 | 108 | |
sahilmgandhi | 18:6a4db94011d3 | 109 | "VMRS R2,FPSCR;" |
sahilmgandhi | 18:6a4db94011d3 | 110 | "STMDB SP!,{R2,R4};" // Push FPSCR, maintain 8-byte alignment |
sahilmgandhi | 18:6a4db94011d3 | 111 | "VSTMDB SP!,{D0-D15};" |
sahilmgandhi | 18:6a4db94011d3 | 112 | "VSTMDB SP!,{D16-D31};" |
sahilmgandhi | 18:6a4db94011d3 | 113 | : |
sahilmgandhi | 18:6a4db94011d3 | 114 | : "i"(MODE_USR) |
sahilmgandhi | 18:6a4db94011d3 | 115 | : ); |
sahilmgandhi | 18:6a4db94011d3 | 116 | return; |
sahilmgandhi | 18:6a4db94011d3 | 117 | } |
sahilmgandhi | 18:6a4db94011d3 | 118 | |
sahilmgandhi | 18:6a4db94011d3 | 119 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_pop(void) |
sahilmgandhi | 18:6a4db94011d3 | 120 | { |
sahilmgandhi | 18:6a4db94011d3 | 121 | __asm__ volatile ( |
sahilmgandhi | 18:6a4db94011d3 | 122 | ".ARM;" |
sahilmgandhi | 18:6a4db94011d3 | 123 | |
sahilmgandhi | 18:6a4db94011d3 | 124 | "VLDMIA SP!,{D16-D31};" |
sahilmgandhi | 18:6a4db94011d3 | 125 | "VLDMIA SP!,{D0-D15};" |
sahilmgandhi | 18:6a4db94011d3 | 126 | "LDR R2,[SP];" |
sahilmgandhi | 18:6a4db94011d3 | 127 | "VMSR FPSCR,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 128 | "ADD SP,SP,#8;" |
sahilmgandhi | 18:6a4db94011d3 | 129 | : |
sahilmgandhi | 18:6a4db94011d3 | 130 | : "i"(MODE_USR) |
sahilmgandhi | 18:6a4db94011d3 | 131 | : ); |
sahilmgandhi | 18:6a4db94011d3 | 132 | return; |
sahilmgandhi | 18:6a4db94011d3 | 133 | } |
sahilmgandhi | 18:6a4db94011d3 | 134 | |
sahilmgandhi | 18:6a4db94011d3 | 135 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_push(void) |
sahilmgandhi | 18:6a4db94011d3 | 136 | { |
sahilmgandhi | 18:6a4db94011d3 | 137 | __asm__ volatile ( |
sahilmgandhi | 18:6a4db94011d3 | 138 | ".ARM;" |
sahilmgandhi | 18:6a4db94011d3 | 139 | |
sahilmgandhi | 18:6a4db94011d3 | 140 | "VMRS R2,FPSCR;" |
sahilmgandhi | 18:6a4db94011d3 | 141 | "STMDB SP!,{R2,R4};" // Push FPSCR, maintain 8-byte alignment |
sahilmgandhi | 18:6a4db94011d3 | 142 | "VSTMDB SP!,{D0-D15};" |
sahilmgandhi | 18:6a4db94011d3 | 143 | : |
sahilmgandhi | 18:6a4db94011d3 | 144 | : "i"(MODE_USR) |
sahilmgandhi | 18:6a4db94011d3 | 145 | : ); |
sahilmgandhi | 18:6a4db94011d3 | 146 | return; |
sahilmgandhi | 18:6a4db94011d3 | 147 | } |
sahilmgandhi | 18:6a4db94011d3 | 148 | |
sahilmgandhi | 18:6a4db94011d3 | 149 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_pop(void) |
sahilmgandhi | 18:6a4db94011d3 | 150 | { |
sahilmgandhi | 18:6a4db94011d3 | 151 | __asm__ volatile ( |
sahilmgandhi | 18:6a4db94011d3 | 152 | ".ARM;" |
sahilmgandhi | 18:6a4db94011d3 | 153 | |
sahilmgandhi | 18:6a4db94011d3 | 154 | "VLDMIA SP!,{D0-D15};" |
sahilmgandhi | 18:6a4db94011d3 | 155 | "LDR R2,[SP];" |
sahilmgandhi | 18:6a4db94011d3 | 156 | "VMSR FPSCR,R2;" |
sahilmgandhi | 18:6a4db94011d3 | 157 | "ADD SP,SP,#8;" |
sahilmgandhi | 18:6a4db94011d3 | 158 | : |
sahilmgandhi | 18:6a4db94011d3 | 159 | : "i"(MODE_USR) |
sahilmgandhi | 18:6a4db94011d3 | 160 | : ); |
sahilmgandhi | 18:6a4db94011d3 | 161 | return; |
sahilmgandhi | 18:6a4db94011d3 | 162 | } |
sahilmgandhi | 18:6a4db94011d3 | 163 | |
sahilmgandhi | 18:6a4db94011d3 | 164 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 165 | |
sahilmgandhi | 18:6a4db94011d3 | 166 | #endif |