Mouse code for the MacroRat
mbed-dev/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/gic.c@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * @file gic.c |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @version |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @date 19 Sept 2013 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * |
sahilmgandhi | 18:6a4db94011d3 | 7 | * @note |
sahilmgandhi | 18:6a4db94011d3 | 8 | * |
sahilmgandhi | 18:6a4db94011d3 | 9 | ******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 10 | /* Copyright (c) 2011 - 2013 ARM LIMITED |
sahilmgandhi | 18:6a4db94011d3 | 11 | |
sahilmgandhi | 18:6a4db94011d3 | 12 | All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 13 | Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 14 | modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 15 | - Redistributions of source code must retain the above copyright |
sahilmgandhi | 18:6a4db94011d3 | 16 | notice, this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | - Redistributions in binary form must reproduce the above copyright |
sahilmgandhi | 18:6a4db94011d3 | 18 | notice, this list of conditions and the following disclaimer in the |
sahilmgandhi | 18:6a4db94011d3 | 19 | documentation and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 20 | - Neither the name of ARM nor the names of its contributors may be used |
sahilmgandhi | 18:6a4db94011d3 | 21 | to endorse or promote products derived from this software without |
sahilmgandhi | 18:6a4db94011d3 | 22 | specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 23 | * |
sahilmgandhi | 18:6a4db94011d3 | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
sahilmgandhi | 18:6a4db94011d3 | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
sahilmgandhi | 18:6a4db94011d3 | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
sahilmgandhi | 18:6a4db94011d3 | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
sahilmgandhi | 18:6a4db94011d3 | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
sahilmgandhi | 18:6a4db94011d3 | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
sahilmgandhi | 18:6a4db94011d3 | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 34 | POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 35 | ---------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 36 | |
sahilmgandhi | 18:6a4db94011d3 | 37 | #include "MBRZA1H.h" |
sahilmgandhi | 18:6a4db94011d3 | 38 | |
sahilmgandhi | 18:6a4db94011d3 | 39 | #define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */ |
sahilmgandhi | 18:6a4db94011d3 | 40 | #define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */ |
sahilmgandhi | 18:6a4db94011d3 | 41 | |
sahilmgandhi | 18:6a4db94011d3 | 42 | /* Globals for use of post-scatterloading code that must access GIC */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE; |
sahilmgandhi | 18:6a4db94011d3 | 44 | const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE; |
sahilmgandhi | 18:6a4db94011d3 | 45 | |
sahilmgandhi | 18:6a4db94011d3 | 46 | void GIC_EnableDistributor(void) |
sahilmgandhi | 18:6a4db94011d3 | 47 | { |
sahilmgandhi | 18:6a4db94011d3 | 48 | GICDistributor->ICDDCR |= 1; //enable distributor |
sahilmgandhi | 18:6a4db94011d3 | 49 | } |
sahilmgandhi | 18:6a4db94011d3 | 50 | |
sahilmgandhi | 18:6a4db94011d3 | 51 | void GIC_DisableDistributor(void) |
sahilmgandhi | 18:6a4db94011d3 | 52 | { |
sahilmgandhi | 18:6a4db94011d3 | 53 | GICDistributor->ICDDCR &=~1; //disable distributor |
sahilmgandhi | 18:6a4db94011d3 | 54 | } |
sahilmgandhi | 18:6a4db94011d3 | 55 | |
sahilmgandhi | 18:6a4db94011d3 | 56 | uint32_t GIC_DistributorInfo(void) |
sahilmgandhi | 18:6a4db94011d3 | 57 | { |
sahilmgandhi | 18:6a4db94011d3 | 58 | return (uint32_t)(GICDistributor->ICDICTR); |
sahilmgandhi | 18:6a4db94011d3 | 59 | } |
sahilmgandhi | 18:6a4db94011d3 | 60 | |
sahilmgandhi | 18:6a4db94011d3 | 61 | uint32_t GIC_DistributorImplementer(void) |
sahilmgandhi | 18:6a4db94011d3 | 62 | { |
sahilmgandhi | 18:6a4db94011d3 | 63 | return (uint32_t)(GICDistributor->ICDIIDR); |
sahilmgandhi | 18:6a4db94011d3 | 64 | } |
sahilmgandhi | 18:6a4db94011d3 | 65 | |
sahilmgandhi | 18:6a4db94011d3 | 66 | void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) |
sahilmgandhi | 18:6a4db94011d3 | 67 | { |
sahilmgandhi | 18:6a4db94011d3 | 68 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); |
sahilmgandhi | 18:6a4db94011d3 | 69 | field += IRQn % 4; |
sahilmgandhi | 18:6a4db94011d3 | 70 | *field = (uint8_t)cpu_target & 0xf; |
sahilmgandhi | 18:6a4db94011d3 | 71 | } |
sahilmgandhi | 18:6a4db94011d3 | 72 | |
sahilmgandhi | 18:6a4db94011d3 | 73 | void GIC_SetICDICFR (const uint32_t *ICDICFRn) |
sahilmgandhi | 18:6a4db94011d3 | 74 | { |
sahilmgandhi | 18:6a4db94011d3 | 75 | uint32_t i, num_irq; |
sahilmgandhi | 18:6a4db94011d3 | 76 | |
sahilmgandhi | 18:6a4db94011d3 | 77 | //Get the maximum number of interrupts that the GIC supports |
sahilmgandhi | 18:6a4db94011d3 | 78 | num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); |
sahilmgandhi | 18:6a4db94011d3 | 79 | |
sahilmgandhi | 18:6a4db94011d3 | 80 | for (i = 0; i < (num_irq/16); i++) |
sahilmgandhi | 18:6a4db94011d3 | 81 | { |
sahilmgandhi | 18:6a4db94011d3 | 82 | GICDistributor->ICDISPR[i] = *ICDICFRn++; |
sahilmgandhi | 18:6a4db94011d3 | 83 | } |
sahilmgandhi | 18:6a4db94011d3 | 84 | } |
sahilmgandhi | 18:6a4db94011d3 | 85 | |
sahilmgandhi | 18:6a4db94011d3 | 86 | uint32_t GIC_GetTarget(IRQn_Type IRQn) |
sahilmgandhi | 18:6a4db94011d3 | 87 | { |
sahilmgandhi | 18:6a4db94011d3 | 88 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); |
sahilmgandhi | 18:6a4db94011d3 | 89 | field += IRQn % 4; |
sahilmgandhi | 18:6a4db94011d3 | 90 | return ((uint32_t)*field & 0xf); |
sahilmgandhi | 18:6a4db94011d3 | 91 | } |
sahilmgandhi | 18:6a4db94011d3 | 92 | |
sahilmgandhi | 18:6a4db94011d3 | 93 | void GIC_EnableInterface(void) |
sahilmgandhi | 18:6a4db94011d3 | 94 | { |
sahilmgandhi | 18:6a4db94011d3 | 95 | GICInterface->ICCICR |= 1; //enable interface |
sahilmgandhi | 18:6a4db94011d3 | 96 | } |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | void GIC_DisableInterface(void) |
sahilmgandhi | 18:6a4db94011d3 | 99 | { |
sahilmgandhi | 18:6a4db94011d3 | 100 | GICInterface->ICCICR &=~1; //disable distributor |
sahilmgandhi | 18:6a4db94011d3 | 101 | } |
sahilmgandhi | 18:6a4db94011d3 | 102 | |
sahilmgandhi | 18:6a4db94011d3 | 103 | IRQn_Type GIC_AcknowledgePending(void) |
sahilmgandhi | 18:6a4db94011d3 | 104 | { |
sahilmgandhi | 18:6a4db94011d3 | 105 | return (IRQn_Type)(GICInterface->ICCIAR); |
sahilmgandhi | 18:6a4db94011d3 | 106 | } |
sahilmgandhi | 18:6a4db94011d3 | 107 | |
sahilmgandhi | 18:6a4db94011d3 | 108 | void GIC_EndInterrupt(IRQn_Type IRQn) |
sahilmgandhi | 18:6a4db94011d3 | 109 | { |
sahilmgandhi | 18:6a4db94011d3 | 110 | GICInterface->ICCEOIR = IRQn; |
sahilmgandhi | 18:6a4db94011d3 | 111 | } |
sahilmgandhi | 18:6a4db94011d3 | 112 | |
sahilmgandhi | 18:6a4db94011d3 | 113 | void GIC_EnableIRQ(IRQn_Type IRQn) |
sahilmgandhi | 18:6a4db94011d3 | 114 | { |
sahilmgandhi | 18:6a4db94011d3 | 115 | GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32); |
sahilmgandhi | 18:6a4db94011d3 | 116 | } |
sahilmgandhi | 18:6a4db94011d3 | 117 | |
sahilmgandhi | 18:6a4db94011d3 | 118 | void GIC_DisableIRQ(IRQn_Type IRQn) |
sahilmgandhi | 18:6a4db94011d3 | 119 | { |
sahilmgandhi | 18:6a4db94011d3 | 120 | GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32); |
sahilmgandhi | 18:6a4db94011d3 | 121 | } |
sahilmgandhi | 18:6a4db94011d3 | 122 | |
sahilmgandhi | 18:6a4db94011d3 | 123 | void GIC_SetPendingIRQ(IRQn_Type IRQn) |
sahilmgandhi | 18:6a4db94011d3 | 124 | { |
sahilmgandhi | 18:6a4db94011d3 | 125 | GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32); |
sahilmgandhi | 18:6a4db94011d3 | 126 | } |
sahilmgandhi | 18:6a4db94011d3 | 127 | |
sahilmgandhi | 18:6a4db94011d3 | 128 | void GIC_ClearPendingIRQ(IRQn_Type IRQn) |
sahilmgandhi | 18:6a4db94011d3 | 129 | { |
sahilmgandhi | 18:6a4db94011d3 | 130 | GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32); |
sahilmgandhi | 18:6a4db94011d3 | 131 | } |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model) |
sahilmgandhi | 18:6a4db94011d3 | 134 | { |
sahilmgandhi | 18:6a4db94011d3 | 135 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]); |
sahilmgandhi | 18:6a4db94011d3 | 136 | int bit_shift = (IRQn % 16)<<1; |
sahilmgandhi | 18:6a4db94011d3 | 137 | uint8_t save_byte; |
sahilmgandhi | 18:6a4db94011d3 | 138 | |
sahilmgandhi | 18:6a4db94011d3 | 139 | field += (bit_shift / 8); |
sahilmgandhi | 18:6a4db94011d3 | 140 | bit_shift %= 8; |
sahilmgandhi | 18:6a4db94011d3 | 141 | |
sahilmgandhi | 18:6a4db94011d3 | 142 | save_byte = *field; |
sahilmgandhi | 18:6a4db94011d3 | 143 | save_byte &= ((uint8_t)~(3u << bit_shift)); |
sahilmgandhi | 18:6a4db94011d3 | 144 | |
sahilmgandhi | 18:6a4db94011d3 | 145 | *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift); |
sahilmgandhi | 18:6a4db94011d3 | 146 | } |
sahilmgandhi | 18:6a4db94011d3 | 147 | |
sahilmgandhi | 18:6a4db94011d3 | 148 | void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
sahilmgandhi | 18:6a4db94011d3 | 149 | { |
sahilmgandhi | 18:6a4db94011d3 | 150 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); |
sahilmgandhi | 18:6a4db94011d3 | 151 | field += (IRQn % 4); |
sahilmgandhi | 18:6a4db94011d3 | 152 | *field = (uint8_t)priority; |
sahilmgandhi | 18:6a4db94011d3 | 153 | } |
sahilmgandhi | 18:6a4db94011d3 | 154 | |
sahilmgandhi | 18:6a4db94011d3 | 155 | uint32_t GIC_GetPriority(IRQn_Type IRQn) |
sahilmgandhi | 18:6a4db94011d3 | 156 | { |
sahilmgandhi | 18:6a4db94011d3 | 157 | volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); |
sahilmgandhi | 18:6a4db94011d3 | 158 | field += (IRQn % 4); |
sahilmgandhi | 18:6a4db94011d3 | 159 | return (uint32_t)*field; |
sahilmgandhi | 18:6a4db94011d3 | 160 | } |
sahilmgandhi | 18:6a4db94011d3 | 161 | |
sahilmgandhi | 18:6a4db94011d3 | 162 | void GIC_InterfacePriorityMask(uint32_t priority) |
sahilmgandhi | 18:6a4db94011d3 | 163 | { |
sahilmgandhi | 18:6a4db94011d3 | 164 | GICInterface->ICCPMR = priority & 0xff; //set priority mask |
sahilmgandhi | 18:6a4db94011d3 | 165 | } |
sahilmgandhi | 18:6a4db94011d3 | 166 | |
sahilmgandhi | 18:6a4db94011d3 | 167 | void GIC_SetBinaryPoint(uint32_t binary_point) |
sahilmgandhi | 18:6a4db94011d3 | 168 | { |
sahilmgandhi | 18:6a4db94011d3 | 169 | GICInterface->ICCBPR = binary_point & 0x07; //set binary point |
sahilmgandhi | 18:6a4db94011d3 | 170 | } |
sahilmgandhi | 18:6a4db94011d3 | 171 | |
sahilmgandhi | 18:6a4db94011d3 | 172 | uint32_t GIC_GetBinaryPoint(uint32_t binary_point) |
sahilmgandhi | 18:6a4db94011d3 | 173 | { |
sahilmgandhi | 18:6a4db94011d3 | 174 | return (uint32_t)GICInterface->ICCBPR; |
sahilmgandhi | 18:6a4db94011d3 | 175 | } |
sahilmgandhi | 18:6a4db94011d3 | 176 | |
sahilmgandhi | 18:6a4db94011d3 | 177 | uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) |
sahilmgandhi | 18:6a4db94011d3 | 178 | { |
sahilmgandhi | 18:6a4db94011d3 | 179 | uint32_t pending, active; |
sahilmgandhi | 18:6a4db94011d3 | 180 | |
sahilmgandhi | 18:6a4db94011d3 | 181 | active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 182 | pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 183 | |
sahilmgandhi | 18:6a4db94011d3 | 184 | return ((active<<1) | pending); |
sahilmgandhi | 18:6a4db94011d3 | 185 | } |
sahilmgandhi | 18:6a4db94011d3 | 186 | |
sahilmgandhi | 18:6a4db94011d3 | 187 | void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) |
sahilmgandhi | 18:6a4db94011d3 | 188 | { |
sahilmgandhi | 18:6a4db94011d3 | 189 | GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf); |
sahilmgandhi | 18:6a4db94011d3 | 190 | } |
sahilmgandhi | 18:6a4db94011d3 | 191 | |
sahilmgandhi | 18:6a4db94011d3 | 192 | void GIC_DistInit(void) |
sahilmgandhi | 18:6a4db94011d3 | 193 | { |
sahilmgandhi | 18:6a4db94011d3 | 194 | //IRQn_Type i; |
sahilmgandhi | 18:6a4db94011d3 | 195 | uint32_t i; |
sahilmgandhi | 18:6a4db94011d3 | 196 | uint32_t num_irq = 0; |
sahilmgandhi | 18:6a4db94011d3 | 197 | uint32_t priority_field; |
sahilmgandhi | 18:6a4db94011d3 | 198 | |
sahilmgandhi | 18:6a4db94011d3 | 199 | //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, |
sahilmgandhi | 18:6a4db94011d3 | 200 | //configuring all of the interrupts as Secure. |
sahilmgandhi | 18:6a4db94011d3 | 201 | |
sahilmgandhi | 18:6a4db94011d3 | 202 | //Disable interrupt forwarding |
sahilmgandhi | 18:6a4db94011d3 | 203 | GIC_DisableDistributor(); |
sahilmgandhi | 18:6a4db94011d3 | 204 | //Get the maximum number of interrupts that the GIC supports |
sahilmgandhi | 18:6a4db94011d3 | 205 | num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); |
sahilmgandhi | 18:6a4db94011d3 | 206 | |
sahilmgandhi | 18:6a4db94011d3 | 207 | /* Priority level is implementation defined. |
sahilmgandhi | 18:6a4db94011d3 | 208 | To determine the number of priority bits implemented write 0xFF to an ICDIPR |
sahilmgandhi | 18:6a4db94011d3 | 209 | priority field and read back the value stored.*/ |
sahilmgandhi | 18:6a4db94011d3 | 210 | GIC_SetPriority((IRQn_Type)0, 0xff); |
sahilmgandhi | 18:6a4db94011d3 | 211 | priority_field = GIC_GetPriority((IRQn_Type)0); |
sahilmgandhi | 18:6a4db94011d3 | 212 | |
sahilmgandhi | 18:6a4db94011d3 | 213 | for (i = 32; i < num_irq; i++) |
sahilmgandhi | 18:6a4db94011d3 | 214 | { |
sahilmgandhi | 18:6a4db94011d3 | 215 | //Disable all SPI the interrupts |
sahilmgandhi | 18:6a4db94011d3 | 216 | GIC_DisableIRQ((IRQn_Type)i); |
sahilmgandhi | 18:6a4db94011d3 | 217 | //Set level-sensitive and N-N model |
sahilmgandhi | 18:6a4db94011d3 | 218 | //GIC_SetLevelModel(i, 0, 0); |
sahilmgandhi | 18:6a4db94011d3 | 219 | //Set priority |
sahilmgandhi | 18:6a4db94011d3 | 220 | GIC_SetPriority((IRQn_Type)i, priority_field/2); |
sahilmgandhi | 18:6a4db94011d3 | 221 | //Set target list to "all cpus" |
sahilmgandhi | 18:6a4db94011d3 | 222 | GIC_SetTarget((IRQn_Type)i, 0xff); |
sahilmgandhi | 18:6a4db94011d3 | 223 | } |
sahilmgandhi | 18:6a4db94011d3 | 224 | /* Set level-edge and 1-N model */ |
sahilmgandhi | 18:6a4db94011d3 | 225 | /* GICDistributor->ICDICFR[ 0] is read only */ |
sahilmgandhi | 18:6a4db94011d3 | 226 | GICDistributor->ICDICFR[ 1] = 0x00000055; |
sahilmgandhi | 18:6a4db94011d3 | 227 | GICDistributor->ICDICFR[ 2] = 0xFFFD5555; |
sahilmgandhi | 18:6a4db94011d3 | 228 | GICDistributor->ICDICFR[ 3] = 0x555FFFFF; |
sahilmgandhi | 18:6a4db94011d3 | 229 | GICDistributor->ICDICFR[ 4] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 230 | GICDistributor->ICDICFR[ 5] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 231 | GICDistributor->ICDICFR[ 6] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 232 | GICDistributor->ICDICFR[ 7] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 233 | GICDistributor->ICDICFR[ 8] = 0x5555F555; |
sahilmgandhi | 18:6a4db94011d3 | 234 | GICDistributor->ICDICFR[ 9] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 235 | GICDistributor->ICDICFR[10] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 236 | GICDistributor->ICDICFR[11] = 0xF5555555; |
sahilmgandhi | 18:6a4db94011d3 | 237 | GICDistributor->ICDICFR[12] = 0xF555F555; |
sahilmgandhi | 18:6a4db94011d3 | 238 | GICDistributor->ICDICFR[13] = 0x5555F555; |
sahilmgandhi | 18:6a4db94011d3 | 239 | GICDistributor->ICDICFR[14] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 240 | GICDistributor->ICDICFR[15] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 241 | GICDistributor->ICDICFR[16] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 242 | GICDistributor->ICDICFR[17] = 0xFD555555; |
sahilmgandhi | 18:6a4db94011d3 | 243 | GICDistributor->ICDICFR[18] = 0x55555557; |
sahilmgandhi | 18:6a4db94011d3 | 244 | GICDistributor->ICDICFR[19] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 245 | GICDistributor->ICDICFR[20] = 0xFFD55555; |
sahilmgandhi | 18:6a4db94011d3 | 246 | GICDistributor->ICDICFR[21] = 0x5F55557F; |
sahilmgandhi | 18:6a4db94011d3 | 247 | GICDistributor->ICDICFR[22] = 0xFD55555F; |
sahilmgandhi | 18:6a4db94011d3 | 248 | GICDistributor->ICDICFR[23] = 0x55555557; |
sahilmgandhi | 18:6a4db94011d3 | 249 | GICDistributor->ICDICFR[24] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 250 | GICDistributor->ICDICFR[25] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 251 | GICDistributor->ICDICFR[26] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 252 | GICDistributor->ICDICFR[27] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 253 | GICDistributor->ICDICFR[28] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 254 | GICDistributor->ICDICFR[29] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 255 | GICDistributor->ICDICFR[30] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 256 | GICDistributor->ICDICFR[31] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 257 | GICDistributor->ICDICFR[32] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 258 | GICDistributor->ICDICFR[33] = 0x55555555; |
sahilmgandhi | 18:6a4db94011d3 | 259 | |
sahilmgandhi | 18:6a4db94011d3 | 260 | //Enable distributor |
sahilmgandhi | 18:6a4db94011d3 | 261 | GIC_EnableDistributor(); |
sahilmgandhi | 18:6a4db94011d3 | 262 | } |
sahilmgandhi | 18:6a4db94011d3 | 263 | |
sahilmgandhi | 18:6a4db94011d3 | 264 | void GIC_CPUInterfaceInit(void) |
sahilmgandhi | 18:6a4db94011d3 | 265 | { |
sahilmgandhi | 18:6a4db94011d3 | 266 | IRQn_Type i; |
sahilmgandhi | 18:6a4db94011d3 | 267 | uint32_t priority_field; |
sahilmgandhi | 18:6a4db94011d3 | 268 | |
sahilmgandhi | 18:6a4db94011d3 | 269 | //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, |
sahilmgandhi | 18:6a4db94011d3 | 270 | //configuring all of the interrupts as Secure. |
sahilmgandhi | 18:6a4db94011d3 | 271 | |
sahilmgandhi | 18:6a4db94011d3 | 272 | //Disable interrupt forwarding |
sahilmgandhi | 18:6a4db94011d3 | 273 | GIC_DisableInterface(); |
sahilmgandhi | 18:6a4db94011d3 | 274 | |
sahilmgandhi | 18:6a4db94011d3 | 275 | /* Priority level is implementation defined. |
sahilmgandhi | 18:6a4db94011d3 | 276 | To determine the number of priority bits implemented write 0xFF to an ICDIPR |
sahilmgandhi | 18:6a4db94011d3 | 277 | priority field and read back the value stored.*/ |
sahilmgandhi | 18:6a4db94011d3 | 278 | GIC_SetPriority((IRQn_Type)0, 0xff); |
sahilmgandhi | 18:6a4db94011d3 | 279 | priority_field = GIC_GetPriority((IRQn_Type)0); |
sahilmgandhi | 18:6a4db94011d3 | 280 | |
sahilmgandhi | 18:6a4db94011d3 | 281 | //SGI and PPI |
sahilmgandhi | 18:6a4db94011d3 | 282 | for (i = (IRQn_Type)0; i < 32; i++) |
sahilmgandhi | 18:6a4db94011d3 | 283 | { |
sahilmgandhi | 18:6a4db94011d3 | 284 | //Set level-sensitive and N-N model for PPI |
sahilmgandhi | 18:6a4db94011d3 | 285 | //if(i > 15) |
sahilmgandhi | 18:6a4db94011d3 | 286 | //GIC_SetLevelModel(i, 0, 0); |
sahilmgandhi | 18:6a4db94011d3 | 287 | //Disable SGI and PPI interrupts |
sahilmgandhi | 18:6a4db94011d3 | 288 | GIC_DisableIRQ(i); |
sahilmgandhi | 18:6a4db94011d3 | 289 | //Set priority |
sahilmgandhi | 18:6a4db94011d3 | 290 | GIC_SetPriority(i, priority_field/2); |
sahilmgandhi | 18:6a4db94011d3 | 291 | } |
sahilmgandhi | 18:6a4db94011d3 | 292 | //Enable interface |
sahilmgandhi | 18:6a4db94011d3 | 293 | GIC_EnableInterface(); |
sahilmgandhi | 18:6a4db94011d3 | 294 | //Set binary point to 0 |
sahilmgandhi | 18:6a4db94011d3 | 295 | GIC_SetBinaryPoint(0); |
sahilmgandhi | 18:6a4db94011d3 | 296 | //Set priority mask |
sahilmgandhi | 18:6a4db94011d3 | 297 | GIC_InterfacePriorityMask(0xff); |
sahilmgandhi | 18:6a4db94011d3 | 298 | } |
sahilmgandhi | 18:6a4db94011d3 | 299 | |
sahilmgandhi | 18:6a4db94011d3 | 300 | void GIC_Enable(void) |
sahilmgandhi | 18:6a4db94011d3 | 301 | { |
sahilmgandhi | 18:6a4db94011d3 | 302 | GIC_DistInit(); |
sahilmgandhi | 18:6a4db94011d3 | 303 | GIC_CPUInterfaceInit(); //per CPU |
sahilmgandhi | 18:6a4db94011d3 | 304 | } |
sahilmgandhi | 18:6a4db94011d3 | 305 |