MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * DISCLAIMER
sahilmgandhi 18:6a4db94011d3 3 * This software is supplied by Renesas Electronics Corporation and is only
sahilmgandhi 18:6a4db94011d3 4 * intended for use with Renesas products. No other uses are authorized. This
sahilmgandhi 18:6a4db94011d3 5 * software is owned by Renesas Electronics Corporation and is protected under
sahilmgandhi 18:6a4db94011d3 6 * all applicable laws, including copyright laws.
sahilmgandhi 18:6a4db94011d3 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
sahilmgandhi 18:6a4db94011d3 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
sahilmgandhi 18:6a4db94011d3 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
sahilmgandhi 18:6a4db94011d3 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
sahilmgandhi 18:6a4db94011d3 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
sahilmgandhi 18:6a4db94011d3 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
sahilmgandhi 18:6a4db94011d3 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
sahilmgandhi 18:6a4db94011d3 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
sahilmgandhi 18:6a4db94011d3 16 * Renesas reserves the right, without notice, to make changes to this software
sahilmgandhi 18:6a4db94011d3 17 * and to discontinue the availability of this software. By using this software,
sahilmgandhi 18:6a4db94011d3 18 * you agree to the additional terms and conditions found by accessing the
sahilmgandhi 18:6a4db94011d3 19 * following link:
sahilmgandhi 18:6a4db94011d3 20 * http://www.renesas.com/disclaimer
sahilmgandhi 18:6a4db94011d3 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
sahilmgandhi 18:6a4db94011d3 22 *******************************************************************************/
sahilmgandhi 18:6a4db94011d3 23 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 24 * @file MBRZA1H.h
sahilmgandhi 18:6a4db94011d3 25 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for
sahilmgandhi 18:6a4db94011d3 26 * Renesas MBRZA1H Device Series
sahilmgandhi 18:6a4db94011d3 27 * @version
sahilmgandhi 18:6a4db94011d3 28 * @date 19 Sept 2013
sahilmgandhi 18:6a4db94011d3 29 *
sahilmgandhi 18:6a4db94011d3 30 * @note
sahilmgandhi 18:6a4db94011d3 31 *
sahilmgandhi 18:6a4db94011d3 32 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #ifndef __MBRZA1H_H__
sahilmgandhi 18:6a4db94011d3 35 #define __MBRZA1H_H__
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 38 extern "C" {
sahilmgandhi 18:6a4db94011d3 39 #endif
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 /* ------------------------- Interrupt Number Definition ------------------------ */
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 typedef enum IRQn
sahilmgandhi 18:6a4db94011d3 45 {
sahilmgandhi 18:6a4db94011d3 46 /****** SGI Interrupts Numbers ****************************************/
sahilmgandhi 18:6a4db94011d3 47 SGI0_IRQn = 0,
sahilmgandhi 18:6a4db94011d3 48 SGI1_IRQn = 1,
sahilmgandhi 18:6a4db94011d3 49 SGI2_IRQn = 2,
sahilmgandhi 18:6a4db94011d3 50 SGI3_IRQn = 3,
sahilmgandhi 18:6a4db94011d3 51 SGI4_IRQn = 4,
sahilmgandhi 18:6a4db94011d3 52 SGI5_IRQn = 5,
sahilmgandhi 18:6a4db94011d3 53 SGI6_IRQn = 6,
sahilmgandhi 18:6a4db94011d3 54 SGI7_IRQn = 7,
sahilmgandhi 18:6a4db94011d3 55 SGI8_IRQn = 8,
sahilmgandhi 18:6a4db94011d3 56 SGI9_IRQn = 9,
sahilmgandhi 18:6a4db94011d3 57 SGI10_IRQn = 10,
sahilmgandhi 18:6a4db94011d3 58 SGI11_IRQn = 11,
sahilmgandhi 18:6a4db94011d3 59 SGI12_IRQn = 12,
sahilmgandhi 18:6a4db94011d3 60 SGI13_IRQn = 13,
sahilmgandhi 18:6a4db94011d3 61 SGI14_IRQn = 14,
sahilmgandhi 18:6a4db94011d3 62 SGI15_IRQn = 15,
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /****** Cortex-A9 Processor Exceptions Numbers ****************************************/
sahilmgandhi 18:6a4db94011d3 65 /* 16 - 578 */
sahilmgandhi 18:6a4db94011d3 66 PMUIRQ0_IRQn = 16,
sahilmgandhi 18:6a4db94011d3 67 COMMRX0_IRQn = 17,
sahilmgandhi 18:6a4db94011d3 68 COMMTX0_IRQn = 18,
sahilmgandhi 18:6a4db94011d3 69 CTIIRQ0_IRQn = 19,
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 IRQ0_IRQn = 32,
sahilmgandhi 18:6a4db94011d3 72 IRQ1_IRQn = 33,
sahilmgandhi 18:6a4db94011d3 73 IRQ2_IRQn = 34,
sahilmgandhi 18:6a4db94011d3 74 IRQ3_IRQn = 35,
sahilmgandhi 18:6a4db94011d3 75 IRQ4_IRQn = 36,
sahilmgandhi 18:6a4db94011d3 76 IRQ5_IRQn = 37,
sahilmgandhi 18:6a4db94011d3 77 IRQ6_IRQn = 38,
sahilmgandhi 18:6a4db94011d3 78 IRQ7_IRQn = 39,
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 PL310ERR_IRQn = 40,
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 83 DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 84 DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 85 DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 86 DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 87 DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 88 DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 89 DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 90 DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 91 DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 92 DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 93 DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 94 DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 95 DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 96 DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 97 DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 98 DMAERR_IRQn = 57, /*!< DMAC Interrupt */
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /* 58-72 Reserved */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 USBI0_IRQn = 73,
sahilmgandhi 18:6a4db94011d3 103 USBI1_IRQn = 74,
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 S0_VI_VSYNC0_IRQn = 75,
sahilmgandhi 18:6a4db94011d3 106 S0_LO_VSYNC0_IRQn = 76,
sahilmgandhi 18:6a4db94011d3 107 S0_VSYNCERR0_IRQn = 77,
sahilmgandhi 18:6a4db94011d3 108 GR3_VLINE0_IRQn = 78,
sahilmgandhi 18:6a4db94011d3 109 S0_VFIELD0_IRQn = 79,
sahilmgandhi 18:6a4db94011d3 110 IV1_VBUFERR0_IRQn = 80,
sahilmgandhi 18:6a4db94011d3 111 IV3_VBUFERR0_IRQn = 81,
sahilmgandhi 18:6a4db94011d3 112 IV5_VBUFERR0_IRQn = 82,
sahilmgandhi 18:6a4db94011d3 113 IV6_VBUFERR0_IRQn = 83,
sahilmgandhi 18:6a4db94011d3 114 S0_WLINE0_IRQn = 84,
sahilmgandhi 18:6a4db94011d3 115 S1_VI_VSYNC0_IRQn = 85,
sahilmgandhi 18:6a4db94011d3 116 S1_LO_VSYNC0_IRQn = 86,
sahilmgandhi 18:6a4db94011d3 117 S1_VSYNCERR0_IRQn = 87,
sahilmgandhi 18:6a4db94011d3 118 S1_VFIELD0_IRQn = 88,
sahilmgandhi 18:6a4db94011d3 119 IV2_VBUFERR0_IRQn = 89,
sahilmgandhi 18:6a4db94011d3 120 IV4_VBUFERR0_IRQn = 90,
sahilmgandhi 18:6a4db94011d3 121 S1_WLINE0_IRQn = 91,
sahilmgandhi 18:6a4db94011d3 122 OIR_VI_VSYNC0_IRQn = 92,
sahilmgandhi 18:6a4db94011d3 123 OIR_LO_VSYNC0_IRQn = 93,
sahilmgandhi 18:6a4db94011d3 124 OIR_VSYNCERR0_IRQn = 94,
sahilmgandhi 18:6a4db94011d3 125 OIR_VFIELD0_IRQn = 95,
sahilmgandhi 18:6a4db94011d3 126 IV7_VBUFERR0_IRQn = 96,
sahilmgandhi 18:6a4db94011d3 127 IV8_VBUFERR0_IRQn = 97,
sahilmgandhi 18:6a4db94011d3 128 /* 98 Reserved */
sahilmgandhi 18:6a4db94011d3 129 S0_VI_VSYNC1_IRQn = 99,
sahilmgandhi 18:6a4db94011d3 130 S0_LO_VSYNC1_IRQn = 100,
sahilmgandhi 18:6a4db94011d3 131 S0_VSYNCERR1_IRQn = 101,
sahilmgandhi 18:6a4db94011d3 132 GR3_VLINE1_IRQn = 102,
sahilmgandhi 18:6a4db94011d3 133 S0_VFIELD1_IRQn = 103,
sahilmgandhi 18:6a4db94011d3 134 IV1_VBUFERR1_IRQn = 104,
sahilmgandhi 18:6a4db94011d3 135 IV3_VBUFERR1_IRQn = 105,
sahilmgandhi 18:6a4db94011d3 136 IV5_VBUFERR1_IRQn = 106,
sahilmgandhi 18:6a4db94011d3 137 IV6_VBUFERR1_IRQn = 107,
sahilmgandhi 18:6a4db94011d3 138 S0_WLINE1_IRQn = 108,
sahilmgandhi 18:6a4db94011d3 139 S1_VI_VSYNC1_IRQn = 109,
sahilmgandhi 18:6a4db94011d3 140 S1_LO_VSYNC1_IRQn = 110,
sahilmgandhi 18:6a4db94011d3 141 S1_VSYNCERR1_IRQn = 111,
sahilmgandhi 18:6a4db94011d3 142 S1_VFIELD1_IRQn = 112,
sahilmgandhi 18:6a4db94011d3 143 IV2_VBUFERR1_IRQn = 113,
sahilmgandhi 18:6a4db94011d3 144 IV4_VBUFERR1_IRQn = 114,
sahilmgandhi 18:6a4db94011d3 145 S1_WLINE1_IRQn = 115,
sahilmgandhi 18:6a4db94011d3 146 OIR_VI_VSYNC1_IRQn = 116,
sahilmgandhi 18:6a4db94011d3 147 OIR_LO_VSYNC1_IRQn = 117,
sahilmgandhi 18:6a4db94011d3 148 OIR_VSYNCERR1_IRQn = 118,
sahilmgandhi 18:6a4db94011d3 149 OIR_VFIELD1_IRQn = 119,
sahilmgandhi 18:6a4db94011d3 150 IV7_VBUFERR1_IRQn = 120,
sahilmgandhi 18:6a4db94011d3 151 IV8_VBUFERR1_IRQn = 121,
sahilmgandhi 18:6a4db94011d3 152 /* Reserved = 122 */
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 IMRDI_IRQn = 123,
sahilmgandhi 18:6a4db94011d3 155 IMR2I0_IRQn = 124,
sahilmgandhi 18:6a4db94011d3 156 IMR2I1_IRQn = 125,
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 JEDI_IRQn = 126,
sahilmgandhi 18:6a4db94011d3 159 JDTI_IRQn = 127,
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 CMP0_IRQn = 128,
sahilmgandhi 18:6a4db94011d3 162 CMP1_IRQn = 129,
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 INT0_IRQn = 130,
sahilmgandhi 18:6a4db94011d3 165 INT1_IRQn = 131,
sahilmgandhi 18:6a4db94011d3 166 INT2_IRQn = 132,
sahilmgandhi 18:6a4db94011d3 167 INT3_IRQn = 133,
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
sahilmgandhi 18:6a4db94011d3 170 OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 CMI_IRQn = 136,
sahilmgandhi 18:6a4db94011d3 173 WTOUT_IRQn = 137,
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 ITI_IRQn = 138,
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 TGI0A_IRQn = 139,
sahilmgandhi 18:6a4db94011d3 178 TGI0B_IRQn = 140,
sahilmgandhi 18:6a4db94011d3 179 TGI0C_IRQn = 141,
sahilmgandhi 18:6a4db94011d3 180 TGI0D_IRQn = 142,
sahilmgandhi 18:6a4db94011d3 181 TGI0V_IRQn = 143,
sahilmgandhi 18:6a4db94011d3 182 TGI0E_IRQn = 144,
sahilmgandhi 18:6a4db94011d3 183 TGI0F_IRQn = 145,
sahilmgandhi 18:6a4db94011d3 184 TGI1A_IRQn = 146,
sahilmgandhi 18:6a4db94011d3 185 TGI1B_IRQn = 147,
sahilmgandhi 18:6a4db94011d3 186 TGI1V_IRQn = 148,
sahilmgandhi 18:6a4db94011d3 187 TGI1U_IRQn = 149,
sahilmgandhi 18:6a4db94011d3 188 TGI2A_IRQn = 150,
sahilmgandhi 18:6a4db94011d3 189 TGI2B_IRQn = 151,
sahilmgandhi 18:6a4db94011d3 190 TGI2V_IRQn = 152,
sahilmgandhi 18:6a4db94011d3 191 TGI2U_IRQn = 153,
sahilmgandhi 18:6a4db94011d3 192 TGI3A_IRQn = 154,
sahilmgandhi 18:6a4db94011d3 193 TGI3B_IRQn = 155,
sahilmgandhi 18:6a4db94011d3 194 TGI3C_IRQn = 156,
sahilmgandhi 18:6a4db94011d3 195 TGI3D_IRQn = 157,
sahilmgandhi 18:6a4db94011d3 196 TGI3V_IRQn = 158,
sahilmgandhi 18:6a4db94011d3 197 TGI4A_IRQn = 159,
sahilmgandhi 18:6a4db94011d3 198 TGI4B_IRQn = 160,
sahilmgandhi 18:6a4db94011d3 199 TGI4C_IRQn = 161,
sahilmgandhi 18:6a4db94011d3 200 TGI4D_IRQn = 162,
sahilmgandhi 18:6a4db94011d3 201 TGI4V_IRQn = 163,
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 CMI1_IRQn = 164,
sahilmgandhi 18:6a4db94011d3 204 CMI2_IRQn = 165,
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 SGDEI0_IRQn = 166,
sahilmgandhi 18:6a4db94011d3 207 SGDEI1_IRQn = 167,
sahilmgandhi 18:6a4db94011d3 208 SGDEI2_IRQn = 168,
sahilmgandhi 18:6a4db94011d3 209 SGDEI3_IRQn = 169,
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 ADI_IRQn = 170,
sahilmgandhi 18:6a4db94011d3 212 LMTI_IRQn = 171,
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 SSII0_IRQn = 172, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 215 SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 216 SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 217 SSII1_IRQn = 175, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 218 SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 219 SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 220 SSII2_IRQn = 178, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 221 SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 222 SSII3_IRQn = 180, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 223 SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 224 SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 225 SSII4_IRQn = 183, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 226 SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 227 SSII5_IRQn = 185, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 228 SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 229 SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 SPDIFI_IRQn = 188,
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 234 INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 235 INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 236 INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 237 INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 238 INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 239 INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 240 INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 241 INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 242 INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 243 INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 244 INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 245 INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 246 INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 247 INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 248 INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 249 INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 250 INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 251 INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 252 INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 253 INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 254 INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 255 INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 256 INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 257 INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 258 INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 259 INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 260 INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 261 INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 262 INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 263 INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 264 INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 267 SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 268 SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 269 SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 270 SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 271 SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 272 SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 273 SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 274 SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 275 SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 276 SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 277 SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 278 SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 279 SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 280 SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 281 SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 282 SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 283 SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 284 SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 285 SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 286 SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 287 SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 288 SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 289 SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 290 SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 291 SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 292 SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 293 SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 294 SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 295 SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 296 SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 297 SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 INTRCANGERR_IRQn = 253,
sahilmgandhi 18:6a4db94011d3 300 INTRCANGRECC_IRQn = 254,
sahilmgandhi 18:6a4db94011d3 301 INTRCAN0REC_IRQn = 255,
sahilmgandhi 18:6a4db94011d3 302 INTRCAN0ERR_IRQn = 256,
sahilmgandhi 18:6a4db94011d3 303 INTRCAN0TRX_IRQn = 257,
sahilmgandhi 18:6a4db94011d3 304 INTRCAN1REC_IRQn = 258,
sahilmgandhi 18:6a4db94011d3 305 INTRCAN1ERR_IRQn = 259,
sahilmgandhi 18:6a4db94011d3 306 INTRCAN1TRX_IRQn = 260,
sahilmgandhi 18:6a4db94011d3 307 INTRCAN2REC_IRQn = 261,
sahilmgandhi 18:6a4db94011d3 308 INTRCAN2ERR_IRQn = 262,
sahilmgandhi 18:6a4db94011d3 309 INTRCAN2TRX_IRQn = 263,
sahilmgandhi 18:6a4db94011d3 310 INTRCAN3REC_IRQn = 264,
sahilmgandhi 18:6a4db94011d3 311 INTRCAN3ERR_IRQn = 265,
sahilmgandhi 18:6a4db94011d3 312 INTRCAN3TRX_IRQn = 266,
sahilmgandhi 18:6a4db94011d3 313 INTRCAN4REC_IRQn = 267,
sahilmgandhi 18:6a4db94011d3 314 INTRCAN4ERR_IRQn = 268,
sahilmgandhi 18:6a4db94011d3 315 INTRCAN4TRX_IRQn = 269,
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 318 RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 319 RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 320 RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 321 RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 322 RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 323 RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 324 RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 325 RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 326 RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 327 RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 328 RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 329 RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 330 RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 331 RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 IEBBTD_IRQn = 285,
sahilmgandhi 18:6a4db94011d3 334 IEBBTERR_IRQn = 286,
sahilmgandhi 18:6a4db94011d3 335 IEBBTSTA_IRQn = 287,
sahilmgandhi 18:6a4db94011d3 336 IEBBTV_IRQn = 288,
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 ISY_IRQn = 289,
sahilmgandhi 18:6a4db94011d3 339 IERR_IRQn = 290,
sahilmgandhi 18:6a4db94011d3 340 ITARG_IRQn = 291,
sahilmgandhi 18:6a4db94011d3 341 ISEC_IRQn = 292,
sahilmgandhi 18:6a4db94011d3 342 IBUF_IRQn = 293,
sahilmgandhi 18:6a4db94011d3 343 IREADY_IRQn = 294,
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 STERB_IRQn = 295,
sahilmgandhi 18:6a4db94011d3 346 FLTENDI_IRQn = 296,
sahilmgandhi 18:6a4db94011d3 347 FLTREQ0I_IRQn = 297,
sahilmgandhi 18:6a4db94011d3 348 FLTREQ1I_IRQn = 298,
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 MMC0_IRQn = 299,
sahilmgandhi 18:6a4db94011d3 351 MMC1_IRQn = 300,
sahilmgandhi 18:6a4db94011d3 352 MMC2_IRQn = 301,
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 SCHI0_3_IRQn = 302,
sahilmgandhi 18:6a4db94011d3 355 SDHI0_0_IRQn = 303,
sahilmgandhi 18:6a4db94011d3 356 SDHI0_1_IRQn = 304,
sahilmgandhi 18:6a4db94011d3 357 SCHI1_3_IRQn = 305,
sahilmgandhi 18:6a4db94011d3 358 SDHI1_0_IRQn = 306,
sahilmgandhi 18:6a4db94011d3 359 SDHI1_1_IRQn = 307,
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 ARM_IRQn = 308,
sahilmgandhi 18:6a4db94011d3 362 PRD_IRQn = 309,
sahilmgandhi 18:6a4db94011d3 363 CUP_IRQn = 310,
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 SCUAI0_IRQn = 311,
sahilmgandhi 18:6a4db94011d3 366 SCUAI1_IRQn = 312,
sahilmgandhi 18:6a4db94011d3 367 SCUFDI0_IRQn = 313,
sahilmgandhi 18:6a4db94011d3 368 SCUFDI1_IRQn = 314,
sahilmgandhi 18:6a4db94011d3 369 SCUFDI2_IRQn = 315,
sahilmgandhi 18:6a4db94011d3 370 SCUFDI3_IRQn = 316,
sahilmgandhi 18:6a4db94011d3 371 SCUFUI0_IRQn = 317,
sahilmgandhi 18:6a4db94011d3 372 SCUFUI1_IRQn = 318,
sahilmgandhi 18:6a4db94011d3 373 SCUFUI2_IRQn = 319,
sahilmgandhi 18:6a4db94011d3 374 SCUFUI3_IRQn = 320,
sahilmgandhi 18:6a4db94011d3 375 SCUDVI0_IRQn = 321,
sahilmgandhi 18:6a4db94011d3 376 SCUDVI1_IRQn = 322,
sahilmgandhi 18:6a4db94011d3 377 SCUDVI2_IRQn = 323,
sahilmgandhi 18:6a4db94011d3 378 SCUDVI3_IRQn = 324,
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 MLB_CINT_IRQn = 325,
sahilmgandhi 18:6a4db94011d3 381 MLB_SINT_IRQn = 326,
sahilmgandhi 18:6a4db94011d3 382
sahilmgandhi 18:6a4db94011d3 383 DRC10_IRQn = 327,
sahilmgandhi 18:6a4db94011d3 384 DRC11_IRQn = 328,
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 /* 329-330 Reserved */
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 LINI0_INT_T_IRQn = 331,
sahilmgandhi 18:6a4db94011d3 389 LINI0_INT_R_IRQn = 332,
sahilmgandhi 18:6a4db94011d3 390 LINI0_INT_S_IRQn = 333,
sahilmgandhi 18:6a4db94011d3 391 LINI0_INT_M_IRQn = 334,
sahilmgandhi 18:6a4db94011d3 392 LINI1_INT_T_IRQn = 335,
sahilmgandhi 18:6a4db94011d3 393 LINI1_INT_R_IRQn = 336,
sahilmgandhi 18:6a4db94011d3 394 LINI1_INT_S_IRQn = 337,
sahilmgandhi 18:6a4db94011d3 395 LINI1_INT_M_IRQn = 338,
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 /* 339-346 Reserved */
sahilmgandhi 18:6a4db94011d3 398
sahilmgandhi 18:6a4db94011d3 399 SCIERI0_IRQn = 347,
sahilmgandhi 18:6a4db94011d3 400 SCIRXI0_IRQn = 348,
sahilmgandhi 18:6a4db94011d3 401 SCITXI0_IRQn = 349,
sahilmgandhi 18:6a4db94011d3 402 SCITEI0_IRQn = 350,
sahilmgandhi 18:6a4db94011d3 403 SCIERI1_IRQn = 351,
sahilmgandhi 18:6a4db94011d3 404 SCIRXI1_IRQn = 352,
sahilmgandhi 18:6a4db94011d3 405 SCITXI1_IRQn = 353,
sahilmgandhi 18:6a4db94011d3 406 SCITEI1_IRQn = 354,
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 AVBI_DATA = 355,
sahilmgandhi 18:6a4db94011d3 409 AVBI_ERROR = 356,
sahilmgandhi 18:6a4db94011d3 410 AVBI_MANAGE = 357,
sahilmgandhi 18:6a4db94011d3 411 AVBI_MAC = 358,
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 ETHERI_IRQn = 359,
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 /* 360-363 Reserved */
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417 CEUI_IRQn = 364,
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 /* 365-380 Reserved */
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 H2XMLB_ERRINT_IRQn = 381,
sahilmgandhi 18:6a4db94011d3 423 H2XIC1_ERRINT_IRQn = 382,
sahilmgandhi 18:6a4db94011d3 424 X2HPERI1_ERRINT_IRQn = 383,
sahilmgandhi 18:6a4db94011d3 425 X2HPERR2_ERRINT_IRQn = 384,
sahilmgandhi 18:6a4db94011d3 426 X2HPERR34_ERRINT_IRQn= 385,
sahilmgandhi 18:6a4db94011d3 427 X2HPERR5_ERRINT_IRQn = 386,
sahilmgandhi 18:6a4db94011d3 428 X2HPERR67_ERRINT_IRQn= 387,
sahilmgandhi 18:6a4db94011d3 429 X2HDBGR_ERRINT_IRQn = 388,
sahilmgandhi 18:6a4db94011d3 430 X2HBSC_ERRINT_IRQn = 389,
sahilmgandhi 18:6a4db94011d3 431 X2HSPI1_ERRINT_IRQn = 390,
sahilmgandhi 18:6a4db94011d3 432 X2HSPI2_ERRINT_IRQn = 391,
sahilmgandhi 18:6a4db94011d3 433 PRRI_IRQn = 392,
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 IFEI0_IRQn = 393,
sahilmgandhi 18:6a4db94011d3 436 OFFI0_IRQn = 394,
sahilmgandhi 18:6a4db94011d3 437 PFVEI0_IRQn = 395,
sahilmgandhi 18:6a4db94011d3 438 IFEI1_IRQn = 396,
sahilmgandhi 18:6a4db94011d3 439 OFFI1_IRQn = 397,
sahilmgandhi 18:6a4db94011d3 440 PFVEI1_IRQn = 398,
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 /* 399-415 Reserved */
sahilmgandhi 18:6a4db94011d3 443 TINT0_IRQn = 416,
sahilmgandhi 18:6a4db94011d3 444 TINT1_IRQn = 417,
sahilmgandhi 18:6a4db94011d3 445 TINT2_IRQn = 418,
sahilmgandhi 18:6a4db94011d3 446 TINT3_IRQn = 419,
sahilmgandhi 18:6a4db94011d3 447 TINT4_IRQn = 420,
sahilmgandhi 18:6a4db94011d3 448 TINT5_IRQn = 421,
sahilmgandhi 18:6a4db94011d3 449 TINT6_IRQn = 422,
sahilmgandhi 18:6a4db94011d3 450 TINT7_IRQn = 423,
sahilmgandhi 18:6a4db94011d3 451 TINT8_IRQn = 424,
sahilmgandhi 18:6a4db94011d3 452 TINT9_IRQn = 425,
sahilmgandhi 18:6a4db94011d3 453 TINT10_IRQn = 426,
sahilmgandhi 18:6a4db94011d3 454 TINT11_IRQn = 427,
sahilmgandhi 18:6a4db94011d3 455 TINT12_IRQn = 428,
sahilmgandhi 18:6a4db94011d3 456 TINT13_IRQn = 429,
sahilmgandhi 18:6a4db94011d3 457 TINT14_IRQn = 430,
sahilmgandhi 18:6a4db94011d3 458 TINT15_IRQn = 431,
sahilmgandhi 18:6a4db94011d3 459 TINT16_IRQn = 432,
sahilmgandhi 18:6a4db94011d3 460 TINT17_IRQn = 433,
sahilmgandhi 18:6a4db94011d3 461 TINT18_IRQn = 434,
sahilmgandhi 18:6a4db94011d3 462 TINT19_IRQn = 435,
sahilmgandhi 18:6a4db94011d3 463 TINT20_IRQn = 436,
sahilmgandhi 18:6a4db94011d3 464 TINT21_IRQn = 437,
sahilmgandhi 18:6a4db94011d3 465 TINT22_IRQn = 438,
sahilmgandhi 18:6a4db94011d3 466 TINT23_IRQn = 439,
sahilmgandhi 18:6a4db94011d3 467 TINT24_IRQn = 440,
sahilmgandhi 18:6a4db94011d3 468 TINT25_IRQn = 441,
sahilmgandhi 18:6a4db94011d3 469 TINT26_IRQn = 442,
sahilmgandhi 18:6a4db94011d3 470 TINT27_IRQn = 443,
sahilmgandhi 18:6a4db94011d3 471 TINT28_IRQn = 444,
sahilmgandhi 18:6a4db94011d3 472 TINT29_IRQn = 445,
sahilmgandhi 18:6a4db94011d3 473 TINT30_IRQn = 446,
sahilmgandhi 18:6a4db94011d3 474 TINT31_IRQn = 447,
sahilmgandhi 18:6a4db94011d3 475 TINT32_IRQn = 448,
sahilmgandhi 18:6a4db94011d3 476 TINT33_IRQn = 449,
sahilmgandhi 18:6a4db94011d3 477 TINT34_IRQn = 450,
sahilmgandhi 18:6a4db94011d3 478 TINT35_IRQn = 451,
sahilmgandhi 18:6a4db94011d3 479 TINT36_IRQn = 452,
sahilmgandhi 18:6a4db94011d3 480 TINT37_IRQn = 453,
sahilmgandhi 18:6a4db94011d3 481 TINT38_IRQn = 454,
sahilmgandhi 18:6a4db94011d3 482 TINT39_IRQn = 455,
sahilmgandhi 18:6a4db94011d3 483 TINT40_IRQn = 456,
sahilmgandhi 18:6a4db94011d3 484 TINT41_IRQn = 457,
sahilmgandhi 18:6a4db94011d3 485 TINT42_IRQn = 458,
sahilmgandhi 18:6a4db94011d3 486 TINT43_IRQn = 459,
sahilmgandhi 18:6a4db94011d3 487 TINT44_IRQn = 460,
sahilmgandhi 18:6a4db94011d3 488 TINT45_IRQn = 461,
sahilmgandhi 18:6a4db94011d3 489 TINT46_IRQn = 462,
sahilmgandhi 18:6a4db94011d3 490 TINT47_IRQn = 463,
sahilmgandhi 18:6a4db94011d3 491 TINT48_IRQn = 464,
sahilmgandhi 18:6a4db94011d3 492 TINT49_IRQn = 465,
sahilmgandhi 18:6a4db94011d3 493 TINT50_IRQn = 466,
sahilmgandhi 18:6a4db94011d3 494 TINT51_IRQn = 467,
sahilmgandhi 18:6a4db94011d3 495 TINT52_IRQn = 468,
sahilmgandhi 18:6a4db94011d3 496 TINT53_IRQn = 469,
sahilmgandhi 18:6a4db94011d3 497 TINT54_IRQn = 470,
sahilmgandhi 18:6a4db94011d3 498 TINT55_IRQn = 471,
sahilmgandhi 18:6a4db94011d3 499 TINT56_IRQn = 472,
sahilmgandhi 18:6a4db94011d3 500 TINT57_IRQn = 473,
sahilmgandhi 18:6a4db94011d3 501 TINT58_IRQn = 474,
sahilmgandhi 18:6a4db94011d3 502 TINT59_IRQn = 475,
sahilmgandhi 18:6a4db94011d3 503 TINT60_IRQn = 476,
sahilmgandhi 18:6a4db94011d3 504 TINT61_IRQn = 477,
sahilmgandhi 18:6a4db94011d3 505 TINT62_IRQn = 478,
sahilmgandhi 18:6a4db94011d3 506 TINT63_IRQn = 479,
sahilmgandhi 18:6a4db94011d3 507 TINT64_IRQn = 480,
sahilmgandhi 18:6a4db94011d3 508 TINT65_IRQn = 481,
sahilmgandhi 18:6a4db94011d3 509 TINT66_IRQn = 482,
sahilmgandhi 18:6a4db94011d3 510 TINT67_IRQn = 483,
sahilmgandhi 18:6a4db94011d3 511 TINT68_IRQn = 484,
sahilmgandhi 18:6a4db94011d3 512 TINT69_IRQn = 485,
sahilmgandhi 18:6a4db94011d3 513 TINT70_IRQn = 486,
sahilmgandhi 18:6a4db94011d3 514 TINT71_IRQn = 487,
sahilmgandhi 18:6a4db94011d3 515 TINT72_IRQn = 488,
sahilmgandhi 18:6a4db94011d3 516 TINT73_IRQn = 489,
sahilmgandhi 18:6a4db94011d3 517 TINT74_IRQn = 490,
sahilmgandhi 18:6a4db94011d3 518 TINT75_IRQn = 491,
sahilmgandhi 18:6a4db94011d3 519 TINT76_IRQn = 492,
sahilmgandhi 18:6a4db94011d3 520 TINT77_IRQn = 493,
sahilmgandhi 18:6a4db94011d3 521 TINT78_IRQn = 494,
sahilmgandhi 18:6a4db94011d3 522 TINT79_IRQn = 495,
sahilmgandhi 18:6a4db94011d3 523 TINT80_IRQn = 496,
sahilmgandhi 18:6a4db94011d3 524 TINT81_IRQn = 497,
sahilmgandhi 18:6a4db94011d3 525 TINT82_IRQn = 498,
sahilmgandhi 18:6a4db94011d3 526 TINT83_IRQn = 499,
sahilmgandhi 18:6a4db94011d3 527 TINT84_IRQn = 500,
sahilmgandhi 18:6a4db94011d3 528 TINT85_IRQn = 501,
sahilmgandhi 18:6a4db94011d3 529 TINT86_IRQn = 502,
sahilmgandhi 18:6a4db94011d3 530 TINT87_IRQn = 503,
sahilmgandhi 18:6a4db94011d3 531 TINT88_IRQn = 504,
sahilmgandhi 18:6a4db94011d3 532 TINT89_IRQn = 505,
sahilmgandhi 18:6a4db94011d3 533 TINT90_IRQn = 506,
sahilmgandhi 18:6a4db94011d3 534 TINT91_IRQn = 507,
sahilmgandhi 18:6a4db94011d3 535 TINT92_IRQn = 508,
sahilmgandhi 18:6a4db94011d3 536 TINT93_IRQn = 509,
sahilmgandhi 18:6a4db94011d3 537 TINT94_IRQn = 510,
sahilmgandhi 18:6a4db94011d3 538 TINT95_IRQn = 511,
sahilmgandhi 18:6a4db94011d3 539 TINT96_IRQn = 512,
sahilmgandhi 18:6a4db94011d3 540 TINT97_IRQn = 513,
sahilmgandhi 18:6a4db94011d3 541 TINT98_IRQn = 514,
sahilmgandhi 18:6a4db94011d3 542 TINT99_IRQn = 515,
sahilmgandhi 18:6a4db94011d3 543 TINT100_IRQn = 516,
sahilmgandhi 18:6a4db94011d3 544 TINT101_IRQn = 517,
sahilmgandhi 18:6a4db94011d3 545 TINT102_IRQn = 518,
sahilmgandhi 18:6a4db94011d3 546 TINT103_IRQn = 519,
sahilmgandhi 18:6a4db94011d3 547 TINT104_IRQn = 520,
sahilmgandhi 18:6a4db94011d3 548 TINT105_IRQn = 521,
sahilmgandhi 18:6a4db94011d3 549 TINT106_IRQn = 522,
sahilmgandhi 18:6a4db94011d3 550 TINT107_IRQn = 523,
sahilmgandhi 18:6a4db94011d3 551 TINT108_IRQn = 524,
sahilmgandhi 18:6a4db94011d3 552 TINT109_IRQn = 525,
sahilmgandhi 18:6a4db94011d3 553 TINT110_IRQn = 526,
sahilmgandhi 18:6a4db94011d3 554 TINT111_IRQn = 527,
sahilmgandhi 18:6a4db94011d3 555 TINT112_IRQn = 528,
sahilmgandhi 18:6a4db94011d3 556 TINT113_IRQn = 529,
sahilmgandhi 18:6a4db94011d3 557 TINT114_IRQn = 530,
sahilmgandhi 18:6a4db94011d3 558 TINT115_IRQn = 531,
sahilmgandhi 18:6a4db94011d3 559 TINT116_IRQn = 532,
sahilmgandhi 18:6a4db94011d3 560 TINT117_IRQn = 533,
sahilmgandhi 18:6a4db94011d3 561 TINT118_IRQn = 534,
sahilmgandhi 18:6a4db94011d3 562 TINT119_IRQn = 535,
sahilmgandhi 18:6a4db94011d3 563 TINT120_IRQn = 536,
sahilmgandhi 18:6a4db94011d3 564 TINT121_IRQn = 537,
sahilmgandhi 18:6a4db94011d3 565 TINT122_IRQn = 538,
sahilmgandhi 18:6a4db94011d3 566 TINT123_IRQn = 539,
sahilmgandhi 18:6a4db94011d3 567 TINT124_IRQn = 540,
sahilmgandhi 18:6a4db94011d3 568 TINT125_IRQn = 541,
sahilmgandhi 18:6a4db94011d3 569 TINT126_IRQn = 542,
sahilmgandhi 18:6a4db94011d3 570 TINT127_IRQn = 543,
sahilmgandhi 18:6a4db94011d3 571 TINT128_IRQn = 544,
sahilmgandhi 18:6a4db94011d3 572 TINT129_IRQn = 545,
sahilmgandhi 18:6a4db94011d3 573 TINT130_IRQn = 546,
sahilmgandhi 18:6a4db94011d3 574 TINT131_IRQn = 547,
sahilmgandhi 18:6a4db94011d3 575 TINT132_IRQn = 548,
sahilmgandhi 18:6a4db94011d3 576 TINT133_IRQn = 549,
sahilmgandhi 18:6a4db94011d3 577 TINT134_IRQn = 550,
sahilmgandhi 18:6a4db94011d3 578 TINT135_IRQn = 551,
sahilmgandhi 18:6a4db94011d3 579 TINT136_IRQn = 552,
sahilmgandhi 18:6a4db94011d3 580 TINT137_IRQn = 553,
sahilmgandhi 18:6a4db94011d3 581 TINT138_IRQn = 554,
sahilmgandhi 18:6a4db94011d3 582 TINT139_IRQn = 555,
sahilmgandhi 18:6a4db94011d3 583 TINT140_IRQn = 556,
sahilmgandhi 18:6a4db94011d3 584 TINT141_IRQn = 557,
sahilmgandhi 18:6a4db94011d3 585 TINT142_IRQn = 558,
sahilmgandhi 18:6a4db94011d3 586 TINT143_IRQn = 559,
sahilmgandhi 18:6a4db94011d3 587 TINT144_IRQn = 560,
sahilmgandhi 18:6a4db94011d3 588 TINT145_IRQn = 561,
sahilmgandhi 18:6a4db94011d3 589 TINT146_IRQn = 562,
sahilmgandhi 18:6a4db94011d3 590 TINT147_IRQn = 563,
sahilmgandhi 18:6a4db94011d3 591 TINT148_IRQn = 564,
sahilmgandhi 18:6a4db94011d3 592 TINT149_IRQn = 565,
sahilmgandhi 18:6a4db94011d3 593 TINT150_IRQn = 566,
sahilmgandhi 18:6a4db94011d3 594 TINT151_IRQn = 567,
sahilmgandhi 18:6a4db94011d3 595 TINT152_IRQn = 568,
sahilmgandhi 18:6a4db94011d3 596 TINT153_IRQn = 569,
sahilmgandhi 18:6a4db94011d3 597 TINT154_IRQn = 570,
sahilmgandhi 18:6a4db94011d3 598 TINT155_IRQn = 571,
sahilmgandhi 18:6a4db94011d3 599 TINT156_IRQn = 572,
sahilmgandhi 18:6a4db94011d3 600 TINT157_IRQn = 573,
sahilmgandhi 18:6a4db94011d3 601 TINT158_IRQn = 574,
sahilmgandhi 18:6a4db94011d3 602 TINT159_IRQn = 575,
sahilmgandhi 18:6a4db94011d3 603 TINT160_IRQn = 576,
sahilmgandhi 18:6a4db94011d3 604 TINT161_IRQn = 577,
sahilmgandhi 18:6a4db94011d3 605 TINT162_IRQn = 578,
sahilmgandhi 18:6a4db94011d3 606 TINT163_IRQn = 579,
sahilmgandhi 18:6a4db94011d3 607 TINT164_IRQn = 580,
sahilmgandhi 18:6a4db94011d3 608 TINT165_IRQn = 581,
sahilmgandhi 18:6a4db94011d3 609 TINT166_IRQn = 582,
sahilmgandhi 18:6a4db94011d3 610 TINT167_IRQn = 583,
sahilmgandhi 18:6a4db94011d3 611 TINT168_IRQn = 584,
sahilmgandhi 18:6a4db94011d3 612 TINT169_IRQn = 585,
sahilmgandhi 18:6a4db94011d3 613 TINT170_IRQn = 586
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 616
sahilmgandhi 18:6a4db94011d3 617 #define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn
sahilmgandhi 18:6a4db94011d3 618
sahilmgandhi 18:6a4db94011d3 619 /* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
sahilmgandhi 18:6a4db94011d3 620 #define __CA9_REV 0x0000 /*!< Core revision r0 */
sahilmgandhi 18:6a4db94011d3 621
sahilmgandhi 18:6a4db94011d3 622 #define __MPU_PRESENT 1 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 #define __FPU_PRESENT 1 /*!< FPU present or not */
sahilmgandhi 18:6a4db94011d3 625
sahilmgandhi 18:6a4db94011d3 626 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 627 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 #include <core_ca9.h>
sahilmgandhi 18:6a4db94011d3 630 #include "system_MBRZA1H.h"
sahilmgandhi 18:6a4db94011d3 631
sahilmgandhi 18:6a4db94011d3 632
sahilmgandhi 18:6a4db94011d3 633 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 634 /* Device Specific Peripheral Section */
sahilmgandhi 18:6a4db94011d3 635 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 636 /** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
sahilmgandhi 18:6a4db94011d3 637 Renesas_RZ_A1 Device Specific Peripheral registers structures
sahilmgandhi 18:6a4db94011d3 638 @{
sahilmgandhi 18:6a4db94011d3 639 */
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 642 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 643 #endif
sahilmgandhi 18:6a4db94011d3 644
sahilmgandhi 18:6a4db94011d3 645 #include "pl310.h"
sahilmgandhi 18:6a4db94011d3 646 #include "gic.h"
sahilmgandhi 18:6a4db94011d3 647 #include "nvic_wrapper.h"
sahilmgandhi 18:6a4db94011d3 648 #include "cmsis_nvic.h"
sahilmgandhi 18:6a4db94011d3 649
sahilmgandhi 18:6a4db94011d3 650 #include "ostm_iodefine.h"
sahilmgandhi 18:6a4db94011d3 651 #include "gpio_iodefine.h"
sahilmgandhi 18:6a4db94011d3 652 #include "cpg_iodefine.h"
sahilmgandhi 18:6a4db94011d3 653 #include "l2c_iodefine.h"
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 656 #pragma no_anon_unions
sahilmgandhi 18:6a4db94011d3 657 #endif
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659 /*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 663 /* Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 664 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 665 /** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
sahilmgandhi 18:6a4db94011d3 666 @{
sahilmgandhi 18:6a4db94011d3 667 */
sahilmgandhi 18:6a4db94011d3 668
sahilmgandhi 18:6a4db94011d3 669 /* R7S72100 CPU board */
sahilmgandhi 18:6a4db94011d3 670 #define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
sahilmgandhi 18:6a4db94011d3 671 #define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
sahilmgandhi 18:6a4db94011d3 672 #define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
sahilmgandhi 18:6a4db94011d3 673 #define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
sahilmgandhi 18:6a4db94011d3 674 #define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
sahilmgandhi 18:6a4db94011d3 675 #define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
sahilmgandhi 18:6a4db94011d3 676 #define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
sahilmgandhi 18:6a4db94011d3 677 #define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
sahilmgandhi 18:6a4db94011d3 678 #define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
sahilmgandhi 18:6a4db94011d3 679 #define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
sahilmgandhi 18:6a4db94011d3 680 #define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
sahilmgandhi 18:6a4db94011d3 681 #define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
sahilmgandhi 18:6a4db94011d3 682 #define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
sahilmgandhi 18:6a4db94011d3 683 #define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
sahilmgandhi 18:6a4db94011d3 684 #define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
sahilmgandhi 18:6a4db94011d3 685 #define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
sahilmgandhi 18:6a4db94011d3 686 #define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
sahilmgandhi 18:6a4db94011d3 687
sahilmgandhi 18:6a4db94011d3 688 //Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
sahilmgandhi 18:6a4db94011d3 689 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
sahilmgandhi 18:6a4db94011d3 690 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
sahilmgandhi 18:6a4db94011d3 691 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 692 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 693 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 694 region.inner_norm_t = WB_WA; \
sahilmgandhi 18:6a4db94011d3 695 region.outer_norm_t = WB_WA; \
sahilmgandhi 18:6a4db94011d3 696 region.mem_t = NORMAL; \
sahilmgandhi 18:6a4db94011d3 697 region.sec_t = NON_SECURE; \
sahilmgandhi 18:6a4db94011d3 698 region.xn_t = EXECUTE; \
sahilmgandhi 18:6a4db94011d3 699 region.priv_t = RW; \
sahilmgandhi 18:6a4db94011d3 700 region.user_t = RW; \
sahilmgandhi 18:6a4db94011d3 701 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 702 __get_section_descriptor(&descriptor_l1, region);
sahilmgandhi 18:6a4db94011d3 703
sahilmgandhi 18:6a4db94011d3 704 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
sahilmgandhi 18:6a4db94011d3 705 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 706 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 707 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 708 region.inner_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 709 region.outer_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 710 region.mem_t = NORMAL; \
sahilmgandhi 18:6a4db94011d3 711 region.sec_t = SECURE; \
sahilmgandhi 18:6a4db94011d3 712 region.xn_t = EXECUTE; \
sahilmgandhi 18:6a4db94011d3 713 region.priv_t = RW; \
sahilmgandhi 18:6a4db94011d3 714 region.user_t = RW; \
sahilmgandhi 18:6a4db94011d3 715 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 716 __get_section_descriptor(&descriptor_l1, region);
sahilmgandhi 18:6a4db94011d3 717
sahilmgandhi 18:6a4db94011d3 718 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
sahilmgandhi 18:6a4db94011d3 719 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
sahilmgandhi 18:6a4db94011d3 720 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 721 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 722 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 723 region.inner_norm_t = WB_WA; \
sahilmgandhi 18:6a4db94011d3 724 region.outer_norm_t = WB_WA; \
sahilmgandhi 18:6a4db94011d3 725 region.mem_t = NORMAL; \
sahilmgandhi 18:6a4db94011d3 726 region.sec_t = NON_SECURE; \
sahilmgandhi 18:6a4db94011d3 727 region.xn_t = EXECUTE; \
sahilmgandhi 18:6a4db94011d3 728 region.priv_t = READ; \
sahilmgandhi 18:6a4db94011d3 729 region.user_t = READ; \
sahilmgandhi 18:6a4db94011d3 730 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 731 __get_section_descriptor(&descriptor_l1, region);
sahilmgandhi 18:6a4db94011d3 732
sahilmgandhi 18:6a4db94011d3 733 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
sahilmgandhi 18:6a4db94011d3 734 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
sahilmgandhi 18:6a4db94011d3 735 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 736 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 737 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 738 region.inner_norm_t = WB_WA; \
sahilmgandhi 18:6a4db94011d3 739 region.outer_norm_t = WB_WA; \
sahilmgandhi 18:6a4db94011d3 740 region.mem_t = NORMAL; \
sahilmgandhi 18:6a4db94011d3 741 region.sec_t = NON_SECURE; \
sahilmgandhi 18:6a4db94011d3 742 region.xn_t = NON_EXECUTE; \
sahilmgandhi 18:6a4db94011d3 743 region.priv_t = READ; \
sahilmgandhi 18:6a4db94011d3 744 region.user_t = READ; \
sahilmgandhi 18:6a4db94011d3 745 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 746 __get_section_descriptor(&descriptor_l1, region);
sahilmgandhi 18:6a4db94011d3 747
sahilmgandhi 18:6a4db94011d3 748 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
sahilmgandhi 18:6a4db94011d3 749 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
sahilmgandhi 18:6a4db94011d3 750 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 751 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 752 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 753 region.inner_norm_t = WB_WA; \
sahilmgandhi 18:6a4db94011d3 754 region.outer_norm_t = WB_WA; \
sahilmgandhi 18:6a4db94011d3 755 region.mem_t = NORMAL; \
sahilmgandhi 18:6a4db94011d3 756 region.sec_t = NON_SECURE; \
sahilmgandhi 18:6a4db94011d3 757 region.xn_t = EXECUTE; \
sahilmgandhi 18:6a4db94011d3 758 region.priv_t = RW; \
sahilmgandhi 18:6a4db94011d3 759 region.user_t = RW; \
sahilmgandhi 18:6a4db94011d3 760 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 761 __get_section_descriptor(&descriptor_l1, region);
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
sahilmgandhi 18:6a4db94011d3 764 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
sahilmgandhi 18:6a4db94011d3 765 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 766 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 767 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 768 region.inner_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 769 region.outer_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 770 region.mem_t = STRONGLY_ORDERED; \
sahilmgandhi 18:6a4db94011d3 771 region.sec_t = SECURE; \
sahilmgandhi 18:6a4db94011d3 772 region.xn_t = NON_EXECUTE; \
sahilmgandhi 18:6a4db94011d3 773 region.priv_t = RW; \
sahilmgandhi 18:6a4db94011d3 774 region.user_t = RW; \
sahilmgandhi 18:6a4db94011d3 775 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 776 __get_section_descriptor(&descriptor_l1, region);
sahilmgandhi 18:6a4db94011d3 777
sahilmgandhi 18:6a4db94011d3 778 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
sahilmgandhi 18:6a4db94011d3 779 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
sahilmgandhi 18:6a4db94011d3 780 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 781 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 782 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 783 region.inner_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 784 region.outer_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 785 region.mem_t = STRONGLY_ORDERED; \
sahilmgandhi 18:6a4db94011d3 786 region.sec_t = SECURE; \
sahilmgandhi 18:6a4db94011d3 787 region.xn_t = NON_EXECUTE; \
sahilmgandhi 18:6a4db94011d3 788 region.priv_t = READ; \
sahilmgandhi 18:6a4db94011d3 789 region.user_t = READ; \
sahilmgandhi 18:6a4db94011d3 790 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 791 __get_section_descriptor(&descriptor_l1, region);
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793 //Sect_Device_RW. Sect_Device_RO, but writeable
sahilmgandhi 18:6a4db94011d3 794 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
sahilmgandhi 18:6a4db94011d3 795 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 796 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 797 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 798 region.inner_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 799 region.outer_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 800 region.mem_t = STRONGLY_ORDERED; \
sahilmgandhi 18:6a4db94011d3 801 region.sec_t = SECURE; \
sahilmgandhi 18:6a4db94011d3 802 region.xn_t = NON_EXECUTE; \
sahilmgandhi 18:6a4db94011d3 803 region.priv_t = RW; \
sahilmgandhi 18:6a4db94011d3 804 region.user_t = RW; \
sahilmgandhi 18:6a4db94011d3 805 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 806 __get_section_descriptor(&descriptor_l1, region);
sahilmgandhi 18:6a4db94011d3 807 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
sahilmgandhi 18:6a4db94011d3 808 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
sahilmgandhi 18:6a4db94011d3 809 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 810 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 811 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 812 region.inner_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 813 region.outer_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 814 region.mem_t = SHARED_DEVICE; \
sahilmgandhi 18:6a4db94011d3 815 region.sec_t = SECURE; \
sahilmgandhi 18:6a4db94011d3 816 region.xn_t = NON_EXECUTE; \
sahilmgandhi 18:6a4db94011d3 817 region.priv_t = RW; \
sahilmgandhi 18:6a4db94011d3 818 region.user_t = RW; \
sahilmgandhi 18:6a4db94011d3 819 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 820 __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
sahilmgandhi 18:6a4db94011d3 821
sahilmgandhi 18:6a4db94011d3 822 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
sahilmgandhi 18:6a4db94011d3 823 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
sahilmgandhi 18:6a4db94011d3 824 region.domain = 0x0; \
sahilmgandhi 18:6a4db94011d3 825 region.e_t = ECC_DISABLED; \
sahilmgandhi 18:6a4db94011d3 826 region.g_t = GLOBAL; \
sahilmgandhi 18:6a4db94011d3 827 region.inner_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 828 region.outer_norm_t = NON_CACHEABLE; \
sahilmgandhi 18:6a4db94011d3 829 region.mem_t = SHARED_DEVICE; \
sahilmgandhi 18:6a4db94011d3 830 region.sec_t = SECURE; \
sahilmgandhi 18:6a4db94011d3 831 region.xn_t = NON_EXECUTE; \
sahilmgandhi 18:6a4db94011d3 832 region.priv_t = RW; \
sahilmgandhi 18:6a4db94011d3 833 region.user_t = RW; \
sahilmgandhi 18:6a4db94011d3 834 region.sh_t = NON_SHARED; \
sahilmgandhi 18:6a4db94011d3 835 __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
sahilmgandhi 18:6a4db94011d3 836
sahilmgandhi 18:6a4db94011d3 837
sahilmgandhi 18:6a4db94011d3 838 /*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 841 /* Clock Settings */
sahilmgandhi 18:6a4db94011d3 842 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 843 /** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
sahilmgandhi 18:6a4db94011d3 844 @{
sahilmgandhi 18:6a4db94011d3 845 */
sahilmgandhi 18:6a4db94011d3 846
sahilmgandhi 18:6a4db94011d3 847 /*
sahilmgandhi 18:6a4db94011d3 848 * Clock Mode 0 settings
sahilmgandhi 18:6a4db94011d3 849 * SW1-4(MD_CLK):ON
sahilmgandhi 18:6a4db94011d3 850 * SW1-5(MD_CLKS):ON
sahilmgandhi 18:6a4db94011d3 851 * FRQCR=0x1035
sahilmgandhi 18:6a4db94011d3 852 * CLKEN2 = 0b - unstable
sahilmgandhi 18:6a4db94011d3 853 * CLKEN[1:0]=01b - Output, Low, Low
sahilmgandhi 18:6a4db94011d3 854 * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
sahilmgandhi 18:6a4db94011d3 855 * FRQCR2=0x0001
sahilmgandhi 18:6a4db94011d3 856 * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
sahilmgandhi 18:6a4db94011d3 857 */
sahilmgandhi 18:6a4db94011d3 858 #define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
sahilmgandhi 18:6a4db94011d3 859 #define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
sahilmgandhi 18:6a4db94011d3 860 #define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
sahilmgandhi 18:6a4db94011d3 861 #define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
sahilmgandhi 18:6a4db94011d3 862 #define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
sahilmgandhi 18:6a4db94011d3 863 #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
sahilmgandhi 18:6a4db94011d3 864 #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 /*
sahilmgandhi 18:6a4db94011d3 867 * Clock Mode 1 settings
sahilmgandhi 18:6a4db94011d3 868 * SW1-4(MD_CLK):OFF
sahilmgandhi 18:6a4db94011d3 869 * SW1-5(MD_CLKS):ON
sahilmgandhi 18:6a4db94011d3 870 * FRQCR=0x1335
sahilmgandhi 18:6a4db94011d3 871 * CLKEN2 = 0b - unstable
sahilmgandhi 18:6a4db94011d3 872 * CLKEN[1:0]=01b - Output, Low, Low
sahilmgandhi 18:6a4db94011d3 873 * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
sahilmgandhi 18:6a4db94011d3 874 * FRQCR2=0x0003
sahilmgandhi 18:6a4db94011d3 875 * GFC[1:0] =11b - graphic clock is 1/3 bus clock
sahilmgandhi 18:6a4db94011d3 876 */
sahilmgandhi 18:6a4db94011d3 877 #define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
sahilmgandhi 18:6a4db94011d3 878 #define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
sahilmgandhi 18:6a4db94011d3 879 #define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
sahilmgandhi 18:6a4db94011d3 880 #define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
sahilmgandhi 18:6a4db94011d3 881 #define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
sahilmgandhi 18:6a4db94011d3 882 #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
sahilmgandhi 18:6a4db94011d3 883 #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
sahilmgandhi 18:6a4db94011d3 884
sahilmgandhi 18:6a4db94011d3 885 /*@}*/ /* end of group Renesas_RZ_A1_Clocks */
sahilmgandhi 18:6a4db94011d3 886
sahilmgandhi 18:6a4db94011d3 887 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 888 /* CPG Settings */
sahilmgandhi 18:6a4db94011d3 889 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 890 /** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
sahilmgandhi 18:6a4db94011d3 891 @{
sahilmgandhi 18:6a4db94011d3 892 */
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 #define CPG_FRQCR_SHIFT_CKOEN2 (14)
sahilmgandhi 18:6a4db94011d3 895 #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
sahilmgandhi 18:6a4db94011d3 896 #define CPG_FRQCR_SHIFT_CKOEN0 (12)
sahilmgandhi 18:6a4db94011d3 897 #define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
sahilmgandhi 18:6a4db94011d3 898 #define CPG_FRQCR_SHIFT_IFC (8)
sahilmgandhi 18:6a4db94011d3 899 #define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
sahilmgandhi 18:6a4db94011d3 900
sahilmgandhi 18:6a4db94011d3 901 #define CPG_FRQCR2_SHIFT_GFC (0)
sahilmgandhi 18:6a4db94011d3 902 #define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
sahilmgandhi 18:6a4db94011d3 903
sahilmgandhi 18:6a4db94011d3 904
sahilmgandhi 18:6a4db94011d3 905 #define CPG_STBCR1_BIT_STBY (0x80u)
sahilmgandhi 18:6a4db94011d3 906 #define CPG_STBCR1_BIT_DEEP (0x40u)
sahilmgandhi 18:6a4db94011d3 907 #define CPG_STBCR2_BIT_HIZ (0x80u)
sahilmgandhi 18:6a4db94011d3 908 #define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
sahilmgandhi 18:6a4db94011d3 909 #define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
sahilmgandhi 18:6a4db94011d3 910 #define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
sahilmgandhi 18:6a4db94011d3 911 #define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
sahilmgandhi 18:6a4db94011d3 912 #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
sahilmgandhi 18:6a4db94011d3 913 #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
sahilmgandhi 18:6a4db94011d3 914 #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
sahilmgandhi 18:6a4db94011d3 915 #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
sahilmgandhi 18:6a4db94011d3 916 #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
sahilmgandhi 18:6a4db94011d3 917 #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
sahilmgandhi 18:6a4db94011d3 918 #define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
sahilmgandhi 18:6a4db94011d3 919 #define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
sahilmgandhi 18:6a4db94011d3 920 #define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
sahilmgandhi 18:6a4db94011d3 921 #define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
sahilmgandhi 18:6a4db94011d3 922 #define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
sahilmgandhi 18:6a4db94011d3 923 #define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
sahilmgandhi 18:6a4db94011d3 924 #define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
sahilmgandhi 18:6a4db94011d3 925 #define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
sahilmgandhi 18:6a4db94011d3 926 #define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
sahilmgandhi 18:6a4db94011d3 927 #define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
sahilmgandhi 18:6a4db94011d3 928 #define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
sahilmgandhi 18:6a4db94011d3 929 #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
sahilmgandhi 18:6a4db94011d3 930 #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
sahilmgandhi 18:6a4db94011d3 931 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
sahilmgandhi 18:6a4db94011d3 932 #define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */
sahilmgandhi 18:6a4db94011d3 933 #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
sahilmgandhi 18:6a4db94011d3 934 #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
sahilmgandhi 18:6a4db94011d3 935 #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
sahilmgandhi 18:6a4db94011d3 936 #define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */
sahilmgandhi 18:6a4db94011d3 937 #define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */
sahilmgandhi 18:6a4db94011d3 938 #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
sahilmgandhi 18:6a4db94011d3 939 #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
sahilmgandhi 18:6a4db94011d3 940 #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
sahilmgandhi 18:6a4db94011d3 941 #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
sahilmgandhi 18:6a4db94011d3 942 #define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */
sahilmgandhi 18:6a4db94011d3 943 #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
sahilmgandhi 18:6a4db94011d3 944 #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
sahilmgandhi 18:6a4db94011d3 945 #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
sahilmgandhi 18:6a4db94011d3 946 #define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
sahilmgandhi 18:6a4db94011d3 947 #define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
sahilmgandhi 18:6a4db94011d3 948 #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
sahilmgandhi 18:6a4db94011d3 949 #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
sahilmgandhi 18:6a4db94011d3 950 #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
sahilmgandhi 18:6a4db94011d3 951 #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
sahilmgandhi 18:6a4db94011d3 952 #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
sahilmgandhi 18:6a4db94011d3 953 #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
sahilmgandhi 18:6a4db94011d3 954 #define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
sahilmgandhi 18:6a4db94011d3 955 #define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
sahilmgandhi 18:6a4db94011d3 956 #define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
sahilmgandhi 18:6a4db94011d3 957 #define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
sahilmgandhi 18:6a4db94011d3 958 #define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
sahilmgandhi 18:6a4db94011d3 959 #define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
sahilmgandhi 18:6a4db94011d3 960 #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
sahilmgandhi 18:6a4db94011d3 961 #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
sahilmgandhi 18:6a4db94011d3 962 #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
sahilmgandhi 18:6a4db94011d3 963 #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
sahilmgandhi 18:6a4db94011d3 964 #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
sahilmgandhi 18:6a4db94011d3 965 #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
sahilmgandhi 18:6a4db94011d3 966 #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
sahilmgandhi 18:6a4db94011d3 967 #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
sahilmgandhi 18:6a4db94011d3 968 #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
sahilmgandhi 18:6a4db94011d3 969 #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
sahilmgandhi 18:6a4db94011d3 970 #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
sahilmgandhi 18:6a4db94011d3 971 #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
sahilmgandhi 18:6a4db94011d3 972 #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
sahilmgandhi 18:6a4db94011d3 973 #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
sahilmgandhi 18:6a4db94011d3 974 #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
sahilmgandhi 18:6a4db94011d3 975 #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
sahilmgandhi 18:6a4db94011d3 976 #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
sahilmgandhi 18:6a4db94011d3 977 #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
sahilmgandhi 18:6a4db94011d3 978 #define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
sahilmgandhi 18:6a4db94011d3 979 #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
sahilmgandhi 18:6a4db94011d3 980 #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
sahilmgandhi 18:6a4db94011d3 981 #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
sahilmgandhi 18:6a4db94011d3 982 #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
sahilmgandhi 18:6a4db94011d3 983 #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
sahilmgandhi 18:6a4db94011d3 984 #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
sahilmgandhi 18:6a4db94011d3 985 #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
sahilmgandhi 18:6a4db94011d3 986 #define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
sahilmgandhi 18:6a4db94011d3 987 #define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
sahilmgandhi 18:6a4db94011d3 988 #define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
sahilmgandhi 18:6a4db94011d3 989 #define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
sahilmgandhi 18:6a4db94011d3 990 #define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
sahilmgandhi 18:6a4db94011d3 991 #define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
sahilmgandhi 18:6a4db94011d3 992 #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
sahilmgandhi 18:6a4db94011d3 993 #define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
sahilmgandhi 18:6a4db94011d3 994 #define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
sahilmgandhi 18:6a4db94011d3 995 #define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
sahilmgandhi 18:6a4db94011d3 996 #define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
sahilmgandhi 18:6a4db94011d3 997 #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
sahilmgandhi 18:6a4db94011d3 998 #define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
sahilmgandhi 18:6a4db94011d3 999 #define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
sahilmgandhi 18:6a4db94011d3 1000 #define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
sahilmgandhi 18:6a4db94011d3 1001 #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
sahilmgandhi 18:6a4db94011d3 1002 #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
sahilmgandhi 18:6a4db94011d3 1003 #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
sahilmgandhi 18:6a4db94011d3 1004 #define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
sahilmgandhi 18:6a4db94011d3 1005 #define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
sahilmgandhi 18:6a4db94011d3 1006 #define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
sahilmgandhi 18:6a4db94011d3 1007 #define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
sahilmgandhi 18:6a4db94011d3 1008 #define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
sahilmgandhi 18:6a4db94011d3 1009 #define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
sahilmgandhi 18:6a4db94011d3 1010 #define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
sahilmgandhi 18:6a4db94011d3 1011 #define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
sahilmgandhi 18:6a4db94011d3 1012 #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
sahilmgandhi 18:6a4db94011d3 1013 #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
sahilmgandhi 18:6a4db94011d3 1014 #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
sahilmgandhi 18:6a4db94011d3 1015
sahilmgandhi 18:6a4db94011d3 1016 /*@}*/ /* end of group Renesas_RZ_A1_CPG */
sahilmgandhi 18:6a4db94011d3 1017
sahilmgandhi 18:6a4db94011d3 1018 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1019 /* GPIO Settings */
sahilmgandhi 18:6a4db94011d3 1020 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1021 /** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
sahilmgandhi 18:6a4db94011d3 1022 @{
sahilmgandhi 18:6a4db94011d3 1023 */
sahilmgandhi 18:6a4db94011d3 1024
sahilmgandhi 18:6a4db94011d3 1025 #define GPIO_BIT_N0 (1u << 0)
sahilmgandhi 18:6a4db94011d3 1026 #define GPIO_BIT_N1 (1u << 1)
sahilmgandhi 18:6a4db94011d3 1027 #define GPIO_BIT_N2 (1u << 2)
sahilmgandhi 18:6a4db94011d3 1028 #define GPIO_BIT_N3 (1u << 3)
sahilmgandhi 18:6a4db94011d3 1029 #define GPIO_BIT_N4 (1u << 4)
sahilmgandhi 18:6a4db94011d3 1030 #define GPIO_BIT_N5 (1u << 5)
sahilmgandhi 18:6a4db94011d3 1031 #define GPIO_BIT_N6 (1u << 6)
sahilmgandhi 18:6a4db94011d3 1032 #define GPIO_BIT_N7 (1u << 7)
sahilmgandhi 18:6a4db94011d3 1033 #define GPIO_BIT_N8 (1u << 8)
sahilmgandhi 18:6a4db94011d3 1034 #define GPIO_BIT_N9 (1u << 9)
sahilmgandhi 18:6a4db94011d3 1035 #define GPIO_BIT_N10 (1u << 10)
sahilmgandhi 18:6a4db94011d3 1036 #define GPIO_BIT_N11 (1u << 11)
sahilmgandhi 18:6a4db94011d3 1037 #define GPIO_BIT_N12 (1u << 12)
sahilmgandhi 18:6a4db94011d3 1038 #define GPIO_BIT_N13 (1u << 13)
sahilmgandhi 18:6a4db94011d3 1039 #define GPIO_BIT_N14 (1u << 14)
sahilmgandhi 18:6a4db94011d3 1040 #define GPIO_BIT_N15 (1u << 15)
sahilmgandhi 18:6a4db94011d3 1041
sahilmgandhi 18:6a4db94011d3 1042
sahilmgandhi 18:6a4db94011d3 1043 #define MD_BOOT10_MASK (0x3)
sahilmgandhi 18:6a4db94011d3 1044
sahilmgandhi 18:6a4db94011d3 1045 #define MD_BOOT10_BM0 (0x0)
sahilmgandhi 18:6a4db94011d3 1046 #define MD_BOOT10_BM1 (0x2)
sahilmgandhi 18:6a4db94011d3 1047 #define MD_BOOT10_BM3 (0x1)
sahilmgandhi 18:6a4db94011d3 1048 #define MD_BOOT10_BM4_5 (0x3)
sahilmgandhi 18:6a4db94011d3 1049
sahilmgandhi 18:6a4db94011d3 1050 #define MD_CLK (1u << 2)
sahilmgandhi 18:6a4db94011d3 1051 #define MD_CLKS (1u << 3)
sahilmgandhi 18:6a4db94011d3 1052
sahilmgandhi 18:6a4db94011d3 1053 /*@}*/ /* end of group Renesas_RZ_A1_GPIO */
sahilmgandhi 18:6a4db94011d3 1054
sahilmgandhi 18:6a4db94011d3 1055 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1056 }
sahilmgandhi 18:6a4db94011d3 1057 #endif
sahilmgandhi 18:6a4db94011d3 1058
sahilmgandhi 18:6a4db94011d3 1059 #endif // __MBRZA1H_H__