MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file uart_16c550_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief UART module hardware register map.
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor.
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 2615 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2013-12-13 13:17:21 +0530 (Fri, 13 Dec 2013) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup uart_16c550
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 * <h1> Reference document(s) </h1>
sahilmgandhi 18:6a4db94011d3 31 * <p>
sahilmgandhi 18:6a4db94011d3 32 * <a href="../pdf/IPC7202_UART_APB_DS_v1P4.pdf" target="_blank">
sahilmgandhi 18:6a4db94011d3 33 * IPC7202 APB UART Design Specification v1.4 </a>
sahilmgandhi 18:6a4db94011d3 34 * </p>
sahilmgandhi 18:6a4db94011d3 35 */
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #ifndef UART_16C550_MAP_H_
sahilmgandhi 18:6a4db94011d3 38 #define UART_16C550_MAP_H_
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 43 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 #define DCTS (uint8_t)0x01
sahilmgandhi 18:6a4db94011d3 47 #define DDSR (uint8_t)0x02
sahilmgandhi 18:6a4db94011d3 48 #define TERI (uint8_t)0x04
sahilmgandhi 18:6a4db94011d3 49 #define DDCD (uint8_t)0x08
sahilmgandhi 18:6a4db94011d3 50 //#define CTS (uint8_t)0x10
sahilmgandhi 18:6a4db94011d3 51 #define DSR (uint8_t)0x20
sahilmgandhi 18:6a4db94011d3 52 #define RI (uint8_t)0x40
sahilmgandhi 18:6a4db94011d3 53 #define DCD (uint8_t)0x80
sahilmgandhi 18:6a4db94011d3 54 #define IER_PWRDNENACTIVE ((uint8_t)(1<<5))
sahilmgandhi 18:6a4db94011d3 55 #define IER_MSI ((uint8_t)(1<<3))
sahilmgandhi 18:6a4db94011d3 56 #define IER_RLSI ((uint8_t)(1<<2))
sahilmgandhi 18:6a4db94011d3 57 #define IER_THRI ((uint8_t)(1<<1))
sahilmgandhi 18:6a4db94011d3 58 #define IER_RDAI ((uint8_t)(1<<0))
sahilmgandhi 18:6a4db94011d3 59 #define FCR_RXFIFOTRIGGERLEVEL_1 ((uint8_t)(0x00))
sahilmgandhi 18:6a4db94011d3 60 #define FCR_RXFIFOTRIGGERLEVEL_4 ((uint8_t)(0x40))
sahilmgandhi 18:6a4db94011d3 61 #define FCR_RXFIFOTRIGGERLEVEL_8 ((uint8_t)(0x80))
sahilmgandhi 18:6a4db94011d3 62 #define FCR_RXFIFOTRIGGERLEVEL_14 ((uint8_t)(0xC0))
sahilmgandhi 18:6a4db94011d3 63 #define FCR_DMA_MODE_0 ((uint8_t)(0<<3))
sahilmgandhi 18:6a4db94011d3 64 #define FCR_DMA_MODE_1 ((uint8_t)(1<<3))
sahilmgandhi 18:6a4db94011d3 65 #define FCR_TXFIFO_RESET ((uint8_t)(1<<2))
sahilmgandhi 18:6a4db94011d3 66 #define FCR_RXFIFO_RESET ((uint8_t)(1<<1))
sahilmgandhi 18:6a4db94011d3 67 #define FCR_FIFO_ENABLE ((uint8_t)(1<<0))
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 /** UART HW Structure Overlay */
sahilmgandhi 18:6a4db94011d3 70 typedef struct {
sahilmgandhi 18:6a4db94011d3 71 /** Base address + 0x0: Receive, transmit and divisor_LSB offset */
sahilmgandhi 18:6a4db94011d3 72 union {
sahilmgandhi 18:6a4db94011d3 73 __I uint32_t RBR; /**< Received data (8 bits wide) / read only */
sahilmgandhi 18:6a4db94011d3 74 __O uint32_t THR; /**< Data to be transmitted (8 bits wide) / write only */
sahilmgandhi 18:6a4db94011d3 75 __IO uint32_t DLL; /**< If DLAB = 1. LS byte for input to baud rate generator */
sahilmgandhi 18:6a4db94011d3 76 };
sahilmgandhi 18:6a4db94011d3 77 /** Base address + 0x4: Interrupt enable and divisor_MSB offset */
sahilmgandhi 18:6a4db94011d3 78 union {
sahilmgandhi 18:6a4db94011d3 79 union {
sahilmgandhi 18:6a4db94011d3 80 struct {
sahilmgandhi 18:6a4db94011d3 81 __IO uint32_t RX_DATA_INT :1; /**< Enables the received data interrupt, write 1 to enable */
sahilmgandhi 18:6a4db94011d3 82 __IO uint32_t TX_HOLD_INT :1; /**< Enables the transmitter holding interrupt, write 1 to enable */
sahilmgandhi 18:6a4db94011d3 83 __IO uint32_t RX_STATUS_INT :1; /**< Enables the receiver line status interrupt, write 1 to enable */
sahilmgandhi 18:6a4db94011d3 84 __IO uint32_t MODEM_STATUS_INT :1; /**< Enables the modem status interrupt, write 1 to enable */
sahilmgandhi 18:6a4db94011d3 85 __IO uint32_t PAD0 :1;
sahilmgandhi 18:6a4db94011d3 86 __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in MCR is set also */
sahilmgandhi 18:6a4db94011d3 87 __IO uint32_t PAD1 :2;
sahilmgandhi 18:6a4db94011d3 88 } BITS;
sahilmgandhi 18:6a4db94011d3 89 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 90 } IER; /** Interrupt enable offset 0x04 */
sahilmgandhi 18:6a4db94011d3 91 __IO uint32_t DLM; /**< If DLAB = 1. MS byte for input to baud rate generator */
sahilmgandhi 18:6a4db94011d3 92 };
sahilmgandhi 18:6a4db94011d3 93 /** Base address + 0x8: Interrupt status and fifo control offset*/
sahilmgandhi 18:6a4db94011d3 94 union {
sahilmgandhi 18:6a4db94011d3 95 union {
sahilmgandhi 18:6a4db94011d3 96 struct {
sahilmgandhi 18:6a4db94011d3 97 __I uint32_t INT_PEND :1; /**< Interrupt is pending if 1 */
sahilmgandhi 18:6a4db94011d3 98 __I uint32_t INT_ID :3; /**< Interrupt identification: 011-RX Line, 010-Rx Data, 110-char TO, 001-TX empty, 000-Modem status*/
sahilmgandhi 18:6a4db94011d3 99 __I uint32_t PAD0 :2;
sahilmgandhi 18:6a4db94011d3 100 __I uint32_t FIFO_EN :2; /**< Fifos enabled: 00-disabled, 01/10-undefined, 11-enabled */
sahilmgandhi 18:6a4db94011d3 101 } BITS;
sahilmgandhi 18:6a4db94011d3 102 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 103 } IIR; /** Interrupt status and fifo status offset 0x08 */
sahilmgandhi 18:6a4db94011d3 104 union {
sahilmgandhi 18:6a4db94011d3 105 struct {
sahilmgandhi 18:6a4db94011d3 106 __O uint32_t FIFO_EN :1; /**< FIFO enable, write 1 to enable */
sahilmgandhi 18:6a4db94011d3 107 __O uint32_t RX_FIFO_RST :1; /**< RX FIFO reset, write 1 to reset */
sahilmgandhi 18:6a4db94011d3 108 __O uint32_t TX_FIFO_RST :1; /**< TX FIFO reset, write 1 to reset */
sahilmgandhi 18:6a4db94011d3 109 __O uint32_t DMA_SEL :1; /**< DMA mode select */
sahilmgandhi 18:6a4db94011d3 110 __O uint32_t PAD0 :2;
sahilmgandhi 18:6a4db94011d3 111 __O uint32_t RX_FIFO_TRIG :2; /**< Receiver FIFO trigger level:00-1byte, 01-4bytes, 10-8bytes, 11-14bytes */
sahilmgandhi 18:6a4db94011d3 112 } BITS;
sahilmgandhi 18:6a4db94011d3 113 __O uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 114 } FCR; /** Fifo control offset 0x08 */
sahilmgandhi 18:6a4db94011d3 115 };
sahilmgandhi 18:6a4db94011d3 116 /** Base address + 0xC: Line control offset */
sahilmgandhi 18:6a4db94011d3 117 union {
sahilmgandhi 18:6a4db94011d3 118 struct {
sahilmgandhi 18:6a4db94011d3 119 __IO uint32_t CHAR_LEN :2; /**< Number of bits per character: 00-5bits, 01-6bits, 10:7bits, 11:8bits */
sahilmgandhi 18:6a4db94011d3 120 __IO uint32_t NUM_STOP :1; /**< Number of stop bits: 0-1bit, 1-2bits */
sahilmgandhi 18:6a4db94011d3 121 __IO uint32_t PARITY :3; /**< Parity: xx0-disable, 001-odd, 011-even, 101-stick generated/checked as 1, 111-stick generated/checked as 0 */
sahilmgandhi 18:6a4db94011d3 122 __IO uint32_t BREAK :1; /**< Set to 1 to force output to 0, set to 0 to return to normal operation */
sahilmgandhi 18:6a4db94011d3 123 __IO uint32_t DLAB :1; /**< Set to 1 to enable the DLL, DLM registers at 0x00 and 0x04 */
sahilmgandhi 18:6a4db94011d3 124 } BITS;
sahilmgandhi 18:6a4db94011d3 125 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 126 } LCR; /** Line control offset 0x0C */
sahilmgandhi 18:6a4db94011d3 127 /** Base address + 0x10: Modem control offset */
sahilmgandhi 18:6a4db94011d3 128 union {
sahilmgandhi 18:6a4db94011d3 129 struct {
sahilmgandhi 18:6a4db94011d3 130 __IO uint32_t DTR :1; /**< Data terminal ready. Write 1 to set DTR high (de-asserted), or read DTR */
sahilmgandhi 18:6a4db94011d3 131 __IO uint32_t RTS :1; /**< Request to send. Write 1 to set RTS high (de-asserted), or read RTS */
sahilmgandhi 18:6a4db94011d3 132 __IO uint32_t OUTN_CTRL :2; /**< Direct control of out2N and out1N */
sahilmgandhi 18:6a4db94011d3 133 __IO uint32_t LOOPBACK :1; /**< Write 1 to enable loop back */
sahilmgandhi 18:6a4db94011d3 134 __IO uint32_t PAD0 :3;
sahilmgandhi 18:6a4db94011d3 135 __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in IER is set also */
sahilmgandhi 18:6a4db94011d3 136 } BITS;
sahilmgandhi 18:6a4db94011d3 137 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 138 } MCR; /**< Modem control offset 0x10 */
sahilmgandhi 18:6a4db94011d3 139 /** Base address + 0x14: Line status offset */
sahilmgandhi 18:6a4db94011d3 140 union {
sahilmgandhi 18:6a4db94011d3 141 struct {
sahilmgandhi 18:6a4db94011d3 142 __O uint32_t READY :1; /**< Rx data available */
sahilmgandhi 18:6a4db94011d3 143 __O uint32_t OVERRUN_ERR :1; /**< Overrun error */
sahilmgandhi 18:6a4db94011d3 144 __O uint32_t PARITY_ERR :1; /**< Parity error */
sahilmgandhi 18:6a4db94011d3 145 __O uint32_t FRAME_ERR :1; /**< Framing error */
sahilmgandhi 18:6a4db94011d3 146 __O uint32_t BREAK_INT :1; /**< Break interrupt is set when output is kept to 0 for more than 1 bit time */
sahilmgandhi 18:6a4db94011d3 147 __O uint32_t TX_HOLD_EMPTY :1; /**< Transmit holding register empty */
sahilmgandhi 18:6a4db94011d3 148 __O uint32_t TX_EMPTY :1; /**< Transmitter empty */
sahilmgandhi 18:6a4db94011d3 149 __O uint32_t FIFO_ERR :1; /**< Receive fifo error */
sahilmgandhi 18:6a4db94011d3 150 } BITS;
sahilmgandhi 18:6a4db94011d3 151 __O uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 152 } LSR; /**< Line status offset 0x14 */
sahilmgandhi 18:6a4db94011d3 153 /** Base address + 0x18: Modem status offset */
sahilmgandhi 18:6a4db94011d3 154 union {
sahilmgandhi 18:6a4db94011d3 155 struct {
sahilmgandhi 18:6a4db94011d3 156 __O uint32_t CHG_CTSN :1; /**< CTS change since last MSR read */
sahilmgandhi 18:6a4db94011d3 157 __O uint32_t CHG_DSRN :1; /**< DSR change since last MSR read */
sahilmgandhi 18:6a4db94011d3 158 __O uint32_t CHG_RIN :1; /**< RI change since last MSR read */
sahilmgandhi 18:6a4db94011d3 159 __O uint32_t CHG_DCDN :1; /**< DCD change since last MSR read */
sahilmgandhi 18:6a4db94011d3 160 __O uint32_t CURR_CTSN :1; /**< CTS current state, 0 = asserted, 1 = de-asserted */
sahilmgandhi 18:6a4db94011d3 161 __O uint32_t CURR_DSRN :1; /**< DSR current state */
sahilmgandhi 18:6a4db94011d3 162 __O uint32_t CURR_RIN :1; /**< RI current state */
sahilmgandhi 18:6a4db94011d3 163 __O uint32_t CURR_DCDN :1; /**< DCD current state */
sahilmgandhi 18:6a4db94011d3 164 } BITS;
sahilmgandhi 18:6a4db94011d3 165 __O uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 166 } MSR; /**< Modem status offset 0x18 */
sahilmgandhi 18:6a4db94011d3 167 /** Base address + 0x1C: Scratch offset*/
sahilmgandhi 18:6a4db94011d3 168 __IO uint32_t SCR; /**< Scratch pad register */
sahilmgandhi 18:6a4db94011d3 169 } Uart16C550Reg_t, *Uart16C550Reg_pt;
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 #endif /* UART_16C550_MAP_H_ */