MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/trim_map.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file trim_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief trim register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3727 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-09-14 14:38:34 +0530 (Mon, 14 Sep 2015) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup trim
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 * <p>
sahilmgandhi 18:6a4db94011d3 31 * Rf and Analog control hw module register map
sahilmgandhi 18:6a4db94011d3 32 * </p>
sahilmgandhi 18:6a4db94011d3 33 */
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 #ifndef TRIM_MAP_H_
sahilmgandhi 18:6a4db94011d3 36 #define TRIM_MAP_H_
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 39 * *
sahilmgandhi 18:6a4db94011d3 40 * Header files *
sahilmgandhi 18:6a4db94011d3 41 * *
sahilmgandhi 18:6a4db94011d3 42 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /**************************************************************************************************
sahilmgandhi 18:6a4db94011d3 47 * *
sahilmgandhi 18:6a4db94011d3 48 * Type definitions *
sahilmgandhi 18:6a4db94011d3 49 * *
sahilmgandhi 18:6a4db94011d3 50 **************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 /** trim register map */
sahilmgandhi 18:6a4db94011d3 53 typedef struct {
sahilmgandhi 18:6a4db94011d3 54 __I uint32_t PAD0; /**< 0x1FA0 */
sahilmgandhi 18:6a4db94011d3 55 __I uint32_t MAC_ADDR_LOW; /**< 0x1FA4 */
sahilmgandhi 18:6a4db94011d3 56 __I uint32_t MAC_ADDR_HIGH; /**< 0x1FA8 */
sahilmgandhi 18:6a4db94011d3 57 __I uint32_t TRIM_32K_EXT; /**< 0x1FAC */
sahilmgandhi 18:6a4db94011d3 58 __I uint32_t TRIM_32M_EXT; /**< 0x1FB0 */
sahilmgandhi 18:6a4db94011d3 59 __I uint32_t FVVDH_COMP_TH; /**< 0x1FB4 */
sahilmgandhi 18:6a4db94011d3 60 union {
sahilmgandhi 18:6a4db94011d3 61 struct {
sahilmgandhi 18:6a4db94011d3 62 __I uint32_t CHANNEL11:4;
sahilmgandhi 18:6a4db94011d3 63 __I uint32_t CHANNEL12:4;
sahilmgandhi 18:6a4db94011d3 64 __I uint32_t CHANNEL13:4;
sahilmgandhi 18:6a4db94011d3 65 __I uint32_t CHANNEL14:4;
sahilmgandhi 18:6a4db94011d3 66 __I uint32_t CHANNEL15:4;
sahilmgandhi 18:6a4db94011d3 67 __I uint32_t CHANNEL16:4;
sahilmgandhi 18:6a4db94011d3 68 __I uint32_t CHANNEL17:4;
sahilmgandhi 18:6a4db94011d3 69 __I uint32_t CHANNEL18:4;
sahilmgandhi 18:6a4db94011d3 70 } BITS;
sahilmgandhi 18:6a4db94011d3 71 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 72 } TX_VCO_LUT1; /**< 0x1FB8 */
sahilmgandhi 18:6a4db94011d3 73 union {
sahilmgandhi 18:6a4db94011d3 74 struct {
sahilmgandhi 18:6a4db94011d3 75 __I uint32_t CHANNEL19:4;
sahilmgandhi 18:6a4db94011d3 76 __I uint32_t CHANNEL20:4;
sahilmgandhi 18:6a4db94011d3 77 __I uint32_t CHANNEL21:4;
sahilmgandhi 18:6a4db94011d3 78 __I uint32_t CHANNEL22:4;
sahilmgandhi 18:6a4db94011d3 79 __I uint32_t CHANNEL23:4;
sahilmgandhi 18:6a4db94011d3 80 __I uint32_t CHANNEL24:4;
sahilmgandhi 18:6a4db94011d3 81 __I uint32_t CHANNEL25:4;
sahilmgandhi 18:6a4db94011d3 82 __I uint32_t CHANNEL26:4;
sahilmgandhi 18:6a4db94011d3 83 } BITS;
sahilmgandhi 18:6a4db94011d3 84 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 85 } TX_VCO_LUT2; /**< 0x1FBC */
sahilmgandhi 18:6a4db94011d3 86 union {
sahilmgandhi 18:6a4db94011d3 87 struct {
sahilmgandhi 18:6a4db94011d3 88 __I uint32_t CHANNEL11:4;
sahilmgandhi 18:6a4db94011d3 89 __I uint32_t CHANNEL12:4;
sahilmgandhi 18:6a4db94011d3 90 __I uint32_t CHANNEL13:4;
sahilmgandhi 18:6a4db94011d3 91 __I uint32_t CHANNEL14:4;
sahilmgandhi 18:6a4db94011d3 92 __I uint32_t CHANNEL15:4;
sahilmgandhi 18:6a4db94011d3 93 __I uint32_t CHANNEL16:4;
sahilmgandhi 18:6a4db94011d3 94 __I uint32_t CHANNEL17:4;
sahilmgandhi 18:6a4db94011d3 95 __I uint32_t CHANNEL18:4;
sahilmgandhi 18:6a4db94011d3 96 } BITS;
sahilmgandhi 18:6a4db94011d3 97 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 98 } RX_VCO_LUT1; /**< 0x1FC0 */
sahilmgandhi 18:6a4db94011d3 99 union {
sahilmgandhi 18:6a4db94011d3 100 struct {
sahilmgandhi 18:6a4db94011d3 101 __I uint32_t CHANNEL19:4;
sahilmgandhi 18:6a4db94011d3 102 __I uint32_t CHANNEL20:4;
sahilmgandhi 18:6a4db94011d3 103 __I uint32_t CHANNEL21:4;
sahilmgandhi 18:6a4db94011d3 104 __I uint32_t CHANNEL22:4;
sahilmgandhi 18:6a4db94011d3 105 __I uint32_t CHANNEL23:4;
sahilmgandhi 18:6a4db94011d3 106 __I uint32_t CHANNEL24:4;
sahilmgandhi 18:6a4db94011d3 107 __I uint32_t CHANNEL25:4;
sahilmgandhi 18:6a4db94011d3 108 __I uint32_t CHANNEL26:4;
sahilmgandhi 18:6a4db94011d3 109 } BITS;
sahilmgandhi 18:6a4db94011d3 110 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 111 } RX_VCO_LUT2; /**< 0x1FC4 */
sahilmgandhi 18:6a4db94011d3 112 __I uint32_t ON_RESERVED0; /**< 0x1FC8 */
sahilmgandhi 18:6a4db94011d3 113 __I uint32_t ON_RESERVED1; /**< 0x1FCC */
sahilmgandhi 18:6a4db94011d3 114 __I uint32_t ADC_OFFSET_TRIM; /**< 0x1FD0 */
sahilmgandhi 18:6a4db94011d3 115 __I uint32_t TX_PRE_CHIPS; /**< 0x1FD4 */
sahilmgandhi 18:6a4db94011d3 116 __I uint32_t TX_TRIM; /**< 0x1FD8 */
sahilmgandhi 18:6a4db94011d3 117 __I uint32_t PLL_VCO_TAP_LOCATION; /**< 0x1FDC */
sahilmgandhi 18:6a4db94011d3 118 __I uint32_t PLL_TRIM; /**< 0x1FE0 */
sahilmgandhi 18:6a4db94011d3 119 __I uint32_t RSSI_OFFSET; /**< 0x1FE4 */
sahilmgandhi 18:6a4db94011d3 120 __I uint32_t RX_CHAIN_TRIM; /**< 0x1FE8 */
sahilmgandhi 18:6a4db94011d3 121 __I uint32_t PMU_TRIM; /**< 0x1FEC */
sahilmgandhi 18:6a4db94011d3 122 __I uint32_t WR_SEED_RD_RAND; /**< 0x1FF0 */
sahilmgandhi 18:6a4db94011d3 123 __I uint32_t WAFER_LOCATION; /**< 0x1FF4 */
sahilmgandhi 18:6a4db94011d3 124 __I uint32_t LOT_NUMBER; /**< 0x1FF8 */
sahilmgandhi 18:6a4db94011d3 125 __I uint32_t REVISION_CODE; /**< 0x1FFC */
sahilmgandhi 18:6a4db94011d3 126 } TrimReg_t, *TrimReg_pt;
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 /** User defined trim register map */
sahilmgandhi 18:6a4db94011d3 130 typedef struct {
sahilmgandhi 18:6a4db94011d3 131 __IO uint32_t MAC_ADDRESS_LOW; /**< 0x2800 */
sahilmgandhi 18:6a4db94011d3 132 __IO uint32_t MAC_ADDRESS_HIGH; /**< 0x2804 */
sahilmgandhi 18:6a4db94011d3 133 __IO uint32_t TRIM_32K_EXT; /**< 0x2808 */
sahilmgandhi 18:6a4db94011d3 134 __IO uint32_t TRIM_32M_EXT; /**< 0x280C */
sahilmgandhi 18:6a4db94011d3 135 __IO uint32_t RSSI_OFFSET; /**< 0x2810 */
sahilmgandhi 18:6a4db94011d3 136 __IO uint32_t TX_TRIM; /**< 0x2814 */
sahilmgandhi 18:6a4db94011d3 137 } UserTrimReg_t, *UserTrimReg_pt;
sahilmgandhi 18:6a4db94011d3 138 #endif /* TRIM_MAP_H_ */