MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file spi_api.c
sahilmgandhi 18:6a4db94011d3 4 * @brief Implementation of a sleep functionality
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 0.1 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 02-05-2016 $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup spi_api
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 * SPI implementation
sahilmgandhi 18:6a4db94011d3 31 *
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33 #if DEVICE_SPI
sahilmgandhi 18:6a4db94011d3 34 #include "spi.h"
sahilmgandhi 18:6a4db94011d3 35 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 36 #include "objects.h"
sahilmgandhi 18:6a4db94011d3 37 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 38 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 39 #include "memory_map.h"
sahilmgandhi 18:6a4db94011d3 40 #include "spi_ipc7207_map.h"
sahilmgandhi 18:6a4db94011d3 41 #include "crossbar.h"
sahilmgandhi 18:6a4db94011d3 42 #include "clock.h"
sahilmgandhi 18:6a4db94011d3 43 #include "cmsis_nvic.h"
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 #define SPI_FREQ_MAX 4000000
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
sahilmgandhi 18:6a4db94011d3 49 {
sahilmgandhi 18:6a4db94011d3 50 fSpiInit(obj, mosi, miso, sclk, ssel);
sahilmgandhi 18:6a4db94011d3 51 }
sahilmgandhi 18:6a4db94011d3 52 void spi_free(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 53 {
sahilmgandhi 18:6a4db94011d3 54 fSpiClose(obj);
sahilmgandhi 18:6a4db94011d3 55 }
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 void spi_format(spi_t *obj, int bits, int mode, int slave)
sahilmgandhi 18:6a4db94011d3 58 {
sahilmgandhi 18:6a4db94011d3 59 /* Clear word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
sahilmgandhi 18:6a4db94011d3 60 obj->membase->CONTROL.WORD &= ~(uint32_t)((True << SPI_WORD_WIDTH_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 61 (True << SPI_SLAVE_MASTER_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 62 (True << SPI_CPOL_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 63 (True << SPI_CPHA_BIT_POS));
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /* Configure word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
sahilmgandhi 18:6a4db94011d3 66 obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) << SPI_WORD_WIDTH_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 67 (!slave << SPI_SLAVE_MASTER_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 68 ((mode >> 0x1) << SPI_CPOL_BIT_POS) |
sahilmgandhi 18:6a4db94011d3 69 ((mode & 0x1) << SPI_CPHA_BIT_POS));
sahilmgandhi 18:6a4db94011d3 70 }
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 void spi_frequency(spi_t *obj, int hz)
sahilmgandhi 18:6a4db94011d3 73 {
sahilmgandhi 18:6a4db94011d3 74 /* If the frequency is outside the allowable range, set it to the max */
sahilmgandhi 18:6a4db94011d3 75 if(hz > SPI_FREQ_MAX) {
sahilmgandhi 18:6a4db94011d3 76 hz = SPI_FREQ_MAX;
sahilmgandhi 18:6a4db94011d3 77 }
sahilmgandhi 18:6a4db94011d3 78 obj->membase->FDIV = ((fClockGetPeriphClockfrequency() / hz) >> 1) - 1;
sahilmgandhi 18:6a4db94011d3 79 }
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 int spi_master_write(spi_t *obj, int value)
sahilmgandhi 18:6a4db94011d3 82 {
sahilmgandhi 18:6a4db94011d3 83 return(fSpiWriteB(obj, value));
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 int spi_busy(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 87 {
sahilmgandhi 18:6a4db94011d3 88 return(obj->membase->STATUS.BITS.XFER_IP);
sahilmgandhi 18:6a4db94011d3 89 }
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 uint8_t spi_get_module(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 92 {
sahilmgandhi 18:6a4db94011d3 93 if(obj->membase == SPI1REG) {
sahilmgandhi 18:6a4db94011d3 94 return 0; /* UART #1 */
sahilmgandhi 18:6a4db94011d3 95 } else if(obj->membase == SPI2REG) {
sahilmgandhi 18:6a4db94011d3 96 return 1; /* UART #2 */
sahilmgandhi 18:6a4db94011d3 97 } else {
sahilmgandhi 18:6a4db94011d3 98 return 2; /* Invalid address */
sahilmgandhi 18:6a4db94011d3 99 }
sahilmgandhi 18:6a4db94011d3 100 }
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 int spi_slave_receive(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 103 {
sahilmgandhi 18:6a4db94011d3 104 if(obj->membase->STATUS.BITS.RX_EMPTY != True){ /* if receive status is not empty */
sahilmgandhi 18:6a4db94011d3 105 return True; /* Byte available to read */
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107 return False; /* Byte not available to read */
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 int spi_slave_read(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 111 {
sahilmgandhi 18:6a4db94011d3 112 int byte;
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
sahilmgandhi 18:6a4db94011d3 115 byte = obj->membase->RX_DATA;
sahilmgandhi 18:6a4db94011d3 116 return byte;
sahilmgandhi 18:6a4db94011d3 117 }
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 void spi_slave_write(spi_t *obj, int value)
sahilmgandhi 18:6a4db94011d3 120 {
sahilmgandhi 18:6a4db94011d3 121 while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
sahilmgandhi 18:6a4db94011d3 122 obj->membase->TX_DATA = value;
sahilmgandhi 18:6a4db94011d3 123 }
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 #if DEVICE_SPI_ASYNCH /* TODO Not yet implemented */
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint)
sahilmgandhi 18:6a4db94011d3 128 {
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 uint32_t i;
sahilmgandhi 18:6a4db94011d3 131 int ndata = 0;
sahilmgandhi 18:6a4db94011d3 132 uint16_t *tx_ptr = (uint16_t *) tx;
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 if(obj->spi->CONTROL.BITS.WORD_WIDTH == 0) {
sahilmgandhi 18:6a4db94011d3 135 /* Word size 8 bits */
sahilmgandhi 18:6a4db94011d3 136 WORD_WIDTH_MASK = 0xFF;
sahilmgandhi 18:6a4db94011d3 137 } else if(obj->spi->CONTROL.BITS.WORD_WIDTH == 1) {
sahilmgandhi 18:6a4db94011d3 138 /* Word size 16 bits */
sahilmgandhi 18:6a4db94011d3 139 WORD_WIDTH_MASK = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 140 } else {
sahilmgandhi 18:6a4db94011d3 141 /* Word size 32 bits */
sahilmgandhi 18:6a4db94011d3 142 WORD_WIDTH_MASK = 0xFFFFFFFF;
sahilmgandhi 18:6a4db94011d3 143 }
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 //frame size
sahilmgandhi 18:6a4db94011d3 146 if(tx_length == 0) {
sahilmgandhi 18:6a4db94011d3 147 tx_length = rx_length;
sahilmgandhi 18:6a4db94011d3 148 tx = (void*) 0;
sahilmgandhi 18:6a4db94011d3 149 }
sahilmgandhi 18:6a4db94011d3 150 //set tx rx buffer
sahilmgandhi 18:6a4db94011d3 151 obj->tx_buff.buffer = (void *)tx;
sahilmgandhi 18:6a4db94011d3 152 obj->rx_buff.buffer = rx;
sahilmgandhi 18:6a4db94011d3 153 obj->tx_buff.length = tx_length;
sahilmgandhi 18:6a4db94011d3 154 obj->rx_buff.length = rx_length;
sahilmgandhi 18:6a4db94011d3 155 obj->tx_buff.pos = 0;
sahilmgandhi 18:6a4db94011d3 156 obj->rx_buff.pos = 0;
sahilmgandhi 18:6a4db94011d3 157 obj->tx_buff.width = bit_width;
sahilmgandhi 18:6a4db94011d3 158 obj->rx_buff.width = bit_width;
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 if((obj->spi.bits == 9) && (tx != 0)) {
sahilmgandhi 18:6a4db94011d3 162 // Make sure we don't have inadvertent non-zero bits outside 9-bit frames which could trigger unwanted operation
sahilmgandhi 18:6a4db94011d3 163 for(i = 0; i < (tx_length / 2); i++) {
sahilmgandhi 18:6a4db94011d3 164 tx_ptr[i] &= 0x1FF;
sahilmgandhi 18:6a4db94011d3 165 }
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 // enable events
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 obj->spi.event |= event;
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 // set sleep_level
sahilmgandhi 18:6a4db94011d3 175 enable irq
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 //write async
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 if ( && ) {
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 }
sahilmgandhi 18:6a4db94011d3 182 while ((obj->tx_buff.pos < obj->tx_buff.length) &&
sahilmgandhi 18:6a4db94011d3 183 (obj->spi->STATUS.BITS.TX_FULL == False) &&
sahilmgandhi 18:6a4db94011d3 184 (obj->spi->STATUS.BITS.RX_FULL == False)) {
sahilmgandhi 18:6a4db94011d3 185 // spi_buffer_tx_write(obj);
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 if (obj->tx_buff.buffer == (void *)0) {
sahilmgandhi 18:6a4db94011d3 188 data = SPI_FILL_WORD;
sahilmgandhi 18:6a4db94011d3 189 } else {
sahilmgandhi 18:6a4db94011d3 190 uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
sahilmgandhi 18:6a4db94011d3 191 data = tx[obj->tx_buff.pos] & 0xFF;
sahilmgandhi 18:6a4db94011d3 192 }
sahilmgandhi 18:6a4db94011d3 193 obj->spi->TX_DATA = data;
sahilmgandhi 18:6a4db94011d3 194 }
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 ndata++;
sahilmgandhi 18:6a4db94011d3 197 }
sahilmgandhi 18:6a4db94011d3 198 return ndata;
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 }
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 uint32_t spi_irq_handler_asynch(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 203 {
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 uint8_t spi_active(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 207 {
sahilmgandhi 18:6a4db94011d3 208 }
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 void spi_abort_asynch(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 211 {
sahilmgandhi 18:6a4db94011d3 212 }
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 #endif /* DEVICE_SPI_ASYNCH */
sahilmgandhi 18:6a4db94011d3 215 #endif /* DEVICE_SPI */