MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file pmu_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief PMU hw module register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3372 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-04-22 12:18:18 +0530 (Wed, 22 Apr 2015) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup pmu
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 #ifndef PMU_MAP_H_
sahilmgandhi 18:6a4db94011d3 33 #define PMU_MAP_H_
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 36 * *
sahilmgandhi 18:6a4db94011d3 37 * Header files *
sahilmgandhi 18:6a4db94011d3 38 * *
sahilmgandhi 18:6a4db94011d3 39 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 /**************************************************************************************************
sahilmgandhi 18:6a4db94011d3 44 * *
sahilmgandhi 18:6a4db94011d3 45 * Type definitions *
sahilmgandhi 18:6a4db94011d3 46 * *
sahilmgandhi 18:6a4db94011d3 47 **************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** PMU control
sahilmgandhi 18:6a4db94011d3 50 * The Power Management Unit (PMU) is used to control the differing power modes.
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52 typedef struct {
sahilmgandhi 18:6a4db94011d3 53 union {
sahilmgandhi 18:6a4db94011d3 54 struct {
sahilmgandhi 18:6a4db94011d3 55 __IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 – Coma */
sahilmgandhi 18:6a4db94011d3 56 __IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
sahilmgandhi 18:6a4db94011d3 57 __IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
sahilmgandhi 18:6a4db94011d3 58 __IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 – Disabled (off), 1 – Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
sahilmgandhi 18:6a4db94011d3 59 __IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 – Enabled (on), 1 – Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
sahilmgandhi 18:6a4db94011d3 60 __IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 – Enabled (on), 1 – Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */
sahilmgandhi 18:6a4db94011d3 61 __IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
sahilmgandhi 18:6a4db94011d3 62 __IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
sahilmgandhi 18:6a4db94011d3 63 __IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 – Normal power behavior when the debugger is present, 1 – When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */
sahilmgandhi 18:6a4db94011d3 64 __IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
sahilmgandhi 18:6a4db94011d3 65 __IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
sahilmgandhi 18:6a4db94011d3 66 __IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
sahilmgandhi 18:6a4db94011d3 67 } BITS;
sahilmgandhi 18:6a4db94011d3 68 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 69 } CONTROL; /* 0x4001D000 */
sahilmgandhi 18:6a4db94011d3 70 union {
sahilmgandhi 18:6a4db94011d3 71 struct {
sahilmgandhi 18:6a4db94011d3 72 __I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */
sahilmgandhi 18:6a4db94011d3 73 __I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 } BITS;
sahilmgandhi 18:6a4db94011d3 76 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 77 } STATUS; /* 0x4001D004 */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 __IO uint32_t PLACEHOLDER; /* 0x4001D008 */
sahilmgandhi 18:6a4db94011d3 80 __IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */
sahilmgandhi 18:6a4db94011d3 81 __IO uint32_t PLACEHOLDER1; /* 0x4001D010 */
sahilmgandhi 18:6a4db94011d3 82 __IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */
sahilmgandhi 18:6a4db94011d3 83 union {
sahilmgandhi 18:6a4db94011d3 84 struct {
sahilmgandhi 18:6a4db94011d3 85 __IO uint32_t TH:6; /**< Threshold */
sahilmgandhi 18:6a4db94011d3 86 __I uint32_t PAD:2;
sahilmgandhi 18:6a4db94011d3 87 __I uint32_t UVIVAL:6; /**< UVI value */
sahilmgandhi 18:6a4db94011d3 88 } BITS;
sahilmgandhi 18:6a4db94011d3 89 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 90 } UVI_TBASE; /* 0x4001D018 */
sahilmgandhi 18:6a4db94011d3 91 __IO uint32_t SRAM_TRIM; /* 0x4001D01C */
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 } PmuReg_t, *PmuReg_pt;
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 #endif /* PMU_MAP_H_ */