MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file dma_map.h
sahilmgandhi 18:6a4db94011d3 4 * @brief DMA hw module register map
sahilmgandhi 18:6a4db94011d3 5 * @internal
sahilmgandhi 18:6a4db94011d3 6 * @author ON Semiconductor
sahilmgandhi 18:6a4db94011d3 7 * $Rev: 3415 $
sahilmgandhi 18:6a4db94011d3 8 * $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
sahilmgandhi 18:6a4db94011d3 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
sahilmgandhi 18:6a4db94011d3 12 * under limited terms and conditions. The terms and conditions pertaining to the software
sahilmgandhi 18:6a4db94011d3 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
sahilmgandhi 18:6a4db94011d3 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
sahilmgandhi 18:6a4db94011d3 15 * if applicable the software license agreement. Do not use this software and/or
sahilmgandhi 18:6a4db94011d3 16 * documentation unless you have carefully read and you agree to the limited terms and
sahilmgandhi 18:6a4db94011d3 17 * conditions. By using this software and/or documentation, you agree to the limited
sahilmgandhi 18:6a4db94011d3 18 * terms and conditions.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
sahilmgandhi 18:6a4db94011d3 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 25 * @endinternal
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * @ingroup dma
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @details
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 #ifndef DMA_MAP_H_
sahilmgandhi 18:6a4db94011d3 33 #define DMA_MAP_H_
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 /*************************************************************************************************
sahilmgandhi 18:6a4db94011d3 36 * *
sahilmgandhi 18:6a4db94011d3 37 * Header files *
sahilmgandhi 18:6a4db94011d3 38 * *
sahilmgandhi 18:6a4db94011d3 39 *************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #include "architecture.h"
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 /**************************************************************************************************
sahilmgandhi 18:6a4db94011d3 44 * *
sahilmgandhi 18:6a4db94011d3 45 * Type definitions *
sahilmgandhi 18:6a4db94011d3 46 * *
sahilmgandhi 18:6a4db94011d3 47 **************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** DMA control HW registers structure overlay */
sahilmgandhi 18:6a4db94011d3 50 typedef struct {
sahilmgandhi 18:6a4db94011d3 51 union {
sahilmgandhi 18:6a4db94011d3 52 struct {
sahilmgandhi 18:6a4db94011d3 53 __IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
sahilmgandhi 18:6a4db94011d3 54 __IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
sahilmgandhi 18:6a4db94011d3 55 } BITS;
sahilmgandhi 18:6a4db94011d3 56 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 57 } CONTROL; /**< Control register */
sahilmgandhi 18:6a4db94011d3 58 __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
sahilmgandhi 18:6a4db94011d3 59 __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
sahilmgandhi 18:6a4db94011d3 60 __IO uint32_t SIZE; /**< Lenght of the entire transfer */
sahilmgandhi 18:6a4db94011d3 61 union {
sahilmgandhi 18:6a4db94011d3 62 struct {
sahilmgandhi 18:6a4db94011d3 63 __I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
sahilmgandhi 18:6a4db94011d3 64 __I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
sahilmgandhi 18:6a4db94011d3 65 __I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
sahilmgandhi 18:6a4db94011d3 66 } BITS;
sahilmgandhi 18:6a4db94011d3 67 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 68 } STATUS; /**< Status register */
sahilmgandhi 18:6a4db94011d3 69 union {
sahilmgandhi 18:6a4db94011d3 70 struct {
sahilmgandhi 18:6a4db94011d3 71 __IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
sahilmgandhi 18:6a4db94011d3 72 __IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
sahilmgandhi 18:6a4db94011d3 73 __IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
sahilmgandhi 18:6a4db94011d3 74 } BITS;
sahilmgandhi 18:6a4db94011d3 75 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 76 } INT_ENABLE; /**< Interrupt enable */
sahilmgandhi 18:6a4db94011d3 77 union {
sahilmgandhi 18:6a4db94011d3 78 struct {
sahilmgandhi 18:6a4db94011d3 79 __IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
sahilmgandhi 18:6a4db94011d3 80 __IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
sahilmgandhi 18:6a4db94011d3 81 __IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
sahilmgandhi 18:6a4db94011d3 82 } BITS;
sahilmgandhi 18:6a4db94011d3 83 __IO uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 84 } INT_CLEAR; /**< Interrupt clear */
sahilmgandhi 18:6a4db94011d3 85 union {
sahilmgandhi 18:6a4db94011d3 86 struct {
sahilmgandhi 18:6a4db94011d3 87 __I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
sahilmgandhi 18:6a4db94011d3 88 __I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
sahilmgandhi 18:6a4db94011d3 89 __I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
sahilmgandhi 18:6a4db94011d3 90 } BITS;
sahilmgandhi 18:6a4db94011d3 91 __I uint32_t WORD;
sahilmgandhi 18:6a4db94011d3 92 } INT_STATUS; /**< Interrupt status */
sahilmgandhi 18:6a4db94011d3 93 } DmaReg_t, *DmaReg_pt;
sahilmgandhi 18:6a4db94011d3 94 #endif /* DMA_MAP_H_ */