MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17 #include "us_ticker_api.h"
sahilmgandhi 18:6a4db94011d3 18 #include "PeripheralNames.h"
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 static int us_ticker_inited = 0;
sahilmgandhi 18:6a4db94011d3 21 int MRT_Clock_MHz;
sahilmgandhi 18:6a4db94011d3 22 unsigned int ticker_fullcount_us;
sahilmgandhi 18:6a4db94011d3 23 unsigned long int ticker_expired_count_us = 0;
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 #define US_TICKER_TIMER_IRQn MRT_IRQn
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 void us_ticker_init(void) {
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 if (us_ticker_inited)
sahilmgandhi 18:6a4db94011d3 30 return;
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 us_ticker_inited = 1;
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 // Calculate MRT clock value (MRT has no prescaler)
sahilmgandhi 18:6a4db94011d3 35 MRT_Clock_MHz = (SystemCoreClock / 1000000);
sahilmgandhi 18:6a4db94011d3 36 // Calculate fullcounter value in us (MRT has 31 bits and clock is 30MHz)
sahilmgandhi 18:6a4db94011d3 37 ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz;
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 // Enable the MRT clock
sahilmgandhi 18:6a4db94011d3 40 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 // Clear peripheral reset the MRT
sahilmgandhi 18:6a4db94011d3 43 LPC_SYSCON->PRESETCTRL |= (1 << 7);
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
sahilmgandhi 18:6a4db94011d3 46 LPC_MRT->INTVAL0 = 0xFFFFFFFFUL;
sahilmgandhi 18:6a4db94011d3 47 // Enable Ch0 interrupt, Mode 0 is Repeat Interrupt
sahilmgandhi 18:6a4db94011d3 48 LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0);
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
sahilmgandhi 18:6a4db94011d3 51 LPC_MRT->INTVAL1 = 0x80000000UL;
sahilmgandhi 18:6a4db94011d3 52 // Disable ch1 interrupt, Mode 0 is Repeat Interrupt
sahilmgandhi 18:6a4db94011d3 53 LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0);
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 // Set MRT interrupt vector
sahilmgandhi 18:6a4db94011d3 56 NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
sahilmgandhi 18:6a4db94011d3 57 NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
sahilmgandhi 18:6a4db94011d3 58 }
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 //TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc)
sahilmgandhi 18:6a4db94011d3 61 uint32_t us_ticker_read() {
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 if (!us_ticker_inited)
sahilmgandhi 18:6a4db94011d3 64 us_ticker_init();
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 // Generate ticker value
sahilmgandhi 18:6a4db94011d3 67 // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
sahilmgandhi 18:6a4db94011d3 68 // Calculate expected value using number of expired times to mimic a 32bit timer @ 1 MHz
sahilmgandhi 18:6a4db94011d3 69 return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us;
sahilmgandhi 18:6a4db94011d3 70 }
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 //TIMER1 is used for Timestamped interrupts (Ticker(), Timeout())
sahilmgandhi 18:6a4db94011d3 73 void us_ticker_set_interrupt(timestamp_t timestamp) {
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
sahilmgandhi 18:6a4db94011d3 76 // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
sahilmgandhi 18:6a4db94011d3 77 // Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz.
sahilmgandhi 18:6a4db94011d3 78 // The calculated counter interval until the next timestamp will be truncated and an
sahilmgandhi 18:6a4db94011d3 79 // 'early' interrupt will be generated in case the max required count interval exceeds
sahilmgandhi 18:6a4db94011d3 80 // the available 31 bits space. However, the mbed us_ticker interrupt handler will
sahilmgandhi 18:6a4db94011d3 81 // check current time against the next scheduled timestamp and simply re-issue the
sahilmgandhi 18:6a4db94011d3 82 // same interrupt again when needed. The calculated counter interval will now be smaller.
sahilmgandhi 18:6a4db94011d3 83 LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL);
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 // Enable interrupt
sahilmgandhi 18:6a4db94011d3 86 LPC_MRT->CTRL1 |= 1;
sahilmgandhi 18:6a4db94011d3 87 }
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 //Disable Timestamped interrupts triggered by TIMER1
sahilmgandhi 18:6a4db94011d3 90 void us_ticker_disable_interrupt() {
sahilmgandhi 18:6a4db94011d3 91 //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
sahilmgandhi 18:6a4db94011d3 92 LPC_MRT->CTRL1 &= ~1;
sahilmgandhi 18:6a4db94011d3 93 }
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 void us_ticker_clear_interrupt() {
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
sahilmgandhi 18:6a4db94011d3 98 if (LPC_MRT->STAT1 & 1)
sahilmgandhi 18:6a4db94011d3 99 LPC_MRT->STAT1 = 1;
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 //Timer0 for us counter (31 bits downcounter @ SystemCoreClock)
sahilmgandhi 18:6a4db94011d3 102 if (LPC_MRT->STAT0 & 1) {
sahilmgandhi 18:6a4db94011d3 103 LPC_MRT->STAT0 = 1;
sahilmgandhi 18:6a4db94011d3 104 ticker_expired_count_us += ticker_fullcount_us;
sahilmgandhi 18:6a4db94011d3 105 }
sahilmgandhi 18:6a4db94011d3 106 }