MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC82X/serial_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 // math.h required for floating point operations for baud rate calculation
sahilmgandhi 18:6a4db94011d3 17 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 18 #include <math.h>
sahilmgandhi 18:6a4db94011d3 19 #include <string.h>
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "serial_api.h"
sahilmgandhi 18:6a4db94011d3 22 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 23 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 24 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #if DEVICE_SERIAL
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 29 * INITIALIZATION
sahilmgandhi 18:6a4db94011d3 30 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 31 #define UART_NUM 3
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 static const SWM_Map SWM_UART_TX[] = {
sahilmgandhi 18:6a4db94011d3 34 {0, 0},
sahilmgandhi 18:6a4db94011d3 35 {1, 8},
sahilmgandhi 18:6a4db94011d3 36 {2, 16},
sahilmgandhi 18:6a4db94011d3 37 };
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 static const SWM_Map SWM_UART_RX[] = {
sahilmgandhi 18:6a4db94011d3 40 {0, 8},
sahilmgandhi 18:6a4db94011d3 41 {1, 16},
sahilmgandhi 18:6a4db94011d3 42 {2, 24},
sahilmgandhi 18:6a4db94011d3 43 };
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 static const SWM_Map SWM_UART_RTS[] = {
sahilmgandhi 18:6a4db94011d3 46 {0, 16},
sahilmgandhi 18:6a4db94011d3 47 {1, 24},
sahilmgandhi 18:6a4db94011d3 48 {3, 0},
sahilmgandhi 18:6a4db94011d3 49 };
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 static const SWM_Map SWM_UART_CTS[] = {
sahilmgandhi 18:6a4db94011d3 52 {0, 24},
sahilmgandhi 18:6a4db94011d3 53 {2, 0},
sahilmgandhi 18:6a4db94011d3 54 {3, 8}
sahilmgandhi 18:6a4db94011d3 55 };
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 // bit flags for used UARTs
sahilmgandhi 18:6a4db94011d3 58 static unsigned char uart_used = 0;
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 static int get_available_uart(void)
sahilmgandhi 18:6a4db94011d3 61 {
sahilmgandhi 18:6a4db94011d3 62 int i;
sahilmgandhi 18:6a4db94011d3 63 for (i=0; i<UART_NUM; i++) {
sahilmgandhi 18:6a4db94011d3 64 if ((uart_used & (1 << i)) == 0)
sahilmgandhi 18:6a4db94011d3 65 return i;
sahilmgandhi 18:6a4db94011d3 66 }
sahilmgandhi 18:6a4db94011d3 67 return -1;
sahilmgandhi 18:6a4db94011d3 68 }
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 #define UART_EN (0x01<<0)
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 #define CTS_DELTA (0x01<<5)
sahilmgandhi 18:6a4db94011d3 73 #define RXBRK (0x01<<10)
sahilmgandhi 18:6a4db94011d3 74 #define DELTA_RXBRK (0x01<<11)
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 #define RXRDY (0x01<<0)
sahilmgandhi 18:6a4db94011d3 77 #define TXRDY (0x01<<2)
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 #define RXRDYEN RXRDY
sahilmgandhi 18:6a4db94011d3 80 #define TXRDYEN TXRDY
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 #define TXBRKEN (0x01<<1)
sahilmgandhi 18:6a4db94011d3 83 #define CTSEN (0x01<<9)
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 static uint32_t UARTSysClk;
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 static uint32_t serial_irq_ids[UART_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 88 static uart_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 int stdio_uart_inited = 0;
sahilmgandhi 18:6a4db94011d3 91 serial_t stdio_uart;
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 static int check_duplication(serial_t *obj, PinName tx, PinName rx)
sahilmgandhi 18:6a4db94011d3 94 {
sahilmgandhi 18:6a4db94011d3 95 if (uart_used == 0)
sahilmgandhi 18:6a4db94011d3 96 return 0;
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 const SWM_Map *swm;
sahilmgandhi 18:6a4db94011d3 99 uint32_t assigned_tx, assigned_rx;
sahilmgandhi 18:6a4db94011d3 100 int ch;
sahilmgandhi 18:6a4db94011d3 101 for (ch=0; ch<UART_NUM; ch++) {
sahilmgandhi 18:6a4db94011d3 102 // read assigned TX in the UART channel of switch matrix
sahilmgandhi 18:6a4db94011d3 103 swm = &SWM_UART_TX[ch];
sahilmgandhi 18:6a4db94011d3 104 assigned_tx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 105 assigned_tx = assigned_tx >> swm->offset;
sahilmgandhi 18:6a4db94011d3 106 // read assigned RX in the UART channel of switch matrix
sahilmgandhi 18:6a4db94011d3 107 swm = &SWM_UART_RX[ch];
sahilmgandhi 18:6a4db94011d3 108 assigned_rx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 109 assigned_rx = assigned_rx >> swm->offset;
sahilmgandhi 18:6a4db94011d3 110 if ((assigned_tx == (uint32_t)(tx >> PIN_SHIFT)) && (assigned_rx == (uint32_t)(rx >> PIN_SHIFT))) {
sahilmgandhi 18:6a4db94011d3 111 obj->index = ch;
sahilmgandhi 18:6a4db94011d3 112 obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * ch));
sahilmgandhi 18:6a4db94011d3 113 return 1;
sahilmgandhi 18:6a4db94011d3 114 }
sahilmgandhi 18:6a4db94011d3 115 }
sahilmgandhi 18:6a4db94011d3 116 return 0;
sahilmgandhi 18:6a4db94011d3 117 }
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 void serial_init(serial_t *obj, PinName tx, PinName rx)
sahilmgandhi 18:6a4db94011d3 120 {
sahilmgandhi 18:6a4db94011d3 121 int is_stdio_uart = 0;
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 if (check_duplication(obj, tx, rx) == 1)
sahilmgandhi 18:6a4db94011d3 124 return;
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 int uart_n = get_available_uart();
sahilmgandhi 18:6a4db94011d3 127 if (uart_n == -1) {
sahilmgandhi 18:6a4db94011d3 128 error("No available UART");
sahilmgandhi 18:6a4db94011d3 129 }
sahilmgandhi 18:6a4db94011d3 130 obj->index = uart_n;
sahilmgandhi 18:6a4db94011d3 131 obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * uart_n));
sahilmgandhi 18:6a4db94011d3 132 uart_used |= (1 << uart_n);
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 const SWM_Map *swm;
sahilmgandhi 18:6a4db94011d3 135 uint32_t regVal;
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 swm = &SWM_UART_TX[uart_n];
sahilmgandhi 18:6a4db94011d3 138 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 139 LPC_SWM->PINASSIGN[swm->n] = regVal | ((tx >> PIN_SHIFT) << swm->offset);
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 swm = &SWM_UART_RX[uart_n];
sahilmgandhi 18:6a4db94011d3 142 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 143 LPC_SWM->PINASSIGN[swm->n] = regVal | ((rx >> PIN_SHIFT) << swm->offset);
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 /* uart clock divided by 1 */
sahilmgandhi 18:6a4db94011d3 146 LPC_SYSCON->UARTCLKDIV = 1;
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 /* disable uart interrupts */
sahilmgandhi 18:6a4db94011d3 149 NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /* Enable UART clock */
sahilmgandhi 18:6a4db94011d3 152 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /* Peripheral reset control to UART, a "1" bring it out of reset. */
sahilmgandhi 18:6a4db94011d3 155 LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
sahilmgandhi 18:6a4db94011d3 156 LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n));
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV;
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 // set default baud rate and format
sahilmgandhi 18:6a4db94011d3 161 serial_baud (obj, 9600);
sahilmgandhi 18:6a4db94011d3 162 serial_format(obj, 8, ParityNone, 1);
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 /* Clear all status bits. */
sahilmgandhi 18:6a4db94011d3 165 obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /* enable uart interrupts */
sahilmgandhi 18:6a4db94011d3 168 NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 /* Enable UART */
sahilmgandhi 18:6a4db94011d3 171 obj->uart->CFG |= UART_EN;
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 if (is_stdio_uart) {
sahilmgandhi 18:6a4db94011d3 176 stdio_uart_inited = 1;
sahilmgandhi 18:6a4db94011d3 177 memcpy(&stdio_uart, obj, sizeof(serial_t));
sahilmgandhi 18:6a4db94011d3 178 }
sahilmgandhi 18:6a4db94011d3 179 }
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 void serial_free(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 182 {
sahilmgandhi 18:6a4db94011d3 183 uart_used &= ~(1 << obj->index);
sahilmgandhi 18:6a4db94011d3 184 serial_irq_ids[obj->index] = 0;
sahilmgandhi 18:6a4db94011d3 185 }
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 void serial_baud(serial_t *obj, int baudrate)
sahilmgandhi 18:6a4db94011d3 188 {
sahilmgandhi 18:6a4db94011d3 189 /* Integer divider:
sahilmgandhi 18:6a4db94011d3 190 BRG = UARTSysClk/(Baudrate * 16) - 1
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 Frational divider:
sahilmgandhi 18:6a4db94011d3 193 FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 where
sahilmgandhi 18:6a4db94011d3 196 FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
sahilmgandhi 18:6a4db94011d3 199 register is 0xFF.
sahilmgandhi 18:6a4db94011d3 200 (2) In ADD register value, depending on the value of UartSysClk,
sahilmgandhi 18:6a4db94011d3 201 baudrate, BRG register value, and SUB register value, be careful
sahilmgandhi 18:6a4db94011d3 202 about the order of multiplier and divider and make sure any
sahilmgandhi 18:6a4db94011d3 203 multiplier doesn't exceed 32-bit boundary and any divider doesn't get
sahilmgandhi 18:6a4db94011d3 204 down below one(integer 0).
sahilmgandhi 18:6a4db94011d3 205 (3) ADD should be always less than SUB.
sahilmgandhi 18:6a4db94011d3 206 */
sahilmgandhi 18:6a4db94011d3 207 obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 LPC_SYSCON->UARTFRGDIV = 0xFF;
sahilmgandhi 18:6a4db94011d3 210 LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
sahilmgandhi 18:6a4db94011d3 211 (baudrate * (obj->uart->BRG + 1))
sahilmgandhi 18:6a4db94011d3 212 ) - (LPC_SYSCON->UARTFRGDIV + 1);
sahilmgandhi 18:6a4db94011d3 213 }
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
sahilmgandhi 18:6a4db94011d3 216 {
sahilmgandhi 18:6a4db94011d3 217 // 0: 1 stop bits, 1: 2 stop bits
sahilmgandhi 18:6a4db94011d3 218 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
sahilmgandhi 18:6a4db94011d3 219 MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
sahilmgandhi 18:6a4db94011d3 220 MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd));
sahilmgandhi 18:6a4db94011d3 221 stop_bits -= 1;
sahilmgandhi 18:6a4db94011d3 222 data_bits -= 7;
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 int paritysel = 0;
sahilmgandhi 18:6a4db94011d3 225 switch (parity) {
sahilmgandhi 18:6a4db94011d3 226 case ParityNone: paritysel = 0; break;
sahilmgandhi 18:6a4db94011d3 227 case ParityEven: paritysel = 2; break;
sahilmgandhi 18:6a4db94011d3 228 case ParityOdd : paritysel = 3; break;
sahilmgandhi 18:6a4db94011d3 229 default:
sahilmgandhi 18:6a4db94011d3 230 break;
sahilmgandhi 18:6a4db94011d3 231 }
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 // First disable the the usart as described in documentation and then enable while updating CFG
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 // 24.6.1 USART Configuration register
sahilmgandhi 18:6a4db94011d3 236 // Remark: If software needs to change configuration values, the following sequence should
sahilmgandhi 18:6a4db94011d3 237 // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable
sahilmgandhi 18:6a4db94011d3 238 // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)
sahilmgandhi 18:6a4db94011d3 239 // Write the new configuration value, with the ENABLE bit set to 1.
sahilmgandhi 18:6a4db94011d3 240 obj->uart->CFG &= ~(1 << 0);
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 obj->uart->CFG = (1 << 0) // this will enable the usart
sahilmgandhi 18:6a4db94011d3 243 | (data_bits << 2)
sahilmgandhi 18:6a4db94011d3 244 | (paritysel << 4)
sahilmgandhi 18:6a4db94011d3 245 | (stop_bits << 6);
sahilmgandhi 18:6a4db94011d3 246 }
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 249 * INTERRUPTS HANDLING
sahilmgandhi 18:6a4db94011d3 250 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 251 static inline void uart_irq(SerialIrq irq_type, uint32_t index)
sahilmgandhi 18:6a4db94011d3 252 {
sahilmgandhi 18:6a4db94011d3 253 if (serial_irq_ids[index] != 0)
sahilmgandhi 18:6a4db94011d3 254 irq_handler(serial_irq_ids[index], irq_type);
sahilmgandhi 18:6a4db94011d3 255 }
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 void uart0_irq() {uart_irq((LPC_USART0->INTSTAT & RXRDY) ? RxIrq : TxIrq, 0);}
sahilmgandhi 18:6a4db94011d3 258 void uart1_irq() {uart_irq((LPC_USART1->INTSTAT & RXRDY) ? RxIrq : TxIrq, 1);}
sahilmgandhi 18:6a4db94011d3 259 void uart2_irq() {uart_irq((LPC_USART2->INTSTAT & RXRDY) ? RxIrq : TxIrq, 2);}
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
sahilmgandhi 18:6a4db94011d3 262 {
sahilmgandhi 18:6a4db94011d3 263 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 264 serial_irq_ids[obj->index] = id;
sahilmgandhi 18:6a4db94011d3 265 }
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
sahilmgandhi 18:6a4db94011d3 268 {
sahilmgandhi 18:6a4db94011d3 269 IRQn_Type irq_n = (IRQn_Type)0;
sahilmgandhi 18:6a4db94011d3 270 uint32_t vector = 0;
sahilmgandhi 18:6a4db94011d3 271 switch ((int)obj->uart) {
sahilmgandhi 18:6a4db94011d3 272 case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
sahilmgandhi 18:6a4db94011d3 273 case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
sahilmgandhi 18:6a4db94011d3 274 case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
sahilmgandhi 18:6a4db94011d3 275 }
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 if (enable) {
sahilmgandhi 18:6a4db94011d3 278 NVIC_DisableIRQ(irq_n);
sahilmgandhi 18:6a4db94011d3 279 obj->uart->INTENSET |= (1 << ((irq == RxIrq) ? 0 : 2));
sahilmgandhi 18:6a4db94011d3 280 NVIC_SetVector(irq_n, vector);
sahilmgandhi 18:6a4db94011d3 281 NVIC_EnableIRQ(irq_n);
sahilmgandhi 18:6a4db94011d3 282 } else { // disable
sahilmgandhi 18:6a4db94011d3 283 obj->uart->INTENCLR |= (1 << ((irq == RxIrq) ? 0 : 2));
sahilmgandhi 18:6a4db94011d3 284 if ( (obj->uart->INTENSET & (RXRDYEN | TXRDYEN)) == 0) {
sahilmgandhi 18:6a4db94011d3 285 NVIC_DisableIRQ(irq_n);
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287 }
sahilmgandhi 18:6a4db94011d3 288 }
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 291 * READ/WRITE
sahilmgandhi 18:6a4db94011d3 292 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 293 int serial_getc(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 294 {
sahilmgandhi 18:6a4db94011d3 295 while (!serial_readable(obj));
sahilmgandhi 18:6a4db94011d3 296 return obj->uart->RXDAT;
sahilmgandhi 18:6a4db94011d3 297 }
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 void serial_putc(serial_t *obj, int c)
sahilmgandhi 18:6a4db94011d3 300 {
sahilmgandhi 18:6a4db94011d3 301 while (!serial_writable(obj));
sahilmgandhi 18:6a4db94011d3 302 obj->uart->TXDAT = c;
sahilmgandhi 18:6a4db94011d3 303 }
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 int serial_readable(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 306 {
sahilmgandhi 18:6a4db94011d3 307 return obj->uart->STAT & RXRDY;
sahilmgandhi 18:6a4db94011d3 308 }
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 int serial_writable(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 311 {
sahilmgandhi 18:6a4db94011d3 312 return obj->uart->STAT & TXRDY;
sahilmgandhi 18:6a4db94011d3 313 }
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 void serial_clear(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 316 {
sahilmgandhi 18:6a4db94011d3 317 // [TODO]
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 void serial_pinout_tx(PinName tx)
sahilmgandhi 18:6a4db94011d3 321 {
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 }
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 void serial_break_set(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 326 {
sahilmgandhi 18:6a4db94011d3 327 obj->uart->CTL |= TXBRKEN;
sahilmgandhi 18:6a4db94011d3 328 }
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 void serial_break_clear(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 331 {
sahilmgandhi 18:6a4db94011d3 332 obj->uart->CTL &= ~TXBRKEN;
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
sahilmgandhi 18:6a4db94011d3 336 {
sahilmgandhi 18:6a4db94011d3 337 const SWM_Map *swm_rts, *swm_cts;
sahilmgandhi 18:6a4db94011d3 338 uint32_t regVal_rts, regVal_cts;
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 swm_rts = &SWM_UART_RTS[obj->index];
sahilmgandhi 18:6a4db94011d3 341 swm_cts = &SWM_UART_CTS[obj->index];
sahilmgandhi 18:6a4db94011d3 342 regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset);
sahilmgandhi 18:6a4db94011d3 343 regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset);
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 if (FlowControlNone == type) {
sahilmgandhi 18:6a4db94011d3 346 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
sahilmgandhi 18:6a4db94011d3 347 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
sahilmgandhi 18:6a4db94011d3 348 obj->uart->CFG &= ~CTSEN;
sahilmgandhi 18:6a4db94011d3 349 return;
sahilmgandhi 18:6a4db94011d3 350 }
sahilmgandhi 18:6a4db94011d3 351 if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) {
sahilmgandhi 18:6a4db94011d3 352 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | ((rxflow >> PIN_SHIFT) << swm_rts->offset);
sahilmgandhi 18:6a4db94011d3 353 if (FlowControlRTS == type) {
sahilmgandhi 18:6a4db94011d3 354 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset);
sahilmgandhi 18:6a4db94011d3 355 obj->uart->CFG &= ~CTSEN;
sahilmgandhi 18:6a4db94011d3 356 }
sahilmgandhi 18:6a4db94011d3 357 }
sahilmgandhi 18:6a4db94011d3 358 if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) {
sahilmgandhi 18:6a4db94011d3 359 LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | ((txflow >> PIN_SHIFT) << swm_cts->offset);
sahilmgandhi 18:6a4db94011d3 360 obj->uart->CFG |= CTSEN;
sahilmgandhi 18:6a4db94011d3 361 if (FlowControlCTS == type) {
sahilmgandhi 18:6a4db94011d3 362 LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset);
sahilmgandhi 18:6a4db94011d3 363 }
sahilmgandhi 18:6a4db94011d3 364 }
sahilmgandhi 18:6a4db94011d3 365 }
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 #endif