Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * @file: system_LPC8xx.h
sahilmgandhi 18:6a4db94011d3 3 * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
sahilmgandhi 18:6a4db94011d3 4 * for the NXP LPC8xx Device Series
sahilmgandhi 18:6a4db94011d3 5 * @version: V1.0
sahilmgandhi 18:6a4db94011d3 6 * @date: 16. Aug. 2012
sahilmgandhi 18:6a4db94011d3 7 *----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2012 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
sahilmgandhi 18:6a4db94011d3 12 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 13 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 #ifndef __SYSTEM_LPC8xx_H
sahilmgandhi 18:6a4db94011d3 25 #define __SYSTEM_LPC8xx_H
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 28 extern "C" {
sahilmgandhi 18:6a4db94011d3 29 #endif
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
sahilmgandhi 18:6a4db94011d3 34 extern uint32_t MainClock; /*!< Main Clock Frequency */
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 /**
sahilmgandhi 18:6a4db94011d3 38 * Initialize the system
sahilmgandhi 18:6a4db94011d3 39 *
sahilmgandhi 18:6a4db94011d3 40 * @param none
sahilmgandhi 18:6a4db94011d3 41 * @return none
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 44 * Initialize the System and update the SystemCoreClock variable.
sahilmgandhi 18:6a4db94011d3 45 */
sahilmgandhi 18:6a4db94011d3 46 extern void SystemInit (void);
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 /**
sahilmgandhi 18:6a4db94011d3 49 * Update SystemCoreClock variable
sahilmgandhi 18:6a4db94011d3 50 *
sahilmgandhi 18:6a4db94011d3 51 * @param none
sahilmgandhi 18:6a4db94011d3 52 * @return none
sahilmgandhi 18:6a4db94011d3 53 *
sahilmgandhi 18:6a4db94011d3 54 * @brief Updates the SystemCoreClock with current core Clock
sahilmgandhi 18:6a4db94011d3 55 * retrieved from cpu registers.
sahilmgandhi 18:6a4db94011d3 56 */
sahilmgandhi 18:6a4db94011d3 57 extern void SystemCoreClockUpdate (void);
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 60 }
sahilmgandhi 18:6a4db94011d3 61 #endif
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 #endif /* __SYSTEM_LPC8xx_H */