MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC408X/port_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "port_api.h"
sahilmgandhi 18:6a4db94011d3 17 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 18 #include "gpio_api.h"
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 PinName port_pin(PortName port, int pin_n) {
sahilmgandhi 18:6a4db94011d3 22 return (PinName)(((port << PORT_SHIFT) | pin_n));
sahilmgandhi 18:6a4db94011d3 23 }
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
sahilmgandhi 18:6a4db94011d3 26 obj->port = port;
sahilmgandhi 18:6a4db94011d3 27 obj->mask = mask;
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *)(LPC_GPIO0_BASE + ((int)port * 0x20));
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31 port_reg->MASK = ~mask;
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 obj->reg_out = &port_reg->PIN;
sahilmgandhi 18:6a4db94011d3 34 obj->reg_in = &port_reg->PIN;
sahilmgandhi 18:6a4db94011d3 35 obj->reg_dir = &port_reg->DIR;
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 uint32_t i;
sahilmgandhi 18:6a4db94011d3 38 // The function is set per pin: reuse gpio logic
sahilmgandhi 18:6a4db94011d3 39 for (i=0; i<32; i++) {
sahilmgandhi 18:6a4db94011d3 40 if (obj->mask & (1<<i)) {
sahilmgandhi 18:6a4db94011d3 41 gpio_set(port_pin(obj->port, i));
sahilmgandhi 18:6a4db94011d3 42 }
sahilmgandhi 18:6a4db94011d3 43 }
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 port_dir(obj, dir);
sahilmgandhi 18:6a4db94011d3 46 }
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 void port_mode(port_t *obj, PinMode mode) {
sahilmgandhi 18:6a4db94011d3 49 uint32_t i;
sahilmgandhi 18:6a4db94011d3 50 // The mode is set per pin: reuse pinmap logic
sahilmgandhi 18:6a4db94011d3 51 for (i=0; i<32; i++) {
sahilmgandhi 18:6a4db94011d3 52 if (obj->mask & (1<<i)) {
sahilmgandhi 18:6a4db94011d3 53 pin_mode(port_pin(obj->port, i), mode);
sahilmgandhi 18:6a4db94011d3 54 }
sahilmgandhi 18:6a4db94011d3 55 }
sahilmgandhi 18:6a4db94011d3 56 }
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 void port_dir(port_t *obj, PinDirection dir) {
sahilmgandhi 18:6a4db94011d3 59 switch (dir) {
sahilmgandhi 18:6a4db94011d3 60 case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
sahilmgandhi 18:6a4db94011d3 61 case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
sahilmgandhi 18:6a4db94011d3 62 }
sahilmgandhi 18:6a4db94011d3 63 }
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 void port_write(port_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 66 *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
sahilmgandhi 18:6a4db94011d3 67 }
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 int port_read(port_t *obj) {
sahilmgandhi 18:6a4db94011d3 70 return (*obj->reg_in & obj->mask);
sahilmgandhi 18:6a4db94011d3 71 }