MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC2460/device/core_arm7.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (C) 2008-2015 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
sahilmgandhi 18:6a4db94011d3 5 * based on core_cm3.h, V1.20
sahilmgandhi 18:6a4db94011d3 6 */
sahilmgandhi 18:6a4db94011d3 7
sahilmgandhi 18:6a4db94011d3 8 #ifndef __ARM7_CORE_H__
sahilmgandhi 18:6a4db94011d3 9 #define __ARM7_CORE_H__
sahilmgandhi 18:6a4db94011d3 10
sahilmgandhi 18:6a4db94011d3 11 #include "vector_defns.h"
sahilmgandhi 18:6a4db94011d3 12 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 13 extern "C" {
sahilmgandhi 18:6a4db94011d3 14 #endif
sahilmgandhi 18:6a4db94011d3 15 //#include "cmsis_nvic.h"
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
sahilmgandhi 18:6a4db94011d3 18 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
sahilmgandhi 18:6a4db94011d3 19 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #define __CORTEX_M (0x00) /*!< Cortex core */
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 /**
sahilmgandhi 18:6a4db94011d3 24 * Lint configuration \n
sahilmgandhi 18:6a4db94011d3 25 * ----------------------- \n
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * The following Lint messages will be suppressed and not shown: \n
sahilmgandhi 18:6a4db94011d3 28 * \n
sahilmgandhi 18:6a4db94011d3 29 * --- Error 10: --- \n
sahilmgandhi 18:6a4db94011d3 30 * register uint32_t __regBasePri __asm("basepri"); \n
sahilmgandhi 18:6a4db94011d3 31 * Error 10: Expecting ';' \n
sahilmgandhi 18:6a4db94011d3 32 * \n
sahilmgandhi 18:6a4db94011d3 33 * --- Error 530: --- \n
sahilmgandhi 18:6a4db94011d3 34 * return(__regBasePri); \n
sahilmgandhi 18:6a4db94011d3 35 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
sahilmgandhi 18:6a4db94011d3 36 * \n
sahilmgandhi 18:6a4db94011d3 37 * --- Error 550: --- \n
sahilmgandhi 18:6a4db94011d3 38 * __regBasePri = (basePri & 0x1ff); \n
sahilmgandhi 18:6a4db94011d3 39 * } \n
sahilmgandhi 18:6a4db94011d3 40 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
sahilmgandhi 18:6a4db94011d3 41 * \n
sahilmgandhi 18:6a4db94011d3 42 * --- Error 754: --- \n
sahilmgandhi 18:6a4db94011d3 43 * uint32_t RESERVED0[24]; \n
sahilmgandhi 18:6a4db94011d3 44 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
sahilmgandhi 18:6a4db94011d3 45 * \n
sahilmgandhi 18:6a4db94011d3 46 * --- Error 750: --- \n
sahilmgandhi 18:6a4db94011d3 47 * #define __CM3_CORE_H__ \n
sahilmgandhi 18:6a4db94011d3 48 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
sahilmgandhi 18:6a4db94011d3 49 * \n
sahilmgandhi 18:6a4db94011d3 50 * --- Error 528: --- \n
sahilmgandhi 18:6a4db94011d3 51 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
sahilmgandhi 18:6a4db94011d3 52 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
sahilmgandhi 18:6a4db94011d3 53 * \n
sahilmgandhi 18:6a4db94011d3 54 * --- Error 751: --- \n
sahilmgandhi 18:6a4db94011d3 55 * } InterruptType_Type; \n
sahilmgandhi 18:6a4db94011d3 56 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
sahilmgandhi 18:6a4db94011d3 57 * \n
sahilmgandhi 18:6a4db94011d3 58 * \n
sahilmgandhi 18:6a4db94011d3 59 * Note: To re-enable a Message, insert a space before 'lint' * \n
sahilmgandhi 18:6a4db94011d3 60 *
sahilmgandhi 18:6a4db94011d3 61 */
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /*lint -save */
sahilmgandhi 18:6a4db94011d3 64 /*lint -e10 */
sahilmgandhi 18:6a4db94011d3 65 /*lint -e530 */
sahilmgandhi 18:6a4db94011d3 66 /*lint -e550 */
sahilmgandhi 18:6a4db94011d3 67 /*lint -e754 */
sahilmgandhi 18:6a4db94011d3 68 /*lint -e750 */
sahilmgandhi 18:6a4db94011d3 69 /*lint -e528 */
sahilmgandhi 18:6a4db94011d3 70 /*lint -e751 */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 #include <stdint.h> /* Include standard types */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 75 /**
sahilmgandhi 18:6a4db94011d3 76 * @brief Return the Main Stack Pointer (current ARM7 stack)
sahilmgandhi 18:6a4db94011d3 77 *
sahilmgandhi 18:6a4db94011d3 78 * @param none
sahilmgandhi 18:6a4db94011d3 79 * @return uint32_t Main Stack Pointer
sahilmgandhi 18:6a4db94011d3 80 *
sahilmgandhi 18:6a4db94011d3 81 * Return the current value of the MSP (main stack pointer)
sahilmgandhi 18:6a4db94011d3 82 * Cortex processor register
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84 extern uint32_t __get_MSP(void);
sahilmgandhi 18:6a4db94011d3 85 #endif
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 #if defined (__ICCARM__)
sahilmgandhi 18:6a4db94011d3 89 #include <intrinsics.h> /* IAR Intrinsics */
sahilmgandhi 18:6a4db94011d3 90 #endif
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 #ifndef __NVIC_PRIO_BITS
sahilmgandhi 18:6a4db94011d3 94 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
sahilmgandhi 18:6a4db94011d3 95 #endif
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 typedef struct
sahilmgandhi 18:6a4db94011d3 98 {
sahilmgandhi 18:6a4db94011d3 99 uint32_t IRQStatus;
sahilmgandhi 18:6a4db94011d3 100 uint32_t FIQStatus;
sahilmgandhi 18:6a4db94011d3 101 uint32_t RawIntr;
sahilmgandhi 18:6a4db94011d3 102 uint32_t IntSelect;
sahilmgandhi 18:6a4db94011d3 103 uint32_t IntEnable;
sahilmgandhi 18:6a4db94011d3 104 uint32_t IntEnClr;
sahilmgandhi 18:6a4db94011d3 105 uint32_t SoftInt;
sahilmgandhi 18:6a4db94011d3 106 uint32_t SoftIntClr;
sahilmgandhi 18:6a4db94011d3 107 uint32_t Protection;
sahilmgandhi 18:6a4db94011d3 108 uint32_t SWPriorityMask;
sahilmgandhi 18:6a4db94011d3 109 uint32_t RESERVED0[54];
sahilmgandhi 18:6a4db94011d3 110 uint32_t VectAddr[32];
sahilmgandhi 18:6a4db94011d3 111 uint32_t RESERVED1[32];
sahilmgandhi 18:6a4db94011d3 112 uint32_t VectPriority[32];
sahilmgandhi 18:6a4db94011d3 113 uint32_t RESERVED2[800];
sahilmgandhi 18:6a4db94011d3 114 uint32_t Address;
sahilmgandhi 18:6a4db94011d3 115 } NVIC_TypeDef;
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 #define NVIC_BASE (0xFFFFF000)
sahilmgandhi 18:6a4db94011d3 118 #define NVIC (( NVIC_TypeDef *) NVIC_BASE)
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 /**
sahilmgandhi 18:6a4db94011d3 123 * IO definitions
sahilmgandhi 18:6a4db94011d3 124 *
sahilmgandhi 18:6a4db94011d3 125 * define access restrictions to peripheral registers
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 129 #define __I volatile /*!< defines 'read only' permissions */
sahilmgandhi 18:6a4db94011d3 130 #else
sahilmgandhi 18:6a4db94011d3 131 #define __I volatile const /*!< defines 'read only' permissions */
sahilmgandhi 18:6a4db94011d3 132 #endif
sahilmgandhi 18:6a4db94011d3 133 #define __O volatile /*!< defines 'write only' permissions */
sahilmgandhi 18:6a4db94011d3 134 #define __IO volatile /*!< defines 'read / write' permissions */
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 141 #define __ASM __asm /*!< asm keyword for ARM Compiler */
sahilmgandhi 18:6a4db94011d3 142 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 145 #define __ASM __asm /*!< asm keyword for IAR Compiler */
sahilmgandhi 18:6a4db94011d3 146 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 #elif defined ( __GNUC__ )
sahilmgandhi 18:6a4db94011d3 149 #define __ASM __asm /*!< asm keyword for GNU Compiler */
sahilmgandhi 18:6a4db94011d3 150 #define __INLINE inline /*!< inline keyword for GNU Compiler */
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 #elif defined ( __TASKING__ )
sahilmgandhi 18:6a4db94011d3 153 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
sahilmgandhi 18:6a4db94011d3 154 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 #endif
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 /* ################### Compiler specific Intrinsics ########################### */
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
sahilmgandhi 18:6a4db94011d3 162 /* ARM armcc specific functions */
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 #define __enable_fault_irq __enable_fiq
sahilmgandhi 18:6a4db94011d3 165 #define __disable_fault_irq __disable_fiq
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 #define __NOP __nop
sahilmgandhi 18:6a4db94011d3 168 //#define __WFI __wfi
sahilmgandhi 18:6a4db94011d3 169 //#define __WFE __wfe
sahilmgandhi 18:6a4db94011d3 170 //#define __SEV __sev
sahilmgandhi 18:6a4db94011d3 171 //#define __ISB() __isb(0)
sahilmgandhi 18:6a4db94011d3 172 //#define __DSB() __dsb(0)
sahilmgandhi 18:6a4db94011d3 173 //#define __DMB() __dmb(0)
sahilmgandhi 18:6a4db94011d3 174 //#define __REV __rev
sahilmgandhi 18:6a4db94011d3 175 //#define __RBIT __rbit
sahilmgandhi 18:6a4db94011d3 176 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
sahilmgandhi 18:6a4db94011d3 177 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
sahilmgandhi 18:6a4db94011d3 178 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
sahilmgandhi 18:6a4db94011d3 179 #define __STREXB(value, ptr) __strex(value, ptr)
sahilmgandhi 18:6a4db94011d3 180 #define __STREXH(value, ptr) __strex(value, ptr)
sahilmgandhi 18:6a4db94011d3 181 #define __STREXW(value, ptr) __strex(value, ptr)
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 #define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
sahilmgandhi 18:6a4db94011d3 184 LPC_VIC->IntEnClr = 0xffffffff
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 #define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
sahilmgandhi 18:6a4db94011d3 191 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
sahilmgandhi 18:6a4db94011d3 192 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 static __INLINE void __enable_irq() {
sahilmgandhi 18:6a4db94011d3 197 unsigned long temp;
sahilmgandhi 18:6a4db94011d3 198 __asm__ __volatile__("mrs %0, cpsr\n"
sahilmgandhi 18:6a4db94011d3 199 "bic %0, %0, #0x80\n"
sahilmgandhi 18:6a4db94011d3 200 "msr cpsr_c, %0"
sahilmgandhi 18:6a4db94011d3 201 : "=r" (temp)
sahilmgandhi 18:6a4db94011d3 202 :
sahilmgandhi 18:6a4db94011d3 203 : "memory");
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 static __INLINE uint32_t __disable_irq() {
sahilmgandhi 18:6a4db94011d3 207 unsigned long old,temp;
sahilmgandhi 18:6a4db94011d3 208 __asm__ __volatile__("mrs %0, cpsr\n"
sahilmgandhi 18:6a4db94011d3 209 "orr %1, %0, #0xc0\n"
sahilmgandhi 18:6a4db94011d3 210 "msr cpsr_c, %1"
sahilmgandhi 18:6a4db94011d3 211 : "=r" (old), "=r" (temp)
sahilmgandhi 18:6a4db94011d3 212 :
sahilmgandhi 18:6a4db94011d3 213 : "memory");
sahilmgandhi 18:6a4db94011d3 214 return (old & 0x80) == 0;
sahilmgandhi 18:6a4db94011d3 215 }
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 static __INLINE void __NOP() { __ASM volatile ("nop"); }
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /** \brief Get Control Bits of Status Register
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 This function returns the content of the Control Bits from the Program Status Register.
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 \return Control Bits value
sahilmgandhi 18:6a4db94011d3 224 */
sahilmgandhi 18:6a4db94011d3 225 __attribute__( ( always_inline ) ) static inline uint32_t __get_CONTROL(void)
sahilmgandhi 18:6a4db94011d3 226 {
sahilmgandhi 18:6a4db94011d3 227 uint32_t result;
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 __asm__ __volatile__ ("MRS %0, CPSR \n"
sahilmgandhi 18:6a4db94011d3 230 "AND %0,%0,#31" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 231 return(result);
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233 #define MODE_USER 0x10
sahilmgandhi 18:6a4db94011d3 234 #define MODE_FIQ 0x11
sahilmgandhi 18:6a4db94011d3 235 #define MODE_IRQ 0x12
sahilmgandhi 18:6a4db94011d3 236 #define MODE_SUPERVISOR 0x13
sahilmgandhi 18:6a4db94011d3 237 #define MODE_ABORT 0x17
sahilmgandhi 18:6a4db94011d3 238 #define MODE_UNDEFINED 0x1B
sahilmgandhi 18:6a4db94011d3 239 #define MODE_SYSTEM 0x1F
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
sahilmgandhi 18:6a4db94011d3 243 /* TASKING carm specific functions */
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 /*
sahilmgandhi 18:6a4db94011d3 246 * The CMSIS functions have been implemented as intrinsics in the compiler.
sahilmgandhi 18:6a4db94011d3 247 * Please use "carm -?i" to get an up to date list of all instrinsics,
sahilmgandhi 18:6a4db94011d3 248 * Including the CMSIS ones.
sahilmgandhi 18:6a4db94011d3 249 */
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 #endif
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /**
sahilmgandhi 18:6a4db94011d3 255 * @brief Enable Interrupt in NVIC Interrupt Controller
sahilmgandhi 18:6a4db94011d3 256 *
sahilmgandhi 18:6a4db94011d3 257 * @param IRQn_Type IRQn specifies the interrupt number
sahilmgandhi 18:6a4db94011d3 258 * @return none
sahilmgandhi 18:6a4db94011d3 259 *
sahilmgandhi 18:6a4db94011d3 260 * Enable a device specific interupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 261 * The interrupt number cannot be a negative value.
sahilmgandhi 18:6a4db94011d3 262 */
sahilmgandhi 18:6a4db94011d3 263 static __INLINE void NVIC_EnableIRQ(uint32_t IRQn)
sahilmgandhi 18:6a4db94011d3 264 {
sahilmgandhi 18:6a4db94011d3 265 NVIC->IntEnable = 1 << (uint32_t)IRQn;
sahilmgandhi 18:6a4db94011d3 266 }
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 /**
sahilmgandhi 18:6a4db94011d3 270 * @brief Disable the interrupt line for external interrupt specified
sahilmgandhi 18:6a4db94011d3 271 *
sahilmgandhi 18:6a4db94011d3 272 * @param IRQn_Type IRQn is the positive number of the external interrupt
sahilmgandhi 18:6a4db94011d3 273 * @return none
sahilmgandhi 18:6a4db94011d3 274 *
sahilmgandhi 18:6a4db94011d3 275 * Disable a device specific interupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 276 * The interrupt number cannot be a negative value.
sahilmgandhi 18:6a4db94011d3 277 */
sahilmgandhi 18:6a4db94011d3 278 static __INLINE void NVIC_DisableIRQ(uint32_t IRQn)
sahilmgandhi 18:6a4db94011d3 279 {
sahilmgandhi 18:6a4db94011d3 280 NVIC->IntEnClr = 1 << (uint32_t)IRQn;
sahilmgandhi 18:6a4db94011d3 281 }
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 /**
sahilmgandhi 18:6a4db94011d3 284 * @brief Pend Interrupt in NVIC Interrupt Controller
sahilmgandhi 18:6a4db94011d3 285 *
sahilmgandhi 18:6a4db94011d3 286 * @param IRQn_Type IRQn specifies the interrupt number
sahilmgandhi 18:6a4db94011d3 287 * @return none
sahilmgandhi 18:6a4db94011d3 288 *
sahilmgandhi 18:6a4db94011d3 289 * Force software a device specific interupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 290 * The interrupt number cannot be a negative value.
sahilmgandhi 18:6a4db94011d3 291 */
sahilmgandhi 18:6a4db94011d3 292 static __INLINE void NVIC_PendIRQ(uint32_t IRQn)
sahilmgandhi 18:6a4db94011d3 293 {
sahilmgandhi 18:6a4db94011d3 294 NVIC->SoftInt = 1 << (uint32_t)IRQn;
sahilmgandhi 18:6a4db94011d3 295 }
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 /**
sahilmgandhi 18:6a4db94011d3 299 * @brief Unpend the interrupt in NVIC Interrupt Controller
sahilmgandhi 18:6a4db94011d3 300 *
sahilmgandhi 18:6a4db94011d3 301 * @param IRQn_Type IRQn is the positive number of the external interrupt
sahilmgandhi 18:6a4db94011d3 302 * @return none
sahilmgandhi 18:6a4db94011d3 303 *
sahilmgandhi 18:6a4db94011d3 304 * Clear software device specific interupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 305 * The interrupt number cannot be a negative value.
sahilmgandhi 18:6a4db94011d3 306 */
sahilmgandhi 18:6a4db94011d3 307 static __INLINE void NVIC_UnpendIRQ(uint32_t IRQn)
sahilmgandhi 18:6a4db94011d3 308 {
sahilmgandhi 18:6a4db94011d3 309 NVIC->SoftIntClr = 1 << (uint32_t)IRQn;
sahilmgandhi 18:6a4db94011d3 310 }
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 /**
sahilmgandhi 18:6a4db94011d3 313 * @brief Is IRQ pending
sahilmgandhi 18:6a4db94011d3 314 *
sahilmgandhi 18:6a4db94011d3 315 * @param IRQn_Type IRQn is the positive number of the external interrupt
sahilmgandhi 18:6a4db94011d3 316 * @return 0 if IRQ is not pending
sahilmgandhi 18:6a4db94011d3 317 * 1 if IRQ is pending
sahilmgandhi 18:6a4db94011d3 318 *
sahilmgandhi 18:6a4db94011d3 319 * Returns software device specific interupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 320 * The interrupt number cannot be a negative value.
sahilmgandhi 18:6a4db94011d3 321 */
sahilmgandhi 18:6a4db94011d3 322 static __INLINE uint32_t NVIC_Pending(uint32_t IRQn)
sahilmgandhi 18:6a4db94011d3 323 {
sahilmgandhi 18:6a4db94011d3 324 return (NVIC->SoftInt & (1 << (uint32_t)IRQn)) != 0;
sahilmgandhi 18:6a4db94011d3 325 }
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 static __INLINE uint32_t __get_IPSR(void)
sahilmgandhi 18:6a4db94011d3 328 {
sahilmgandhi 18:6a4db94011d3 329 unsigned i;
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 for(i = 0; i < 32; i ++)
sahilmgandhi 18:6a4db94011d3 332 if(NVIC->Address == NVIC->VectAddr[i])
sahilmgandhi 18:6a4db94011d3 333 return i;
sahilmgandhi 18:6a4db94011d3 334 return 1; // 1 is an invalid entry in the interrupt table on LPC2460
sahilmgandhi 18:6a4db94011d3 335 }
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 338 }
sahilmgandhi 18:6a4db94011d3 339 #endif
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 #endif /* __ARM7_CORE_H__ */
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 /*lint -restore */