MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC2460/device/LPC24xx.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library - LPC24xx CMSIS-like structs
sahilmgandhi 18:6a4db94011d3 2 * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * An LPC24xx header file, based on LPC23xx.h
sahilmgandhi 18:6a4db94011d3 5 */
sahilmgandhi 18:6a4db94011d3 6
sahilmgandhi 18:6a4db94011d3 7 #ifndef __LPC24xx_H
sahilmgandhi 18:6a4db94011d3 8 #define __LPC24xx_H
sahilmgandhi 18:6a4db94011d3 9
sahilmgandhi 18:6a4db94011d3 10 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 11 extern "C" {
sahilmgandhi 18:6a4db94011d3 12 #endif
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 /*
sahilmgandhi 18:6a4db94011d3 15 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 16 * ---------- Interrupt Number Definition -----------------------------------
sahilmgandhi 18:6a4db94011d3 17 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 18 */
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 typedef enum IRQn
sahilmgandhi 18:6a4db94011d3 21 {
sahilmgandhi 18:6a4db94011d3 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
sahilmgandhi 18:6a4db94011d3 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
sahilmgandhi 18:6a4db94011d3 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
sahilmgandhi 18:6a4db94011d3 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
sahilmgandhi 18:6a4db94011d3 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
sahilmgandhi 18:6a4db94011d3 29 PWM0_IRQn = 8, /*!< PWM0 Interrupt */
sahilmgandhi 18:6a4db94011d3 30 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
sahilmgandhi 18:6a4db94011d3 31 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
sahilmgandhi 18:6a4db94011d3 32 SPI_IRQn = 10, /*!< SPI Interrupt */
sahilmgandhi 18:6a4db94011d3 33 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
sahilmgandhi 18:6a4db94011d3 34 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
sahilmgandhi 18:6a4db94011d3 35 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
sahilmgandhi 18:6a4db94011d3 36 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
sahilmgandhi 18:6a4db94011d3 37 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 38 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 39 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
sahilmgandhi 18:6a4db94011d3 40 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
sahilmgandhi 18:6a4db94011d3 41 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
sahilmgandhi 18:6a4db94011d3 42 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
sahilmgandhi 18:6a4db94011d3 43 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
sahilmgandhi 18:6a4db94011d3 44 ENET_IRQn = 21, /*!< Ethernet Interrupt */
sahilmgandhi 18:6a4db94011d3 45 USB_IRQn = 22, /*!< USB Interrupt */
sahilmgandhi 18:6a4db94011d3 46 CAN_IRQn = 23, /*!< CAN Interrupt */
sahilmgandhi 18:6a4db94011d3 47 SDMMC_IRQn = 24, /*!< SD/MMC Interrupt */
sahilmgandhi 18:6a4db94011d3 48 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
sahilmgandhi 18:6a4db94011d3 49 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
sahilmgandhi 18:6a4db94011d3 50 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
sahilmgandhi 18:6a4db94011d3 51 UART2_IRQn = 28, /*!< UART2 Interrupt */
sahilmgandhi 18:6a4db94011d3 52 UART3_IRQn = 29, /*!< UART3 Interrupt */
sahilmgandhi 18:6a4db94011d3 53 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
sahilmgandhi 18:6a4db94011d3 54 I2S_IRQn = 31, /*!< I2S Interrupt */
sahilmgandhi 18:6a4db94011d3 55 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /*
sahilmgandhi 18:6a4db94011d3 58 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 59 * ----------- Processor and Core Peripheral Section ------------------------
sahilmgandhi 18:6a4db94011d3 60 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 61 */
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /* Configuration of the ARM7 Processor and Core Peripherals */
sahilmgandhi 18:6a4db94011d3 64 #define __MPU_PRESENT 0 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 65 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 66 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 #include <core_arm7.h>
sahilmgandhi 18:6a4db94011d3 70 #include "system_LPC24xx.h" /* System Header */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 74 /* Device Specific Peripheral registers structures */
sahilmgandhi 18:6a4db94011d3 75 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 76 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 77 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 78 #endif
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
sahilmgandhi 18:6a4db94011d3 81 typedef struct
sahilmgandhi 18:6a4db94011d3 82 {
sahilmgandhi 18:6a4db94011d3 83 __I uint32_t IRQStatus;
sahilmgandhi 18:6a4db94011d3 84 __I uint32_t FIQStatus;
sahilmgandhi 18:6a4db94011d3 85 __I uint32_t RawIntr;
sahilmgandhi 18:6a4db94011d3 86 __IO uint32_t IntSelect;
sahilmgandhi 18:6a4db94011d3 87 __IO uint32_t IntEnable;
sahilmgandhi 18:6a4db94011d3 88 __O uint32_t IntEnClr;
sahilmgandhi 18:6a4db94011d3 89 __IO uint32_t SoftInt;
sahilmgandhi 18:6a4db94011d3 90 __O uint32_t SoftIntClr;
sahilmgandhi 18:6a4db94011d3 91 __IO uint32_t Protection;
sahilmgandhi 18:6a4db94011d3 92 __IO uint32_t SWPriorityMask;
sahilmgandhi 18:6a4db94011d3 93 __IO uint32_t RESERVED0[54];
sahilmgandhi 18:6a4db94011d3 94 __IO uint32_t VectAddr[32];
sahilmgandhi 18:6a4db94011d3 95 __IO uint32_t RESERVED1[32];
sahilmgandhi 18:6a4db94011d3 96 __IO uint32_t VectPriority[32];
sahilmgandhi 18:6a4db94011d3 97 __IO uint32_t RESERVED2[800];
sahilmgandhi 18:6a4db94011d3 98 __IO uint32_t Address;
sahilmgandhi 18:6a4db94011d3 99 } LPC_VIC_TypeDef;
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /*------------- System Control (SC) ------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 102 typedef struct
sahilmgandhi 18:6a4db94011d3 103 {
sahilmgandhi 18:6a4db94011d3 104 __IO uint32_t MAMCR;
sahilmgandhi 18:6a4db94011d3 105 __IO uint32_t MAMTIM;
sahilmgandhi 18:6a4db94011d3 106 uint32_t RESERVED0[14];
sahilmgandhi 18:6a4db94011d3 107 __IO uint32_t MEMMAP;
sahilmgandhi 18:6a4db94011d3 108 uint32_t RESERVED1[15];
sahilmgandhi 18:6a4db94011d3 109 __IO uint32_t PLL0CON; /* Clocking and Power Control */
sahilmgandhi 18:6a4db94011d3 110 __IO uint32_t PLL0CFG;
sahilmgandhi 18:6a4db94011d3 111 __I uint32_t PLL0STAT;
sahilmgandhi 18:6a4db94011d3 112 __O uint32_t PLL0FEED;
sahilmgandhi 18:6a4db94011d3 113 uint32_t RESERVED2[12];
sahilmgandhi 18:6a4db94011d3 114 __IO uint32_t PCON;
sahilmgandhi 18:6a4db94011d3 115 __IO uint32_t PCONP;
sahilmgandhi 18:6a4db94011d3 116 uint32_t RESERVED3[15];
sahilmgandhi 18:6a4db94011d3 117 __IO uint32_t CCLKCFG;
sahilmgandhi 18:6a4db94011d3 118 __IO uint32_t USBCLKCFG;
sahilmgandhi 18:6a4db94011d3 119 __IO uint32_t CLKSRCSEL;
sahilmgandhi 18:6a4db94011d3 120 uint32_t RESERVED4[12];
sahilmgandhi 18:6a4db94011d3 121 __IO uint32_t EXTINT; /* External Interrupts */
sahilmgandhi 18:6a4db94011d3 122 __IO uint32_t INTWAKE;
sahilmgandhi 18:6a4db94011d3 123 __IO uint32_t EXTMODE;
sahilmgandhi 18:6a4db94011d3 124 __IO uint32_t EXTPOLAR;
sahilmgandhi 18:6a4db94011d3 125 uint32_t RESERVED6[12];
sahilmgandhi 18:6a4db94011d3 126 __IO uint32_t RSID; /* Reset */
sahilmgandhi 18:6a4db94011d3 127 __IO uint32_t CSPR;
sahilmgandhi 18:6a4db94011d3 128 __IO uint32_t AHBCFG1;
sahilmgandhi 18:6a4db94011d3 129 __IO uint32_t AHBCFG2;
sahilmgandhi 18:6a4db94011d3 130 uint32_t RESERVED7[4];
sahilmgandhi 18:6a4db94011d3 131 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
sahilmgandhi 18:6a4db94011d3 132 __IO uint32_t IRCTRIM; /* Clock Dividers */
sahilmgandhi 18:6a4db94011d3 133 __IO uint32_t PCLKSEL0;
sahilmgandhi 18:6a4db94011d3 134 __IO uint32_t PCLKSEL1;
sahilmgandhi 18:6a4db94011d3 135 uint32_t RESERVED8[4];
sahilmgandhi 18:6a4db94011d3 136 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
sahilmgandhi 18:6a4db94011d3 137 uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 138 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
sahilmgandhi 18:6a4db94011d3 139 } LPC_SC_TypeDef;
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 142 typedef struct
sahilmgandhi 18:6a4db94011d3 143 {
sahilmgandhi 18:6a4db94011d3 144 __IO uint32_t PINSEL0;
sahilmgandhi 18:6a4db94011d3 145 __IO uint32_t PINSEL1;
sahilmgandhi 18:6a4db94011d3 146 __IO uint32_t PINSEL2;
sahilmgandhi 18:6a4db94011d3 147 __IO uint32_t PINSEL3;
sahilmgandhi 18:6a4db94011d3 148 __IO uint32_t PINSEL4;
sahilmgandhi 18:6a4db94011d3 149 __IO uint32_t PINSEL5;
sahilmgandhi 18:6a4db94011d3 150 __IO uint32_t PINSEL6;
sahilmgandhi 18:6a4db94011d3 151 __IO uint32_t PINSEL7;
sahilmgandhi 18:6a4db94011d3 152 __IO uint32_t PINSEL8;
sahilmgandhi 18:6a4db94011d3 153 __IO uint32_t PINSEL9;
sahilmgandhi 18:6a4db94011d3 154 __IO uint32_t PINSEL10;
sahilmgandhi 18:6a4db94011d3 155 uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 156 __IO uint32_t PINMODE0;
sahilmgandhi 18:6a4db94011d3 157 __IO uint32_t PINMODE1;
sahilmgandhi 18:6a4db94011d3 158 __IO uint32_t PINMODE2;
sahilmgandhi 18:6a4db94011d3 159 __IO uint32_t PINMODE3;
sahilmgandhi 18:6a4db94011d3 160 __IO uint32_t PINMODE4;
sahilmgandhi 18:6a4db94011d3 161 __IO uint32_t PINMODE5;
sahilmgandhi 18:6a4db94011d3 162 __IO uint32_t PINMODE6;
sahilmgandhi 18:6a4db94011d3 163 __IO uint32_t PINMODE7;
sahilmgandhi 18:6a4db94011d3 164 __IO uint32_t PINMODE8;
sahilmgandhi 18:6a4db94011d3 165 __IO uint32_t PINMODE9;
sahilmgandhi 18:6a4db94011d3 166 __IO uint32_t PINMODE_OD0;
sahilmgandhi 18:6a4db94011d3 167 __IO uint32_t PINMODE_OD1;
sahilmgandhi 18:6a4db94011d3 168 __IO uint32_t PINMODE_OD2;
sahilmgandhi 18:6a4db94011d3 169 __IO uint32_t PINMODE_OD3;
sahilmgandhi 18:6a4db94011d3 170 __IO uint32_t PINMODE_OD4;
sahilmgandhi 18:6a4db94011d3 171 } LPC_PINCON_TypeDef;
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 #define PCTIM0 1
sahilmgandhi 18:6a4db94011d3 174 #define PCTIM1 2
sahilmgandhi 18:6a4db94011d3 175 #define PCUART0 3
sahilmgandhi 18:6a4db94011d3 176 #define PCUART1 4
sahilmgandhi 18:6a4db94011d3 177 #define PCPWM1 6
sahilmgandhi 18:6a4db94011d3 178 #define PCI2C0 7
sahilmgandhi 18:6a4db94011d3 179 #define PCSPI 8
sahilmgandhi 18:6a4db94011d3 180 #define PCRTC 9
sahilmgandhi 18:6a4db94011d3 181 #define PCSSP1 10
sahilmgandhi 18:6a4db94011d3 182 #define PCEMC 11
sahilmgandhi 18:6a4db94011d3 183 #define PCADC 12
sahilmgandhi 18:6a4db94011d3 184 #define PCAN1 13
sahilmgandhi 18:6a4db94011d3 185 #define PCAN2 14
sahilmgandhi 18:6a4db94011d3 186 #define PCI2C1 19
sahilmgandhi 18:6a4db94011d3 187 #define PCSSP0 21
sahilmgandhi 18:6a4db94011d3 188 #define PCTIM2 22
sahilmgandhi 18:6a4db94011d3 189 #define PCTIM3 23
sahilmgandhi 18:6a4db94011d3 190 #define PCUART2 24
sahilmgandhi 18:6a4db94011d3 191 #define PCUART3 25
sahilmgandhi 18:6a4db94011d3 192 #define PCI2C2 26
sahilmgandhi 18:6a4db94011d3 193 #define PCI2S 27
sahilmgandhi 18:6a4db94011d3 194 #define PCSDC 28
sahilmgandhi 18:6a4db94011d3 195 #define PCGPDMA 29
sahilmgandhi 18:6a4db94011d3 196 #define PCENET 30
sahilmgandhi 18:6a4db94011d3 197 #define PCUSB 31
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
sahilmgandhi 18:6a4db94011d3 200 typedef struct
sahilmgandhi 18:6a4db94011d3 201 {
sahilmgandhi 18:6a4db94011d3 202 __IO uint32_t FIODIR;
sahilmgandhi 18:6a4db94011d3 203 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 204 __IO uint32_t FIOMASK;
sahilmgandhi 18:6a4db94011d3 205 __IO uint32_t FIOPIN;
sahilmgandhi 18:6a4db94011d3 206 __IO uint32_t FIOSET;
sahilmgandhi 18:6a4db94011d3 207 __O uint32_t FIOCLR;
sahilmgandhi 18:6a4db94011d3 208 } LPC_GPIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 typedef struct
sahilmgandhi 18:6a4db94011d3 211 {
sahilmgandhi 18:6a4db94011d3 212 __I uint32_t IntStatus;
sahilmgandhi 18:6a4db94011d3 213 __I uint32_t IO0IntStatR;
sahilmgandhi 18:6a4db94011d3 214 __I uint32_t IO0IntStatF;
sahilmgandhi 18:6a4db94011d3 215 __O uint32_t IO0IntClr;
sahilmgandhi 18:6a4db94011d3 216 __IO uint32_t IO0IntEnR;
sahilmgandhi 18:6a4db94011d3 217 __IO uint32_t IO0IntEnF;
sahilmgandhi 18:6a4db94011d3 218 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 219 __I uint32_t IO2IntStatR;
sahilmgandhi 18:6a4db94011d3 220 __I uint32_t IO2IntStatF;
sahilmgandhi 18:6a4db94011d3 221 __O uint32_t IO2IntClr;
sahilmgandhi 18:6a4db94011d3 222 __IO uint32_t IO2IntEnR;
sahilmgandhi 18:6a4db94011d3 223 __IO uint32_t IO2IntEnF;
sahilmgandhi 18:6a4db94011d3 224 } LPC_GPIOINT_TypeDef;
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /*------------- Timer (TIM) --------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 227 typedef struct
sahilmgandhi 18:6a4db94011d3 228 {
sahilmgandhi 18:6a4db94011d3 229 __IO uint32_t IR;
sahilmgandhi 18:6a4db94011d3 230 __IO uint32_t TCR;
sahilmgandhi 18:6a4db94011d3 231 __IO uint32_t TC;
sahilmgandhi 18:6a4db94011d3 232 __IO uint32_t PR;
sahilmgandhi 18:6a4db94011d3 233 __IO uint32_t PC;
sahilmgandhi 18:6a4db94011d3 234 __IO uint32_t MCR;
sahilmgandhi 18:6a4db94011d3 235 __IO uint32_t MR0;
sahilmgandhi 18:6a4db94011d3 236 __IO uint32_t MR1;
sahilmgandhi 18:6a4db94011d3 237 __IO uint32_t MR2;
sahilmgandhi 18:6a4db94011d3 238 __IO uint32_t MR3;
sahilmgandhi 18:6a4db94011d3 239 __IO uint32_t CCR;
sahilmgandhi 18:6a4db94011d3 240 __I uint32_t CR0;
sahilmgandhi 18:6a4db94011d3 241 __I uint32_t CR1;
sahilmgandhi 18:6a4db94011d3 242 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 243 __IO uint32_t EMR;
sahilmgandhi 18:6a4db94011d3 244 uint32_t RESERVED1[12];
sahilmgandhi 18:6a4db94011d3 245 __IO uint32_t CTCR;
sahilmgandhi 18:6a4db94011d3 246 } LPC_TIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
sahilmgandhi 18:6a4db94011d3 249 typedef struct
sahilmgandhi 18:6a4db94011d3 250 {
sahilmgandhi 18:6a4db94011d3 251 __IO uint32_t IR;
sahilmgandhi 18:6a4db94011d3 252 __IO uint32_t TCR;
sahilmgandhi 18:6a4db94011d3 253 __IO uint32_t TC;
sahilmgandhi 18:6a4db94011d3 254 __IO uint32_t PR;
sahilmgandhi 18:6a4db94011d3 255 __IO uint32_t PC;
sahilmgandhi 18:6a4db94011d3 256 __IO uint32_t MCR;
sahilmgandhi 18:6a4db94011d3 257 __IO uint32_t MR0;
sahilmgandhi 18:6a4db94011d3 258 __IO uint32_t MR1;
sahilmgandhi 18:6a4db94011d3 259 __IO uint32_t MR2;
sahilmgandhi 18:6a4db94011d3 260 __IO uint32_t MR3;
sahilmgandhi 18:6a4db94011d3 261 __IO uint32_t CCR;
sahilmgandhi 18:6a4db94011d3 262 __I uint32_t CR0;
sahilmgandhi 18:6a4db94011d3 263 __I uint32_t CR1;
sahilmgandhi 18:6a4db94011d3 264 __I uint32_t CR2;
sahilmgandhi 18:6a4db94011d3 265 __I uint32_t CR3;
sahilmgandhi 18:6a4db94011d3 266 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 267 __IO uint32_t MR4;
sahilmgandhi 18:6a4db94011d3 268 __IO uint32_t MR5;
sahilmgandhi 18:6a4db94011d3 269 __IO uint32_t MR6;
sahilmgandhi 18:6a4db94011d3 270 __IO uint32_t PCR;
sahilmgandhi 18:6a4db94011d3 271 __IO uint32_t LER;
sahilmgandhi 18:6a4db94011d3 272 uint32_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 273 __IO uint32_t CTCR;
sahilmgandhi 18:6a4db94011d3 274 } LPC_PWM_TypeDef;
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
sahilmgandhi 18:6a4db94011d3 277 typedef struct
sahilmgandhi 18:6a4db94011d3 278 {
sahilmgandhi 18:6a4db94011d3 279 union {
sahilmgandhi 18:6a4db94011d3 280 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 281 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 282 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 283 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 284 };
sahilmgandhi 18:6a4db94011d3 285 union {
sahilmgandhi 18:6a4db94011d3 286 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 287 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 288 };
sahilmgandhi 18:6a4db94011d3 289 union {
sahilmgandhi 18:6a4db94011d3 290 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 291 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 292 };
sahilmgandhi 18:6a4db94011d3 293 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 294 uint8_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 295 __IO uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 296 uint8_t RESERVED2[7];
sahilmgandhi 18:6a4db94011d3 297 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 298 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 299 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 300 __IO uint8_t ICR;
sahilmgandhi 18:6a4db94011d3 301 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 302 __IO uint8_t FDR;
sahilmgandhi 18:6a4db94011d3 303 uint8_t RESERVED5[7];
sahilmgandhi 18:6a4db94011d3 304 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 305 uint8_t RESERVED6[27];
sahilmgandhi 18:6a4db94011d3 306 __IO uint8_t RS485CTRL;
sahilmgandhi 18:6a4db94011d3 307 uint8_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 308 __IO uint8_t ADRMATCH;
sahilmgandhi 18:6a4db94011d3 309 } LPC_UART_TypeDef;
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 typedef struct
sahilmgandhi 18:6a4db94011d3 312 {
sahilmgandhi 18:6a4db94011d3 313 union {
sahilmgandhi 18:6a4db94011d3 314 __I uint8_t RBR;
sahilmgandhi 18:6a4db94011d3 315 __O uint8_t THR;
sahilmgandhi 18:6a4db94011d3 316 __IO uint8_t DLL;
sahilmgandhi 18:6a4db94011d3 317 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 318 };
sahilmgandhi 18:6a4db94011d3 319 union {
sahilmgandhi 18:6a4db94011d3 320 __IO uint8_t DLM;
sahilmgandhi 18:6a4db94011d3 321 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 322 };
sahilmgandhi 18:6a4db94011d3 323 union {
sahilmgandhi 18:6a4db94011d3 324 __I uint32_t IIR;
sahilmgandhi 18:6a4db94011d3 325 __O uint8_t FCR;
sahilmgandhi 18:6a4db94011d3 326 };
sahilmgandhi 18:6a4db94011d3 327 __IO uint8_t LCR;
sahilmgandhi 18:6a4db94011d3 328 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 329 __IO uint8_t MCR;
sahilmgandhi 18:6a4db94011d3 330 uint8_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 331 __IO uint8_t LSR;
sahilmgandhi 18:6a4db94011d3 332 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 333 __IO uint8_t MSR;
sahilmgandhi 18:6a4db94011d3 334 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 335 __IO uint8_t SCR;
sahilmgandhi 18:6a4db94011d3 336 uint8_t RESERVED5[3];
sahilmgandhi 18:6a4db94011d3 337 __IO uint32_t ACR;
sahilmgandhi 18:6a4db94011d3 338 uint32_t RESERVED6;
sahilmgandhi 18:6a4db94011d3 339 __IO uint32_t FDR;
sahilmgandhi 18:6a4db94011d3 340 uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 341 __IO uint8_t TER;
sahilmgandhi 18:6a4db94011d3 342 uint8_t RESERVED8[27];
sahilmgandhi 18:6a4db94011d3 343 __IO uint8_t RS485CTRL;
sahilmgandhi 18:6a4db94011d3 344 uint8_t RESERVED9[3];
sahilmgandhi 18:6a4db94011d3 345 __IO uint8_t ADRMATCH;
sahilmgandhi 18:6a4db94011d3 346 uint8_t RESERVED10[3];
sahilmgandhi 18:6a4db94011d3 347 __IO uint8_t RS485DLY;
sahilmgandhi 18:6a4db94011d3 348 } LPC_UART1_TypeDef;
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 351 typedef struct
sahilmgandhi 18:6a4db94011d3 352 {
sahilmgandhi 18:6a4db94011d3 353 __IO uint32_t SPCR;
sahilmgandhi 18:6a4db94011d3 354 __I uint32_t SPSR;
sahilmgandhi 18:6a4db94011d3 355 __IO uint32_t SPDR;
sahilmgandhi 18:6a4db94011d3 356 __IO uint32_t SPCCR;
sahilmgandhi 18:6a4db94011d3 357 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 358 __IO uint32_t SPINT;
sahilmgandhi 18:6a4db94011d3 359 } LPC_SPI_TypeDef;
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
sahilmgandhi 18:6a4db94011d3 362 typedef struct
sahilmgandhi 18:6a4db94011d3 363 {
sahilmgandhi 18:6a4db94011d3 364 __IO uint32_t CR0;
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t CR1;
sahilmgandhi 18:6a4db94011d3 366 __IO uint32_t DR;
sahilmgandhi 18:6a4db94011d3 367 __I uint32_t SR;
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t CPSR;
sahilmgandhi 18:6a4db94011d3 369 __IO uint32_t IMSC;
sahilmgandhi 18:6a4db94011d3 370 __IO uint32_t RIS;
sahilmgandhi 18:6a4db94011d3 371 __IO uint32_t MIS;
sahilmgandhi 18:6a4db94011d3 372 __IO uint32_t ICR;
sahilmgandhi 18:6a4db94011d3 373 __IO uint32_t DMACR;
sahilmgandhi 18:6a4db94011d3 374 } LPC_SSP_TypeDef;
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
sahilmgandhi 18:6a4db94011d3 377 typedef struct
sahilmgandhi 18:6a4db94011d3 378 {
sahilmgandhi 18:6a4db94011d3 379 __IO uint32_t I2CONSET;
sahilmgandhi 18:6a4db94011d3 380 __I uint32_t I2STAT;
sahilmgandhi 18:6a4db94011d3 381 __IO uint32_t I2DAT;
sahilmgandhi 18:6a4db94011d3 382 __IO uint32_t I2ADR0;
sahilmgandhi 18:6a4db94011d3 383 __IO uint32_t I2SCLH;
sahilmgandhi 18:6a4db94011d3 384 __IO uint32_t I2SCLL;
sahilmgandhi 18:6a4db94011d3 385 __O uint32_t I2CONCLR;
sahilmgandhi 18:6a4db94011d3 386 __IO uint32_t MMCTRL;
sahilmgandhi 18:6a4db94011d3 387 __IO uint32_t I2ADR1;
sahilmgandhi 18:6a4db94011d3 388 __IO uint32_t I2ADR2;
sahilmgandhi 18:6a4db94011d3 389 __IO uint32_t I2ADR3;
sahilmgandhi 18:6a4db94011d3 390 __I uint32_t I2DATA_BUFFER;
sahilmgandhi 18:6a4db94011d3 391 __IO uint32_t I2MASK0;
sahilmgandhi 18:6a4db94011d3 392 __IO uint32_t I2MASK1;
sahilmgandhi 18:6a4db94011d3 393 __IO uint32_t I2MASK2;
sahilmgandhi 18:6a4db94011d3 394 __IO uint32_t I2MASK3;
sahilmgandhi 18:6a4db94011d3 395 } LPC_I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 398 typedef struct
sahilmgandhi 18:6a4db94011d3 399 {
sahilmgandhi 18:6a4db94011d3 400 __IO uint32_t I2SDAO;
sahilmgandhi 18:6a4db94011d3 401 __I uint32_t I2SDAI;
sahilmgandhi 18:6a4db94011d3 402 __O uint32_t I2STXFIFO;
sahilmgandhi 18:6a4db94011d3 403 __I uint32_t I2SRXFIFO;
sahilmgandhi 18:6a4db94011d3 404 __I uint32_t I2SSTATE;
sahilmgandhi 18:6a4db94011d3 405 __IO uint32_t I2SDMA1;
sahilmgandhi 18:6a4db94011d3 406 __IO uint32_t I2SDMA2;
sahilmgandhi 18:6a4db94011d3 407 __IO uint32_t I2SIRQ;
sahilmgandhi 18:6a4db94011d3 408 __IO uint32_t I2STXRATE;
sahilmgandhi 18:6a4db94011d3 409 __IO uint32_t I2SRXRATE;
sahilmgandhi 18:6a4db94011d3 410 __IO uint32_t I2STXBITRATE;
sahilmgandhi 18:6a4db94011d3 411 __IO uint32_t I2SRXBITRATE;
sahilmgandhi 18:6a4db94011d3 412 __IO uint32_t I2STXMODE;
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t I2SRXMODE;
sahilmgandhi 18:6a4db94011d3 414 } LPC_I2S_TypeDef;
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 417 typedef struct
sahilmgandhi 18:6a4db94011d3 418 {
sahilmgandhi 18:6a4db94011d3 419 __IO uint8_t ILR;
sahilmgandhi 18:6a4db94011d3 420 uint8_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 421 __IO uint8_t CTC;
sahilmgandhi 18:6a4db94011d3 422 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 423 __IO uint8_t CCR;
sahilmgandhi 18:6a4db94011d3 424 uint8_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 425 __IO uint8_t CIIR;
sahilmgandhi 18:6a4db94011d3 426 uint8_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 427 __IO uint8_t AMR;
sahilmgandhi 18:6a4db94011d3 428 uint8_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 429 __I uint32_t CTIME0;
sahilmgandhi 18:6a4db94011d3 430 __I uint32_t CTIME1;
sahilmgandhi 18:6a4db94011d3 431 __I uint32_t CTIME2;
sahilmgandhi 18:6a4db94011d3 432 __IO uint8_t SEC;
sahilmgandhi 18:6a4db94011d3 433 uint8_t RESERVED5[3];
sahilmgandhi 18:6a4db94011d3 434 __IO uint8_t MIN;
sahilmgandhi 18:6a4db94011d3 435 uint8_t RESERVED6[3];
sahilmgandhi 18:6a4db94011d3 436 __IO uint8_t HOUR;
sahilmgandhi 18:6a4db94011d3 437 uint8_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 438 __IO uint8_t DOM;
sahilmgandhi 18:6a4db94011d3 439 uint8_t RESERVED8[3];
sahilmgandhi 18:6a4db94011d3 440 __IO uint8_t DOW;
sahilmgandhi 18:6a4db94011d3 441 uint8_t RESERVED9[3];
sahilmgandhi 18:6a4db94011d3 442 __IO uint16_t DOY;
sahilmgandhi 18:6a4db94011d3 443 uint16_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 444 __IO uint8_t MONTH;
sahilmgandhi 18:6a4db94011d3 445 uint8_t RESERVED11[3];
sahilmgandhi 18:6a4db94011d3 446 __IO uint16_t YEAR;
sahilmgandhi 18:6a4db94011d3 447 uint16_t RESERVED12;
sahilmgandhi 18:6a4db94011d3 448 __IO uint32_t CALIBRATION;
sahilmgandhi 18:6a4db94011d3 449 __IO uint32_t GPREG0;
sahilmgandhi 18:6a4db94011d3 450 __IO uint32_t GPREG1;
sahilmgandhi 18:6a4db94011d3 451 __IO uint32_t GPREG2;
sahilmgandhi 18:6a4db94011d3 452 __IO uint32_t GPREG3;
sahilmgandhi 18:6a4db94011d3 453 __IO uint32_t GPREG4;
sahilmgandhi 18:6a4db94011d3 454 __IO uint8_t WAKEUPDIS;
sahilmgandhi 18:6a4db94011d3 455 uint8_t RESERVED13[3];
sahilmgandhi 18:6a4db94011d3 456 __IO uint8_t PWRCTRL;
sahilmgandhi 18:6a4db94011d3 457 uint8_t RESERVED14[3];
sahilmgandhi 18:6a4db94011d3 458 __IO uint8_t ALSEC;
sahilmgandhi 18:6a4db94011d3 459 uint8_t RESERVED15[3];
sahilmgandhi 18:6a4db94011d3 460 __IO uint8_t ALMIN;
sahilmgandhi 18:6a4db94011d3 461 uint8_t RESERVED16[3];
sahilmgandhi 18:6a4db94011d3 462 __IO uint8_t ALHOUR;
sahilmgandhi 18:6a4db94011d3 463 uint8_t RESERVED17[3];
sahilmgandhi 18:6a4db94011d3 464 __IO uint8_t ALDOM;
sahilmgandhi 18:6a4db94011d3 465 uint8_t RESERVED18[3];
sahilmgandhi 18:6a4db94011d3 466 __IO uint8_t ALDOW;
sahilmgandhi 18:6a4db94011d3 467 uint8_t RESERVED19[3];
sahilmgandhi 18:6a4db94011d3 468 __IO uint16_t ALDOY;
sahilmgandhi 18:6a4db94011d3 469 uint16_t RESERVED20;
sahilmgandhi 18:6a4db94011d3 470 __IO uint8_t ALMON;
sahilmgandhi 18:6a4db94011d3 471 uint8_t RESERVED21[3];
sahilmgandhi 18:6a4db94011d3 472 __IO uint16_t ALYEAR;
sahilmgandhi 18:6a4db94011d3 473 uint16_t RESERVED22;
sahilmgandhi 18:6a4db94011d3 474 } LPC_RTC_TypeDef;
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 477 typedef struct
sahilmgandhi 18:6a4db94011d3 478 {
sahilmgandhi 18:6a4db94011d3 479 __IO uint8_t WDMOD;
sahilmgandhi 18:6a4db94011d3 480 uint8_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 481 __IO uint32_t WDTC;
sahilmgandhi 18:6a4db94011d3 482 __O uint8_t WDFEED;
sahilmgandhi 18:6a4db94011d3 483 uint8_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 484 __I uint32_t WDTV;
sahilmgandhi 18:6a4db94011d3 485 __IO uint32_t WDCLKSEL;
sahilmgandhi 18:6a4db94011d3 486 } LPC_WDT_TypeDef;
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 489 typedef struct
sahilmgandhi 18:6a4db94011d3 490 {
sahilmgandhi 18:6a4db94011d3 491 __IO uint32_t ADCR;
sahilmgandhi 18:6a4db94011d3 492 __IO uint32_t ADGDR;
sahilmgandhi 18:6a4db94011d3 493 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t ADINTEN;
sahilmgandhi 18:6a4db94011d3 495 __I uint32_t ADDR0;
sahilmgandhi 18:6a4db94011d3 496 __I uint32_t ADDR1;
sahilmgandhi 18:6a4db94011d3 497 __I uint32_t ADDR2;
sahilmgandhi 18:6a4db94011d3 498 __I uint32_t ADDR3;
sahilmgandhi 18:6a4db94011d3 499 __I uint32_t ADDR4;
sahilmgandhi 18:6a4db94011d3 500 __I uint32_t ADDR5;
sahilmgandhi 18:6a4db94011d3 501 __I uint32_t ADDR6;
sahilmgandhi 18:6a4db94011d3 502 __I uint32_t ADDR7;
sahilmgandhi 18:6a4db94011d3 503 __I uint32_t ADSTAT;
sahilmgandhi 18:6a4db94011d3 504 __IO uint32_t ADTRM;
sahilmgandhi 18:6a4db94011d3 505 } LPC_ADC_TypeDef;
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
sahilmgandhi 18:6a4db94011d3 508 typedef struct
sahilmgandhi 18:6a4db94011d3 509 {
sahilmgandhi 18:6a4db94011d3 510 __IO uint32_t DACR;
sahilmgandhi 18:6a4db94011d3 511 __IO uint32_t DACCTRL;
sahilmgandhi 18:6a4db94011d3 512 __IO uint16_t DACCNTVAL;
sahilmgandhi 18:6a4db94011d3 513 } LPC_DAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
sahilmgandhi 18:6a4db94011d3 516 typedef struct
sahilmgandhi 18:6a4db94011d3 517 {
sahilmgandhi 18:6a4db94011d3 518 __IO uint32_t MCIPower; /* Power control */
sahilmgandhi 18:6a4db94011d3 519 __IO uint32_t MCIClock; /* Clock control */
sahilmgandhi 18:6a4db94011d3 520 __IO uint32_t MCIArgument;
sahilmgandhi 18:6a4db94011d3 521 __IO uint32_t MMCCommand;
sahilmgandhi 18:6a4db94011d3 522 __I uint32_t MCIRespCmd;
sahilmgandhi 18:6a4db94011d3 523 __I uint32_t MCIResponse0;
sahilmgandhi 18:6a4db94011d3 524 __I uint32_t MCIResponse1;
sahilmgandhi 18:6a4db94011d3 525 __I uint32_t MCIResponse2;
sahilmgandhi 18:6a4db94011d3 526 __I uint32_t MCIResponse3;
sahilmgandhi 18:6a4db94011d3 527 __IO uint32_t MCIDataTimer;
sahilmgandhi 18:6a4db94011d3 528 __IO uint32_t MCIDataLength;
sahilmgandhi 18:6a4db94011d3 529 __IO uint32_t MCIDataCtrl;
sahilmgandhi 18:6a4db94011d3 530 __I uint32_t MCIDataCnt;
sahilmgandhi 18:6a4db94011d3 531 __I uint32_t MCIStatus;
sahilmgandhi 18:6a4db94011d3 532 __O uint32_t MCIClear;
sahilmgandhi 18:6a4db94011d3 533 __IO uint32_t MCIMask0;
sahilmgandhi 18:6a4db94011d3 534 uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 535 __I uint32_t MCIFifoCnt;
sahilmgandhi 18:6a4db94011d3 536 uint32_t RESERVED2[13];
sahilmgandhi 18:6a4db94011d3 537 __IO uint32_t MCIFIFO[16];
sahilmgandhi 18:6a4db94011d3 538 } LPC_MCI_TypeDef;
sahilmgandhi 18:6a4db94011d3 539
sahilmgandhi 18:6a4db94011d3 540 /*------------- Controller Area Network (CAN) --------------------------------*/
sahilmgandhi 18:6a4db94011d3 541 typedef struct
sahilmgandhi 18:6a4db94011d3 542 {
sahilmgandhi 18:6a4db94011d3 543 __IO uint32_t mask[512]; /* ID Masks */
sahilmgandhi 18:6a4db94011d3 544 } LPC_CANAF_RAM_TypeDef;
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 typedef struct /* Acceptance Filter Registers */
sahilmgandhi 18:6a4db94011d3 547 {
sahilmgandhi 18:6a4db94011d3 548 __IO uint32_t AFMR;
sahilmgandhi 18:6a4db94011d3 549 __IO uint32_t SFF_sa;
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t SFF_GRP_sa;
sahilmgandhi 18:6a4db94011d3 551 __IO uint32_t EFF_sa;
sahilmgandhi 18:6a4db94011d3 552 __IO uint32_t EFF_GRP_sa;
sahilmgandhi 18:6a4db94011d3 553 __IO uint32_t ENDofTable;
sahilmgandhi 18:6a4db94011d3 554 __I uint32_t LUTerrAd;
sahilmgandhi 18:6a4db94011d3 555 __I uint32_t LUTerr;
sahilmgandhi 18:6a4db94011d3 556 __IO uint32_t FCANIE;
sahilmgandhi 18:6a4db94011d3 557 __IO uint32_t FCANIC0;
sahilmgandhi 18:6a4db94011d3 558 __IO uint32_t FCANIC1;
sahilmgandhi 18:6a4db94011d3 559 } LPC_CANAF_TypeDef;
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 typedef struct /* Central Registers */
sahilmgandhi 18:6a4db94011d3 562 {
sahilmgandhi 18:6a4db94011d3 563 __I uint32_t CANTxSR;
sahilmgandhi 18:6a4db94011d3 564 __I uint32_t CANRxSR;
sahilmgandhi 18:6a4db94011d3 565 __I uint32_t CANMSR;
sahilmgandhi 18:6a4db94011d3 566 } LPC_CANCR_TypeDef;
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 typedef struct /* Controller Registers */
sahilmgandhi 18:6a4db94011d3 569 {
sahilmgandhi 18:6a4db94011d3 570 __IO uint32_t MOD;
sahilmgandhi 18:6a4db94011d3 571 __O uint32_t CMR;
sahilmgandhi 18:6a4db94011d3 572 __IO uint32_t GSR;
sahilmgandhi 18:6a4db94011d3 573 __I uint32_t ICR;
sahilmgandhi 18:6a4db94011d3 574 __IO uint32_t IER;
sahilmgandhi 18:6a4db94011d3 575 __IO uint32_t BTR;
sahilmgandhi 18:6a4db94011d3 576 __IO uint32_t EWL;
sahilmgandhi 18:6a4db94011d3 577 __I uint32_t SR;
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t RFS;
sahilmgandhi 18:6a4db94011d3 579 __IO uint32_t RID;
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t RDA;
sahilmgandhi 18:6a4db94011d3 581 __IO uint32_t RDB;
sahilmgandhi 18:6a4db94011d3 582 __IO uint32_t TFI1;
sahilmgandhi 18:6a4db94011d3 583 __IO uint32_t TID1;
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t TDA1;
sahilmgandhi 18:6a4db94011d3 585 __IO uint32_t TDB1;
sahilmgandhi 18:6a4db94011d3 586 __IO uint32_t TFI2;
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t TID2;
sahilmgandhi 18:6a4db94011d3 588 __IO uint32_t TDA2;
sahilmgandhi 18:6a4db94011d3 589 __IO uint32_t TDB2;
sahilmgandhi 18:6a4db94011d3 590 __IO uint32_t TFI3;
sahilmgandhi 18:6a4db94011d3 591 __IO uint32_t TID3;
sahilmgandhi 18:6a4db94011d3 592 __IO uint32_t TDA3;
sahilmgandhi 18:6a4db94011d3 593 __IO uint32_t TDB3;
sahilmgandhi 18:6a4db94011d3 594 } LPC_CAN_TypeDef;
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
sahilmgandhi 18:6a4db94011d3 597 typedef struct /* Common Registers */
sahilmgandhi 18:6a4db94011d3 598 {
sahilmgandhi 18:6a4db94011d3 599 __I uint32_t DMACIntStat;
sahilmgandhi 18:6a4db94011d3 600 __I uint32_t DMACIntTCStat;
sahilmgandhi 18:6a4db94011d3 601 __O uint32_t DMACIntTCClear;
sahilmgandhi 18:6a4db94011d3 602 __I uint32_t DMACIntErrStat;
sahilmgandhi 18:6a4db94011d3 603 __O uint32_t DMACIntErrClr;
sahilmgandhi 18:6a4db94011d3 604 __I uint32_t DMACRawIntTCStat;
sahilmgandhi 18:6a4db94011d3 605 __I uint32_t DMACRawIntErrStat;
sahilmgandhi 18:6a4db94011d3 606 __I uint32_t DMACEnbldChns;
sahilmgandhi 18:6a4db94011d3 607 __IO uint32_t DMACSoftBReq;
sahilmgandhi 18:6a4db94011d3 608 __IO uint32_t DMACSoftSReq;
sahilmgandhi 18:6a4db94011d3 609 __IO uint32_t DMACSoftLBReq;
sahilmgandhi 18:6a4db94011d3 610 __IO uint32_t DMACSoftLSReq;
sahilmgandhi 18:6a4db94011d3 611 __IO uint32_t DMACConfig;
sahilmgandhi 18:6a4db94011d3 612 __IO uint32_t DMACSync;
sahilmgandhi 18:6a4db94011d3 613 } LPC_GPDMA_TypeDef;
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 typedef struct /* Channel Registers */
sahilmgandhi 18:6a4db94011d3 616 {
sahilmgandhi 18:6a4db94011d3 617 __IO uint32_t DMACCSrcAddr;
sahilmgandhi 18:6a4db94011d3 618 __IO uint32_t DMACCDestAddr;
sahilmgandhi 18:6a4db94011d3 619 __IO uint32_t DMACCLLI;
sahilmgandhi 18:6a4db94011d3 620 __IO uint32_t DMACCControl;
sahilmgandhi 18:6a4db94011d3 621 __IO uint32_t DMACCConfig;
sahilmgandhi 18:6a4db94011d3 622 } LPC_GPDMACH_TypeDef;
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 /*------------- Universal Serial Bus (USB) -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 625 typedef struct
sahilmgandhi 18:6a4db94011d3 626 {
sahilmgandhi 18:6a4db94011d3 627 __I uint32_t HcRevision; /* USB Host Registers */
sahilmgandhi 18:6a4db94011d3 628 __IO uint32_t HcControl;
sahilmgandhi 18:6a4db94011d3 629 __IO uint32_t HcCommandStatus;
sahilmgandhi 18:6a4db94011d3 630 __IO uint32_t HcInterruptStatus;
sahilmgandhi 18:6a4db94011d3 631 __IO uint32_t HcInterruptEnable;
sahilmgandhi 18:6a4db94011d3 632 __IO uint32_t HcInterruptDisable;
sahilmgandhi 18:6a4db94011d3 633 __IO uint32_t HcHCCA;
sahilmgandhi 18:6a4db94011d3 634 __I uint32_t HcPeriodCurrentED;
sahilmgandhi 18:6a4db94011d3 635 __IO uint32_t HcControlHeadED;
sahilmgandhi 18:6a4db94011d3 636 __IO uint32_t HcControlCurrentED;
sahilmgandhi 18:6a4db94011d3 637 __IO uint32_t HcBulkHeadED;
sahilmgandhi 18:6a4db94011d3 638 __IO uint32_t HcBulkCurrentED;
sahilmgandhi 18:6a4db94011d3 639 __I uint32_t HcDoneHead;
sahilmgandhi 18:6a4db94011d3 640 __IO uint32_t HcFmInterval;
sahilmgandhi 18:6a4db94011d3 641 __I uint32_t HcFmRemaining;
sahilmgandhi 18:6a4db94011d3 642 __I uint32_t HcFmNumber;
sahilmgandhi 18:6a4db94011d3 643 __IO uint32_t HcPeriodicStart;
sahilmgandhi 18:6a4db94011d3 644 __IO uint32_t HcLSTreshold;
sahilmgandhi 18:6a4db94011d3 645 __IO uint32_t HcRhDescriptorA;
sahilmgandhi 18:6a4db94011d3 646 __IO uint32_t HcRhDescriptorB;
sahilmgandhi 18:6a4db94011d3 647 __IO uint32_t HcRhStatus;
sahilmgandhi 18:6a4db94011d3 648 __IO uint32_t HcRhPortStatus1;
sahilmgandhi 18:6a4db94011d3 649 __IO uint32_t HcRhPortStatus2;
sahilmgandhi 18:6a4db94011d3 650 uint32_t RESERVED0[40];
sahilmgandhi 18:6a4db94011d3 651 __I uint32_t Module_ID;
sahilmgandhi 18:6a4db94011d3 652
sahilmgandhi 18:6a4db94011d3 653 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
sahilmgandhi 18:6a4db94011d3 654 __IO uint32_t OTGIntEn;
sahilmgandhi 18:6a4db94011d3 655 __O uint32_t OTGIntSet;
sahilmgandhi 18:6a4db94011d3 656 __O uint32_t OTGIntClr;
sahilmgandhi 18:6a4db94011d3 657 __IO uint32_t OTGStCtrl;
sahilmgandhi 18:6a4db94011d3 658 __IO uint32_t OTGTmr;
sahilmgandhi 18:6a4db94011d3 659 uint32_t RESERVED1[58];
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
sahilmgandhi 18:6a4db94011d3 662 __IO uint32_t USBDevIntEn;
sahilmgandhi 18:6a4db94011d3 663 __O uint32_t USBDevIntClr;
sahilmgandhi 18:6a4db94011d3 664 __O uint32_t USBDevIntSet;
sahilmgandhi 18:6a4db94011d3 665
sahilmgandhi 18:6a4db94011d3 666 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
sahilmgandhi 18:6a4db94011d3 667 __I uint32_t USBCmdData;
sahilmgandhi 18:6a4db94011d3 668
sahilmgandhi 18:6a4db94011d3 669 __I uint32_t USBRxData; /* USB Device Transfer Registers */
sahilmgandhi 18:6a4db94011d3 670 __O uint32_t USBTxData;
sahilmgandhi 18:6a4db94011d3 671 __I uint32_t USBRxPLen;
sahilmgandhi 18:6a4db94011d3 672 __O uint32_t USBTxPLen;
sahilmgandhi 18:6a4db94011d3 673 __IO uint32_t USBCtrl;
sahilmgandhi 18:6a4db94011d3 674 __O uint32_t USBDevIntPri;
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
sahilmgandhi 18:6a4db94011d3 677 __IO uint32_t USBEpIntEn;
sahilmgandhi 18:6a4db94011d3 678 __O uint32_t USBEpIntClr;
sahilmgandhi 18:6a4db94011d3 679 __O uint32_t USBEpIntSet;
sahilmgandhi 18:6a4db94011d3 680 __O uint32_t USBEpIntPri;
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
sahilmgandhi 18:6a4db94011d3 683 __O uint32_t USBEpInd;
sahilmgandhi 18:6a4db94011d3 684 __IO uint32_t USBMaxPSize;
sahilmgandhi 18:6a4db94011d3 685
sahilmgandhi 18:6a4db94011d3 686 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
sahilmgandhi 18:6a4db94011d3 687 __O uint32_t USBDMARClr;
sahilmgandhi 18:6a4db94011d3 688 __O uint32_t USBDMARSet;
sahilmgandhi 18:6a4db94011d3 689 uint32_t RESERVED2[9];
sahilmgandhi 18:6a4db94011d3 690 __IO uint32_t USBUDCAH;
sahilmgandhi 18:6a4db94011d3 691 __I uint32_t USBEpDMASt;
sahilmgandhi 18:6a4db94011d3 692 __O uint32_t USBEpDMAEn;
sahilmgandhi 18:6a4db94011d3 693 __O uint32_t USBEpDMADis;
sahilmgandhi 18:6a4db94011d3 694 __I uint32_t USBDMAIntSt;
sahilmgandhi 18:6a4db94011d3 695 __IO uint32_t USBDMAIntEn;
sahilmgandhi 18:6a4db94011d3 696 uint32_t RESERVED3[2];
sahilmgandhi 18:6a4db94011d3 697 __I uint32_t USBEoTIntSt;
sahilmgandhi 18:6a4db94011d3 698 __O uint32_t USBEoTIntClr;
sahilmgandhi 18:6a4db94011d3 699 __O uint32_t USBEoTIntSet;
sahilmgandhi 18:6a4db94011d3 700 __I uint32_t USBNDDRIntSt;
sahilmgandhi 18:6a4db94011d3 701 __O uint32_t USBNDDRIntClr;
sahilmgandhi 18:6a4db94011d3 702 __O uint32_t USBNDDRIntSet;
sahilmgandhi 18:6a4db94011d3 703 __I uint32_t USBSysErrIntSt;
sahilmgandhi 18:6a4db94011d3 704 __O uint32_t USBSysErrIntClr;
sahilmgandhi 18:6a4db94011d3 705 __O uint32_t USBSysErrIntSet;
sahilmgandhi 18:6a4db94011d3 706 uint32_t RESERVED4[15];
sahilmgandhi 18:6a4db94011d3 707
sahilmgandhi 18:6a4db94011d3 708 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
sahilmgandhi 18:6a4db94011d3 709 __O uint32_t I2C_WO;
sahilmgandhi 18:6a4db94011d3 710 __I uint32_t I2C_STS;
sahilmgandhi 18:6a4db94011d3 711 __IO uint32_t I2C_CTL;
sahilmgandhi 18:6a4db94011d3 712 __IO uint32_t I2C_CLKHI;
sahilmgandhi 18:6a4db94011d3 713 __O uint32_t I2C_CLKLO;
sahilmgandhi 18:6a4db94011d3 714 uint32_t RESERVED5[823];
sahilmgandhi 18:6a4db94011d3 715
sahilmgandhi 18:6a4db94011d3 716 union {
sahilmgandhi 18:6a4db94011d3 717 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
sahilmgandhi 18:6a4db94011d3 718 __IO uint32_t OTGClkCtrl;
sahilmgandhi 18:6a4db94011d3 719 };
sahilmgandhi 18:6a4db94011d3 720 union {
sahilmgandhi 18:6a4db94011d3 721 __I uint32_t USBClkSt;
sahilmgandhi 18:6a4db94011d3 722 __I uint32_t OTGClkSt;
sahilmgandhi 18:6a4db94011d3 723 };
sahilmgandhi 18:6a4db94011d3 724 } LPC_USB_TypeDef;
sahilmgandhi 18:6a4db94011d3 725
sahilmgandhi 18:6a4db94011d3 726 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
sahilmgandhi 18:6a4db94011d3 727 typedef struct
sahilmgandhi 18:6a4db94011d3 728 {
sahilmgandhi 18:6a4db94011d3 729 __IO uint32_t MAC1; /* MAC Registers */
sahilmgandhi 18:6a4db94011d3 730 __IO uint32_t MAC2;
sahilmgandhi 18:6a4db94011d3 731 __IO uint32_t IPGT;
sahilmgandhi 18:6a4db94011d3 732 __IO uint32_t IPGR;
sahilmgandhi 18:6a4db94011d3 733 __IO uint32_t CLRT;
sahilmgandhi 18:6a4db94011d3 734 __IO uint32_t MAXF;
sahilmgandhi 18:6a4db94011d3 735 __IO uint32_t SUPP;
sahilmgandhi 18:6a4db94011d3 736 __IO uint32_t TEST;
sahilmgandhi 18:6a4db94011d3 737 __IO uint32_t MCFG;
sahilmgandhi 18:6a4db94011d3 738 __IO uint32_t MCMD;
sahilmgandhi 18:6a4db94011d3 739 __IO uint32_t MADR;
sahilmgandhi 18:6a4db94011d3 740 __O uint32_t MWTD;
sahilmgandhi 18:6a4db94011d3 741 __I uint32_t MRDD;
sahilmgandhi 18:6a4db94011d3 742 __I uint32_t MIND;
sahilmgandhi 18:6a4db94011d3 743 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 744 __IO uint32_t SA0;
sahilmgandhi 18:6a4db94011d3 745 __IO uint32_t SA1;
sahilmgandhi 18:6a4db94011d3 746 __IO uint32_t SA2;
sahilmgandhi 18:6a4db94011d3 747 uint32_t RESERVED1[45];
sahilmgandhi 18:6a4db94011d3 748 __IO uint32_t Command; /* Control Registers */
sahilmgandhi 18:6a4db94011d3 749 __I uint32_t Status;
sahilmgandhi 18:6a4db94011d3 750 __IO uint32_t RxDescriptor;
sahilmgandhi 18:6a4db94011d3 751 __IO uint32_t RxStatus;
sahilmgandhi 18:6a4db94011d3 752 __IO uint32_t RxDescriptorNumber;
sahilmgandhi 18:6a4db94011d3 753 __I uint32_t RxProduceIndex;
sahilmgandhi 18:6a4db94011d3 754 __IO uint32_t RxConsumeIndex;
sahilmgandhi 18:6a4db94011d3 755 __IO uint32_t TxDescriptor;
sahilmgandhi 18:6a4db94011d3 756 __IO uint32_t TxStatus;
sahilmgandhi 18:6a4db94011d3 757 __IO uint32_t TxDescriptorNumber;
sahilmgandhi 18:6a4db94011d3 758 __IO uint32_t TxProduceIndex;
sahilmgandhi 18:6a4db94011d3 759 __I uint32_t TxConsumeIndex;
sahilmgandhi 18:6a4db94011d3 760 uint32_t RESERVED2[10];
sahilmgandhi 18:6a4db94011d3 761 __I uint32_t TSV0;
sahilmgandhi 18:6a4db94011d3 762 __I uint32_t TSV1;
sahilmgandhi 18:6a4db94011d3 763 __I uint32_t RSV;
sahilmgandhi 18:6a4db94011d3 764 uint32_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 765 __IO uint32_t FlowControlCounter;
sahilmgandhi 18:6a4db94011d3 766 __I uint32_t FlowControlStatus;
sahilmgandhi 18:6a4db94011d3 767 uint32_t RESERVED4[34];
sahilmgandhi 18:6a4db94011d3 768 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
sahilmgandhi 18:6a4db94011d3 769 __IO uint32_t RxFilterWoLStatus;
sahilmgandhi 18:6a4db94011d3 770 __IO uint32_t RxFilterWoLClear;
sahilmgandhi 18:6a4db94011d3 771 uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 772 __IO uint32_t HashFilterL;
sahilmgandhi 18:6a4db94011d3 773 __IO uint32_t HashFilterH;
sahilmgandhi 18:6a4db94011d3 774 uint32_t RESERVED6[882];
sahilmgandhi 18:6a4db94011d3 775 __I uint32_t IntStatus; /* Module Control Registers */
sahilmgandhi 18:6a4db94011d3 776 __IO uint32_t IntEnable;
sahilmgandhi 18:6a4db94011d3 777 __O uint32_t IntClear;
sahilmgandhi 18:6a4db94011d3 778 __O uint32_t IntSet;
sahilmgandhi 18:6a4db94011d3 779 uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 780 __IO uint32_t PowerDown;
sahilmgandhi 18:6a4db94011d3 781 uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 782 __IO uint32_t Module_ID;
sahilmgandhi 18:6a4db94011d3 783 } LPC_EMAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 /*-------------------- External Memory Controller (EMC) ----------------------*/
sahilmgandhi 18:6a4db94011d3 786 typedef struct
sahilmgandhi 18:6a4db94011d3 787 {
sahilmgandhi 18:6a4db94011d3 788 __IO uint32_t EMCControl;
sahilmgandhi 18:6a4db94011d3 789 __I uint32_t EMCStatus;
sahilmgandhi 18:6a4db94011d3 790 __IO uint32_t EMCConfig;
sahilmgandhi 18:6a4db94011d3 791 uint32_t RESERVED1[5];
sahilmgandhi 18:6a4db94011d3 792 __IO uint32_t EMCDynamicControl;
sahilmgandhi 18:6a4db94011d3 793 __IO uint32_t EMCDynamicRefresh;
sahilmgandhi 18:6a4db94011d3 794 __IO uint32_t EMCDynamicReadConfig;
sahilmgandhi 18:6a4db94011d3 795 uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 796 __IO uint32_t EMCDynamicRP;
sahilmgandhi 18:6a4db94011d3 797 __IO uint32_t EMCDynamicRAS;
sahilmgandhi 18:6a4db94011d3 798 __IO uint32_t EMCDynamicSREX;
sahilmgandhi 18:6a4db94011d3 799 __IO uint32_t EMCDynamicAPR;
sahilmgandhi 18:6a4db94011d3 800 __IO uint32_t EMCDynamicDAL;
sahilmgandhi 18:6a4db94011d3 801 __IO uint32_t EMCDynamicWR;
sahilmgandhi 18:6a4db94011d3 802 __IO uint32_t EMCDynamicRC;
sahilmgandhi 18:6a4db94011d3 803 __IO uint32_t EMCDynamicRFC;
sahilmgandhi 18:6a4db94011d3 804 __IO uint32_t EMCDynamicXSR;
sahilmgandhi 18:6a4db94011d3 805 __IO uint32_t EMCDynamicRRD;
sahilmgandhi 18:6a4db94011d3 806 __IO uint32_t EMCDynamicMRD;
sahilmgandhi 18:6a4db94011d3 807 uint32_t RESERVED3[9];
sahilmgandhi 18:6a4db94011d3 808 __IO uint32_t EMCStaticExtendedWait;
sahilmgandhi 18:6a4db94011d3 809 uint32_t RESERVED4[31];
sahilmgandhi 18:6a4db94011d3 810 __IO uint32_t EMCDynamicConfig0;
sahilmgandhi 18:6a4db94011d3 811 __IO uint32_t EMCDynamicRasCas0;
sahilmgandhi 18:6a4db94011d3 812 uint32_t RESERVED5[6];
sahilmgandhi 18:6a4db94011d3 813 __IO uint32_t EMCDynamicConfig1;
sahilmgandhi 18:6a4db94011d3 814 __IO uint32_t EMCDynamicRasCas1;
sahilmgandhi 18:6a4db94011d3 815 uint32_t RESERVED6[6];
sahilmgandhi 18:6a4db94011d3 816 __IO uint32_t EMCDynamicConfic2;
sahilmgandhi 18:6a4db94011d3 817 __IO uint32_t EMCDynamicRasCas2;
sahilmgandhi 18:6a4db94011d3 818 uint32_t RESERVED7[6];
sahilmgandhi 18:6a4db94011d3 819 __IO uint32_t EMCDynamicConfig3;
sahilmgandhi 18:6a4db94011d3 820 __IO uint32_t EMCDynamicRasCas3;
sahilmgandhi 18:6a4db94011d3 821 uint32_t RESERVED8[38];
sahilmgandhi 18:6a4db94011d3 822 __IO uint32_t EMCStaticConfig0;
sahilmgandhi 18:6a4db94011d3 823 __IO uint32_t EMCStaticWaitWen0;
sahilmgandhi 18:6a4db94011d3 824 __IO uint32_t EMCStaticWaitOen0;
sahilmgandhi 18:6a4db94011d3 825 __IO uint32_t EMCStaticWaitRd0;
sahilmgandhi 18:6a4db94011d3 826 __IO uint32_t EMCStaticWaitPage0;
sahilmgandhi 18:6a4db94011d3 827 __IO uint32_t EMCStaticWaitWr0;
sahilmgandhi 18:6a4db94011d3 828 __IO uint32_t EMCStaticWaitTurn0;
sahilmgandhi 18:6a4db94011d3 829 uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 830 __IO uint32_t EMCStaticConfig1;
sahilmgandhi 18:6a4db94011d3 831 __IO uint32_t EMCStaticWaitWen1;
sahilmgandhi 18:6a4db94011d3 832 __IO uint32_t EMCStaticWaitOen1;
sahilmgandhi 18:6a4db94011d3 833 __IO uint32_t EMCStaticWaitRd1;
sahilmgandhi 18:6a4db94011d3 834 __IO uint32_t EMCStaticWaitPage1;
sahilmgandhi 18:6a4db94011d3 835 __IO uint32_t EMCStaticWaitWr1;
sahilmgandhi 18:6a4db94011d3 836 __IO uint32_t EMCStaticWaitTurn1;
sahilmgandhi 18:6a4db94011d3 837 uint32_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 838 __IO uint32_t EMCStaticConfig2;
sahilmgandhi 18:6a4db94011d3 839 __IO uint32_t EMCStaticWaitWen2;
sahilmgandhi 18:6a4db94011d3 840 __IO uint32_t EMCStaticWaitOen2;
sahilmgandhi 18:6a4db94011d3 841 __IO uint32_t EMCStaticWaitRd2;
sahilmgandhi 18:6a4db94011d3 842 __IO uint32_t EMCStaticWaitPage2;
sahilmgandhi 18:6a4db94011d3 843 __IO uint32_t EMCStaticWaitWr2;
sahilmgandhi 18:6a4db94011d3 844 __IO uint32_t EMCStaticWaitTurn2;
sahilmgandhi 18:6a4db94011d3 845 uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 846 __IO uint32_t EMCStaticConfig3;
sahilmgandhi 18:6a4db94011d3 847 __IO uint32_t EMCStaticWaitWen3;
sahilmgandhi 18:6a4db94011d3 848 __IO uint32_t EMCStaticWaitOen3;
sahilmgandhi 18:6a4db94011d3 849 __IO uint32_t EMCStaticWaitRd3;
sahilmgandhi 18:6a4db94011d3 850 __IO uint32_t EMCStaticWaitPage3;
sahilmgandhi 18:6a4db94011d3 851 __IO uint32_t EMCStaticWaitWr3;
sahilmgandhi 18:6a4db94011d3 852 __IO uint32_t EMCStaticWaitTurn3;
sahilmgandhi 18:6a4db94011d3 853 } LPC_EMC_TypeDef;
sahilmgandhi 18:6a4db94011d3 854 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 855 #pragma no_anon_unions
sahilmgandhi 18:6a4db94011d3 856 #endif
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 859 /* Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 860 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 861 /* Base addresses */
sahilmgandhi 18:6a4db94011d3 862
sahilmgandhi 18:6a4db94011d3 863 /* AHB Peripheral # 0 */
sahilmgandhi 18:6a4db94011d3 864
sahilmgandhi 18:6a4db94011d3 865 /*
sahilmgandhi 18:6a4db94011d3 866 #define FLASH_BASE (0x00000000UL)
sahilmgandhi 18:6a4db94011d3 867 #define RAM_BASE (0x10000000UL)
sahilmgandhi 18:6a4db94011d3 868 #define GPIO_BASE (0x2009C000UL)
sahilmgandhi 18:6a4db94011d3 869 #define APB0_BASE (0x40000000UL)
sahilmgandhi 18:6a4db94011d3 870 #define APB1_BASE (0x40080000UL)
sahilmgandhi 18:6a4db94011d3 871 #define AHB_BASE (0x50000000UL)
sahilmgandhi 18:6a4db94011d3 872 #define CM3_BASE (0xE0000000UL)
sahilmgandhi 18:6a4db94011d3 873 */
sahilmgandhi 18:6a4db94011d3 874
sahilmgandhi 18:6a4db94011d3 875 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
sahilmgandhi 18:6a4db94011d3 876
sahilmgandhi 18:6a4db94011d3 877 #define LPC_WDT_BASE (0xE0000000)
sahilmgandhi 18:6a4db94011d3 878 #define LPC_TIM0_BASE (0xE0004000)
sahilmgandhi 18:6a4db94011d3 879 #define LPC_TIM1_BASE (0xE0008000)
sahilmgandhi 18:6a4db94011d3 880 #define LPC_UART0_BASE (0xE000C000)
sahilmgandhi 18:6a4db94011d3 881 #define LPC_UART1_BASE (0xE0010000)
sahilmgandhi 18:6a4db94011d3 882 #define LPC_PWM1_BASE (0xE0018000)
sahilmgandhi 18:6a4db94011d3 883 #define LPC_I2C0_BASE (0xE001C000)
sahilmgandhi 18:6a4db94011d3 884 #define LPC_SPI_BASE (0xE0020000)
sahilmgandhi 18:6a4db94011d3 885 #define LPC_RTC_BASE (0xE0024000)
sahilmgandhi 18:6a4db94011d3 886 #define LPC_GPIOINT_BASE (0xE0028080)
sahilmgandhi 18:6a4db94011d3 887 #define LPC_PINCON_BASE (0xE002C000)
sahilmgandhi 18:6a4db94011d3 888 #define LPC_SSP1_BASE (0xE0030000)
sahilmgandhi 18:6a4db94011d3 889 #define LPC_ADC_BASE (0xE0034000)
sahilmgandhi 18:6a4db94011d3 890 #define LPC_CANAF_RAM_BASE (0xE0038000)
sahilmgandhi 18:6a4db94011d3 891 #define LPC_CANAF_BASE (0xE003C000)
sahilmgandhi 18:6a4db94011d3 892 #define LPC_CANCR_BASE (0xE0040000)
sahilmgandhi 18:6a4db94011d3 893 #define LPC_CAN1_BASE (0xE0044000)
sahilmgandhi 18:6a4db94011d3 894 #define LPC_CAN2_BASE (0xE0048000)
sahilmgandhi 18:6a4db94011d3 895 #define LPC_I2C1_BASE (0xE005C000)
sahilmgandhi 18:6a4db94011d3 896 #define LPC_SSP0_BASE (0xE0068000)
sahilmgandhi 18:6a4db94011d3 897 #define LPC_DAC_BASE (0xE006C000)
sahilmgandhi 18:6a4db94011d3 898 #define LPC_TIM2_BASE (0xE0070000)
sahilmgandhi 18:6a4db94011d3 899 #define LPC_TIM3_BASE (0xE0074000)
sahilmgandhi 18:6a4db94011d3 900 #define LPC_UART2_BASE (0xE0078000)
sahilmgandhi 18:6a4db94011d3 901 #define LPC_UART3_BASE (0xE007C000)
sahilmgandhi 18:6a4db94011d3 902 #define LPC_I2C2_BASE (0xE0080000)
sahilmgandhi 18:6a4db94011d3 903 #define LPC_I2S_BASE (0xE0088000)
sahilmgandhi 18:6a4db94011d3 904 #define LPC_MCI_BASE (0xE008C000)
sahilmgandhi 18:6a4db94011d3 905 #define LPC_SC_BASE (0xE01FC000)
sahilmgandhi 18:6a4db94011d3 906 #define LPC_EMAC_BASE (0xFFE00000)
sahilmgandhi 18:6a4db94011d3 907 #define LPC_GPDMA_BASE (0xFFE04000)
sahilmgandhi 18:6a4db94011d3 908 #define LPC_GPDMACH0_BASE (0xFFE04100)
sahilmgandhi 18:6a4db94011d3 909 #define LPC_GPDMACH1_BASE (0xFFE04120)
sahilmgandhi 18:6a4db94011d3 910 #define LPC_EMC_BASE (0xFFE08000)
sahilmgandhi 18:6a4db94011d3 911 #define LPC_USB_BASE (0xFFE0C000)
sahilmgandhi 18:6a4db94011d3 912 #define LPC_VIC_BASE (0xFFFFF000)
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 /* GPIOs */
sahilmgandhi 18:6a4db94011d3 915 #define LPC_GPIO0_BASE (0x3FFFC000)
sahilmgandhi 18:6a4db94011d3 916 #define LPC_GPIO1_BASE (0x3FFFC020)
sahilmgandhi 18:6a4db94011d3 917 #define LPC_GPIO2_BASE (0x3FFFC040)
sahilmgandhi 18:6a4db94011d3 918 #define LPC_GPIO3_BASE (0x3FFFC060)
sahilmgandhi 18:6a4db94011d3 919 #define LPC_GPIO4_BASE (0x3FFFC080)
sahilmgandhi 18:6a4db94011d3 920
sahilmgandhi 18:6a4db94011d3 921
sahilmgandhi 18:6a4db94011d3 922 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 923 /* Peripheral declaration */
sahilmgandhi 18:6a4db94011d3 924 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 925 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
sahilmgandhi 18:6a4db94011d3 926 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
sahilmgandhi 18:6a4db94011d3 927 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
sahilmgandhi 18:6a4db94011d3 928 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
sahilmgandhi 18:6a4db94011d3 929 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
sahilmgandhi 18:6a4db94011d3 930 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
sahilmgandhi 18:6a4db94011d3 931 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
sahilmgandhi 18:6a4db94011d3 932 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
sahilmgandhi 18:6a4db94011d3 933 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
sahilmgandhi 18:6a4db94011d3 934 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
sahilmgandhi 18:6a4db94011d3 935 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
sahilmgandhi 18:6a4db94011d3 936 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
sahilmgandhi 18:6a4db94011d3 937 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
sahilmgandhi 18:6a4db94011d3 938 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
sahilmgandhi 18:6a4db94011d3 939 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
sahilmgandhi 18:6a4db94011d3 940 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
sahilmgandhi 18:6a4db94011d3 941 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
sahilmgandhi 18:6a4db94011d3 942 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 943 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
sahilmgandhi 18:6a4db94011d3 944 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
sahilmgandhi 18:6a4db94011d3 945 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
sahilmgandhi 18:6a4db94011d3 946 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
sahilmgandhi 18:6a4db94011d3 947 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
sahilmgandhi 18:6a4db94011d3 948 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
sahilmgandhi 18:6a4db94011d3 949 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
sahilmgandhi 18:6a4db94011d3 950 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
sahilmgandhi 18:6a4db94011d3 951 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
sahilmgandhi 18:6a4db94011d3 952 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
sahilmgandhi 18:6a4db94011d3 953 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
sahilmgandhi 18:6a4db94011d3 954 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
sahilmgandhi 18:6a4db94011d3 955 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
sahilmgandhi 18:6a4db94011d3 956 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
sahilmgandhi 18:6a4db94011d3 957 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
sahilmgandhi 18:6a4db94011d3 958 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
sahilmgandhi 18:6a4db94011d3 959 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
sahilmgandhi 18:6a4db94011d3 960 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
sahilmgandhi 18:6a4db94011d3 961 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
sahilmgandhi 18:6a4db94011d3 962 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
sahilmgandhi 18:6a4db94011d3 963 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
sahilmgandhi 18:6a4db94011d3 964 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
sahilmgandhi 18:6a4db94011d3 965 #define LPC_EMC (( LPC_EMC_TypeDef *) LPC_EMC_BASE)
sahilmgandhi 18:6a4db94011d3 966
sahilmgandhi 18:6a4db94011d3 967 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 968 }
sahilmgandhi 18:6a4db94011d3 969 #endif
sahilmgandhi 18:6a4db94011d3 970
sahilmgandhi 18:6a4db94011d3 971 #endif // __LPC24xx_H
sahilmgandhi 18:6a4db94011d3 972