MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC23XX/spi_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 17 #include <math.h>
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 21 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 22 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 static const PinMap PinMap_SPI_SCLK[] = {
sahilmgandhi 18:6a4db94011d3 25 {P0_7 , SPI_1, 2},
sahilmgandhi 18:6a4db94011d3 26 {P0_15, SPI_0, 2},
sahilmgandhi 18:6a4db94011d3 27 {P1_20, SPI_0, 3},
sahilmgandhi 18:6a4db94011d3 28 {P1_31, SPI_1, 2},
sahilmgandhi 18:6a4db94011d3 29 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 30 };
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 static const PinMap PinMap_SPI_MOSI[] = {
sahilmgandhi 18:6a4db94011d3 33 {P0_9 , SPI_1, 2},
sahilmgandhi 18:6a4db94011d3 34 {P0_13, SPI_1, 2},
sahilmgandhi 18:6a4db94011d3 35 {P0_18, SPI_0, 2},
sahilmgandhi 18:6a4db94011d3 36 {P1_24, SPI_0, 3},
sahilmgandhi 18:6a4db94011d3 37 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 38 };
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 static const PinMap PinMap_SPI_MISO[] = {
sahilmgandhi 18:6a4db94011d3 41 {P0_8 , SPI_1, 2},
sahilmgandhi 18:6a4db94011d3 42 {P0_12, SPI_1, 2},
sahilmgandhi 18:6a4db94011d3 43 {P0_17, SPI_0, 2},
sahilmgandhi 18:6a4db94011d3 44 {P1_23, SPI_0, 3},
sahilmgandhi 18:6a4db94011d3 45 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 46 };
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 static const PinMap PinMap_SPI_SSEL[] = {
sahilmgandhi 18:6a4db94011d3 49 {P0_6 , SPI_1, 2},
sahilmgandhi 18:6a4db94011d3 50 {P0_11, SPI_1, 2},
sahilmgandhi 18:6a4db94011d3 51 {P0_16, SPI_0, 2},
sahilmgandhi 18:6a4db94011d3 52 {P1_21, SPI_0, 3},
sahilmgandhi 18:6a4db94011d3 53 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 54 };
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 static inline int ssp_disable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 57 static inline int ssp_enable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
sahilmgandhi 18:6a4db94011d3 60 // determine the SPI to use
sahilmgandhi 18:6a4db94011d3 61 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 62 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 63 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 64 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 65 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
sahilmgandhi 18:6a4db94011d3 66 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
sahilmgandhi 18:6a4db94011d3 67 obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
sahilmgandhi 18:6a4db94011d3 68 MBED_ASSERT((int)obj->spi != NC);
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 // enable power and clocking
sahilmgandhi 18:6a4db94011d3 71 switch ((int)obj->spi) {
sahilmgandhi 18:6a4db94011d3 72 case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
sahilmgandhi 18:6a4db94011d3 73 case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
sahilmgandhi 18:6a4db94011d3 74 }
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 // pin out the spi pins
sahilmgandhi 18:6a4db94011d3 77 pinmap_pinout(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 78 pinmap_pinout(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 79 pinmap_pinout(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 80 if (ssel != NC) {
sahilmgandhi 18:6a4db94011d3 81 pinmap_pinout(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 82 }
sahilmgandhi 18:6a4db94011d3 83 }
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 void spi_free(spi_t *obj) {}
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 void spi_format(spi_t *obj, int bits, int mode, int slave) {
sahilmgandhi 18:6a4db94011d3 88 MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
sahilmgandhi 18:6a4db94011d3 89 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 int polarity = (mode & 0x2) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 92 int phase = (mode & 0x1) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 // set it up
sahilmgandhi 18:6a4db94011d3 95 int DSS = bits - 1; // DSS (data select size)
sahilmgandhi 18:6a4db94011d3 96 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
sahilmgandhi 18:6a4db94011d3 97 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 int FRF = 0; // FRF (frame format) = SPI
sahilmgandhi 18:6a4db94011d3 100 uint32_t tmp = obj->spi->CR0;
sahilmgandhi 18:6a4db94011d3 101 tmp &= ~(0xFFFF);
sahilmgandhi 18:6a4db94011d3 102 tmp |= DSS << 0
sahilmgandhi 18:6a4db94011d3 103 | FRF << 4
sahilmgandhi 18:6a4db94011d3 104 | SPO << 6
sahilmgandhi 18:6a4db94011d3 105 | SPH << 7;
sahilmgandhi 18:6a4db94011d3 106 obj->spi->CR0 = tmp;
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 tmp = obj->spi->CR1;
sahilmgandhi 18:6a4db94011d3 109 tmp &= ~(0xD);
sahilmgandhi 18:6a4db94011d3 110 tmp |= 0 << 0 // LBM - loop back mode - off
sahilmgandhi 18:6a4db94011d3 111 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
sahilmgandhi 18:6a4db94011d3 112 | 0 << 3; // SOD - slave output disable - na
sahilmgandhi 18:6a4db94011d3 113 obj->spi->CR1 = tmp;
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 116 }
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 void spi_frequency(spi_t *obj, int hz) {
sahilmgandhi 18:6a4db94011d3 119 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 // setup the spi clock diveder to /1
sahilmgandhi 18:6a4db94011d3 122 switch ((int)obj->spi) {
sahilmgandhi 18:6a4db94011d3 123 case SPI_0:
sahilmgandhi 18:6a4db94011d3 124 LPC_SC->PCLKSEL1 &= ~(3 << 10);
sahilmgandhi 18:6a4db94011d3 125 LPC_SC->PCLKSEL1 |= (1 << 10);
sahilmgandhi 18:6a4db94011d3 126 break;
sahilmgandhi 18:6a4db94011d3 127 case SPI_1:
sahilmgandhi 18:6a4db94011d3 128 LPC_SC->PCLKSEL0 &= ~(3 << 20);
sahilmgandhi 18:6a4db94011d3 129 LPC_SC->PCLKSEL0 |= (1 << 20);
sahilmgandhi 18:6a4db94011d3 130 break;
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 uint32_t PCLK = SystemCoreClock;
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 int prescaler;
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
sahilmgandhi 18:6a4db94011d3 138 int prescale_hz = PCLK / prescaler;
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 // calculate the divider
sahilmgandhi 18:6a4db94011d3 141 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 // check we can support the divider
sahilmgandhi 18:6a4db94011d3 144 if (divider < 256) {
sahilmgandhi 18:6a4db94011d3 145 // prescaler
sahilmgandhi 18:6a4db94011d3 146 obj->spi->CPSR = prescaler;
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 // divider
sahilmgandhi 18:6a4db94011d3 149 obj->spi->CR0 &= ~(0xFFFF << 8);
sahilmgandhi 18:6a4db94011d3 150 obj->spi->CR0 |= (divider - 1) << 8;
sahilmgandhi 18:6a4db94011d3 151 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 152 return;
sahilmgandhi 18:6a4db94011d3 153 }
sahilmgandhi 18:6a4db94011d3 154 }
sahilmgandhi 18:6a4db94011d3 155 error("Couldn't setup requested SPI frequency");
sahilmgandhi 18:6a4db94011d3 156 }
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 static inline int ssp_disable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 159 return obj->spi->CR1 &= ~(1 << 1);
sahilmgandhi 18:6a4db94011d3 160 }
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 static inline int ssp_enable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 163 return obj->spi->CR1 |= (1 << 1);
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 static inline int ssp_readable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 167 return obj->spi->SR & (1 << 2);
sahilmgandhi 18:6a4db94011d3 168 }
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 static inline int ssp_writeable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 171 return obj->spi->SR & (1 << 1);
sahilmgandhi 18:6a4db94011d3 172 }
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 static inline void ssp_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 175 while (!ssp_writeable(obj));
sahilmgandhi 18:6a4db94011d3 176 obj->spi->DR = value;
sahilmgandhi 18:6a4db94011d3 177 }
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 static inline int ssp_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 180 while (!ssp_readable(obj));
sahilmgandhi 18:6a4db94011d3 181 return obj->spi->DR;
sahilmgandhi 18:6a4db94011d3 182 }
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 static inline int ssp_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 185 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 186 }
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 int spi_master_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 189 ssp_write(obj, value);
sahilmgandhi 18:6a4db94011d3 190 return ssp_read(obj);
sahilmgandhi 18:6a4db94011d3 191 }
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 int spi_slave_receive(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 194 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 195 }
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 int spi_slave_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 198 return obj->spi->DR;
sahilmgandhi 18:6a4db94011d3 199 }
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 void spi_slave_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 202 while (ssp_writeable(obj) == 0) ;
sahilmgandhi 18:6a4db94011d3 203 obj->spi->DR = value;
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 int spi_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 207 return ssp_busy(obj);
sahilmgandhi 18:6a4db94011d3 208 }