MacroRat
Mouse code for the MacroRat
mbed-dev/targets/TARGET_NXP/TARGET_LPC23XX/device/vector_defns.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library - Vectors |
| sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2006-2009 ARM Limited. All rights reserved. |
| sahilmgandhi | 18:6a4db94011d3 | 3 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 4 | |
| sahilmgandhi | 18:6a4db94011d3 | 5 | #ifndef MBED_VECTOR_DEFNS_H |
| sahilmgandhi | 18:6a4db94011d3 | 6 | #define MBED_VECTOR_DEFNS_H |
| sahilmgandhi | 18:6a4db94011d3 | 7 | |
| sahilmgandhi | 18:6a4db94011d3 | 8 | // Assember Macros |
| sahilmgandhi | 18:6a4db94011d3 | 9 | #ifdef __ARMCC_VERSION |
| sahilmgandhi | 18:6a4db94011d3 | 10 | #define EXPORT(x) EXPORT x |
| sahilmgandhi | 18:6a4db94011d3 | 11 | #define WEAK_EXPORT(x) EXPORT x [WEAK] |
| sahilmgandhi | 18:6a4db94011d3 | 12 | #define IMPORT(x) IMPORT x |
| sahilmgandhi | 18:6a4db94011d3 | 13 | #define LABEL(x) x |
| sahilmgandhi | 18:6a4db94011d3 | 14 | #else |
| sahilmgandhi | 18:6a4db94011d3 | 15 | #define EXPORT(x) .global x |
| sahilmgandhi | 18:6a4db94011d3 | 16 | #define WEAK_EXPORT(x) .weak x |
| sahilmgandhi | 18:6a4db94011d3 | 17 | #define IMPORT(x) .global x |
| sahilmgandhi | 18:6a4db94011d3 | 18 | #define LABEL(x) x: |
| sahilmgandhi | 18:6a4db94011d3 | 19 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 20 | |
| sahilmgandhi | 18:6a4db94011d3 | 21 | // RealMonitor |
| sahilmgandhi | 18:6a4db94011d3 | 22 | // Requires RAM (0x40000040-0x4000011F) to be allocated by the linker |
| sahilmgandhi | 18:6a4db94011d3 | 23 | |
| sahilmgandhi | 18:6a4db94011d3 | 24 | // RealMonitor entry points |
| sahilmgandhi | 18:6a4db94011d3 | 25 | #define rm_init_entry 0x7fffff91 |
| sahilmgandhi | 18:6a4db94011d3 | 26 | #define rm_undef_handler 0x7fffffa0 |
| sahilmgandhi | 18:6a4db94011d3 | 27 | #define rm_prefetchabort_handler 0x7fffffb0 |
| sahilmgandhi | 18:6a4db94011d3 | 28 | #define rm_dataabort_handler 0x7fffffc0 |
| sahilmgandhi | 18:6a4db94011d3 | 29 | #define rm_irqhandler2 0x7fffffe0 |
| sahilmgandhi | 18:6a4db94011d3 | 30 | //#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64 |
| sahilmgandhi | 18:6a4db94011d3 | 31 | #define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40 |
| sahilmgandhi | 18:6a4db94011d3 | 32 | |
| sahilmgandhi | 18:6a4db94011d3 | 33 | // Unofficial RealMonitor entry points and variables |
| sahilmgandhi | 18:6a4db94011d3 | 34 | #define RM_MSG_SWI 0x00940000 |
| sahilmgandhi | 18:6a4db94011d3 | 35 | #define StateP 0x40000040 |
| sahilmgandhi | 18:6a4db94011d3 | 36 | |
| sahilmgandhi | 18:6a4db94011d3 | 37 | // VIC register addresses |
| sahilmgandhi | 18:6a4db94011d3 | 38 | #define VIC_Base 0xfffff000 |
| sahilmgandhi | 18:6a4db94011d3 | 39 | #define VICAddress_Offset 0xf00 |
| sahilmgandhi | 18:6a4db94011d3 | 40 | #define VICVectAddr0_Offset 0x100 |
| sahilmgandhi | 18:6a4db94011d3 | 41 | #define VICVectAddr2_Offset 0x108 |
| sahilmgandhi | 18:6a4db94011d3 | 42 | #define VICVectAddr3_Offset 0x10c |
| sahilmgandhi | 18:6a4db94011d3 | 43 | #define VICVectAddr31_Offset 0x17c |
| sahilmgandhi | 18:6a4db94011d3 | 44 | #define VICIntEnClr_Offset 0x014 |
| sahilmgandhi | 18:6a4db94011d3 | 45 | #define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014)) |
| sahilmgandhi | 18:6a4db94011d3 | 46 | #define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108)) |
| sahilmgandhi | 18:6a4db94011d3 | 47 | #define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C)) |
| sahilmgandhi | 18:6a4db94011d3 | 48 | |
| sahilmgandhi | 18:6a4db94011d3 | 49 | // ARM Mode bits and Interrupt flags in PSRs |
| sahilmgandhi | 18:6a4db94011d3 | 50 | #define Mode_USR 0x10 |
| sahilmgandhi | 18:6a4db94011d3 | 51 | #define Mode_FIQ 0x11 |
| sahilmgandhi | 18:6a4db94011d3 | 52 | #define Mode_IRQ 0x12 |
| sahilmgandhi | 18:6a4db94011d3 | 53 | #define Mode_SVC 0x13 |
| sahilmgandhi | 18:6a4db94011d3 | 54 | #define Mode_ABT 0x17 |
| sahilmgandhi | 18:6a4db94011d3 | 55 | #define Mode_UND 0x1B |
| sahilmgandhi | 18:6a4db94011d3 | 56 | #define Mode_SYS 0x1F |
| sahilmgandhi | 18:6a4db94011d3 | 57 | #define I_Bit 0x80 // when I bit is set, IRQ is disabled |
| sahilmgandhi | 18:6a4db94011d3 | 58 | #define F_Bit 0x40 // when F bit is set, FIQ is disabled |
| sahilmgandhi | 18:6a4db94011d3 | 59 | |
| sahilmgandhi | 18:6a4db94011d3 | 60 | // MCU RAM |
| sahilmgandhi | 18:6a4db94011d3 | 61 | #define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base |
| sahilmgandhi | 18:6a4db94011d3 | 62 | #define LPC2368_RAM_SIZE 0x8000 // 32KB |
| sahilmgandhi | 18:6a4db94011d3 | 63 | |
| sahilmgandhi | 18:6a4db94011d3 | 64 | // ISR Stack Allocation |
| sahilmgandhi | 18:6a4db94011d3 | 65 | #define UND_stack_size 0x00000040 |
| sahilmgandhi | 18:6a4db94011d3 | 66 | #define SVC_stack_size 0x00000040 |
| sahilmgandhi | 18:6a4db94011d3 | 67 | #define ABT_stack_size 0x00000040 |
| sahilmgandhi | 18:6a4db94011d3 | 68 | #define FIQ_stack_size 0x00000000 |
| sahilmgandhi | 18:6a4db94011d3 | 69 | #define IRQ_stack_size 0x00000040 |
| sahilmgandhi | 18:6a4db94011d3 | 70 | |
| sahilmgandhi | 18:6a4db94011d3 | 71 | #define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size) |
| sahilmgandhi | 18:6a4db94011d3 | 72 | |
| sahilmgandhi | 18:6a4db94011d3 | 73 | // Full Descending Stack, so top-most stack points to just above the top of RAM |
| sahilmgandhi | 18:6a4db94011d3 | 74 | #define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE) |
| sahilmgandhi | 18:6a4db94011d3 | 75 | #define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size) |
| sahilmgandhi | 18:6a4db94011d3 | 76 | |
| sahilmgandhi | 18:6a4db94011d3 | 77 | #endif |