MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC23XX/device/system_LPC23xx.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
sahilmgandhi 18:6a4db94011d3 5 */
sahilmgandhi 18:6a4db94011d3 6
sahilmgandhi 18:6a4db94011d3 7 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 8 #include "LPC23xx.h"
sahilmgandhi 18:6a4db94011d3 9
sahilmgandhi 18:6a4db94011d3 10 #define CLOCK_SETUP 1
sahilmgandhi 18:6a4db94011d3 11 #define SCS_Val 0x00000020
sahilmgandhi 18:6a4db94011d3 12 #define CLKSRCSEL_Val 0x00000001
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 #define PLL0_SETUP 1
sahilmgandhi 18:6a4db94011d3 15 #define PLL0CFG_Val 0x00000013
sahilmgandhi 18:6a4db94011d3 16 #define CCLKCFG_Val 0x00000007
sahilmgandhi 18:6a4db94011d3 17 #define USBCLKCFG_Val 0x00000009
sahilmgandhi 18:6a4db94011d3 18 #define PCLKSEL0_Val 0x00000000
sahilmgandhi 18:6a4db94011d3 19 #define PCLKSEL1_Val 0x00000000
sahilmgandhi 18:6a4db94011d3 20 #define PCONP_Val 0x042887DE
sahilmgandhi 18:6a4db94011d3 21 #define CLKOUTCFG_Val 0x00000000
sahilmgandhi 18:6a4db94011d3 22 #define MAMCR_Val 0x00000001 // there is a bug in the MAM so it should never be fully enabled (only disabled or partially enabled)
sahilmgandhi 18:6a4db94011d3 23 #define MAMTIM_Val 0x00000004
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 26 DEFINES
sahilmgandhi 18:6a4db94011d3 27 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 #define XTAL (12000000UL) /* Oscillator frequency */
sahilmgandhi 18:6a4db94011d3 30 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
sahilmgandhi 18:6a4db94011d3 31 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
sahilmgandhi 18:6a4db94011d3 32 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 /* F_cco0 = (2 * M * F_in) / N */
sahilmgandhi 18:6a4db94011d3 35 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
sahilmgandhi 18:6a4db94011d3 36 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
sahilmgandhi 18:6a4db94011d3 37 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
sahilmgandhi 18:6a4db94011d3 38 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 /* Determine core clock frequency according to settings */
sahilmgandhi 18:6a4db94011d3 41 #if (PLL0_SETUP)
sahilmgandhi 18:6a4db94011d3 42 #if ((CLKSRCSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 43 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 44 #elif ((CLKSRCSEL_Val & 0x03) == 2)
sahilmgandhi 18:6a4db94011d3 45 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 46 #else
sahilmgandhi 18:6a4db94011d3 47 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
sahilmgandhi 18:6a4db94011d3 48 #endif
sahilmgandhi 18:6a4db94011d3 49 #endif
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 53 Clock Variable definitions
sahilmgandhi 18:6a4db94011d3 54 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 55 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 58 Clock functions
sahilmgandhi 18:6a4db94011d3 59 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 60 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
sahilmgandhi 18:6a4db94011d3 61 {
sahilmgandhi 18:6a4db94011d3 62 /* Determine clock frequency according to clock register values */
sahilmgandhi 18:6a4db94011d3 63 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
sahilmgandhi 18:6a4db94011d3 64 switch (LPC_SC->CLKSRCSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 65 case 0: /* Int. RC oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 66 case 3: /* Reserved, default to Int. RC */
sahilmgandhi 18:6a4db94011d3 67 SystemCoreClock = (IRC_OSC *
sahilmgandhi 18:6a4db94011d3 68 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
sahilmgandhi 18:6a4db94011d3 69 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
sahilmgandhi 18:6a4db94011d3 70 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
sahilmgandhi 18:6a4db94011d3 71 break;
sahilmgandhi 18:6a4db94011d3 72 case 1: /* Main oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 73 SystemCoreClock = (OSC_CLK *
sahilmgandhi 18:6a4db94011d3 74 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
sahilmgandhi 18:6a4db94011d3 75 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
sahilmgandhi 18:6a4db94011d3 76 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
sahilmgandhi 18:6a4db94011d3 77 break;
sahilmgandhi 18:6a4db94011d3 78 case 2: /* RTC oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 79 SystemCoreClock = (RTC_CLK *
sahilmgandhi 18:6a4db94011d3 80 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
sahilmgandhi 18:6a4db94011d3 81 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
sahilmgandhi 18:6a4db94011d3 82 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
sahilmgandhi 18:6a4db94011d3 83 break;
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85 } else {
sahilmgandhi 18:6a4db94011d3 86 switch (LPC_SC->CLKSRCSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 87 case 0: /* Int. RC oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 88 case 3: /* Reserved, default to Int. RC */
sahilmgandhi 18:6a4db94011d3 89 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
sahilmgandhi 18:6a4db94011d3 90 break;
sahilmgandhi 18:6a4db94011d3 91 case 1: /* Main oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 92 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
sahilmgandhi 18:6a4db94011d3 93 break;
sahilmgandhi 18:6a4db94011d3 94 case 2: /* RTC oscillator => PLL0 */
sahilmgandhi 18:6a4db94011d3 95 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
sahilmgandhi 18:6a4db94011d3 96 break;
sahilmgandhi 18:6a4db94011d3 97 }
sahilmgandhi 18:6a4db94011d3 98 }
sahilmgandhi 18:6a4db94011d3 99 }
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /**
sahilmgandhi 18:6a4db94011d3 102 * Initialize the system
sahilmgandhi 18:6a4db94011d3 103 *
sahilmgandhi 18:6a4db94011d3 104 * @param none
sahilmgandhi 18:6a4db94011d3 105 * @return none
sahilmgandhi 18:6a4db94011d3 106 *
sahilmgandhi 18:6a4db94011d3 107 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 108 * Initialize the System and update the SystemFrequency variable.
sahilmgandhi 18:6a4db94011d3 109 */
sahilmgandhi 18:6a4db94011d3 110 void SystemInit (void)
sahilmgandhi 18:6a4db94011d3 111 {
sahilmgandhi 18:6a4db94011d3 112 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 113 LPC_SC->SCS = SCS_Val;
sahilmgandhi 18:6a4db94011d3 114 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
sahilmgandhi 18:6a4db94011d3 115 while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
sahilmgandhi 18:6a4db94011d3 116 }
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 #if (PLL0_SETUP)
sahilmgandhi 18:6a4db94011d3 121 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
sahilmgandhi 18:6a4db94011d3 122 LPC_SC->PLL0CFG = PLL0CFG_Val;
sahilmgandhi 18:6a4db94011d3 123 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
sahilmgandhi 18:6a4db94011d3 124 LPC_SC->PLL0FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 125 LPC_SC->PLL0FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 126 while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
sahilmgandhi 18:6a4db94011d3 129 LPC_SC->PLL0FEED = 0xAA;
sahilmgandhi 18:6a4db94011d3 130 LPC_SC->PLL0FEED = 0x55;
sahilmgandhi 18:6a4db94011d3 131 #endif
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
sahilmgandhi 18:6a4db94011d3 134 #endif
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
sahilmgandhi 18:6a4db94011d3 137 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 // Setup MAM
sahilmgandhi 18:6a4db94011d3 142 LPC_SC->MAMTIM = MAMTIM_Val;
sahilmgandhi 18:6a4db94011d3 143 LPC_SC->MAMCR = MAMCR_Val;
sahilmgandhi 18:6a4db94011d3 144 }