MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/startup_LPC17xx.S@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* File: startup_ARMCM3.s
sahilmgandhi 18:6a4db94011d3 2 * Purpose: startup file for Cortex-M3/M4 devices. Should use with
sahilmgandhi 18:6a4db94011d3 3 * GNU Tools for ARM Embedded Processors
sahilmgandhi 18:6a4db94011d3 4 * Version: V1.1
sahilmgandhi 18:6a4db94011d3 5 * Date: 17 June 2011
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * Copyright (C) 2011 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 8 * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
sahilmgandhi 18:6a4db94011d3 9 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 10 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 13 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 15 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 16 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 17 */
sahilmgandhi 18:6a4db94011d3 18 .syntax unified
sahilmgandhi 18:6a4db94011d3 19 .arch armv7-m
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 /* Memory Model
sahilmgandhi 18:6a4db94011d3 22 The HEAP starts at the end of the DATA section and grows upward.
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 The STACK starts at the end of the RAM and grows downward.
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 The HEAP and stack STACK are only checked at compile time:
sahilmgandhi 18:6a4db94011d3 27 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 This is just a check for the bare minimum for the Heap+Stack area before
sahilmgandhi 18:6a4db94011d3 30 aborting compilation, it is not the run time limit:
sahilmgandhi 18:6a4db94011d3 31 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33 .section .stack
sahilmgandhi 18:6a4db94011d3 34 .align 3
sahilmgandhi 18:6a4db94011d3 35 #ifdef __STACK_SIZE
sahilmgandhi 18:6a4db94011d3 36 .equ Stack_Size, __STACK_SIZE
sahilmgandhi 18:6a4db94011d3 37 #else
sahilmgandhi 18:6a4db94011d3 38 .equ Stack_Size, 0xc00
sahilmgandhi 18:6a4db94011d3 39 #endif
sahilmgandhi 18:6a4db94011d3 40 .globl __StackTop
sahilmgandhi 18:6a4db94011d3 41 .globl __StackLimit
sahilmgandhi 18:6a4db94011d3 42 __StackLimit:
sahilmgandhi 18:6a4db94011d3 43 .space Stack_Size
sahilmgandhi 18:6a4db94011d3 44 .size __StackLimit, . - __StackLimit
sahilmgandhi 18:6a4db94011d3 45 __StackTop:
sahilmgandhi 18:6a4db94011d3 46 .size __StackTop, . - __StackTop
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 .section .heap
sahilmgandhi 18:6a4db94011d3 49 .align 3
sahilmgandhi 18:6a4db94011d3 50 #ifdef __HEAP_SIZE
sahilmgandhi 18:6a4db94011d3 51 .equ Heap_Size, __HEAP_SIZE
sahilmgandhi 18:6a4db94011d3 52 #else
sahilmgandhi 18:6a4db94011d3 53 .equ Heap_Size, 0x800
sahilmgandhi 18:6a4db94011d3 54 #endif
sahilmgandhi 18:6a4db94011d3 55 .globl __HeapBase
sahilmgandhi 18:6a4db94011d3 56 .globl __HeapLimit
sahilmgandhi 18:6a4db94011d3 57 __HeapBase:
sahilmgandhi 18:6a4db94011d3 58 .space Heap_Size
sahilmgandhi 18:6a4db94011d3 59 .size __HeapBase, . - __HeapBase
sahilmgandhi 18:6a4db94011d3 60 __HeapLimit:
sahilmgandhi 18:6a4db94011d3 61 .size __HeapLimit, . - __HeapLimit
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 .section .isr_vector
sahilmgandhi 18:6a4db94011d3 64 .align 2
sahilmgandhi 18:6a4db94011d3 65 .globl __isr_vector
sahilmgandhi 18:6a4db94011d3 66 __isr_vector:
sahilmgandhi 18:6a4db94011d3 67 .long __StackTop /* Top of Stack */
sahilmgandhi 18:6a4db94011d3 68 .long Reset_Handler /* Reset Handler */
sahilmgandhi 18:6a4db94011d3 69 .long NMI_Handler /* NMI Handler */
sahilmgandhi 18:6a4db94011d3 70 .long HardFault_Handler /* Hard Fault Handler */
sahilmgandhi 18:6a4db94011d3 71 .long MemManage_Handler /* MPU Fault Handler */
sahilmgandhi 18:6a4db94011d3 72 .long BusFault_Handler /* Bus Fault Handler */
sahilmgandhi 18:6a4db94011d3 73 .long UsageFault_Handler /* Usage Fault Handler */
sahilmgandhi 18:6a4db94011d3 74 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 75 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 76 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 77 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 78 .long SVC_Handler /* SVCall Handler */
sahilmgandhi 18:6a4db94011d3 79 .long DebugMon_Handler /* Debug Monitor Handler */
sahilmgandhi 18:6a4db94011d3 80 .long 0 /* Reserved */
sahilmgandhi 18:6a4db94011d3 81 .long PendSV_Handler /* PendSV Handler */
sahilmgandhi 18:6a4db94011d3 82 .long SysTick_Handler /* SysTick Handler */
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 /* External interrupts */
sahilmgandhi 18:6a4db94011d3 85 .long WDT_IRQHandler /* 16: Watchdog Timer */
sahilmgandhi 18:6a4db94011d3 86 .long TIMER0_IRQHandler /* 17: Timer0 */
sahilmgandhi 18:6a4db94011d3 87 .long TIMER1_IRQHandler /* 18: Timer1 */
sahilmgandhi 18:6a4db94011d3 88 .long TIMER2_IRQHandler /* 19: Timer2 */
sahilmgandhi 18:6a4db94011d3 89 .long TIMER3_IRQHandler /* 20: Timer3 */
sahilmgandhi 18:6a4db94011d3 90 .long UART0_IRQHandler /* 21: UART0 */
sahilmgandhi 18:6a4db94011d3 91 .long UART1_IRQHandler /* 22: UART1 */
sahilmgandhi 18:6a4db94011d3 92 .long UART2_IRQHandler /* 23: UART2 */
sahilmgandhi 18:6a4db94011d3 93 .long UART3_IRQHandler /* 24: UART3 */
sahilmgandhi 18:6a4db94011d3 94 .long PWM1_IRQHandler /* 25: PWM1 */
sahilmgandhi 18:6a4db94011d3 95 .long I2C0_IRQHandler /* 26: I2C0 */
sahilmgandhi 18:6a4db94011d3 96 .long I2C1_IRQHandler /* 27: I2C1 */
sahilmgandhi 18:6a4db94011d3 97 .long I2C2_IRQHandler /* 28: I2C2 */
sahilmgandhi 18:6a4db94011d3 98 .long SPI_IRQHandler /* 29: SPI */
sahilmgandhi 18:6a4db94011d3 99 .long SSP0_IRQHandler /* 30: SSP0 */
sahilmgandhi 18:6a4db94011d3 100 .long SSP1_IRQHandler /* 31: SSP1 */
sahilmgandhi 18:6a4db94011d3 101 .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
sahilmgandhi 18:6a4db94011d3 102 .long RTC_IRQHandler /* 33: Real Time Clock */
sahilmgandhi 18:6a4db94011d3 103 .long EINT0_IRQHandler /* 34: External Interrupt 0 */
sahilmgandhi 18:6a4db94011d3 104 .long EINT1_IRQHandler /* 35: External Interrupt 1 */
sahilmgandhi 18:6a4db94011d3 105 .long EINT2_IRQHandler /* 36: External Interrupt 2 */
sahilmgandhi 18:6a4db94011d3 106 .long EINT3_IRQHandler /* 37: External Interrupt 3 */
sahilmgandhi 18:6a4db94011d3 107 .long ADC_IRQHandler /* 38: A/D Converter */
sahilmgandhi 18:6a4db94011d3 108 .long BOD_IRQHandler /* 39: Brown-Out Detect */
sahilmgandhi 18:6a4db94011d3 109 .long USB_IRQHandler /* 40: USB */
sahilmgandhi 18:6a4db94011d3 110 .long CAN_IRQHandler /* 41: CAN */
sahilmgandhi 18:6a4db94011d3 111 .long DMA_IRQHandler /* 42: General Purpose DMA */
sahilmgandhi 18:6a4db94011d3 112 .long I2S_IRQHandler /* 43: I2S */
sahilmgandhi 18:6a4db94011d3 113 .long ENET_IRQHandler /* 44: Ethernet */
sahilmgandhi 18:6a4db94011d3 114 .long RIT_IRQHandler /* 45: Repetitive Interrupt Timer */
sahilmgandhi 18:6a4db94011d3 115 .long MCPWM_IRQHandler /* 46: Motor Control PWM */
sahilmgandhi 18:6a4db94011d3 116 .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
sahilmgandhi 18:6a4db94011d3 117 .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
sahilmgandhi 18:6a4db94011d3 118 .long USBActivity_IRQHandler /* 49: USB Activity */
sahilmgandhi 18:6a4db94011d3 119 .long CANActivity_IRQHandler /* 50: CAN Activity */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 .size __isr_vector, . - __isr_vector
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 .text
sahilmgandhi 18:6a4db94011d3 124 .thumb
sahilmgandhi 18:6a4db94011d3 125 .thumb_func
sahilmgandhi 18:6a4db94011d3 126 .align 2
sahilmgandhi 18:6a4db94011d3 127 .globl Reset_Handler
sahilmgandhi 18:6a4db94011d3 128 .type Reset_Handler, %function
sahilmgandhi 18:6a4db94011d3 129 Reset_Handler:
sahilmgandhi 18:6a4db94011d3 130 /* Loop to copy data from read only memory to RAM. The ranges
sahilmgandhi 18:6a4db94011d3 131 * of copy from/to are specified by following symbols evaluated in
sahilmgandhi 18:6a4db94011d3 132 * linker script.
sahilmgandhi 18:6a4db94011d3 133 * _etext: End of code section, i.e., begin of data sections to copy from.
sahilmgandhi 18:6a4db94011d3 134 * __data_start__/__data_end__: RAM address range that data should be
sahilmgandhi 18:6a4db94011d3 135 * copied to. Both must be aligned to 4 bytes boundary. */
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 ldr r1, =__etext
sahilmgandhi 18:6a4db94011d3 138 ldr r2, =__data_start__
sahilmgandhi 18:6a4db94011d3 139 ldr r3, =__data_end__
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 .Lflash_to_ram_loop:
sahilmgandhi 18:6a4db94011d3 142 cmp r2, r3
sahilmgandhi 18:6a4db94011d3 143 ittt lt
sahilmgandhi 18:6a4db94011d3 144 ldrlt r0, [r1], #4
sahilmgandhi 18:6a4db94011d3 145 strlt r0, [r2], #4
sahilmgandhi 18:6a4db94011d3 146 blt .Lflash_to_ram_loop
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 ldr r0, =SystemInit
sahilmgandhi 18:6a4db94011d3 149 blx r0
sahilmgandhi 18:6a4db94011d3 150 ldr r0, =_start
sahilmgandhi 18:6a4db94011d3 151 bx r0
sahilmgandhi 18:6a4db94011d3 152 .pool
sahilmgandhi 18:6a4db94011d3 153 .size Reset_Handler, . - Reset_Handler
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 .text
sahilmgandhi 18:6a4db94011d3 156 /* Macro to define default handlers. Default handler
sahilmgandhi 18:6a4db94011d3 157 * will be weak symbol and just dead loops. They can be
sahilmgandhi 18:6a4db94011d3 158 * overwritten by other handlers */
sahilmgandhi 18:6a4db94011d3 159 .macro def_default_handler handler_name
sahilmgandhi 18:6a4db94011d3 160 .align 1
sahilmgandhi 18:6a4db94011d3 161 .thumb_func
sahilmgandhi 18:6a4db94011d3 162 .weak \handler_name
sahilmgandhi 18:6a4db94011d3 163 .type \handler_name, %function
sahilmgandhi 18:6a4db94011d3 164 \handler_name :
sahilmgandhi 18:6a4db94011d3 165 b .
sahilmgandhi 18:6a4db94011d3 166 .size \handler_name, . - \handler_name
sahilmgandhi 18:6a4db94011d3 167 .endm
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 def_default_handler NMI_Handler
sahilmgandhi 18:6a4db94011d3 170 def_default_handler HardFault_Handler
sahilmgandhi 18:6a4db94011d3 171 def_default_handler MemManage_Handler
sahilmgandhi 18:6a4db94011d3 172 def_default_handler BusFault_Handler
sahilmgandhi 18:6a4db94011d3 173 def_default_handler UsageFault_Handler
sahilmgandhi 18:6a4db94011d3 174 def_default_handler SVC_Handler
sahilmgandhi 18:6a4db94011d3 175 def_default_handler DebugMon_Handler
sahilmgandhi 18:6a4db94011d3 176 def_default_handler PendSV_Handler
sahilmgandhi 18:6a4db94011d3 177 def_default_handler SysTick_Handler
sahilmgandhi 18:6a4db94011d3 178 def_default_handler Default_Handler
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 .macro def_irq_default_handler handler_name
sahilmgandhi 18:6a4db94011d3 181 .weak \handler_name
sahilmgandhi 18:6a4db94011d3 182 .set \handler_name, Default_Handler
sahilmgandhi 18:6a4db94011d3 183 .endm
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 def_irq_default_handler WDT_IRQHandler
sahilmgandhi 18:6a4db94011d3 186 def_irq_default_handler TIMER0_IRQHandler
sahilmgandhi 18:6a4db94011d3 187 def_irq_default_handler TIMER1_IRQHandler
sahilmgandhi 18:6a4db94011d3 188 def_irq_default_handler TIMER2_IRQHandler
sahilmgandhi 18:6a4db94011d3 189 def_irq_default_handler TIMER3_IRQHandler
sahilmgandhi 18:6a4db94011d3 190 def_irq_default_handler UART0_IRQHandler
sahilmgandhi 18:6a4db94011d3 191 def_irq_default_handler UART1_IRQHandler
sahilmgandhi 18:6a4db94011d3 192 def_irq_default_handler UART2_IRQHandler
sahilmgandhi 18:6a4db94011d3 193 def_irq_default_handler UART3_IRQHandler
sahilmgandhi 18:6a4db94011d3 194 def_irq_default_handler PWM1_IRQHandler
sahilmgandhi 18:6a4db94011d3 195 def_irq_default_handler I2C0_IRQHandler
sahilmgandhi 18:6a4db94011d3 196 def_irq_default_handler I2C1_IRQHandler
sahilmgandhi 18:6a4db94011d3 197 def_irq_default_handler I2C2_IRQHandler
sahilmgandhi 18:6a4db94011d3 198 def_irq_default_handler SPI_IRQHandler
sahilmgandhi 18:6a4db94011d3 199 def_irq_default_handler SSP0_IRQHandler
sahilmgandhi 18:6a4db94011d3 200 def_irq_default_handler SSP1_IRQHandler
sahilmgandhi 18:6a4db94011d3 201 def_irq_default_handler PLL0_IRQHandler
sahilmgandhi 18:6a4db94011d3 202 def_irq_default_handler RTC_IRQHandler
sahilmgandhi 18:6a4db94011d3 203 def_irq_default_handler EINT0_IRQHandler
sahilmgandhi 18:6a4db94011d3 204 def_irq_default_handler EINT1_IRQHandler
sahilmgandhi 18:6a4db94011d3 205 def_irq_default_handler EINT2_IRQHandler
sahilmgandhi 18:6a4db94011d3 206 def_irq_default_handler EINT3_IRQHandler
sahilmgandhi 18:6a4db94011d3 207 def_irq_default_handler ADC_IRQHandler
sahilmgandhi 18:6a4db94011d3 208 def_irq_default_handler BOD_IRQHandler
sahilmgandhi 18:6a4db94011d3 209 def_irq_default_handler USB_IRQHandler
sahilmgandhi 18:6a4db94011d3 210 def_irq_default_handler CAN_IRQHandler
sahilmgandhi 18:6a4db94011d3 211 def_irq_default_handler DMA_IRQHandler
sahilmgandhi 18:6a4db94011d3 212 def_irq_default_handler I2S_IRQHandler
sahilmgandhi 18:6a4db94011d3 213 def_irq_default_handler ENET_IRQHandler
sahilmgandhi 18:6a4db94011d3 214 def_irq_default_handler RIT_IRQHandler
sahilmgandhi 18:6a4db94011d3 215 def_irq_default_handler MCPWM_IRQHandler
sahilmgandhi 18:6a4db94011d3 216 def_irq_default_handler QEI_IRQHandler
sahilmgandhi 18:6a4db94011d3 217 def_irq_default_handler PLL1_IRQHandler
sahilmgandhi 18:6a4db94011d3 218 def_irq_default_handler USBActivity_IRQHandler
sahilmgandhi 18:6a4db94011d3 219 def_irq_default_handler CANActivity_IRQHandler
sahilmgandhi 18:6a4db94011d3 220 def_irq_default_handler DEF_IRQHandler
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 .end
sahilmgandhi 18:6a4db94011d3 223