MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC15XX/spi_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 17 #include <math.h>
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 21 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 22 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 static const SWM_Map SWM_SPI_SSEL[] = {
sahilmgandhi 18:6a4db94011d3 25 {4, 0},
sahilmgandhi 18:6a4db94011d3 26 {5, 24},
sahilmgandhi 18:6a4db94011d3 27 };
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 static const SWM_Map SWM_SPI_SCLK[] = {
sahilmgandhi 18:6a4db94011d3 30 {3, 8},
sahilmgandhi 18:6a4db94011d3 31 {5, 0},
sahilmgandhi 18:6a4db94011d3 32 };
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 static const SWM_Map SWM_SPI_MOSI[] = {
sahilmgandhi 18:6a4db94011d3 35 {3, 16},
sahilmgandhi 18:6a4db94011d3 36 {5, 8},
sahilmgandhi 18:6a4db94011d3 37 };
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 static const SWM_Map SWM_SPI_MISO[] = {
sahilmgandhi 18:6a4db94011d3 40 {3, 24},
sahilmgandhi 18:6a4db94011d3 41 {5, 16},
sahilmgandhi 18:6a4db94011d3 42 };
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 // bit flags for used SPIs
sahilmgandhi 18:6a4db94011d3 45 static unsigned char spi_used = 0;
sahilmgandhi 18:6a4db94011d3 46 static int get_available_spi(PinName mosi, PinName miso, PinName sclk, PinName ssel)
sahilmgandhi 18:6a4db94011d3 47 {
sahilmgandhi 18:6a4db94011d3 48 if (spi_used == 0) {
sahilmgandhi 18:6a4db94011d3 49 return 0; // The first user
sahilmgandhi 18:6a4db94011d3 50 }
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 const SWM_Map *swm;
sahilmgandhi 18:6a4db94011d3 53 uint32_t regVal;
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 // Investigate if same pins as the used SPI0/1 - to be able to reuse it
sahilmgandhi 18:6a4db94011d3 56 for (int spi_n = 0; spi_n < 2; spi_n++) {
sahilmgandhi 18:6a4db94011d3 57 if (spi_used & (1<<spi_n)) {
sahilmgandhi 18:6a4db94011d3 58 if (sclk != NC) {
sahilmgandhi 18:6a4db94011d3 59 swm = &SWM_SPI_SCLK[spi_n];
sahilmgandhi 18:6a4db94011d3 60 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 61 if (regVal != (sclk << swm->offset)) {
sahilmgandhi 18:6a4db94011d3 62 // Existing pin is not the same as the one we want
sahilmgandhi 18:6a4db94011d3 63 continue;
sahilmgandhi 18:6a4db94011d3 64 }
sahilmgandhi 18:6a4db94011d3 65 }
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 if (mosi != NC) {
sahilmgandhi 18:6a4db94011d3 68 swm = &SWM_SPI_MOSI[spi_n];
sahilmgandhi 18:6a4db94011d3 69 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 70 if (regVal != (mosi << swm->offset)) {
sahilmgandhi 18:6a4db94011d3 71 // Existing pin is not the same as the one we want
sahilmgandhi 18:6a4db94011d3 72 continue;
sahilmgandhi 18:6a4db94011d3 73 }
sahilmgandhi 18:6a4db94011d3 74 }
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 if (miso != NC) {
sahilmgandhi 18:6a4db94011d3 77 swm = &SWM_SPI_MISO[spi_n];
sahilmgandhi 18:6a4db94011d3 78 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 79 if (regVal != (miso << swm->offset)) {
sahilmgandhi 18:6a4db94011d3 80 // Existing pin is not the same as the one we want
sahilmgandhi 18:6a4db94011d3 81 continue;
sahilmgandhi 18:6a4db94011d3 82 }
sahilmgandhi 18:6a4db94011d3 83 }
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 if (ssel != NC) {
sahilmgandhi 18:6a4db94011d3 86 swm = &SWM_SPI_SSEL[spi_n];
sahilmgandhi 18:6a4db94011d3 87 regVal = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 88 if (regVal != (ssel << swm->offset)) {
sahilmgandhi 18:6a4db94011d3 89 // Existing pin is not the same as the one we want
sahilmgandhi 18:6a4db94011d3 90 continue;
sahilmgandhi 18:6a4db94011d3 91 }
sahilmgandhi 18:6a4db94011d3 92 }
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 // The pins for the currently used SPIx are the same as the
sahilmgandhi 18:6a4db94011d3 95 // ones we want so we will reuse it
sahilmgandhi 18:6a4db94011d3 96 return spi_n;
sahilmgandhi 18:6a4db94011d3 97 }
sahilmgandhi 18:6a4db94011d3 98 }
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 // None of the existing SPIx pin setups match the pins we want
sahilmgandhi 18:6a4db94011d3 101 // so the last hope is to select one unused SPIx
sahilmgandhi 18:6a4db94011d3 102 if ((spi_used & 1) == 0) {
sahilmgandhi 18:6a4db94011d3 103 return 0;
sahilmgandhi 18:6a4db94011d3 104 } else if ((spi_used & 2) == 0) {
sahilmgandhi 18:6a4db94011d3 105 return 1;
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 // No matching setup and no free SPIx
sahilmgandhi 18:6a4db94011d3 109 return -1;
sahilmgandhi 18:6a4db94011d3 110 }
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 static inline void spi_disable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 113 static inline void spi_enable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
sahilmgandhi 18:6a4db94011d3 116 {
sahilmgandhi 18:6a4db94011d3 117 int spi_n = get_available_spi(mosi, miso, sclk, ssel);
sahilmgandhi 18:6a4db94011d3 118 if (spi_n == -1) {
sahilmgandhi 18:6a4db94011d3 119 error("No available SPI");
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 obj->spi_n = spi_n;
sahilmgandhi 18:6a4db94011d3 123 spi_used |= (1 << spi_n);
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE);
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 const SWM_Map *swm;
sahilmgandhi 18:6a4db94011d3 128 uint32_t regVal;
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 if (sclk != NC) {
sahilmgandhi 18:6a4db94011d3 131 swm = &SWM_SPI_SCLK[obj->spi_n];
sahilmgandhi 18:6a4db94011d3 132 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 133 LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
sahilmgandhi 18:6a4db94011d3 134 }
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 if (mosi != NC) {
sahilmgandhi 18:6a4db94011d3 137 swm = &SWM_SPI_MOSI[obj->spi_n];
sahilmgandhi 18:6a4db94011d3 138 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 139 LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
sahilmgandhi 18:6a4db94011d3 140 }
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 if (miso != NC) {
sahilmgandhi 18:6a4db94011d3 143 swm = &SWM_SPI_MISO[obj->spi_n];
sahilmgandhi 18:6a4db94011d3 144 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 145 LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
sahilmgandhi 18:6a4db94011d3 146 }
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 if (ssel != NC) {
sahilmgandhi 18:6a4db94011d3 149 swm = &SWM_SPI_SSEL[obj->spi_n];
sahilmgandhi 18:6a4db94011d3 150 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 151 LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 // clear interrupts
sahilmgandhi 18:6a4db94011d3 155 obj->spi->INTENCLR = 0x3f;
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 // enable power and clocking
sahilmgandhi 18:6a4db94011d3 158 LPC_SYSCON->SYSAHBCLKCTRL1 |= (0x1 << (obj->spi_n + 9));
sahilmgandhi 18:6a4db94011d3 159 LPC_SYSCON->PRESETCTRL1 |= (0x1 << (obj->spi_n + 9));
sahilmgandhi 18:6a4db94011d3 160 LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (obj->spi_n + 9));
sahilmgandhi 18:6a4db94011d3 161 }
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 void spi_free(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 164 {
sahilmgandhi 18:6a4db94011d3 165 }
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 void spi_format(spi_t *obj, int bits, int mode, int slave)
sahilmgandhi 18:6a4db94011d3 168 {
sahilmgandhi 18:6a4db94011d3 169 spi_disable(obj);
sahilmgandhi 18:6a4db94011d3 170 MBED_ASSERT((bits >= 1 && bits <= 16) && (mode >= 0 && mode <= 3));
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 int polarity = (mode & 0x2) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 173 int phase = (mode & 0x1) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 // set it up
sahilmgandhi 18:6a4db94011d3 176 int LEN = bits - 1; // LEN - Data Length
sahilmgandhi 18:6a4db94011d3 177 int CPOL = (polarity) ? 1 : 0; // CPOL - Clock Polarity select
sahilmgandhi 18:6a4db94011d3 178 int CPHA = (phase) ? 1 : 0; // CPHA - Clock Phase select
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 uint32_t tmp = obj->spi->CFG;
sahilmgandhi 18:6a4db94011d3 181 tmp &= ~((1 << 5) | (1 << 4) | (1 << 2));
sahilmgandhi 18:6a4db94011d3 182 tmp |= (CPOL << 5) | (CPHA << 4) | ((slave ? 0 : 1) << 2);
sahilmgandhi 18:6a4db94011d3 183 obj->spi->CFG = tmp;
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 // select frame length
sahilmgandhi 18:6a4db94011d3 186 tmp = obj->spi->TXCTL;
sahilmgandhi 18:6a4db94011d3 187 tmp &= ~(0xf << 24);
sahilmgandhi 18:6a4db94011d3 188 tmp |= (LEN << 24);
sahilmgandhi 18:6a4db94011d3 189 obj->spi->TXCTL = tmp;
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 spi_enable(obj);
sahilmgandhi 18:6a4db94011d3 192 }
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 void spi_frequency(spi_t *obj, int hz)
sahilmgandhi 18:6a4db94011d3 195 {
sahilmgandhi 18:6a4db94011d3 196 spi_disable(obj);
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 // rise DIV value if it cannot be divided
sahilmgandhi 18:6a4db94011d3 199 obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1;
sahilmgandhi 18:6a4db94011d3 200 obj->spi->DLY = 0;
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 spi_enable(obj);
sahilmgandhi 18:6a4db94011d3 203 }
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 static inline void spi_disable(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 206 {
sahilmgandhi 18:6a4db94011d3 207 obj->spi->CFG &= ~(1 << 0);
sahilmgandhi 18:6a4db94011d3 208 }
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 static inline void spi_enable(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 211 {
sahilmgandhi 18:6a4db94011d3 212 obj->spi->CFG |= (1 << 0);
sahilmgandhi 18:6a4db94011d3 213 }
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 static inline int spi_readable(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 216 {
sahilmgandhi 18:6a4db94011d3 217 return obj->spi->STAT & (1 << 0);
sahilmgandhi 18:6a4db94011d3 218 }
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 static inline int spi_writeable(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 221 {
sahilmgandhi 18:6a4db94011d3 222 return obj->spi->STAT & (1 << 1);
sahilmgandhi 18:6a4db94011d3 223 }
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 static inline void spi_write(spi_t *obj, int value)
sahilmgandhi 18:6a4db94011d3 226 {
sahilmgandhi 18:6a4db94011d3 227 while (!spi_writeable(obj));
sahilmgandhi 18:6a4db94011d3 228 // end of transfer
sahilmgandhi 18:6a4db94011d3 229 obj->spi->TXCTL |= (1 << 20);
sahilmgandhi 18:6a4db94011d3 230 obj->spi->TXDAT = (value & 0xffff);
sahilmgandhi 18:6a4db94011d3 231 }
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 static inline int spi_read(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 234 {
sahilmgandhi 18:6a4db94011d3 235 while (!spi_readable(obj));
sahilmgandhi 18:6a4db94011d3 236 return obj->spi->RXDAT & 0xffff; // Only the lower 16 bits contain data
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 int spi_busy(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 240 {
sahilmgandhi 18:6a4db94011d3 241 // checking RXOV(Receiver Overrun interrupt flag)
sahilmgandhi 18:6a4db94011d3 242 return obj->spi->STAT & (1 << 2);
sahilmgandhi 18:6a4db94011d3 243 }
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 int spi_master_write(spi_t *obj, int value)
sahilmgandhi 18:6a4db94011d3 246 {
sahilmgandhi 18:6a4db94011d3 247 spi_write(obj, value);
sahilmgandhi 18:6a4db94011d3 248 return spi_read(obj);
sahilmgandhi 18:6a4db94011d3 249 }
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 int spi_slave_receive(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 252 {
sahilmgandhi 18:6a4db94011d3 253 return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 254 }
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 int spi_slave_read(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 return obj->spi->RXDAT & 0xffff; // Only the lower 16 bits contain data
sahilmgandhi 18:6a4db94011d3 259 }
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 void spi_slave_write(spi_t *obj, int value)
sahilmgandhi 18:6a4db94011d3 262 {
sahilmgandhi 18:6a4db94011d3 263 while (spi_writeable(obj) == 0) ;
sahilmgandhi 18:6a4db94011d3 264 obj->spi->TXDAT = value;
sahilmgandhi 18:6a4db94011d3 265 }