MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17
sahilmgandhi 18:6a4db94011d3 18 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 19 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 #define CHANNEL_NUM 8
sahilmgandhi 18:6a4db94011d3 23 #define LPC_GPIO_X LPC_PINT
sahilmgandhi 18:6a4db94011d3 24 #define PININT_IRQ PIN_INT0_IRQn
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 27 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 static inline void handle_interrupt_in(uint32_t channel) {
sahilmgandhi 18:6a4db94011d3 30 uint32_t ch_bit = (1 << channel);
sahilmgandhi 18:6a4db94011d3 31 // Return immediately if:
sahilmgandhi 18:6a4db94011d3 32 // * The interrupt was already served
sahilmgandhi 18:6a4db94011d3 33 // * There is no user handler
sahilmgandhi 18:6a4db94011d3 34 // * It is a level interrupt, not an edge interrupt
sahilmgandhi 18:6a4db94011d3 35 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
sahilmgandhi 18:6a4db94011d3 36 (channel_ids[channel] == 0 ) ||
sahilmgandhi 18:6a4db94011d3 37 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
sahilmgandhi 18:6a4db94011d3 40 irq_handler(channel_ids[channel], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 41 LPC_GPIO_X->RISE = ch_bit;
sahilmgandhi 18:6a4db94011d3 42 }
sahilmgandhi 18:6a4db94011d3 43 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
sahilmgandhi 18:6a4db94011d3 44 irq_handler(channel_ids[channel], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 45 LPC_GPIO_X->FALL = ch_bit;
sahilmgandhi 18:6a4db94011d3 46 }
sahilmgandhi 18:6a4db94011d3 47 LPC_GPIO_X->IST = ch_bit;
sahilmgandhi 18:6a4db94011d3 48 }
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 void gpio_irq0(void) {handle_interrupt_in(0);}
sahilmgandhi 18:6a4db94011d3 51 void gpio_irq1(void) {handle_interrupt_in(1);}
sahilmgandhi 18:6a4db94011d3 52 void gpio_irq2(void) {handle_interrupt_in(2);}
sahilmgandhi 18:6a4db94011d3 53 void gpio_irq3(void) {handle_interrupt_in(3);}
sahilmgandhi 18:6a4db94011d3 54 void gpio_irq4(void) {handle_interrupt_in(4);}
sahilmgandhi 18:6a4db94011d3 55 void gpio_irq5(void) {handle_interrupt_in(5);}
sahilmgandhi 18:6a4db94011d3 56 void gpio_irq6(void) {handle_interrupt_in(6);}
sahilmgandhi 18:6a4db94011d3 57 void gpio_irq7(void) {handle_interrupt_in(7);}
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 60 // PINT only supprt GPIO port 0 and 1 interrupt
sahilmgandhi 18:6a4db94011d3 61 if (pin >= P2_0) return -1;
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 int found_free_channel = 0;
sahilmgandhi 18:6a4db94011d3 66 int i = 0;
sahilmgandhi 18:6a4db94011d3 67 for (i=0; i<CHANNEL_NUM; i++) {
sahilmgandhi 18:6a4db94011d3 68 if (channel_ids[i] == 0) {
sahilmgandhi 18:6a4db94011d3 69 channel_ids[i] = id;
sahilmgandhi 18:6a4db94011d3 70 obj->ch = i;
sahilmgandhi 18:6a4db94011d3 71 found_free_channel = 1;
sahilmgandhi 18:6a4db94011d3 72 break;
sahilmgandhi 18:6a4db94011d3 73 }
sahilmgandhi 18:6a4db94011d3 74 }
sahilmgandhi 18:6a4db94011d3 75 if (!found_free_channel) return -1;
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 /* Enable AHB clock to the PIN, GPIO0/1, IOCON and MUX domain. */
sahilmgandhi 18:6a4db94011d3 78 LPC_SYSCON->SYSAHBCLKCTRL0 |= ((1 << 18) | (0x1D << 11));
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 LPC_INMUX->PINTSEL[obj->ch] = pin;
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 // Interrupt Wake-Up Enable
sahilmgandhi 18:6a4db94011d3 83 LPC_SYSCON->STARTERP0 |= (1 << (obj->ch + 5));
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 LPC_GPIO_PORT->DIR[pin >> 5] &= ~(1 << (pin & 0x1F));
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 void (*channels_irq)(void) = NULL;
sahilmgandhi 18:6a4db94011d3 88 switch (obj->ch) {
sahilmgandhi 18:6a4db94011d3 89 case 0: channels_irq = &gpio_irq0; break;
sahilmgandhi 18:6a4db94011d3 90 case 1: channels_irq = &gpio_irq1; break;
sahilmgandhi 18:6a4db94011d3 91 case 2: channels_irq = &gpio_irq2; break;
sahilmgandhi 18:6a4db94011d3 92 case 3: channels_irq = &gpio_irq3; break;
sahilmgandhi 18:6a4db94011d3 93 case 4: channels_irq = &gpio_irq4; break;
sahilmgandhi 18:6a4db94011d3 94 case 5: channels_irq = &gpio_irq5; break;
sahilmgandhi 18:6a4db94011d3 95 case 6: channels_irq = &gpio_irq6; break;
sahilmgandhi 18:6a4db94011d3 96 case 7: channels_irq = &gpio_irq7; break;
sahilmgandhi 18:6a4db94011d3 97 }
sahilmgandhi 18:6a4db94011d3 98 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
sahilmgandhi 18:6a4db94011d3 99 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 return 0;
sahilmgandhi 18:6a4db94011d3 102 }
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 void gpio_irq_free(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 105 channel_ids[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 106 LPC_SYSCON->STARTERP0 &= ~(1 << (obj->ch + 5));
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 110 unsigned int ch_bit = (1 << obj->ch);
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 // Clear interrupt
sahilmgandhi 18:6a4db94011d3 113 if (!(LPC_GPIO_X->ISEL & ch_bit))
sahilmgandhi 18:6a4db94011d3 114 LPC_GPIO_X->IST = ch_bit;
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 // Edge trigger
sahilmgandhi 18:6a4db94011d3 117 LPC_GPIO_X->ISEL &= ~ch_bit;
sahilmgandhi 18:6a4db94011d3 118 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 119 if (enable) {
sahilmgandhi 18:6a4db94011d3 120 LPC_GPIO_X->IENR |= ch_bit;
sahilmgandhi 18:6a4db94011d3 121 } else {
sahilmgandhi 18:6a4db94011d3 122 LPC_GPIO_X->IENR &= ~ch_bit;
sahilmgandhi 18:6a4db94011d3 123 }
sahilmgandhi 18:6a4db94011d3 124 } else {
sahilmgandhi 18:6a4db94011d3 125 if (enable) {
sahilmgandhi 18:6a4db94011d3 126 LPC_GPIO_X->IENF |= ch_bit;
sahilmgandhi 18:6a4db94011d3 127 } else {
sahilmgandhi 18:6a4db94011d3 128 LPC_GPIO_X->IENF &= ~ch_bit;
sahilmgandhi 18:6a4db94011d3 129 }
sahilmgandhi 18:6a4db94011d3 130 }
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 void gpio_irq_enable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 134 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
sahilmgandhi 18:6a4db94011d3 135 }
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 void gpio_irq_disable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 138 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
sahilmgandhi 18:6a4db94011d3 139 }