MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC15XX/device/system_LPC15xx.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file system_LPC15xx.c
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-M3 Device System Source File for
sahilmgandhi 18:6a4db94011d3 4 * NXP LPC15xx Device Series
sahilmgandhi 18:6a4db94011d3 5 * @version V1.00
sahilmgandhi 18:6a4db94011d3 6 * @date 19. July 2013
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * @par
sahilmgandhi 18:6a4db94011d3 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
sahilmgandhi 18:6a4db94011d3 13 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 14 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * @par
sahilmgandhi 18:6a4db94011d3 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 27 #include "LPC15xx.h"
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 /*
sahilmgandhi 18:6a4db94011d3 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
sahilmgandhi 18:6a4db94011d3 31 */
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 /*- SystemCoreClock Configuration -------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 34 // <e0> SystemCoreClock Configuration
sahilmgandhi 18:6a4db94011d3 35 #define CLOCK_SETUP 1
sahilmgandhi 18:6a4db94011d3 36 //
sahilmgandhi 18:6a4db94011d3 37 // <h> System Oscillator Control (SYSOSCCTRL)
sahilmgandhi 18:6a4db94011d3 38 // <o.0> BYPASS: System Oscillator Bypass Enable
sahilmgandhi 18:6a4db94011d3 39 // <i> If enabled then PLL input (sys_osc_clk) is fed
sahilmgandhi 18:6a4db94011d3 40 // <i> directly from XTALIN and XTALOUT pins.
sahilmgandhi 18:6a4db94011d3 41 // <o.1> FREQRANGE: System Oscillator Frequency Range
sahilmgandhi 18:6a4db94011d3 42 // <i> Determines frequency range for Low-power oscillator.
sahilmgandhi 18:6a4db94011d3 43 // <0=> 1 - 20 MHz
sahilmgandhi 18:6a4db94011d3 44 // <1=> 15 - 25 MHz
sahilmgandhi 18:6a4db94011d3 45 // </h>
sahilmgandhi 18:6a4db94011d3 46 #define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 47 //
sahilmgandhi 18:6a4db94011d3 48 // <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
sahilmgandhi 18:6a4db94011d3 49 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 50 // <1=> Crystal Oscillator (SYSOSC)
sahilmgandhi 18:6a4db94011d3 51 #define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 52 //
sahilmgandhi 18:6a4db94011d3 53 // <e> Clock Configuration (Manual)
sahilmgandhi 18:6a4db94011d3 54 #define CLOCK_SETUP_REG 1
sahilmgandhi 18:6a4db94011d3 55 //
sahilmgandhi 18:6a4db94011d3 56 // <o.0..1> Main Clock Source Select A (MAINCLKSELA)
sahilmgandhi 18:6a4db94011d3 57 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 58 // <1=> System Oscillator
sahilmgandhi 18:6a4db94011d3 59 // <2=> WD Oscillator
sahilmgandhi 18:6a4db94011d3 60 #define MAINCLKSELA_Val 0x00000001 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 61 //
sahilmgandhi 18:6a4db94011d3 62 // <o.0..1> Main Clock Source Select B (MAINCLKSELB)
sahilmgandhi 18:6a4db94011d3 63 // <0=> MAINCLKSELA
sahilmgandhi 18:6a4db94011d3 64 // <1=> System PLL Input
sahilmgandhi 18:6a4db94011d3 65 // <2=> System PLL Output
sahilmgandhi 18:6a4db94011d3 66 // <3=> RTC Oscillator
sahilmgandhi 18:6a4db94011d3 67 #define MAINCLKSELB_Val 0x00000002 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 68 //
sahilmgandhi 18:6a4db94011d3 69 // <h> System PLL Setting (SYSPLLCTRL)
sahilmgandhi 18:6a4db94011d3 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
sahilmgandhi 18:6a4db94011d3 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 73 // <o.0..5> MSEL: Feedback Divider Selection
sahilmgandhi 18:6a4db94011d3 74 // <i> M = MSEL + 1
sahilmgandhi 18:6a4db94011d3 75 // <0-31>
sahilmgandhi 18:6a4db94011d3 76 // <o.6..7> PSEL: Post Divider Selection
sahilmgandhi 18:6a4db94011d3 77 // <i> Post divider ratio P. Division ratio is 2 * P
sahilmgandhi 18:6a4db94011d3 78 // <0=> P = 1
sahilmgandhi 18:6a4db94011d3 79 // <1=> P = 2
sahilmgandhi 18:6a4db94011d3 80 // <2=> P = 4
sahilmgandhi 18:6a4db94011d3 81 // <3=> P = 8
sahilmgandhi 18:6a4db94011d3 82 // </h>
sahilmgandhi 18:6a4db94011d3 83 #define SYSPLLCTRL_Val 0x00000045 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 84 //
sahilmgandhi 18:6a4db94011d3 85 // <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
sahilmgandhi 18:6a4db94011d3 86 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
sahilmgandhi 18:6a4db94011d3 87 // <i> 0 = is disabled
sahilmgandhi 18:6a4db94011d3 88 // <0-255>
sahilmgandhi 18:6a4db94011d3 89 #define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
sahilmgandhi 18:6a4db94011d3 90 // </e>
sahilmgandhi 18:6a4db94011d3 91 //
sahilmgandhi 18:6a4db94011d3 92 // <e> Clock Configuration (via ROM PLL API)
sahilmgandhi 18:6a4db94011d3 93 #define CLOCK_SETUP_API 0
sahilmgandhi 18:6a4db94011d3 94 //
sahilmgandhi 18:6a4db94011d3 95 // <o> PLL API Mode Select
sahilmgandhi 18:6a4db94011d3 96 // <0=> Exact
sahilmgandhi 18:6a4db94011d3 97 // <1=> Less than or equal
sahilmgandhi 18:6a4db94011d3 98 // <2=> Greater than or equal
sahilmgandhi 18:6a4db94011d3 99 // <3=> As close as possible
sahilmgandhi 18:6a4db94011d3 100 #define PLL_API_MODE_Val 0
sahilmgandhi 18:6a4db94011d3 101 //
sahilmgandhi 18:6a4db94011d3 102 // <o> CPU Frequency [Hz] <1000000-72000000:1000>
sahilmgandhi 18:6a4db94011d3 103 #define PLL_API_FREQ_Val 72000000
sahilmgandhi 18:6a4db94011d3 104 // </e>
sahilmgandhi 18:6a4db94011d3 105 //
sahilmgandhi 18:6a4db94011d3 106 // <e> USB Clock Configuration
sahilmgandhi 18:6a4db94011d3 107 #define USB_CLOCK_SETUP 0
sahilmgandhi 18:6a4db94011d3 108 // <h> USB PLL Control (USBPLLCTRL)
sahilmgandhi 18:6a4db94011d3 109 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
sahilmgandhi 18:6a4db94011d3 110 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 111 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 112 // <o.0..5> MSEL: Feedback Divider Selection
sahilmgandhi 18:6a4db94011d3 113 // <i> M = MSEL + 1
sahilmgandhi 18:6a4db94011d3 114 // <0-31>
sahilmgandhi 18:6a4db94011d3 115 // <o.7..6> PSEL: Post Divider Selection
sahilmgandhi 18:6a4db94011d3 116 // <i> Post divider ratio P. Division ratio is 2 * P
sahilmgandhi 18:6a4db94011d3 117 // <0=> P = 1
sahilmgandhi 18:6a4db94011d3 118 // <1=> P = 2
sahilmgandhi 18:6a4db94011d3 119 // <2=> P = 4
sahilmgandhi 18:6a4db94011d3 120 // <3=> P = 8
sahilmgandhi 18:6a4db94011d3 121 // </h>
sahilmgandhi 18:6a4db94011d3 122 #define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 123 //
sahilmgandhi 18:6a4db94011d3 124 // <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
sahilmgandhi 18:6a4db94011d3 125 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 126 // <1=> System Oscillator
sahilmgandhi 18:6a4db94011d3 127 #define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 128 //
sahilmgandhi 18:6a4db94011d3 129 // <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
sahilmgandhi 18:6a4db94011d3 130 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 131 // <1=> System Oscillator
sahilmgandhi 18:6a4db94011d3 132 // <2=> USB PLL out
sahilmgandhi 18:6a4db94011d3 133 // <3=> Main clock
sahilmgandhi 18:6a4db94011d3 134 #define USBCLKSEL_Val 0x00000002 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 135 //
sahilmgandhi 18:6a4db94011d3 136 // <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
sahilmgandhi 18:6a4db94011d3 137 // <i> Divides USB clock to 48 MHz.
sahilmgandhi 18:6a4db94011d3 138 // <i> 0 = is disabled
sahilmgandhi 18:6a4db94011d3 139 // <0-255>
sahilmgandhi 18:6a4db94011d3 140 #define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
sahilmgandhi 18:6a4db94011d3 141 // </e>
sahilmgandhi 18:6a4db94011d3 142 //
sahilmgandhi 18:6a4db94011d3 143 // <e> SCT Clock Configuration
sahilmgandhi 18:6a4db94011d3 144 #define SCT_CLOCK_SETUP 1
sahilmgandhi 18:6a4db94011d3 145 // <h> SCT PLL Control (SCTPLLCTRL)
sahilmgandhi 18:6a4db94011d3 146 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
sahilmgandhi 18:6a4db94011d3 147 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 148 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 149 // <o.0..5> MSEL: Feedback Divider Selection
sahilmgandhi 18:6a4db94011d3 150 // <i> M = MSEL + 1
sahilmgandhi 18:6a4db94011d3 151 // <0-31>
sahilmgandhi 18:6a4db94011d3 152 // <o.7..6> PSEL: Post Divider Selection
sahilmgandhi 18:6a4db94011d3 153 // <i> Post divider ratio P. Division ratio is 2 * P
sahilmgandhi 18:6a4db94011d3 154 // <0=> P = 1
sahilmgandhi 18:6a4db94011d3 155 // <1=> P = 2
sahilmgandhi 18:6a4db94011d3 156 // <2=> P = 4
sahilmgandhi 18:6a4db94011d3 157 // <3=> P = 8
sahilmgandhi 18:6a4db94011d3 158 // </h>
sahilmgandhi 18:6a4db94011d3 159 #define SCTPLLCTRL_Val 0x00000045 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 160 //
sahilmgandhi 18:6a4db94011d3 161 // <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL)
sahilmgandhi 18:6a4db94011d3 162 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 163 // <1=> System Oscillator
sahilmgandhi 18:6a4db94011d3 164 #define SCTPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 165 // </e>
sahilmgandhi 18:6a4db94011d3 166 //
sahilmgandhi 18:6a4db94011d3 167 // </e>
sahilmgandhi 18:6a4db94011d3 168 //
sahilmgandhi 18:6a4db94011d3 169 // <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
sahilmgandhi 18:6a4db94011d3 170 // <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 171 //
sahilmgandhi 18:6a4db94011d3 172 #define XTAL_CLK_Val 12000000
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 /*
sahilmgandhi 18:6a4db94011d3 175 //-------- <<< end of configuration section >>> ------------------------------
sahilmgandhi 18:6a4db94011d3 176 */
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 179 Define clocks
sahilmgandhi 18:6a4db94011d3 180 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 181 #define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
sahilmgandhi 18:6a4db94011d3 182 #define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
sahilmgandhi 18:6a4db94011d3 183 #define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
sahilmgandhi 18:6a4db94011d3 184 #define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
sahilmgandhi 18:6a4db94011d3 185 #define __WDT_OSC_CLK ( 503000UL) /* WDT oscillator freq */
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 188 Check the register settings
sahilmgandhi 18:6a4db94011d3 189 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 190 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
sahilmgandhi 18:6a4db94011d3 191 #define CHECK_RSVD(val, mask) (val & mask)
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 #if (CHECK_RANGE((SYSOSCCTRL_Val), 0, 1))
sahilmgandhi 18:6a4db94011d3 194 #error "SYSOSCCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 195 #endif
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
sahilmgandhi 18:6a4db94011d3 198 #error "SYSPLLCLKSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 199 #endif
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000000FF))
sahilmgandhi 18:6a4db94011d3 202 #error "SYSPLLCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 203 #endif
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 #if (CHECK_RANGE((MAINCLKSELA_Val), 0, 2))
sahilmgandhi 18:6a4db94011d3 206 #error "MAINCLKSELA: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 207 #endif
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 #if (CHECK_RSVD((MAINCLKSELB_Val), ~0x00000003))
sahilmgandhi 18:6a4db94011d3 210 #error "MAINCLKSELB: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 211 #endif
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
sahilmgandhi 18:6a4db94011d3 214 #error "SYSAHBCLKDIV: Value out of range!"
sahilmgandhi 18:6a4db94011d3 215 #endif
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 #if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
sahilmgandhi 18:6a4db94011d3 218 #error "You must select either manual or API based Clock Configuration!"
sahilmgandhi 18:6a4db94011d3 219 #endif
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
sahilmgandhi 18:6a4db94011d3 222 #error "USBPLLCLKSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 223 #endif
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x00000FF))
sahilmgandhi 18:6a4db94011d3 226 #error "USBPLLCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 227 #endif
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 #if (CHECK_RANGE((USBCLKSEL_Val), 0, 3))
sahilmgandhi 18:6a4db94011d3 230 #error "USBCLKSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 231 #endif
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
sahilmgandhi 18:6a4db94011d3 234 #error "USBCLKDIV: Value out of range!"
sahilmgandhi 18:6a4db94011d3 235 #endif
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 #if (CHECK_RANGE((SCTPLLCLKSEL_Val), 0, 1))
sahilmgandhi 18:6a4db94011d3 238 #error "SCTPLLCLKSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 239 #endif
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 #if (CHECK_RSVD((SCTPLLCTRL_Val), ~0x00000FF))
sahilmgandhi 18:6a4db94011d3 242 #error "SCTPLLCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 243 #endif
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 #if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
sahilmgandhi 18:6a4db94011d3 246 #error "XTAL frequency is out of bounds"
sahilmgandhi 18:6a4db94011d3 247 #endif
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 #if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
sahilmgandhi 18:6a4db94011d3 250 #error "PLL API Mode Select not valid"
sahilmgandhi 18:6a4db94011d3 251 #endif
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 #if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 72000000))
sahilmgandhi 18:6a4db94011d3 254 #error "CPU Frequency (API mode) not valid"
sahilmgandhi 18:6a4db94011d3 255 #endif
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 260 Calculate system core clock
sahilmgandhi 18:6a4db94011d3 261 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 262 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 /* sys_pllclkin calculation */
sahilmgandhi 18:6a4db94011d3 265 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
sahilmgandhi 18:6a4db94011d3 266 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 267 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 268 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 269 #else
sahilmgandhi 18:6a4db94011d3 270 #error "Oops"
sahilmgandhi 18:6a4db94011d3 271 #endif
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 #if ((MAINCLKSELA_Val & 0x03) == 0)
sahilmgandhi 18:6a4db94011d3 276 #define __MAINA_CLOCK (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 277 #elif ((MAINCLKSELA_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 278 #define __MAINA_CLOCK (__SYS_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 279 #elif ((MAINCLKSELA_Val & 0x03) == 2)
sahilmgandhi 18:6a4db94011d3 280 #define __MAINA_CLOCK (__WDT_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 281 #else
sahilmgandhi 18:6a4db94011d3 282 #error "Oops"
sahilmgandhi 18:6a4db94011d3 283 #endif
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 /* main clock calculation */
sahilmgandhi 18:6a4db94011d3 288 #if ((MAINCLKSELB_Val & 0x03) == 0)
sahilmgandhi 18:6a4db94011d3 289 #define __MAINB_CLOCK (__MAINA_CLOCK)
sahilmgandhi 18:6a4db94011d3 290 #elif ((MAINCLKSELB_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 291 #define __MAINB_CLOCK (__SYS_PLLCLKIN)
sahilmgandhi 18:6a4db94011d3 292 #elif ((MAINCLKSELB_Val & 0x03) == 2)
sahilmgandhi 18:6a4db94011d3 293 #define __MAINB_CLOCK (__SYS_PLLCLKOUT)
sahilmgandhi 18:6a4db94011d3 294 #elif ((MAINCLKSELB_Val & 0x03) == 3)
sahilmgandhi 18:6a4db94011d3 295 #define __MAINB_CLOCK (__RTC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 296 #else
sahilmgandhi 18:6a4db94011d3 297 #error "Oops"
sahilmgandhi 18:6a4db94011d3 298 #endif
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 #define __SYSTEM_CLOCK (__MAINB_CLOCK / SYSAHBCLKDIV_Val)
sahilmgandhi 18:6a4db94011d3 301 #endif /* Clock Setup via Register */
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
sahilmgandhi 18:6a4db94011d3 304 #define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
sahilmgandhi 18:6a4db94011d3 305 #endif /* Clock Setup via PLL API */
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 #else
sahilmgandhi 18:6a4db94011d3 308 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 309 #endif /* CLOCK_SETUP */
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 #if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
sahilmgandhi 18:6a4db94011d3 314 #include "power_api.h"
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 typedef struct _ROM {
sahilmgandhi 18:6a4db94011d3 317 const unsigned p_dev0;
sahilmgandhi 18:6a4db94011d3 318 const unsigned p_dev1;
sahilmgandhi 18:6a4db94011d3 319 const unsigned p_dev2;
sahilmgandhi 18:6a4db94011d3 320 const PWRD * pPWRD; /* ROM Power Management API */
sahilmgandhi 18:6a4db94011d3 321 const unsigned p_dev4;
sahilmgandhi 18:6a4db94011d3 322 const unsigned p_dev5;
sahilmgandhi 18:6a4db94011d3 323 const unsigned p_dev6;
sahilmgandhi 18:6a4db94011d3 324 const unsigned p_dev7;
sahilmgandhi 18:6a4db94011d3 325 } ROM;
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 328 PLL API Function
sahilmgandhi 18:6a4db94011d3 329 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 330 static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
sahilmgandhi 18:6a4db94011d3 331 {
sahilmgandhi 18:6a4db94011d3 332 uint32_t cmd[5], res[5];
sahilmgandhi 18:6a4db94011d3 333 ROM ** rom = (ROM **) 0x03000200; /* pointer to power API calls */
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 cmd[0] = pllInFreq; /* PLL's input freq in KHz */
sahilmgandhi 18:6a4db94011d3 336 cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
sahilmgandhi 18:6a4db94011d3 337 cmd[2] = pllMode;
sahilmgandhi 18:6a4db94011d3 338 cmd[3] = 0; /* no timeout for PLL to lock */
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 /* Execute API call */
sahilmgandhi 18:6a4db94011d3 341 (*rom)->pPWRD->set_pll(cmd, res); /* call API function */
sahilmgandhi 18:6a4db94011d3 342 if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
sahilmgandhi 18:6a4db94011d3 343 while(1); /* ... stay here */
sahilmgandhi 18:6a4db94011d3 344 }
sahilmgandhi 18:6a4db94011d3 345 }
sahilmgandhi 18:6a4db94011d3 346 #endif
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 352 Clock Variable definitions
sahilmgandhi 18:6a4db94011d3 353 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 354 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 358 Clock functions
sahilmgandhi 18:6a4db94011d3 359 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 360 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
sahilmgandhi 18:6a4db94011d3 361 {
sahilmgandhi 18:6a4db94011d3 362 /* Determine clock frequency according to clock register values */
sahilmgandhi 18:6a4db94011d3 363 switch (LPC_SYSCON->MAINCLKSELB & 0x03) {
sahilmgandhi 18:6a4db94011d3 364 case 0: /* MAINCLKSELA clock sel */
sahilmgandhi 18:6a4db94011d3 365 switch (LPC_SYSCON->MAINCLKSELA & 0x03) {
sahilmgandhi 18:6a4db94011d3 366 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 367 SystemCoreClock = __IRC_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 368 break;
sahilmgandhi 18:6a4db94011d3 369 case 1: /* System oscillator */
sahilmgandhi 18:6a4db94011d3 370 SystemCoreClock = __SYS_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 371 break;
sahilmgandhi 18:6a4db94011d3 372 case 2: /* Watchdog oscillator */
sahilmgandhi 18:6a4db94011d3 373 SystemCoreClock = __WDT_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 374 break;
sahilmgandhi 18:6a4db94011d3 375 case 3: /* Reserved */
sahilmgandhi 18:6a4db94011d3 376 SystemCoreClock = 0;
sahilmgandhi 18:6a4db94011d3 377 break;
sahilmgandhi 18:6a4db94011d3 378 }
sahilmgandhi 18:6a4db94011d3 379 break;
sahilmgandhi 18:6a4db94011d3 380 case 1: /* Input Clock to System PLL */
sahilmgandhi 18:6a4db94011d3 381 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 382 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 383 SystemCoreClock = __IRC_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 384 break;
sahilmgandhi 18:6a4db94011d3 385 case 1: /* System oscillator */
sahilmgandhi 18:6a4db94011d3 386 SystemCoreClock = __SYS_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 387 break;
sahilmgandhi 18:6a4db94011d3 388 case 2: /* Reserved */
sahilmgandhi 18:6a4db94011d3 389 case 3: /* Reserved */
sahilmgandhi 18:6a4db94011d3 390 SystemCoreClock = 0;
sahilmgandhi 18:6a4db94011d3 391 break;
sahilmgandhi 18:6a4db94011d3 392 }
sahilmgandhi 18:6a4db94011d3 393 break;
sahilmgandhi 18:6a4db94011d3 394 case 2: /* System PLL Clock Out */
sahilmgandhi 18:6a4db94011d3 395 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 396 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 397 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
sahilmgandhi 18:6a4db94011d3 398 break;
sahilmgandhi 18:6a4db94011d3 399 case 1: /* System oscillator */
sahilmgandhi 18:6a4db94011d3 400 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
sahilmgandhi 18:6a4db94011d3 401 break;
sahilmgandhi 18:6a4db94011d3 402 case 2: /* Reserved */
sahilmgandhi 18:6a4db94011d3 403 case 3: /* Reserved */
sahilmgandhi 18:6a4db94011d3 404 SystemCoreClock = 0;
sahilmgandhi 18:6a4db94011d3 405 break;
sahilmgandhi 18:6a4db94011d3 406 }
sahilmgandhi 18:6a4db94011d3 407 break;
sahilmgandhi 18:6a4db94011d3 408 case 3: /* WDT Oscillator */
sahilmgandhi 18:6a4db94011d3 409 SystemCoreClock = __WDT_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 410 break;
sahilmgandhi 18:6a4db94011d3 411 }
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 }
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417 /**
sahilmgandhi 18:6a4db94011d3 418 * Initialize the system
sahilmgandhi 18:6a4db94011d3 419 *
sahilmgandhi 18:6a4db94011d3 420 * @param none
sahilmgandhi 18:6a4db94011d3 421 * @return none
sahilmgandhi 18:6a4db94011d3 422 *
sahilmgandhi 18:6a4db94011d3 423 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 424 */
sahilmgandhi 18:6a4db94011d3 425 void SystemInit (void) {
sahilmgandhi 18:6a4db94011d3 426 #if (CLOCK_SETUP)
sahilmgandhi 18:6a4db94011d3 427 volatile uint32_t i;
sahilmgandhi 18:6a4db94011d3 428 #endif
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 433 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
sahilmgandhi 18:6a4db94011d3 434 LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
sahilmgandhi 18:6a4db94011d3 435 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
sahilmgandhi 18:6a4db94011d3 436 #endif
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 #if (((MAINCLKSELA_Val & 0x03) == 1) )
sahilmgandhi 18:6a4db94011d3 443 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
sahilmgandhi 18:6a4db94011d3 444 LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
sahilmgandhi 18:6a4db94011d3 445 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
sahilmgandhi 18:6a4db94011d3 446 #endif
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 #if (((MAINCLKSELA_Val & 0x03) == 2) )
sahilmgandhi 18:6a4db94011d3 449 LPC_SYSCON->PDRUNCFG &= ~(1 << 20); /* Power-up WDT Clock */
sahilmgandhi 18:6a4db94011d3 450 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
sahilmgandhi 18:6a4db94011d3 451 #endif
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 #if ((MAINCLKSELB_Val & 0x03) == 3)
sahilmgandhi 18:6a4db94011d3 454 LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
sahilmgandhi 18:6a4db94011d3 455 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
sahilmgandhi 18:6a4db94011d3 456 #endif
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 LPC_SYSCON->MAINCLKSELA = MAINCLKSELA_Val; /* select MAINCLKA clock */
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 #if ((MAINCLKSELB_Val & 0x03) == 2) /* Main Clock is PLL Out */
sahilmgandhi 18:6a4db94011d3 461 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
sahilmgandhi 18:6a4db94011d3 462 LPC_SYSCON->PDRUNCFG &= ~(1 << 22); /* Power-up SYSPLL */
sahilmgandhi 18:6a4db94011d3 463 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
sahilmgandhi 18:6a4db94011d3 464 #endif
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 LPC_SYSCON->MAINCLKSELB = MAINCLKSELB_Val; /* select Main clock */
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
sahilmgandhi 18:6a4db94011d3 469 #endif /* Clock Setup via Register */
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 #if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
sahilmgandhi 18:6a4db94011d3 472 // LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 LPC_SYSCON->MAINCLKSELB = (1 << 2); /* Select System PLL output */
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 LPC_SYSCON->SYSAHBCLKDIV = 1;
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
sahilmgandhi 18:6a4db94011d3 479 #endif /* Clock Setup via PLL API */
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 #if (USB_CLOCK_SETUP == 1) /* USB clock is used */
sahilmgandhi 18:6a4db94011d3 482 LPC_SYSCON->PDRUNCFG &= ~(1 << 9); /* Power-up USB PHY */
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 #if ((USBCLKSEL_Val & 0x003) == 2) /* USB clock is USB PLL out */
sahilmgandhi 18:6a4db94011d3 485 LPC_SYSCON->PDRUNCFG &= ~(1 << 23); /* Power-up USB PLL */
sahilmgandhi 18:6a4db94011d3 486 LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
sahilmgandhi 18:6a4db94011d3 489 while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 LPC_SYSCON->USBCLKSEL = 0x02; /* Select USB PLL */
sahilmgandhi 18:6a4db94011d3 492 #endif
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
sahilmgandhi 18:6a4db94011d3 495 LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 #else /* USB clock is not used */
sahilmgandhi 18:6a4db94011d3 498 LPC_SYSCON->PDRUNCFG |= (1 << 9); /* Power-down USB PHY */
sahilmgandhi 18:6a4db94011d3 499 LPC_SYSCON->PDRUNCFG |= (1 << 23); /* Power-down USB PLL */
sahilmgandhi 18:6a4db94011d3 500 #endif
sahilmgandhi 18:6a4db94011d3 501
sahilmgandhi 18:6a4db94011d3 502 #if (SCT_CLOCK_SETUP == 1) /* SCT clock is used */
sahilmgandhi 18:6a4db94011d3 503 LPC_SYSCON->PDRUNCFG &= ~(1 << 24); /* Power-up SCT PLL */
sahilmgandhi 18:6a4db94011d3 504 LPC_SYSCON->SCTPLLCLKSEL = SCTPLLCLKSEL_Val; /* Select PLL Input */
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 LPC_SYSCON->SCTPLLCTRL = SCTPLLCTRL_Val;
sahilmgandhi 18:6a4db94011d3 507 while (!(LPC_SYSCON->SCTPLLSTAT & 0x01)); /* Wait Until PLL Locked */
sahilmgandhi 18:6a4db94011d3 508 #else /* SCT clock is not used */
sahilmgandhi 18:6a4db94011d3 509 LPC_SYSCON->PDRUNCFG |= (1 << 24); /* Power-down SCT PLL */
sahilmgandhi 18:6a4db94011d3 510 #endif
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 #endif /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << 12); /* enable clock for SWM */
sahilmgandhi 18:6a4db94011d3 516
sahilmgandhi 18:6a4db94011d3 517 }