MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC15XX/device/LPC15xx.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1
sahilmgandhi 18:6a4db94011d3 2 /****************************************************************************************************//**
sahilmgandhi 18:6a4db94011d3 3 * @file LPC15xx.h
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
sahilmgandhi 18:6a4db94011d3 6 * LPC15xx from .
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @version V0.3
sahilmgandhi 18:6a4db94011d3 9 * @date 17. July 2013
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * @note Generated with SVDConv V2.80
sahilmgandhi 18:6a4db94011d3 12 * from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * modified by Keil
sahilmgandhi 18:6a4db94011d3 15 * modified by ytsuboi
sahilmgandhi 18:6a4db94011d3 16 *******************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 17
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup (null)
sahilmgandhi 18:6a4db94011d3 21 * @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 /** @addtogroup LPC15xx
sahilmgandhi 18:6a4db94011d3 25 * @{
sahilmgandhi 18:6a4db94011d3 26 */
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 #ifndef LPC15XX_H
sahilmgandhi 18:6a4db94011d3 29 #define LPC15XX_H
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 32 extern "C" {
sahilmgandhi 18:6a4db94011d3 33 #endif
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 /* ------------------------- Interrupt Number Definition ------------------------ */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 typedef enum {
sahilmgandhi 18:6a4db94011d3 39 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
sahilmgandhi 18:6a4db94011d3 40 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
sahilmgandhi 18:6a4db94011d3 41 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
sahilmgandhi 18:6a4db94011d3 42 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
sahilmgandhi 18:6a4db94011d3 43 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
sahilmgandhi 18:6a4db94011d3 44 and No Match */
sahilmgandhi 18:6a4db94011d3 45 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
sahilmgandhi 18:6a4db94011d3 46 related Fault */
sahilmgandhi 18:6a4db94011d3 47 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
sahilmgandhi 18:6a4db94011d3 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
sahilmgandhi 18:6a4db94011d3 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
sahilmgandhi 18:6a4db94011d3 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
sahilmgandhi 18:6a4db94011d3 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
sahilmgandhi 18:6a4db94011d3 52 /* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
sahilmgandhi 18:6a4db94011d3 53 WDT_IRQn = 0, /*!< 0 WDT */
sahilmgandhi 18:6a4db94011d3 54 BOD_IRQn = 1, /*!< 1 BOD */
sahilmgandhi 18:6a4db94011d3 55 FLASH_IRQn = 2, /*!< 2 FLASH */
sahilmgandhi 18:6a4db94011d3 56 EE_IRQn = 3, /*!< 3 EE */
sahilmgandhi 18:6a4db94011d3 57 DMA_IRQn = 4, /*!< 4 DMA */
sahilmgandhi 18:6a4db94011d3 58 GINT0_IRQn = 5, /*!< 5 GINT0 */
sahilmgandhi 18:6a4db94011d3 59 GINT1_IRQn = 6, /*!< 6 GINT1 */
sahilmgandhi 18:6a4db94011d3 60 PIN_INT0_IRQn = 7, /*!< 7 PIN_INT0 */
sahilmgandhi 18:6a4db94011d3 61 PIN_INT1_IRQn = 8, /*!< 8 PIN_INT1 */
sahilmgandhi 18:6a4db94011d3 62 PIN_INT2_IRQn = 9, /*!< 9 PIN_INT2 */
sahilmgandhi 18:6a4db94011d3 63 PIN_INT3_IRQn = 10, /*!< 10 PIN_INT3 */
sahilmgandhi 18:6a4db94011d3 64 PIN_INT4_IRQn = 11, /*!< 11 PIN_INT4 */
sahilmgandhi 18:6a4db94011d3 65 PIN_INT5_IRQn = 12, /*!< 12 PIN_INT5 */
sahilmgandhi 18:6a4db94011d3 66 PIN_INT6_IRQn = 13, /*!< 13 PIN_INT6 */
sahilmgandhi 18:6a4db94011d3 67 PIN_INT7_IRQn = 14, /*!< 14 PIN_INT7 */
sahilmgandhi 18:6a4db94011d3 68 RIT_IRQn = 15, /*!< 15 RIT */
sahilmgandhi 18:6a4db94011d3 69 SCT0_IRQn = 16, /*!< 16 SCT0 */
sahilmgandhi 18:6a4db94011d3 70 SCT1_IRQn = 17, /*!< 17 SCT1 */
sahilmgandhi 18:6a4db94011d3 71 SCT2_IRQn = 18, /*!< 18 SCT2 */
sahilmgandhi 18:6a4db94011d3 72 SCT3_IRQn = 19, /*!< 19 SCT3 */
sahilmgandhi 18:6a4db94011d3 73 MRT_IRQn = 20, /*!< 20 MRT */
sahilmgandhi 18:6a4db94011d3 74 UART0_IRQn = 21, /*!< 21 UART0 */
sahilmgandhi 18:6a4db94011d3 75 UART1_IRQn = 22, /*!< 22 UART1 */
sahilmgandhi 18:6a4db94011d3 76 UART2_IRQn = 23, /*!< 23 UART2 */
sahilmgandhi 18:6a4db94011d3 77 I2C0_IRQn = 24, /*!< 24 I2C0 */
sahilmgandhi 18:6a4db94011d3 78 SPI0_IRQn = 25, /*!< 25 SPI0 */
sahilmgandhi 18:6a4db94011d3 79 SPI1_IRQn = 26, /*!< 26 SPI1 */
sahilmgandhi 18:6a4db94011d3 80 C_CAN0_IRQn = 27, /*!< 27 C_CAN0 */
sahilmgandhi 18:6a4db94011d3 81 USB_IRQ_IRQn = 28, /*!< 28 USB_IRQ */
sahilmgandhi 18:6a4db94011d3 82 USB_FIQ_IRQn = 29, /*!< 29 USB_FIQ */
sahilmgandhi 18:6a4db94011d3 83 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
sahilmgandhi 18:6a4db94011d3 84 ADC0_SEQA_IRQn = 31, /*!< 31 ADC0_SEQA */
sahilmgandhi 18:6a4db94011d3 85 ADC0_SEQB_IRQn = 32, /*!< 32 ADC0_SEQB */
sahilmgandhi 18:6a4db94011d3 86 ADC0_THCMP_IRQn = 33, /*!< 33 ADC0_THCMP */
sahilmgandhi 18:6a4db94011d3 87 ADC0_OVR_IRQn = 34, /*!< 34 ADC0_OVR */
sahilmgandhi 18:6a4db94011d3 88 ADC1_SEQA_IRQn = 35, /*!< 35 ADC1_SEQA */
sahilmgandhi 18:6a4db94011d3 89 ADC1_SEQB_IRQn = 36, /*!< 36 ADC1_SEQB */
sahilmgandhi 18:6a4db94011d3 90 ADC1_THCMP_IRQn = 37, /*!< 37 ADC1_THCMP */
sahilmgandhi 18:6a4db94011d3 91 ADC1_OVR_IRQn = 38, /*!< 38 ADC1_OVR */
sahilmgandhi 18:6a4db94011d3 92 DAC_IRQn = 39, /*!< 39 DAC */
sahilmgandhi 18:6a4db94011d3 93 CMP0_IRQn = 40, /*!< 40 CMP0 */
sahilmgandhi 18:6a4db94011d3 94 CMP1_IRQn = 41, /*!< 41 CMP1 */
sahilmgandhi 18:6a4db94011d3 95 CMP2_IRQn = 42, /*!< 42 CMP2 */
sahilmgandhi 18:6a4db94011d3 96 CMP3_IRQn = 43, /*!< 43 CMP3 */
sahilmgandhi 18:6a4db94011d3 97 QEI_IRQn = 44, /*!< 44 QEI */
sahilmgandhi 18:6a4db94011d3 98 RTC_ALARM_IRQn = 45, /*!< 45 RTC_ALARM */
sahilmgandhi 18:6a4db94011d3 99 RTC_WAKE_IRQn = 46 /*!< 46 RTC_WAKE */
sahilmgandhi 18:6a4db94011d3 100 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 /** @addtogroup Configuration_of_CMSIS
sahilmgandhi 18:6a4db94011d3 104 * @{
sahilmgandhi 18:6a4db94011d3 105 */
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 109 /* ================ Processor and Core Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 110 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 /* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
sahilmgandhi 18:6a4db94011d3 113 #define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */
sahilmgandhi 18:6a4db94011d3 114 #define __MPU_PRESENT 0 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 115 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 117 /** @} */ /* End of group Configuration_of_CMSIS */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 #include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 120 #include "system_LPC15xx.h" /*!< LPC15xx System */
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 124 /* ================ Device Specific Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 125 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /** @addtogroup Device_Peripheral_Registers
sahilmgandhi 18:6a4db94011d3 129 * @{
sahilmgandhi 18:6a4db94011d3 130 */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 /* ------------------- Start of section using anonymous unions ------------------ */
sahilmgandhi 18:6a4db94011d3 134 #if defined(__CC_ARM)
sahilmgandhi 18:6a4db94011d3 135 #pragma push
sahilmgandhi 18:6a4db94011d3 136 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 137 #elif defined(__ICCARM__)
sahilmgandhi 18:6a4db94011d3 138 #pragma language=extended
sahilmgandhi 18:6a4db94011d3 139 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 140 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 141 #elif defined(__TMS470__)
sahilmgandhi 18:6a4db94011d3 142 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 143 #elif defined(__TASKING__)
sahilmgandhi 18:6a4db94011d3 144 #pragma warning 586
sahilmgandhi 18:6a4db94011d3 145 #else
sahilmgandhi 18:6a4db94011d3 146 #warning Not supported compiler type
sahilmgandhi 18:6a4db94011d3 147 #endif
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 152 /* ================ GPIO_PORT ================ */
sahilmgandhi 18:6a4db94011d3 153 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /**
sahilmgandhi 18:6a4db94011d3 157 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
sahilmgandhi 18:6a4db94011d3 158 */
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 typedef struct { /*!< GPIO_PORT Structure */
sahilmgandhi 18:6a4db94011d3 161 __IO uint8_t B[76]; /*!< Byte pin registers */
sahilmgandhi 18:6a4db94011d3 162 __I uint32_t RESERVED0[1005];
sahilmgandhi 18:6a4db94011d3 163 __IO uint32_t W[76]; /*!< Word pin registers */
sahilmgandhi 18:6a4db94011d3 164 __I uint32_t RESERVED1[948];
sahilmgandhi 18:6a4db94011d3 165 __IO uint32_t DIR[3]; /*!< Port Direction registers */
sahilmgandhi 18:6a4db94011d3 166 __I uint32_t RESERVED2[29];
sahilmgandhi 18:6a4db94011d3 167 __IO uint32_t MASK[3]; /*!< Port Mask register */
sahilmgandhi 18:6a4db94011d3 168 __I uint32_t RESERVED3[29];
sahilmgandhi 18:6a4db94011d3 169 __IO uint32_t PIN[3]; /*!< Port pin register */
sahilmgandhi 18:6a4db94011d3 170 __I uint32_t RESERVED4[29];
sahilmgandhi 18:6a4db94011d3 171 __IO uint32_t MPIN[3]; /*!< Masked port register */
sahilmgandhi 18:6a4db94011d3 172 __I uint32_t RESERVED5[29];
sahilmgandhi 18:6a4db94011d3 173 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
sahilmgandhi 18:6a4db94011d3 174 __I uint32_t RESERVED6[29];
sahilmgandhi 18:6a4db94011d3 175 __O uint32_t CLR[3]; /*!< Clear port */
sahilmgandhi 18:6a4db94011d3 176 __I uint32_t RESERVED7[29];
sahilmgandhi 18:6a4db94011d3 177 __O uint32_t NOT[3]; /*!< Toggle port */
sahilmgandhi 18:6a4db94011d3 178 } LPC_GPIO_PORT_Type;
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 182 /* ================ DMA ================ */
sahilmgandhi 18:6a4db94011d3 183 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 /**
sahilmgandhi 18:6a4db94011d3 187 * @brief DMA controller (DMA)
sahilmgandhi 18:6a4db94011d3 188 */
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 typedef struct { /*!< DMA Structure */
sahilmgandhi 18:6a4db94011d3 191 __IO uint32_t CTRL; /*!< DMA control. */
sahilmgandhi 18:6a4db94011d3 192 __I uint32_t INTSTAT; /*!< Interrupt status. */
sahilmgandhi 18:6a4db94011d3 193 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
sahilmgandhi 18:6a4db94011d3 194 __I uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 195 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 196 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 197 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 198 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 199 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 200 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 201 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 202 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 203 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 204 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 205 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 206 __I uint32_t RESERVED6;
sahilmgandhi 18:6a4db94011d3 207 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 208 __I uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 209 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 210 __I uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 212 __I uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 213 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 214 __I uint32_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 215 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 216 __I uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 217 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 218 __I uint32_t RESERVED12[225];
sahilmgandhi 18:6a4db94011d3 219 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 220 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 221 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 222 __I uint32_t RESERVED13;
sahilmgandhi 18:6a4db94011d3 223 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 224 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 226 __I uint32_t RESERVED14;
sahilmgandhi 18:6a4db94011d3 227 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 228 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 229 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 230 __I uint32_t RESERVED15;
sahilmgandhi 18:6a4db94011d3 231 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 232 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 233 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 234 __I uint32_t RESERVED16;
sahilmgandhi 18:6a4db94011d3 235 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 236 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 237 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 238 __I uint32_t RESERVED17;
sahilmgandhi 18:6a4db94011d3 239 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 240 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 241 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 242 __I uint32_t RESERVED18;
sahilmgandhi 18:6a4db94011d3 243 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 244 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 245 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 246 __I uint32_t RESERVED19;
sahilmgandhi 18:6a4db94011d3 247 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 248 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 249 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 250 __I uint32_t RESERVED20;
sahilmgandhi 18:6a4db94011d3 251 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 252 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 253 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 254 __I uint32_t RESERVED21;
sahilmgandhi 18:6a4db94011d3 255 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 256 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 257 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 258 __I uint32_t RESERVED22;
sahilmgandhi 18:6a4db94011d3 259 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 260 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 261 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 262 __I uint32_t RESERVED23;
sahilmgandhi 18:6a4db94011d3 263 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 264 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 265 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 266 __I uint32_t RESERVED24;
sahilmgandhi 18:6a4db94011d3 267 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 268 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 269 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 270 __I uint32_t RESERVED25;
sahilmgandhi 18:6a4db94011d3 271 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 272 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 273 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 274 __I uint32_t RESERVED26;
sahilmgandhi 18:6a4db94011d3 275 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 276 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 277 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 278 __I uint32_t RESERVED27;
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 280 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 281 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 282 __I uint32_t RESERVED28;
sahilmgandhi 18:6a4db94011d3 283 __IO uint32_t CFG16; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 284 __I uint32_t CTLSTAT16; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 285 __IO uint32_t XFERCFG16; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 286 __I uint32_t RESERVED29;
sahilmgandhi 18:6a4db94011d3 287 __IO uint32_t CFG17; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 288 __I uint32_t CTLSTAT17; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 289 __IO uint32_t XFERCFG17; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 290 } LPC_DMA_Type;
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 294 /* ================ USB ================ */
sahilmgandhi 18:6a4db94011d3 295 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 /**
sahilmgandhi 18:6a4db94011d3 299 * @brief USB device controller (USB)
sahilmgandhi 18:6a4db94011d3 300 */
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 typedef struct { /*!< USB Structure */
sahilmgandhi 18:6a4db94011d3 303 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
sahilmgandhi 18:6a4db94011d3 304 __IO uint32_t INFO; /*!< USB Info register */
sahilmgandhi 18:6a4db94011d3 305 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
sahilmgandhi 18:6a4db94011d3 306 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
sahilmgandhi 18:6a4db94011d3 307 __IO uint32_t LPM; /*!< Link Power Management register */
sahilmgandhi 18:6a4db94011d3 308 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
sahilmgandhi 18:6a4db94011d3 309 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
sahilmgandhi 18:6a4db94011d3 310 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
sahilmgandhi 18:6a4db94011d3 311 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
sahilmgandhi 18:6a4db94011d3 312 __IO uint32_t INTEN; /*!< USB interrupt enable register */
sahilmgandhi 18:6a4db94011d3 313 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
sahilmgandhi 18:6a4db94011d3 314 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
sahilmgandhi 18:6a4db94011d3 315 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 316 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
sahilmgandhi 18:6a4db94011d3 317 } LPC_USB_Type;
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 321 /* ================ CRC ================ */
sahilmgandhi 18:6a4db94011d3 322 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 /**
sahilmgandhi 18:6a4db94011d3 326 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
sahilmgandhi 18:6a4db94011d3 327 */
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 typedef struct { /*!< CRC Structure */
sahilmgandhi 18:6a4db94011d3 330 __IO uint32_t MODE; /*!< CRC mode register */
sahilmgandhi 18:6a4db94011d3 331 __IO uint32_t SEED; /*!< CRC seed register */
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 union {
sahilmgandhi 18:6a4db94011d3 334 __O uint32_t WR_DATA; /*!< CRC data register */
sahilmgandhi 18:6a4db94011d3 335 __I uint32_t SUM; /*!< CRC checksum register */
sahilmgandhi 18:6a4db94011d3 336 };
sahilmgandhi 18:6a4db94011d3 337 } LPC_CRC_Type;
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 341 /* ================ SCT0 ================ */
sahilmgandhi 18:6a4db94011d3 342 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 343
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 /**
sahilmgandhi 18:6a4db94011d3 346 * @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
sahilmgandhi 18:6a4db94011d3 347 */
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 typedef struct { /*!< SCT0 Structure */
sahilmgandhi 18:6a4db94011d3 350 __IO uint32_t CONFIG; /*!< SCT configuration register */
sahilmgandhi 18:6a4db94011d3 351 __IO uint32_t CTRL; /*!< SCT control register */
sahilmgandhi 18:6a4db94011d3 352 __IO uint32_t LIMIT; /*!< SCT limit register */
sahilmgandhi 18:6a4db94011d3 353 __IO uint32_t HALT; /*!< SCT halt condition register */
sahilmgandhi 18:6a4db94011d3 354 __IO uint32_t STOP; /*!< SCT stop condition register */
sahilmgandhi 18:6a4db94011d3 355 __IO uint32_t START; /*!< SCT start condition register */
sahilmgandhi 18:6a4db94011d3 356 __IO uint32_t DITHER; /*!< SCT dither condition register */
sahilmgandhi 18:6a4db94011d3 357 __I uint32_t RESERVED0[9];
sahilmgandhi 18:6a4db94011d3 358 __IO uint32_t COUNT; /*!< SCT counter register */
sahilmgandhi 18:6a4db94011d3 359 __IO uint32_t STATE; /*!< SCT state register */
sahilmgandhi 18:6a4db94011d3 360 __I uint32_t INPUT; /*!< SCT input register */
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t OUTPUT; /*!< SCT output register */
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
sahilmgandhi 18:6a4db94011d3 364 __IO uint32_t RES; /*!< SCT conflict resolution register */
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
sahilmgandhi 18:6a4db94011d3 366 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
sahilmgandhi 18:6a4db94011d3 367 __I uint32_t RESERVED1[35];
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t EVEN; /*!< SCT event enable register */
sahilmgandhi 18:6a4db94011d3 369 __IO uint32_t EVFLAG; /*!< SCT event flag register */
sahilmgandhi 18:6a4db94011d3 370 __IO uint32_t CONEN; /*!< SCT conflict enable register */
sahilmgandhi 18:6a4db94011d3 371 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 union {
sahilmgandhi 18:6a4db94011d3 374 __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 375 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 376 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 377 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 378 };
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 union {
sahilmgandhi 18:6a4db94011d3 381 __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 382 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 383 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 384 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 385 };
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 union {
sahilmgandhi 18:6a4db94011d3 388 __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 389 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 390 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 391 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 392 };
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 union {
sahilmgandhi 18:6a4db94011d3 395 __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 396 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 397 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 398 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 399 };
sahilmgandhi 18:6a4db94011d3 400
sahilmgandhi 18:6a4db94011d3 401 union {
sahilmgandhi 18:6a4db94011d3 402 __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 403 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 404 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 405 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 406 };
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 union {
sahilmgandhi 18:6a4db94011d3 409 __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 410 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 411 __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 412 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 413 };
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 union {
sahilmgandhi 18:6a4db94011d3 416 __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 417 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 418 __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 419 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 420 };
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 union {
sahilmgandhi 18:6a4db94011d3 423 __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 424 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 425 __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 426 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 427 };
sahilmgandhi 18:6a4db94011d3 428
sahilmgandhi 18:6a4db94011d3 429 union {
sahilmgandhi 18:6a4db94011d3 430 __I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 431 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 432 __IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 433 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 434 };
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 union {
sahilmgandhi 18:6a4db94011d3 437 __IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 438 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 439 __I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 440 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 441 };
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 union {
sahilmgandhi 18:6a4db94011d3 444 __IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 445 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 446 __I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 447 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 448 };
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 union {
sahilmgandhi 18:6a4db94011d3 451 __IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 452 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 453 __I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 454 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 455 };
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 union {
sahilmgandhi 18:6a4db94011d3 458 __IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 459 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 460 __I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 461 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 462 };
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 union {
sahilmgandhi 18:6a4db94011d3 465 __IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 466 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 467 __I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 468 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 469 };
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 union {
sahilmgandhi 18:6a4db94011d3 472 __I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 473 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 474 __IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 475 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 476 };
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 union {
sahilmgandhi 18:6a4db94011d3 479 __IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
sahilmgandhi 18:6a4db94011d3 480 to REGMODE15 = 0 */
sahilmgandhi 18:6a4db94011d3 481 __I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 482 REGMODE15 = 1 */
sahilmgandhi 18:6a4db94011d3 483 };
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
sahilmgandhi 18:6a4db94011d3 485 0 to 5. */
sahilmgandhi 18:6a4db94011d3 486 __IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
sahilmgandhi 18:6a4db94011d3 487 0 to 5. */
sahilmgandhi 18:6a4db94011d3 488 __IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
sahilmgandhi 18:6a4db94011d3 489 0 to 5. */
sahilmgandhi 18:6a4db94011d3 490 __IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
sahilmgandhi 18:6a4db94011d3 491 0 to 5. */
sahilmgandhi 18:6a4db94011d3 492 __IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
sahilmgandhi 18:6a4db94011d3 493 0 to 5. */
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
sahilmgandhi 18:6a4db94011d3 495 0 to 5. */
sahilmgandhi 18:6a4db94011d3 496 __I uint32_t RESERVED2[42];
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 union {
sahilmgandhi 18:6a4db94011d3 499 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 500 = 1 */
sahilmgandhi 18:6a4db94011d3 501 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 502 = 0 */
sahilmgandhi 18:6a4db94011d3 503 };
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 union {
sahilmgandhi 18:6a4db94011d3 506 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 507 = 0 */
sahilmgandhi 18:6a4db94011d3 508 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 509 = 1 */
sahilmgandhi 18:6a4db94011d3 510 };
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 union {
sahilmgandhi 18:6a4db94011d3 513 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 514 = 0 */
sahilmgandhi 18:6a4db94011d3 515 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 516 = 1 */
sahilmgandhi 18:6a4db94011d3 517 };
sahilmgandhi 18:6a4db94011d3 518
sahilmgandhi 18:6a4db94011d3 519 union {
sahilmgandhi 18:6a4db94011d3 520 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 521 = 1 */
sahilmgandhi 18:6a4db94011d3 522 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 523 = 0 */
sahilmgandhi 18:6a4db94011d3 524 };
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 union {
sahilmgandhi 18:6a4db94011d3 527 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 528 = 1 */
sahilmgandhi 18:6a4db94011d3 529 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 530 = 0 */
sahilmgandhi 18:6a4db94011d3 531 };
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 union {
sahilmgandhi 18:6a4db94011d3 534 __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 535 = 1 */
sahilmgandhi 18:6a4db94011d3 536 __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 537 = 0 */
sahilmgandhi 18:6a4db94011d3 538 };
sahilmgandhi 18:6a4db94011d3 539
sahilmgandhi 18:6a4db94011d3 540 union {
sahilmgandhi 18:6a4db94011d3 541 __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 542 = 0 */
sahilmgandhi 18:6a4db94011d3 543 __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 544 = 1 */
sahilmgandhi 18:6a4db94011d3 545 };
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 union {
sahilmgandhi 18:6a4db94011d3 548 __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 549 = 0 */
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 551 = 1 */
sahilmgandhi 18:6a4db94011d3 552 };
sahilmgandhi 18:6a4db94011d3 553
sahilmgandhi 18:6a4db94011d3 554 union {
sahilmgandhi 18:6a4db94011d3 555 __IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 556 = 1 */
sahilmgandhi 18:6a4db94011d3 557 __IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 558 = 0 */
sahilmgandhi 18:6a4db94011d3 559 };
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 union {
sahilmgandhi 18:6a4db94011d3 562 __IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 563 = 1 */
sahilmgandhi 18:6a4db94011d3 564 __IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 565 = 0 */
sahilmgandhi 18:6a4db94011d3 566 };
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 union {
sahilmgandhi 18:6a4db94011d3 569 __IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 570 = 1 */
sahilmgandhi 18:6a4db94011d3 571 __IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 572 = 0 */
sahilmgandhi 18:6a4db94011d3 573 };
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 union {
sahilmgandhi 18:6a4db94011d3 576 __IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 577 = 1 */
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 579 = 0 */
sahilmgandhi 18:6a4db94011d3 580 };
sahilmgandhi 18:6a4db94011d3 581
sahilmgandhi 18:6a4db94011d3 582 union {
sahilmgandhi 18:6a4db94011d3 583 __IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 584 = 0 */
sahilmgandhi 18:6a4db94011d3 585 __IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 586 = 1 */
sahilmgandhi 18:6a4db94011d3 587 };
sahilmgandhi 18:6a4db94011d3 588
sahilmgandhi 18:6a4db94011d3 589 union {
sahilmgandhi 18:6a4db94011d3 590 __IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 591 = 0 */
sahilmgandhi 18:6a4db94011d3 592 __IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 593 = 1 */
sahilmgandhi 18:6a4db94011d3 594 };
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 union {
sahilmgandhi 18:6a4db94011d3 597 __IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 598 = 1 */
sahilmgandhi 18:6a4db94011d3 599 __IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 600 = 0 */
sahilmgandhi 18:6a4db94011d3 601 };
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 union {
sahilmgandhi 18:6a4db94011d3 604 __IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
sahilmgandhi 18:6a4db94011d3 605 = 1 */
sahilmgandhi 18:6a4db94011d3 606 __IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
sahilmgandhi 18:6a4db94011d3 607 = 0 */
sahilmgandhi 18:6a4db94011d3 608 };
sahilmgandhi 18:6a4db94011d3 609 __IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
sahilmgandhi 18:6a4db94011d3 610 registers 0 to 5. */
sahilmgandhi 18:6a4db94011d3 611 __IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
sahilmgandhi 18:6a4db94011d3 612 registers 0 to 5. */
sahilmgandhi 18:6a4db94011d3 613 __IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
sahilmgandhi 18:6a4db94011d3 614 registers 0 to 5. */
sahilmgandhi 18:6a4db94011d3 615 __IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
sahilmgandhi 18:6a4db94011d3 616 registers 0 to 5. */
sahilmgandhi 18:6a4db94011d3 617 __IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
sahilmgandhi 18:6a4db94011d3 618 registers 0 to 5. */
sahilmgandhi 18:6a4db94011d3 619 __IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
sahilmgandhi 18:6a4db94011d3 620 registers 0 to 5. */
sahilmgandhi 18:6a4db94011d3 621 __I uint32_t RESERVED3[42];
sahilmgandhi 18:6a4db94011d3 622 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 623 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 624 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 625 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 626 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 627 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 628 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 629 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 630 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 631 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 632 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 633 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 634 __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 635 __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 636 __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 637 __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 638 __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 639 __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 640 __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 641 __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 642 __IO uint32_t EV10_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 643 __IO uint32_t EV10_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 644 __IO uint32_t EV11_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 645 __IO uint32_t EV11_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 646 __IO uint32_t EV12_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 647 __IO uint32_t EV12_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 648 __IO uint32_t EV13_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 649 __IO uint32_t EV13_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 650 __IO uint32_t EV14_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 651 __IO uint32_t EV14_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 652 __IO uint32_t EV15_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 653 __IO uint32_t EV15_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 654 __I uint32_t RESERVED4[96];
sahilmgandhi 18:6a4db94011d3 655 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 656 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 657 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 658 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 659 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 660 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 661 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 662 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 663 __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 664 __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 665 __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 666 __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 667 __IO uint32_t OUT6_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 668 __IO uint32_t OUT6_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 669 __IO uint32_t OUT7_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 670 __IO uint32_t OUT7_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 671 __IO uint32_t OUT8_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 672 __IO uint32_t OUT8_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 673 __IO uint32_t OUT9_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 674 __IO uint32_t OUT9_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 675 } LPC_SCT0_Type;
sahilmgandhi 18:6a4db94011d3 676
sahilmgandhi 18:6a4db94011d3 677
sahilmgandhi 18:6a4db94011d3 678 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 679 /* ================ SCT2 ================ */
sahilmgandhi 18:6a4db94011d3 680 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682
sahilmgandhi 18:6a4db94011d3 683 /**
sahilmgandhi 18:6a4db94011d3 684 * @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
sahilmgandhi 18:6a4db94011d3 685 */
sahilmgandhi 18:6a4db94011d3 686
sahilmgandhi 18:6a4db94011d3 687 typedef struct { /*!< SCT2 Structure */
sahilmgandhi 18:6a4db94011d3 688 __IO uint32_t CONFIG; /*!< SCT configuration register */
sahilmgandhi 18:6a4db94011d3 689 __IO uint32_t CTRL; /*!< SCT control register */
sahilmgandhi 18:6a4db94011d3 690 __IO uint32_t LIMIT; /*!< SCT limit register */
sahilmgandhi 18:6a4db94011d3 691 __IO uint32_t HALT; /*!< SCT halt condition register */
sahilmgandhi 18:6a4db94011d3 692 __IO uint32_t STOP; /*!< SCT stop condition register */
sahilmgandhi 18:6a4db94011d3 693 __IO uint32_t START; /*!< SCT start condition register */
sahilmgandhi 18:6a4db94011d3 694 __I uint32_t RESERVED0[10];
sahilmgandhi 18:6a4db94011d3 695 __IO uint32_t COUNT; /*!< SCT counter register */
sahilmgandhi 18:6a4db94011d3 696 __IO uint32_t STATE; /*!< SCT state register */
sahilmgandhi 18:6a4db94011d3 697 __I uint32_t INPUT; /*!< SCT input register */
sahilmgandhi 18:6a4db94011d3 698 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
sahilmgandhi 18:6a4db94011d3 699 __IO uint32_t OUTPUT; /*!< SCT output register */
sahilmgandhi 18:6a4db94011d3 700 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
sahilmgandhi 18:6a4db94011d3 701 __IO uint32_t RES; /*!< SCT conflict resolution register */
sahilmgandhi 18:6a4db94011d3 702 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
sahilmgandhi 18:6a4db94011d3 703 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
sahilmgandhi 18:6a4db94011d3 704 __I uint32_t RESERVED1[35];
sahilmgandhi 18:6a4db94011d3 705 __IO uint32_t EVEN; /*!< SCT event enable register */
sahilmgandhi 18:6a4db94011d3 706 __IO uint32_t EVFLAG; /*!< SCT event flag register */
sahilmgandhi 18:6a4db94011d3 707 __IO uint32_t CONEN; /*!< SCT conflict enable register */
sahilmgandhi 18:6a4db94011d3 708 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 union {
sahilmgandhi 18:6a4db94011d3 711 __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 712 = 1 */
sahilmgandhi 18:6a4db94011d3 713 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 714 REGMODE7 = 0 */
sahilmgandhi 18:6a4db94011d3 715 };
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 union {
sahilmgandhi 18:6a4db94011d3 718 __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 719 = 1 */
sahilmgandhi 18:6a4db94011d3 720 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 721 REGMODE7 = 0 */
sahilmgandhi 18:6a4db94011d3 722 };
sahilmgandhi 18:6a4db94011d3 723
sahilmgandhi 18:6a4db94011d3 724 union {
sahilmgandhi 18:6a4db94011d3 725 __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 726 = 1 */
sahilmgandhi 18:6a4db94011d3 727 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 728 REGMODE7 = 0 */
sahilmgandhi 18:6a4db94011d3 729 };
sahilmgandhi 18:6a4db94011d3 730
sahilmgandhi 18:6a4db94011d3 731 union {
sahilmgandhi 18:6a4db94011d3 732 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 733 REGMODE7 = 0 */
sahilmgandhi 18:6a4db94011d3 734 __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 735 = 1 */
sahilmgandhi 18:6a4db94011d3 736 };
sahilmgandhi 18:6a4db94011d3 737
sahilmgandhi 18:6a4db94011d3 738 union {
sahilmgandhi 18:6a4db94011d3 739 __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 740 = 1 */
sahilmgandhi 18:6a4db94011d3 741 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 742 REGMODE7 = 0 */
sahilmgandhi 18:6a4db94011d3 743 };
sahilmgandhi 18:6a4db94011d3 744
sahilmgandhi 18:6a4db94011d3 745 union {
sahilmgandhi 18:6a4db94011d3 746 __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 747 REGMODE7 = 0 */
sahilmgandhi 18:6a4db94011d3 748 __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 749 = 1 */
sahilmgandhi 18:6a4db94011d3 750 };
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752 union {
sahilmgandhi 18:6a4db94011d3 753 __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 754 = 1 */
sahilmgandhi 18:6a4db94011d3 755 __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 756 REGMODE7 = 0 */
sahilmgandhi 18:6a4db94011d3 757 };
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 union {
sahilmgandhi 18:6a4db94011d3 760 __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 761 = 1 */
sahilmgandhi 18:6a4db94011d3 762 __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 763 REGMODE7 = 0 */
sahilmgandhi 18:6a4db94011d3 764 };
sahilmgandhi 18:6a4db94011d3 765 __I uint32_t RESERVED2[56];
sahilmgandhi 18:6a4db94011d3 766
sahilmgandhi 18:6a4db94011d3 767 union {
sahilmgandhi 18:6a4db94011d3 768 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
sahilmgandhi 18:6a4db94011d3 769 = 1 */
sahilmgandhi 18:6a4db94011d3 770 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 771 = 0 */
sahilmgandhi 18:6a4db94011d3 772 };
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 union {
sahilmgandhi 18:6a4db94011d3 775 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
sahilmgandhi 18:6a4db94011d3 776 = 1 */
sahilmgandhi 18:6a4db94011d3 777 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 778 = 0 */
sahilmgandhi 18:6a4db94011d3 779 };
sahilmgandhi 18:6a4db94011d3 780
sahilmgandhi 18:6a4db94011d3 781 union {
sahilmgandhi 18:6a4db94011d3 782 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
sahilmgandhi 18:6a4db94011d3 783 = 1 */
sahilmgandhi 18:6a4db94011d3 784 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 785 = 0 */
sahilmgandhi 18:6a4db94011d3 786 };
sahilmgandhi 18:6a4db94011d3 787
sahilmgandhi 18:6a4db94011d3 788 union {
sahilmgandhi 18:6a4db94011d3 789 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 790 = 0 */
sahilmgandhi 18:6a4db94011d3 791 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
sahilmgandhi 18:6a4db94011d3 792 = 1 */
sahilmgandhi 18:6a4db94011d3 793 };
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 union {
sahilmgandhi 18:6a4db94011d3 796 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
sahilmgandhi 18:6a4db94011d3 797 = 1 */
sahilmgandhi 18:6a4db94011d3 798 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 799 = 0 */
sahilmgandhi 18:6a4db94011d3 800 };
sahilmgandhi 18:6a4db94011d3 801
sahilmgandhi 18:6a4db94011d3 802 union {
sahilmgandhi 18:6a4db94011d3 803 __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 804 = 0 */
sahilmgandhi 18:6a4db94011d3 805 __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
sahilmgandhi 18:6a4db94011d3 806 = 1 */
sahilmgandhi 18:6a4db94011d3 807 };
sahilmgandhi 18:6a4db94011d3 808
sahilmgandhi 18:6a4db94011d3 809 union {
sahilmgandhi 18:6a4db94011d3 810 __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
sahilmgandhi 18:6a4db94011d3 811 = 1 */
sahilmgandhi 18:6a4db94011d3 812 __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 813 = 0 */
sahilmgandhi 18:6a4db94011d3 814 };
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 union {
sahilmgandhi 18:6a4db94011d3 817 __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
sahilmgandhi 18:6a4db94011d3 818 = 1 */
sahilmgandhi 18:6a4db94011d3 819 __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
sahilmgandhi 18:6a4db94011d3 820 = 0 */
sahilmgandhi 18:6a4db94011d3 821 };
sahilmgandhi 18:6a4db94011d3 822 __I uint32_t RESERVED3[56];
sahilmgandhi 18:6a4db94011d3 823 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 824 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 825 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 826 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 827 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 828 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 829 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 830 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 831 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 832 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 833 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 834 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 835 __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 836 __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 837 __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 838 __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 839 __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 840 __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 841 __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 842 __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 843 __I uint32_t RESERVED4[108];
sahilmgandhi 18:6a4db94011d3 844 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 845 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 846 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 847 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 848 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 849 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 850 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 851 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 852 __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 853 __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 854 __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 855 __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 856 } LPC_SCT2_Type;
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858
sahilmgandhi 18:6a4db94011d3 859 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 860 /* ================ ADC0 ================ */
sahilmgandhi 18:6a4db94011d3 861 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 862
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 /**
sahilmgandhi 18:6a4db94011d3 865 * @brief 12-bit ADC controller ADC0/1 (ADC0)
sahilmgandhi 18:6a4db94011d3 866 */
sahilmgandhi 18:6a4db94011d3 867
sahilmgandhi 18:6a4db94011d3 868 typedef struct { /*!< ADC0 Structure */
sahilmgandhi 18:6a4db94011d3 869 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
sahilmgandhi 18:6a4db94011d3 870 bits for each sequence and the A/D power-down bit. */
sahilmgandhi 18:6a4db94011d3 871 __IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
sahilmgandhi 18:6a4db94011d3 872 internal source for various channels */
sahilmgandhi 18:6a4db94011d3 873 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
sahilmgandhi 18:6a4db94011d3 874 and channel selection for conversion sequence-A. Also specifies
sahilmgandhi 18:6a4db94011d3 875 interrupt mode for sequence-A. */
sahilmgandhi 18:6a4db94011d3 876 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
sahilmgandhi 18:6a4db94011d3 877 and channel selection for conversion sequence-B. Also specifies
sahilmgandhi 18:6a4db94011d3 878 interrupt mode for sequence-B. */
sahilmgandhi 18:6a4db94011d3 879 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
sahilmgandhi 18:6a4db94011d3 880 the result of the most recent A/D conversion performed under
sahilmgandhi 18:6a4db94011d3 881 sequence-A */
sahilmgandhi 18:6a4db94011d3 882 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
sahilmgandhi 18:6a4db94011d3 883 the result of the most recent A/D conversion performed under
sahilmgandhi 18:6a4db94011d3 884 sequence-B */
sahilmgandhi 18:6a4db94011d3 885 __I uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 886 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
sahilmgandhi 18:6a4db94011d3 887 of the most recent conversion completed on channel 0. */
sahilmgandhi 18:6a4db94011d3 888 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
sahilmgandhi 18:6a4db94011d3 889 level for automatic threshold comparison for any channels linked
sahilmgandhi 18:6a4db94011d3 890 to threshold pair 0. */
sahilmgandhi 18:6a4db94011d3 891 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
sahilmgandhi 18:6a4db94011d3 892 level for automatic threshold comparison for any channels linked
sahilmgandhi 18:6a4db94011d3 893 to threshold pair 1. */
sahilmgandhi 18:6a4db94011d3 894 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
sahilmgandhi 18:6a4db94011d3 895 level for automatic threshold comparison for any channels linked
sahilmgandhi 18:6a4db94011d3 896 to threshold pair 0. */
sahilmgandhi 18:6a4db94011d3 897 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
sahilmgandhi 18:6a4db94011d3 898 level for automatic threshold comparison for any channels linked
sahilmgandhi 18:6a4db94011d3 899 to threshold pair 1. */
sahilmgandhi 18:6a4db94011d3 900 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
sahilmgandhi 18:6a4db94011d3 901 threshold compare registers are to be used for each channel */
sahilmgandhi 18:6a4db94011d3 902 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
sahilmgandhi 18:6a4db94011d3 903 bits that enable the sequence-A, sequence-B, threshold compare
sahilmgandhi 18:6a4db94011d3 904 and data overrun interrupts to be generated. */
sahilmgandhi 18:6a4db94011d3 905 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
sahilmgandhi 18:6a4db94011d3 906 and the individual component overrun and threshold-compare flags.
sahilmgandhi 18:6a4db94011d3 907 (The overrun bits replicate information stored in the result
sahilmgandhi 18:6a4db94011d3 908 registers). */
sahilmgandhi 18:6a4db94011d3 909 __IO uint32_t TRM; /*!< ADC trim register. */
sahilmgandhi 18:6a4db94011d3 910 } LPC_ADC0_Type;
sahilmgandhi 18:6a4db94011d3 911
sahilmgandhi 18:6a4db94011d3 912
sahilmgandhi 18:6a4db94011d3 913 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 914 /* ================ DAC ================ */
sahilmgandhi 18:6a4db94011d3 915 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917
sahilmgandhi 18:6a4db94011d3 918 /**
sahilmgandhi 18:6a4db94011d3 919 * @brief 12-bit DAC Modification (DAC)
sahilmgandhi 18:6a4db94011d3 920 */
sahilmgandhi 18:6a4db94011d3 921
sahilmgandhi 18:6a4db94011d3 922 typedef struct { /*!< DAC Structure */
sahilmgandhi 18:6a4db94011d3 923 __IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
sahilmgandhi 18:6a4db94011d3 924 value to be converted to analog. */
sahilmgandhi 18:6a4db94011d3 925 __IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
sahilmgandhi 18:6a4db94011d3 926 DAC operation and the interrupt/dma request flag. */
sahilmgandhi 18:6a4db94011d3 927 __IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
sahilmgandhi 18:6a4db94011d3 928 value for the internal DAC DMA/Interrupt timer. */
sahilmgandhi 18:6a4db94011d3 929 } LPC_DAC_Type;
sahilmgandhi 18:6a4db94011d3 930
sahilmgandhi 18:6a4db94011d3 931
sahilmgandhi 18:6a4db94011d3 932 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 933 /* ================ ACMP ================ */
sahilmgandhi 18:6a4db94011d3 934 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 935
sahilmgandhi 18:6a4db94011d3 936
sahilmgandhi 18:6a4db94011d3 937 /**
sahilmgandhi 18:6a4db94011d3 938 * @brief Analog comparators ACMP0/1/2/3 (ACMP)
sahilmgandhi 18:6a4db94011d3 939 */
sahilmgandhi 18:6a4db94011d3 940
sahilmgandhi 18:6a4db94011d3 941 typedef struct { /*!< ACMP Structure */
sahilmgandhi 18:6a4db94011d3 942 __IO uint32_t CTRL; /*!< Comparator block control register */
sahilmgandhi 18:6a4db94011d3 943 __IO uint32_t CMP0; /*!< Comparator 0 source control */
sahilmgandhi 18:6a4db94011d3 944 __IO uint32_t CMPFILTR0; /*!< Comparator 0 pin filter set-up */
sahilmgandhi 18:6a4db94011d3 945 __IO uint32_t CMP1; /*!< Comparator 1 source control */
sahilmgandhi 18:6a4db94011d3 946 __IO uint32_t CMPFILTR1; /*!< Comparator 0 pin filter set-up */
sahilmgandhi 18:6a4db94011d3 947 __IO uint32_t CMP2; /*!< Comparator 2 source control */
sahilmgandhi 18:6a4db94011d3 948 __IO uint32_t CMPFILTR2; /*!< Comparator 0 pin filter set-up */
sahilmgandhi 18:6a4db94011d3 949 __IO uint32_t CMP3; /*!< Comparator 3 source control */
sahilmgandhi 18:6a4db94011d3 950 __IO uint32_t CMPFILTR3; /*!< Comparator 0 pin filter set-up */
sahilmgandhi 18:6a4db94011d3 951 } LPC_ACMP_Type;
sahilmgandhi 18:6a4db94011d3 952
sahilmgandhi 18:6a4db94011d3 953
sahilmgandhi 18:6a4db94011d3 954 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 955 /* ================ INMUX ================ */
sahilmgandhi 18:6a4db94011d3 956 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 957
sahilmgandhi 18:6a4db94011d3 958
sahilmgandhi 18:6a4db94011d3 959 /**
sahilmgandhi 18:6a4db94011d3 960 * @brief Input multiplexing (INMUX) (INMUX)
sahilmgandhi 18:6a4db94011d3 961 */
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 typedef struct { /*!< INMUX Structure */
sahilmgandhi 18:6a4db94011d3 964 __IO uint32_t SCT0_INMUX[7]; /*!< Pinmux register for SCT0 input 0 */
sahilmgandhi 18:6a4db94011d3 965 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 966 __IO uint32_t SCT1_INMUX[7]; /*!< Pinmux register for SCT1 input 0 */
sahilmgandhi 18:6a4db94011d3 967 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 968 __IO uint32_t SCT2_INMUX[3]; /*!< Pinmux register for SCT2 input 0 */
sahilmgandhi 18:6a4db94011d3 969 __I uint32_t RESERVED2[5];
sahilmgandhi 18:6a4db94011d3 970 __IO uint32_t SCT3_INMUX[3]; /*!< Pinmux register for SCT3 input 0 */
sahilmgandhi 18:6a4db94011d3 971 __I uint32_t RESERVED3[21];
sahilmgandhi 18:6a4db94011d3 972 __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select register 0 */
sahilmgandhi 18:6a4db94011d3 973 __IO uint32_t DMA_ITRIG_INMUX[18]; /*!< Trigger input for DMA channel 0 select register. */
sahilmgandhi 18:6a4db94011d3 974 __I uint32_t RESERVED4[14];
sahilmgandhi 18:6a4db94011d3 975 __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
sahilmgandhi 18:6a4db94011d3 976 clock */
sahilmgandhi 18:6a4db94011d3 977 __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement function target clock */
sahilmgandhi 18:6a4db94011d3 978 } LPC_INMUX_Type;
sahilmgandhi 18:6a4db94011d3 979
sahilmgandhi 18:6a4db94011d3 980
sahilmgandhi 18:6a4db94011d3 981 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 982 /* ================ RTC ================ */
sahilmgandhi 18:6a4db94011d3 983 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 984
sahilmgandhi 18:6a4db94011d3 985
sahilmgandhi 18:6a4db94011d3 986 /**
sahilmgandhi 18:6a4db94011d3 987 * @brief Real-Time Clock (RTC) (RTC)
sahilmgandhi 18:6a4db94011d3 988 */
sahilmgandhi 18:6a4db94011d3 989
sahilmgandhi 18:6a4db94011d3 990 typedef struct { /*!< RTC Structure */
sahilmgandhi 18:6a4db94011d3 991 __IO uint32_t CTRL; /*!< RTC control register */
sahilmgandhi 18:6a4db94011d3 992 __IO uint32_t MATCH; /*!< RTC match register */
sahilmgandhi 18:6a4db94011d3 993 __IO uint32_t COUNT; /*!< RTC counter register */
sahilmgandhi 18:6a4db94011d3 994 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
sahilmgandhi 18:6a4db94011d3 995 } LPC_RTC_Type;
sahilmgandhi 18:6a4db94011d3 996
sahilmgandhi 18:6a4db94011d3 997
sahilmgandhi 18:6a4db94011d3 998 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 999 /* ================ WWDT ================ */
sahilmgandhi 18:6a4db94011d3 1000 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1001
sahilmgandhi 18:6a4db94011d3 1002
sahilmgandhi 18:6a4db94011d3 1003 /**
sahilmgandhi 18:6a4db94011d3 1004 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
sahilmgandhi 18:6a4db94011d3 1005 */
sahilmgandhi 18:6a4db94011d3 1006
sahilmgandhi 18:6a4db94011d3 1007 typedef struct { /*!< WWDT Structure */
sahilmgandhi 18:6a4db94011d3 1008 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
sahilmgandhi 18:6a4db94011d3 1009 and status of the Watchdog Timer. */
sahilmgandhi 18:6a4db94011d3 1010 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
sahilmgandhi 18:6a4db94011d3 1011 the time-out value. */
sahilmgandhi 18:6a4db94011d3 1012 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
sahilmgandhi 18:6a4db94011d3 1013 to this register reloads the Watchdog timer with the value contained
sahilmgandhi 18:6a4db94011d3 1014 in WDTC. */
sahilmgandhi 18:6a4db94011d3 1015 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
sahilmgandhi 18:6a4db94011d3 1016 the current value of the Watchdog timer. */
sahilmgandhi 18:6a4db94011d3 1017 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1018 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
sahilmgandhi 18:6a4db94011d3 1019 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
sahilmgandhi 18:6a4db94011d3 1020 } LPC_WWDT_Type;
sahilmgandhi 18:6a4db94011d3 1021
sahilmgandhi 18:6a4db94011d3 1022
sahilmgandhi 18:6a4db94011d3 1023 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1024 /* ================ SWM ================ */
sahilmgandhi 18:6a4db94011d3 1025 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1026
sahilmgandhi 18:6a4db94011d3 1027
sahilmgandhi 18:6a4db94011d3 1028 /**
sahilmgandhi 18:6a4db94011d3 1029 * @brief Switch Matrix (SWM) (SWM)
sahilmgandhi 18:6a4db94011d3 1030 */
sahilmgandhi 18:6a4db94011d3 1031
sahilmgandhi 18:6a4db94011d3 1032 typedef struct { /*!< SWM Structure */
sahilmgandhi 18:6a4db94011d3 1033 union {
sahilmgandhi 18:6a4db94011d3 1034 __IO uint32_t PINASSIGN[16];
sahilmgandhi 18:6a4db94011d3 1035 struct {
sahilmgandhi 18:6a4db94011d3 1036 __IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
sahilmgandhi 18:6a4db94011d3 1037 U0_RTS, U0_CTS. */
sahilmgandhi 18:6a4db94011d3 1038 __IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
sahilmgandhi 18:6a4db94011d3 1039 U1_RXD, U1_RTS. */
sahilmgandhi 18:6a4db94011d3 1040 __IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
sahilmgandhi 18:6a4db94011d3 1041 U2_TXD, U2_RXD. */
sahilmgandhi 18:6a4db94011d3 1042 __IO uint32_t PINASSIGN3; /*!< Pin assign register 3. Assign movable function . */
sahilmgandhi 18:6a4db94011d3 1043 __IO uint32_t PINASSIGN4; /*!< Pin assign register 4. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1044 __IO uint32_t PINASSIGN5; /*!< Pin assign register 5. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1045 __IO uint32_t PINASSIGN6; /*!< Pin assign register 6. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1046 __IO uint32_t PINASSIGN7; /*!< Pin assign register 7. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1047 __IO uint32_t PINASSIGN8; /*!< Pin assign register 8. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1048 __IO uint32_t PINASSIGN9; /*!< Pin assign register 9. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1049 __IO uint32_t PINASSIGN10; /*!< Pin assign register 10. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1050 __IO uint32_t PINASSIGN11; /*!< Pin assign register 11. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1051 __IO uint32_t PINASSIGN12; /*!< Pin assign register 12. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1052 __IO uint32_t PINASSIGN13; /*!< Pin assign register 13. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1053 __IO uint32_t PINASSIGN14; /*!< Pin assign register 14. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1054 __IO uint32_t PINASSIGN15; /*!< Pin assign register 15. Assign movable functions */
sahilmgandhi 18:6a4db94011d3 1055 };
sahilmgandhi 18:6a4db94011d3 1056 };
sahilmgandhi 18:6a4db94011d3 1057 __I uint32_t RESERVED0[96];
sahilmgandhi 18:6a4db94011d3 1058 __IO uint32_t PINENABLE0; /*!< Pin enable register 0. Enables fixed-pin functions */
sahilmgandhi 18:6a4db94011d3 1059 __IO uint32_t PINENABLE1; /*!< Pin enable register 0. Enables fixed-pin functions */
sahilmgandhi 18:6a4db94011d3 1060 } LPC_SWM_Type;
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062
sahilmgandhi 18:6a4db94011d3 1063 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1064 /* ================ PMU ================ */
sahilmgandhi 18:6a4db94011d3 1065 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1066
sahilmgandhi 18:6a4db94011d3 1067
sahilmgandhi 18:6a4db94011d3 1068 /**
sahilmgandhi 18:6a4db94011d3 1069 * @brief Power Management Unit (PMU) (PMU)
sahilmgandhi 18:6a4db94011d3 1070 */
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 typedef struct { /*!< PMU Structure */
sahilmgandhi 18:6a4db94011d3 1073 __IO uint32_t PCON; /*!< Power control register */
sahilmgandhi 18:6a4db94011d3 1074 __IO uint32_t GPREG0; /*!< General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 1075 __IO uint32_t GPREG1; /*!< General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 1076 __IO uint32_t GPREG2; /*!< General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 1077 __IO uint32_t GPREG3; /*!< General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 1078 __IO uint32_t DPDCTRL; /*!< Deep power-down control register */
sahilmgandhi 18:6a4db94011d3 1079 } LPC_PMU_Type;
sahilmgandhi 18:6a4db94011d3 1080
sahilmgandhi 18:6a4db94011d3 1081
sahilmgandhi 18:6a4db94011d3 1082 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1083 /* ================ USART0 ================ */
sahilmgandhi 18:6a4db94011d3 1084 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1085
sahilmgandhi 18:6a4db94011d3 1086
sahilmgandhi 18:6a4db94011d3 1087 /**
sahilmgandhi 18:6a4db94011d3 1088 * @brief USART0 (USART0)
sahilmgandhi 18:6a4db94011d3 1089 */
sahilmgandhi 18:6a4db94011d3 1090
sahilmgandhi 18:6a4db94011d3 1091 typedef struct { /*!< USART0 Structure */
sahilmgandhi 18:6a4db94011d3 1092 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
sahilmgandhi 18:6a4db94011d3 1093 that typically are not changed during operation. */
sahilmgandhi 18:6a4db94011d3 1094 __IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
sahilmgandhi 18:6a4db94011d3 1095 likely to change during operation. */
sahilmgandhi 18:6a4db94011d3 1096 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
sahilmgandhi 18:6a4db94011d3 1097 here. Writing ones clears some bits in the register. Some bits
sahilmgandhi 18:6a4db94011d3 1098 can be cleared by writing a 1 to them. */
sahilmgandhi 18:6a4db94011d3 1099 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
sahilmgandhi 18:6a4db94011d3 1100 interrupt enable bit for each potential USART interrupt. A complete
sahilmgandhi 18:6a4db94011d3 1101 value may be read from this register. Writing a 1 to any implemented
sahilmgandhi 18:6a4db94011d3 1102 bit position causes that bit to be set. */
sahilmgandhi 18:6a4db94011d3 1103 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
sahilmgandhi 18:6a4db94011d3 1104 of bits in the INTENSET register. Writing a 1 to any implemented
sahilmgandhi 18:6a4db94011d3 1105 bit position causes the corresponding bit to be cleared. */
sahilmgandhi 18:6a4db94011d3 1106 __I uint32_t RXDATA; /*!< Receiver Data register. Contains the last character received. */
sahilmgandhi 18:6a4db94011d3 1107 __I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
sahilmgandhi 18:6a4db94011d3 1108 received with the current USART receive status. Allows DMA or
sahilmgandhi 18:6a4db94011d3 1109 software to recover incoming data and status together. */
sahilmgandhi 18:6a4db94011d3 1110 __IO uint32_t TXDATA; /*!< Transmit Data register. Data to be transmitted is written here. */
sahilmgandhi 18:6a4db94011d3 1111 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
sahilmgandhi 18:6a4db94011d3 1112 value. */
sahilmgandhi 18:6a4db94011d3 1113 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
sahilmgandhi 18:6a4db94011d3 1114 enabled. */
sahilmgandhi 18:6a4db94011d3 1115 } LPC_USART0_Type;
sahilmgandhi 18:6a4db94011d3 1116
sahilmgandhi 18:6a4db94011d3 1117
sahilmgandhi 18:6a4db94011d3 1118 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1119 /* ================ SPI0 ================ */
sahilmgandhi 18:6a4db94011d3 1120 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1121
sahilmgandhi 18:6a4db94011d3 1122
sahilmgandhi 18:6a4db94011d3 1123 /**
sahilmgandhi 18:6a4db94011d3 1124 * @brief SPI0 (SPI0)
sahilmgandhi 18:6a4db94011d3 1125 */
sahilmgandhi 18:6a4db94011d3 1126
sahilmgandhi 18:6a4db94011d3 1127 typedef struct { /*!< SPI0 Structure */
sahilmgandhi 18:6a4db94011d3 1128 __IO uint32_t CFG; /*!< SPI Configuration register */
sahilmgandhi 18:6a4db94011d3 1129 __IO uint32_t DLY; /*!< SPI Delay register */
sahilmgandhi 18:6a4db94011d3 1130 __IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
sahilmgandhi 18:6a4db94011d3 1131 to that bit position */
sahilmgandhi 18:6a4db94011d3 1132 __IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
sahilmgandhi 18:6a4db94011d3 1133 from this register. Writing a 1 to any implemented bit position
sahilmgandhi 18:6a4db94011d3 1134 causes that bit to be set. */
sahilmgandhi 18:6a4db94011d3 1135 __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
sahilmgandhi 18:6a4db94011d3 1136 position causes the corresponding bit in INTENSET to be cleared. */
sahilmgandhi 18:6a4db94011d3 1137 __I uint32_t RXDAT; /*!< SPI Receive Data */
sahilmgandhi 18:6a4db94011d3 1138 __IO uint32_t TXDATCTL; /*!< SPI Transmit Data with Control */
sahilmgandhi 18:6a4db94011d3 1139 __IO uint32_t TXDAT; /*!< SPI Transmit Data with Control */
sahilmgandhi 18:6a4db94011d3 1140 __IO uint32_t TXCTL; /*!< SPI Transmit Control */
sahilmgandhi 18:6a4db94011d3 1141 __IO uint32_t DIV; /*!< SPI clock Divider */
sahilmgandhi 18:6a4db94011d3 1142 __I uint32_t INTSTAT; /*!< SPI Interrupt Status */
sahilmgandhi 18:6a4db94011d3 1143 } LPC_SPI0_Type;
sahilmgandhi 18:6a4db94011d3 1144
sahilmgandhi 18:6a4db94011d3 1145
sahilmgandhi 18:6a4db94011d3 1146 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1147 /* ================ I2C0 ================ */
sahilmgandhi 18:6a4db94011d3 1148 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1149
sahilmgandhi 18:6a4db94011d3 1150
sahilmgandhi 18:6a4db94011d3 1151 /**
sahilmgandhi 18:6a4db94011d3 1152 * @brief I2C-bus interface (I2C0)
sahilmgandhi 18:6a4db94011d3 1153 */
sahilmgandhi 18:6a4db94011d3 1154
sahilmgandhi 18:6a4db94011d3 1155 typedef struct { /*!< I2C0 Structure */
sahilmgandhi 18:6a4db94011d3 1156 __IO uint32_t CFG; /*!< Configuration for shared functions. */
sahilmgandhi 18:6a4db94011d3 1157 __IO uint32_t STAT; /*!< Status register for Master, Slave, and Monitor functions. */
sahilmgandhi 18:6a4db94011d3 1158 __IO uint32_t INTENSET; /*!< Interrupt Enable Set and read register. */
sahilmgandhi 18:6a4db94011d3 1159 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. */
sahilmgandhi 18:6a4db94011d3 1160 __IO uint32_t TIMEOUT; /*!< Time-out value register. */
sahilmgandhi 18:6a4db94011d3 1161 __IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
sahilmgandhi 18:6a4db94011d3 1162 what time increments are used for the MSTTIME and SLVTIME registers. */
sahilmgandhi 18:6a4db94011d3 1163 __I uint32_t INTSTAT; /*!< Interrupt Status register for Master, Slave, and Monitor functions. */
sahilmgandhi 18:6a4db94011d3 1164 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1165 __IO uint32_t MSTCTL; /*!< Master control register. */
sahilmgandhi 18:6a4db94011d3 1166 __IO uint32_t MSTTIME; /*!< Master timing configuration. */
sahilmgandhi 18:6a4db94011d3 1167 __IO uint32_t MSTDAT; /*!< Combined Master receiver and transmitter data register. */
sahilmgandhi 18:6a4db94011d3 1168 __I uint32_t RESERVED1[5];
sahilmgandhi 18:6a4db94011d3 1169 __IO uint32_t SLVCTL; /*!< Slave control register. */
sahilmgandhi 18:6a4db94011d3 1170 __IO uint32_t SLVDAT; /*!< Combined Slave receiver and transmitter data register. */
sahilmgandhi 18:6a4db94011d3 1171 __IO uint32_t SLVADR0; /*!< Slave address 0. */
sahilmgandhi 18:6a4db94011d3 1172 __IO uint32_t SLVADR1; /*!< Slave address 0. */
sahilmgandhi 18:6a4db94011d3 1173 __IO uint32_t SLVADR2; /*!< Slave address 0. */
sahilmgandhi 18:6a4db94011d3 1174 __IO uint32_t SLVADR3; /*!< Slave address 0. */
sahilmgandhi 18:6a4db94011d3 1175 __IO uint32_t SLVQUAL0; /*!< Slave Qualification for address 0. */
sahilmgandhi 18:6a4db94011d3 1176 __I uint32_t RESERVED2[9];
sahilmgandhi 18:6a4db94011d3 1177 __I uint32_t MONRXDAT; /*!< Monitor receiver data register. */
sahilmgandhi 18:6a4db94011d3 1178 } LPC_I2C0_Type;
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180
sahilmgandhi 18:6a4db94011d3 1181 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1182 /* ================ QEI ================ */
sahilmgandhi 18:6a4db94011d3 1183 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1184
sahilmgandhi 18:6a4db94011d3 1185
sahilmgandhi 18:6a4db94011d3 1186 /**
sahilmgandhi 18:6a4db94011d3 1187 * @brief Quadrature Encoder Interface (QEI) (QEI)
sahilmgandhi 18:6a4db94011d3 1188 */
sahilmgandhi 18:6a4db94011d3 1189
sahilmgandhi 18:6a4db94011d3 1190 typedef struct { /*!< QEI Structure */
sahilmgandhi 18:6a4db94011d3 1191 __O uint32_t CON; /*!< Control register */
sahilmgandhi 18:6a4db94011d3 1192 __I uint32_t STAT; /*!< Encoder status register */
sahilmgandhi 18:6a4db94011d3 1193 __IO uint32_t CONF; /*!< Configuration register */
sahilmgandhi 18:6a4db94011d3 1194 __I uint32_t POS; /*!< Position register */
sahilmgandhi 18:6a4db94011d3 1195 __IO uint32_t MAXPOS; /*!< Maximum position register */
sahilmgandhi 18:6a4db94011d3 1196 __IO uint32_t CMPOS0; /*!< position compare register 0 */
sahilmgandhi 18:6a4db94011d3 1197 __IO uint32_t CMPOS1; /*!< position compare register 1 */
sahilmgandhi 18:6a4db94011d3 1198 __IO uint32_t CMPOS2; /*!< position compare register 2 */
sahilmgandhi 18:6a4db94011d3 1199 __I uint32_t INXCNT; /*!< Index count register */
sahilmgandhi 18:6a4db94011d3 1200 __IO uint32_t INXCMP0; /*!< Index compare register 0 */
sahilmgandhi 18:6a4db94011d3 1201 __IO uint32_t LOAD; /*!< Velocity timer reload register */
sahilmgandhi 18:6a4db94011d3 1202 __I uint32_t TIME; /*!< Velocity timer register */
sahilmgandhi 18:6a4db94011d3 1203 __I uint32_t VEL; /*!< Velocity counter register */
sahilmgandhi 18:6a4db94011d3 1204 __I uint32_t CAP; /*!< Velocity capture register */
sahilmgandhi 18:6a4db94011d3 1205 __IO uint32_t VELCOMP; /*!< Velocity compare register */
sahilmgandhi 18:6a4db94011d3 1206 __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */
sahilmgandhi 18:6a4db94011d3 1207 __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */
sahilmgandhi 18:6a4db94011d3 1208 __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */
sahilmgandhi 18:6a4db94011d3 1209 __IO uint32_t WINDOW; /*!< Index acceptance window register */
sahilmgandhi 18:6a4db94011d3 1210 __IO uint32_t INXCMP1; /*!< Index compare register 1 */
sahilmgandhi 18:6a4db94011d3 1211 __IO uint32_t INXCMP2; /*!< Index compare register 2 */
sahilmgandhi 18:6a4db94011d3 1212 __I uint32_t RESERVED0[993];
sahilmgandhi 18:6a4db94011d3 1213 __O uint32_t IEC; /*!< Interrupt enable clear register */
sahilmgandhi 18:6a4db94011d3 1214 __O uint32_t IES; /*!< Interrupt enable set register */
sahilmgandhi 18:6a4db94011d3 1215 __I uint32_t INTSTAT; /*!< Interrupt status register */
sahilmgandhi 18:6a4db94011d3 1216 __O uint32_t IE; /*!< Interrupt enable clear register */
sahilmgandhi 18:6a4db94011d3 1217 __O uint32_t CLR; /*!< Interrupt status clear register */
sahilmgandhi 18:6a4db94011d3 1218 __O uint32_t SET; /*!< Interrupt status set register */
sahilmgandhi 18:6a4db94011d3 1219 } LPC_QEI_Type;
sahilmgandhi 18:6a4db94011d3 1220
sahilmgandhi 18:6a4db94011d3 1221
sahilmgandhi 18:6a4db94011d3 1222 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1223 /* ================ SYSCON ================ */
sahilmgandhi 18:6a4db94011d3 1224 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1225
sahilmgandhi 18:6a4db94011d3 1226
sahilmgandhi 18:6a4db94011d3 1227 /**
sahilmgandhi 18:6a4db94011d3 1228 * @brief System configuration (SYSCON) (SYSCON)
sahilmgandhi 18:6a4db94011d3 1229 */
sahilmgandhi 18:6a4db94011d3 1230
sahilmgandhi 18:6a4db94011d3 1231 typedef struct { /*!< SYSCON Structure */
sahilmgandhi 18:6a4db94011d3 1232 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
sahilmgandhi 18:6a4db94011d3 1233 __I uint32_t RESERVED0[4];
sahilmgandhi 18:6a4db94011d3 1234 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
sahilmgandhi 18:6a4db94011d3 1235 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 1236 __IO uint32_t NMISRC; /*!< NMI Source Control */
sahilmgandhi 18:6a4db94011d3 1237 __I uint32_t RESERVED2[8];
sahilmgandhi 18:6a4db94011d3 1238 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
sahilmgandhi 18:6a4db94011d3 1239 __IO uint32_t PRESETCTRL0; /*!< Peripheral reset control 0 */
sahilmgandhi 18:6a4db94011d3 1240 __IO uint32_t PRESETCTRL1; /*!< Peripheral reset control 1 */
sahilmgandhi 18:6a4db94011d3 1241 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
sahilmgandhi 18:6a4db94011d3 1242 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
sahilmgandhi 18:6a4db94011d3 1243 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 2 */
sahilmgandhi 18:6a4db94011d3 1244 __I uint32_t RESERVED3[10];
sahilmgandhi 18:6a4db94011d3 1245 __IO uint32_t MAINCLKSELA; /*!< Main clock source select A */
sahilmgandhi 18:6a4db94011d3 1246 __IO uint32_t MAINCLKSELB; /*!< Main clock source select B */
sahilmgandhi 18:6a4db94011d3 1247 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
sahilmgandhi 18:6a4db94011d3 1248 __IO uint32_t ADCASYNCCLKSEL; /*!< ADC asynchronous clock source select */
sahilmgandhi 18:6a4db94011d3 1249 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 1250 __IO uint32_t CLKOUTSELA; /*!< CLKOUT clock source select A */
sahilmgandhi 18:6a4db94011d3 1251 __IO uint32_t CLKOUTSELB; /*!< CLKOUT clock source select B */
sahilmgandhi 18:6a4db94011d3 1252 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 1253 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
sahilmgandhi 18:6a4db94011d3 1254 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
sahilmgandhi 18:6a4db94011d3 1255 __IO uint32_t SCTPLLCLKSEL; /*!< SCT PLL clock source select */
sahilmgandhi 18:6a4db94011d3 1256 __I uint32_t RESERVED6[5];
sahilmgandhi 18:6a4db94011d3 1257 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
sahilmgandhi 18:6a4db94011d3 1258 __IO uint32_t SYSAHBCLKCTRL0; /*!< System clock control 0 */
sahilmgandhi 18:6a4db94011d3 1259 __IO uint32_t SYSAHBCLKCTRL1; /*!< System clock control 1 */
sahilmgandhi 18:6a4db94011d3 1260 __IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider */
sahilmgandhi 18:6a4db94011d3 1261 __IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
sahilmgandhi 18:6a4db94011d3 1262 baud rate generator. */
sahilmgandhi 18:6a4db94011d3 1263 __IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
sahilmgandhi 18:6a4db94011d3 1264 filter */
sahilmgandhi 18:6a4db94011d3 1265 __IO uint32_t TRACECLKDIV; /*!< ARM trace clock divider */
sahilmgandhi 18:6a4db94011d3 1266 __I uint32_t RESERVED7[4];
sahilmgandhi 18:6a4db94011d3 1267 __IO uint32_t USBCLKDIV; /*!< USB clock divider */
sahilmgandhi 18:6a4db94011d3 1268 __IO uint32_t ADCASYNCCLKDIV; /*!< Asynchronous ADC clock divider */
sahilmgandhi 18:6a4db94011d3 1269 __I uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 1270 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
sahilmgandhi 18:6a4db94011d3 1271 __I uint32_t RESERVED9[11];
sahilmgandhi 18:6a4db94011d3 1272 __IO uint32_t FRGCTRL; /*!< USART fractional baud rate generator control */
sahilmgandhi 18:6a4db94011d3 1273 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
sahilmgandhi 18:6a4db94011d3 1274 __IO uint32_t USBCLKST; /*!< USB clock status */
sahilmgandhi 18:6a4db94011d3 1275 __I uint32_t RESERVED10[19];
sahilmgandhi 18:6a4db94011d3 1276 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
sahilmgandhi 18:6a4db94011d3 1277 __I uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 1278 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
sahilmgandhi 18:6a4db94011d3 1279 __I uint32_t RESERVED12;
sahilmgandhi 18:6a4db94011d3 1280 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator control */
sahilmgandhi 18:6a4db94011d3 1281 __I uint32_t RESERVED13;
sahilmgandhi 18:6a4db94011d3 1282 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
sahilmgandhi 18:6a4db94011d3 1283 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
sahilmgandhi 18:6a4db94011d3 1284 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
sahilmgandhi 18:6a4db94011d3 1285 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
sahilmgandhi 18:6a4db94011d3 1286 __IO uint32_t SCTPLLCTRL; /*!< SCT PLL control */
sahilmgandhi 18:6a4db94011d3 1287 __I uint32_t SCTPLLSTAT; /*!< SCT PLL status */
sahilmgandhi 18:6a4db94011d3 1288 __I uint32_t RESERVED14[21];
sahilmgandhi 18:6a4db94011d3 1289 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
sahilmgandhi 18:6a4db94011d3 1290 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
sahilmgandhi 18:6a4db94011d3 1291 __I uint32_t RESERVED15[3];
sahilmgandhi 18:6a4db94011d3 1292 __IO uint32_t STARTERP0; /*!< Start logic 0 wake-up enable register */
sahilmgandhi 18:6a4db94011d3 1293 __IO uint32_t STARTERP1; /*!< Start logic 1 wake-up enable register */
sahilmgandhi 18:6a4db94011d3 1294 } LPC_SYSCON_Type;
sahilmgandhi 18:6a4db94011d3 1295
sahilmgandhi 18:6a4db94011d3 1296
sahilmgandhi 18:6a4db94011d3 1297 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1298 /* ================ MRT ================ */
sahilmgandhi 18:6a4db94011d3 1299 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1300
sahilmgandhi 18:6a4db94011d3 1301
sahilmgandhi 18:6a4db94011d3 1302 /**
sahilmgandhi 18:6a4db94011d3 1303 * @brief Multi-Rate Timer (MRT) (MRT)
sahilmgandhi 18:6a4db94011d3 1304 */
sahilmgandhi 18:6a4db94011d3 1305
sahilmgandhi 18:6a4db94011d3 1306 typedef struct { /*!< MRT Structure */
sahilmgandhi 18:6a4db94011d3 1307 __IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
sahilmgandhi 18:6a4db94011d3 1308 the TIMER0 register. */
sahilmgandhi 18:6a4db94011d3 1309 __I uint32_t TIMER0; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
sahilmgandhi 18:6a4db94011d3 1310 __IO uint32_t CTRL0; /*!< MRT0 Control register. This register controls the MRT0 modes. */
sahilmgandhi 18:6a4db94011d3 1311 __IO uint32_t STAT0; /*!< MRT0 Status register. */
sahilmgandhi 18:6a4db94011d3 1312 __IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
sahilmgandhi 18:6a4db94011d3 1313 the TIMER0 register. */
sahilmgandhi 18:6a4db94011d3 1314 __I uint32_t TIMER1; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
sahilmgandhi 18:6a4db94011d3 1315 __IO uint32_t CTRL1; /*!< MRT0 Control register. This register controls the MRT0 modes. */
sahilmgandhi 18:6a4db94011d3 1316 __IO uint32_t STAT1; /*!< MRT0 Status register. */
sahilmgandhi 18:6a4db94011d3 1317 __IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
sahilmgandhi 18:6a4db94011d3 1318 the TIMER0 register. */
sahilmgandhi 18:6a4db94011d3 1319 __I uint32_t TIMER2; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
sahilmgandhi 18:6a4db94011d3 1320 __IO uint32_t CTRL2; /*!< MRT0 Control register. This register controls the MRT0 modes. */
sahilmgandhi 18:6a4db94011d3 1321 __IO uint32_t STAT2; /*!< MRT0 Status register. */
sahilmgandhi 18:6a4db94011d3 1322 __IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
sahilmgandhi 18:6a4db94011d3 1323 the TIMER0 register. */
sahilmgandhi 18:6a4db94011d3 1324 __I uint32_t TIMER3; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
sahilmgandhi 18:6a4db94011d3 1325 __IO uint32_t CTRL3; /*!< MRT0 Control register. This register controls the MRT0 modes. */
sahilmgandhi 18:6a4db94011d3 1326 __IO uint32_t STAT3; /*!< MRT0 Status register. */
sahilmgandhi 18:6a4db94011d3 1327 __I uint32_t RESERVED0[45];
sahilmgandhi 18:6a4db94011d3 1328 __I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
sahilmgandhi 18:6a4db94011d3 1329 first idle channel. */
sahilmgandhi 18:6a4db94011d3 1330 __IO uint32_t IRQ_FLAG; /*!< Global interrupt flag register */
sahilmgandhi 18:6a4db94011d3 1331 } LPC_MRT_Type;
sahilmgandhi 18:6a4db94011d3 1332
sahilmgandhi 18:6a4db94011d3 1333
sahilmgandhi 18:6a4db94011d3 1334 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1335 /* ================ PINT ================ */
sahilmgandhi 18:6a4db94011d3 1336 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1337
sahilmgandhi 18:6a4db94011d3 1338
sahilmgandhi 18:6a4db94011d3 1339 /**
sahilmgandhi 18:6a4db94011d3 1340 * @brief Pin interruptand pattern match (PINT) (PINT)
sahilmgandhi 18:6a4db94011d3 1341 */
sahilmgandhi 18:6a4db94011d3 1342
sahilmgandhi 18:6a4db94011d3 1343 typedef struct { /*!< PINT Structure */
sahilmgandhi 18:6a4db94011d3 1344 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
sahilmgandhi 18:6a4db94011d3 1345 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
sahilmgandhi 18:6a4db94011d3 1346 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
sahilmgandhi 18:6a4db94011d3 1347 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
sahilmgandhi 18:6a4db94011d3 1348 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
sahilmgandhi 18:6a4db94011d3 1349 register */
sahilmgandhi 18:6a4db94011d3 1350 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
sahilmgandhi 18:6a4db94011d3 1351 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
sahilmgandhi 18:6a4db94011d3 1352 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
sahilmgandhi 18:6a4db94011d3 1353 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
sahilmgandhi 18:6a4db94011d3 1354 __IO uint32_t IST; /*!< Pin interrupt status register */
sahilmgandhi 18:6a4db94011d3 1355 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
sahilmgandhi 18:6a4db94011d3 1356 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
sahilmgandhi 18:6a4db94011d3 1357 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
sahilmgandhi 18:6a4db94011d3 1358 } LPC_PINT_Type;
sahilmgandhi 18:6a4db94011d3 1359
sahilmgandhi 18:6a4db94011d3 1360
sahilmgandhi 18:6a4db94011d3 1361 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1362 /* ================ GINT0 ================ */
sahilmgandhi 18:6a4db94011d3 1363 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1364
sahilmgandhi 18:6a4db94011d3 1365
sahilmgandhi 18:6a4db94011d3 1366 /**
sahilmgandhi 18:6a4db94011d3 1367 * @brief Group interrupt 0/1 (GINT0/1) (GINT0)
sahilmgandhi 18:6a4db94011d3 1368 */
sahilmgandhi 18:6a4db94011d3 1369
sahilmgandhi 18:6a4db94011d3 1370 typedef struct { /*!< GINT0 Structure */
sahilmgandhi 18:6a4db94011d3 1371 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
sahilmgandhi 18:6a4db94011d3 1372 __I uint32_t RESERVED0[7];
sahilmgandhi 18:6a4db94011d3 1373 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
sahilmgandhi 18:6a4db94011d3 1374 __I uint32_t RESERVED1[5];
sahilmgandhi 18:6a4db94011d3 1375 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port 0 enable register */
sahilmgandhi 18:6a4db94011d3 1376 } LPC_GINT0_Type;
sahilmgandhi 18:6a4db94011d3 1377
sahilmgandhi 18:6a4db94011d3 1378
sahilmgandhi 18:6a4db94011d3 1379 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1380 /* ================ RIT ================ */
sahilmgandhi 18:6a4db94011d3 1381 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1382
sahilmgandhi 18:6a4db94011d3 1383
sahilmgandhi 18:6a4db94011d3 1384 /**
sahilmgandhi 18:6a4db94011d3 1385 * @brief Repetitive Interrupt Timer (RIT) (RIT)
sahilmgandhi 18:6a4db94011d3 1386 */
sahilmgandhi 18:6a4db94011d3 1387
sahilmgandhi 18:6a4db94011d3 1388 typedef struct { /*!< RIT Structure */
sahilmgandhi 18:6a4db94011d3 1389 __IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
sahilmgandhi 18:6a4db94011d3 1390 value. */
sahilmgandhi 18:6a4db94011d3 1391 __IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
sahilmgandhi 18:6a4db94011d3 1392 value. A 1 written to any bit will force a compare on the corresponding
sahilmgandhi 18:6a4db94011d3 1393 bit of the counter and compare register. */
sahilmgandhi 18:6a4db94011d3 1394 __IO uint32_t CTRL; /*!< Control register. */
sahilmgandhi 18:6a4db94011d3 1395 __IO uint32_t COUNTER; /*!< Counter LSB register. 32 LSBs of the counter. */
sahilmgandhi 18:6a4db94011d3 1396 __IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
sahilmgandhi 18:6a4db94011d3 1397 value. */
sahilmgandhi 18:6a4db94011d3 1398 __IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
sahilmgandhi 18:6a4db94011d3 1399 value. A 1 written to any bit will force a compare on the corresponding
sahilmgandhi 18:6a4db94011d3 1400 bit of the counter and compare register. */
sahilmgandhi 18:6a4db94011d3 1401 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1402 __IO uint32_t COUNTER_H; /*!< Counter MSB register. 16 MSBs of the counter. */
sahilmgandhi 18:6a4db94011d3 1403 } LPC_RIT_Type;
sahilmgandhi 18:6a4db94011d3 1404
sahilmgandhi 18:6a4db94011d3 1405
sahilmgandhi 18:6a4db94011d3 1406 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1407 /* ================ SCTIPU ================ */
sahilmgandhi 18:6a4db94011d3 1408 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1409
sahilmgandhi 18:6a4db94011d3 1410
sahilmgandhi 18:6a4db94011d3 1411 /**
sahilmgandhi 18:6a4db94011d3 1412 * @brief SCT Input Processing Unit (IPU) (SCTIPU)
sahilmgandhi 18:6a4db94011d3 1413 */
sahilmgandhi 18:6a4db94011d3 1414
sahilmgandhi 18:6a4db94011d3 1415 typedef struct { /*!< SCTIPU Structure */
sahilmgandhi 18:6a4db94011d3 1416 __IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
sahilmgandhi 18:6a4db94011d3 1417 latch/sample-enable mux selects, and sample overrride bits for
sahilmgandhi 18:6a4db94011d3 1418 the SAMPLE module. */
sahilmgandhi 18:6a4db94011d3 1419 __I uint32_t RESERVED0[7];
sahilmgandhi 18:6a4db94011d3 1420 __IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
sahilmgandhi 18:6a4db94011d3 1421 to ORed Abort Output 0. */
sahilmgandhi 18:6a4db94011d3 1422 __IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
sahilmgandhi 18:6a4db94011d3 1423 input source caused abort output 0. */
sahilmgandhi 18:6a4db94011d3 1424 __I uint32_t RESERVED1[6];
sahilmgandhi 18:6a4db94011d3 1425 __IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
sahilmgandhi 18:6a4db94011d3 1426 to ORed Abort Output 0. */
sahilmgandhi 18:6a4db94011d3 1427 __IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
sahilmgandhi 18:6a4db94011d3 1428 input source caused abort output 0. */
sahilmgandhi 18:6a4db94011d3 1429 __I uint32_t RESERVED2[6];
sahilmgandhi 18:6a4db94011d3 1430 __IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
sahilmgandhi 18:6a4db94011d3 1431 to ORed Abort Output 0. */
sahilmgandhi 18:6a4db94011d3 1432 __IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
sahilmgandhi 18:6a4db94011d3 1433 input source caused abort output 0. */
sahilmgandhi 18:6a4db94011d3 1434 __I uint32_t RESERVED3[6];
sahilmgandhi 18:6a4db94011d3 1435 __IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
sahilmgandhi 18:6a4db94011d3 1436 to ORed Abort Output 0. */
sahilmgandhi 18:6a4db94011d3 1437 __IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
sahilmgandhi 18:6a4db94011d3 1438 input source caused abort output 0. */
sahilmgandhi 18:6a4db94011d3 1439 } LPC_SCTIPU_Type;
sahilmgandhi 18:6a4db94011d3 1440
sahilmgandhi 18:6a4db94011d3 1441
sahilmgandhi 18:6a4db94011d3 1442 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1443 /* ================ FLASHCTRL ================ */
sahilmgandhi 18:6a4db94011d3 1444 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1445
sahilmgandhi 18:6a4db94011d3 1446
sahilmgandhi 18:6a4db94011d3 1447 /**
sahilmgandhi 18:6a4db94011d3 1448 * @brief Flash controller (FLASHCTRL)
sahilmgandhi 18:6a4db94011d3 1449 */
sahilmgandhi 18:6a4db94011d3 1450
sahilmgandhi 18:6a4db94011d3 1451 typedef struct { /*!< FLASHCTRL Structure */
sahilmgandhi 18:6a4db94011d3 1452 __I uint32_t RESERVED0[8];
sahilmgandhi 18:6a4db94011d3 1453 __IO uint32_t FMSSTART; /*!< Signature start address register */
sahilmgandhi 18:6a4db94011d3 1454 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
sahilmgandhi 18:6a4db94011d3 1455 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 1456 __I uint32_t FMSW0; /*!< Signature word */
sahilmgandhi 18:6a4db94011d3 1457 } LPC_FLASHCTRL_Type;
sahilmgandhi 18:6a4db94011d3 1458
sahilmgandhi 18:6a4db94011d3 1459
sahilmgandhi 18:6a4db94011d3 1460 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1461 /* ================ C_CAN0 ================ */
sahilmgandhi 18:6a4db94011d3 1462 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1463
sahilmgandhi 18:6a4db94011d3 1464
sahilmgandhi 18:6a4db94011d3 1465 /**
sahilmgandhi 18:6a4db94011d3 1466 * @brief Controller Area Network C_CAN0 (C_CAN0)
sahilmgandhi 18:6a4db94011d3 1467 */
sahilmgandhi 18:6a4db94011d3 1468
sahilmgandhi 18:6a4db94011d3 1469 typedef struct { /*!< C_CAN0 Structure */
sahilmgandhi 18:6a4db94011d3 1470 __IO uint32_t CANCNTL; /*!< CAN control */
sahilmgandhi 18:6a4db94011d3 1471 __IO uint32_t CANSTAT; /*!< Status register */
sahilmgandhi 18:6a4db94011d3 1472 __I uint32_t CANEC; /*!< Error counter */
sahilmgandhi 18:6a4db94011d3 1473 __IO uint32_t CANBT; /*!< Bit timing register */
sahilmgandhi 18:6a4db94011d3 1474 __I uint32_t CANINT; /*!< Interrupt register */
sahilmgandhi 18:6a4db94011d3 1475 __IO uint32_t CANTEST; /*!< Test register */
sahilmgandhi 18:6a4db94011d3 1476 __IO uint32_t CANBRPE; /*!< Baud rate prescaler extension register */
sahilmgandhi 18:6a4db94011d3 1477 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1478 __IO uint32_t CANIF1_CMDREQ; /*!< Message interface 1 command request */
sahilmgandhi 18:6a4db94011d3 1479
sahilmgandhi 18:6a4db94011d3 1480 union {
sahilmgandhi 18:6a4db94011d3 1481 __IO uint32_t CANIF1_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
sahilmgandhi 18:6a4db94011d3 1482 __IO uint32_t CANIF1_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
sahilmgandhi 18:6a4db94011d3 1483 };
sahilmgandhi 18:6a4db94011d3 1484 __IO uint32_t CANIF1_MSK1; /*!< Message interface 1 mask 1 */
sahilmgandhi 18:6a4db94011d3 1485 __IO uint32_t CANIF1_MSK2; /*!< Message interface 1 mask 2 */
sahilmgandhi 18:6a4db94011d3 1486 __IO uint32_t CANIF1_ARB1; /*!< Message interface 1 arbitration 1 */
sahilmgandhi 18:6a4db94011d3 1487 __IO uint32_t CANIF1_ARB2; /*!< Message interface 1 arbitration 2 */
sahilmgandhi 18:6a4db94011d3 1488 __IO uint32_t CANIF1_MCTRL; /*!< Message interface 1 message control */
sahilmgandhi 18:6a4db94011d3 1489 __IO uint32_t CANIF1_DA1; /*!< Message interface 1 data A1 */
sahilmgandhi 18:6a4db94011d3 1490 __IO uint32_t CANIF1_DA2; /*!< Message interface 1 data A2 */
sahilmgandhi 18:6a4db94011d3 1491 __IO uint32_t CANIF1_DB1; /*!< Message interface 1 data B1 */
sahilmgandhi 18:6a4db94011d3 1492 __IO uint32_t CANIF1_DB2; /*!< Message interface 1 data B2 */
sahilmgandhi 18:6a4db94011d3 1493 __I uint32_t RESERVED1[13];
sahilmgandhi 18:6a4db94011d3 1494 __IO uint32_t CANIF2_CMDREQ; /*!< Message interface 1 command request */
sahilmgandhi 18:6a4db94011d3 1495
sahilmgandhi 18:6a4db94011d3 1496 union {
sahilmgandhi 18:6a4db94011d3 1497 __IO uint32_t CANIF2_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
sahilmgandhi 18:6a4db94011d3 1498 __IO uint32_t CANIF2_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
sahilmgandhi 18:6a4db94011d3 1499 };
sahilmgandhi 18:6a4db94011d3 1500 __IO uint32_t CANIF2_MSK1; /*!< Message interface 1 mask 1 */
sahilmgandhi 18:6a4db94011d3 1501 __IO uint32_t CANIF2_MSK2; /*!< Message interface 1 mask 2 */
sahilmgandhi 18:6a4db94011d3 1502 __IO uint32_t CANIF2_ARB1; /*!< Message interface 1 arbitration 1 */
sahilmgandhi 18:6a4db94011d3 1503 __IO uint32_t CANIF2_ARB2; /*!< Message interface 1 arbitration 2 */
sahilmgandhi 18:6a4db94011d3 1504 __IO uint32_t CANIF2_MCTRL; /*!< Message interface 1 message control */
sahilmgandhi 18:6a4db94011d3 1505 __IO uint32_t CANIF2_DA1; /*!< Message interface 2 data A1 */
sahilmgandhi 18:6a4db94011d3 1506 __IO uint32_t CANIF2_DA2; /*!< Message interface 2 data A2 */
sahilmgandhi 18:6a4db94011d3 1507 __IO uint32_t CANIF2_DB1; /*!< Message interface 2 data B1 */
sahilmgandhi 18:6a4db94011d3 1508 __IO uint32_t CANIF2_DB2; /*!< Message interface 2 data B2 */
sahilmgandhi 18:6a4db94011d3 1509 __I uint32_t RESERVED2[21];
sahilmgandhi 18:6a4db94011d3 1510 __I uint32_t CANTXREQ1; /*!< Transmission request 1 */
sahilmgandhi 18:6a4db94011d3 1511 __I uint32_t CANTXREQ2; /*!< Transmission request 2 */
sahilmgandhi 18:6a4db94011d3 1512 __I uint32_t RESERVED3[6];
sahilmgandhi 18:6a4db94011d3 1513 __I uint32_t CANND1; /*!< New data 1 */
sahilmgandhi 18:6a4db94011d3 1514 __I uint32_t CANND2; /*!< New data 2 */
sahilmgandhi 18:6a4db94011d3 1515 __I uint32_t RESERVED4[6];
sahilmgandhi 18:6a4db94011d3 1516 __I uint32_t CANIR1; /*!< Interrupt pending 1 */
sahilmgandhi 18:6a4db94011d3 1517 __I uint32_t CANIR2; /*!< Interrupt pending 2 */
sahilmgandhi 18:6a4db94011d3 1518 __I uint32_t RESERVED5[6];
sahilmgandhi 18:6a4db94011d3 1519 __I uint32_t CANMSGV1; /*!< Message valid 1 */
sahilmgandhi 18:6a4db94011d3 1520 __I uint32_t CANMSGV2; /*!< Message valid 2 */
sahilmgandhi 18:6a4db94011d3 1521 __I uint32_t RESERVED6[6];
sahilmgandhi 18:6a4db94011d3 1522 __IO uint32_t CANCLKDIV; /*!< Can clock divider register */
sahilmgandhi 18:6a4db94011d3 1523 } LPC_C_CAN0_Type;
sahilmgandhi 18:6a4db94011d3 1524
sahilmgandhi 18:6a4db94011d3 1525
sahilmgandhi 18:6a4db94011d3 1526 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1527 /* ================ IOCON ================ */
sahilmgandhi 18:6a4db94011d3 1528 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1529
sahilmgandhi 18:6a4db94011d3 1530
sahilmgandhi 18:6a4db94011d3 1531 /**
sahilmgandhi 18:6a4db94011d3 1532 * @brief I/O pin configuration (IOCON) (IOCON)
sahilmgandhi 18:6a4db94011d3 1533 */
sahilmgandhi 18:6a4db94011d3 1534
sahilmgandhi 18:6a4db94011d3 1535 typedef struct { /*!< IOCON Structure */
sahilmgandhi 18:6a4db94011d3 1536 __IO uint32_t PIO0_0; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1537 __IO uint32_t PIO0_1; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1538 __IO uint32_t PIO0_2; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1539 __IO uint32_t PIO0_3; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1540 __IO uint32_t PIO0_4; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1541 __IO uint32_t PIO0_5; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1542 __IO uint32_t PIO0_6; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1543 __IO uint32_t PIO0_7; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1544 __IO uint32_t PIO0_8; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1545 __IO uint32_t PIO0_9; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1546 __IO uint32_t PIO0_10; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1547 __IO uint32_t PIO0_11; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1548 __IO uint32_t PIO0_12; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1549 __IO uint32_t PIO0_13; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1550 __IO uint32_t PIO0_14; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1551 __IO uint32_t PIO0_15; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1552 __IO uint32_t PIO0_16; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1553 __IO uint32_t PIO0_17; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1554 __IO uint32_t PIO0_18; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1555 __IO uint32_t PIO0_19; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1556 __IO uint32_t PIO0_20; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1557 __IO uint32_t PIO0_21; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
sahilmgandhi 18:6a4db94011d3 1558 __IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
sahilmgandhi 18:6a4db94011d3 1559 the I2C-bus SCL function. */
sahilmgandhi 18:6a4db94011d3 1560 __IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
sahilmgandhi 18:6a4db94011d3 1561 the I2C-bus SCL function. */
sahilmgandhi 18:6a4db94011d3 1562 __IO uint32_t PIO0_24; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
sahilmgandhi 18:6a4db94011d3 1563 __IO uint32_t PIO0_25; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
sahilmgandhi 18:6a4db94011d3 1564 __IO uint32_t PIO0_26; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
sahilmgandhi 18:6a4db94011d3 1565 __IO uint32_t PIO0_27; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
sahilmgandhi 18:6a4db94011d3 1566 __IO uint32_t PIO0_28; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
sahilmgandhi 18:6a4db94011d3 1567 __IO uint32_t PIO0_29; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
sahilmgandhi 18:6a4db94011d3 1568 __IO uint32_t PIO0_30; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
sahilmgandhi 18:6a4db94011d3 1569 __IO uint32_t PIO0_31; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
sahilmgandhi 18:6a4db94011d3 1570 __IO uint32_t PIO1_0; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1571 __IO uint32_t PIO1_1; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1572 __IO uint32_t PIO1_2; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1573 __IO uint32_t PIO1_3; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1574 __IO uint32_t PIO1_4; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1575 __IO uint32_t PIO1_5; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1576 __IO uint32_t PIO1_6; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1577 __IO uint32_t PIO1_7; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1578 __IO uint32_t PIO1_8; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1579 __IO uint32_t PIO1_9; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1580 __IO uint32_t PIO1_10; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1581 __IO uint32_t PIO1_11; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1582 __IO uint32_t PIO1_12; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1583 __IO uint32_t PIO1_13; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1584 __IO uint32_t PIO1_14; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1585 __IO uint32_t PIO1_15; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1586 __IO uint32_t PIO1_16; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1587 __IO uint32_t PIO1_17; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1588 __IO uint32_t PIO1_18; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1589 __IO uint32_t PIO1_19; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1590 __IO uint32_t PIO1_20; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1591 __IO uint32_t PIO1_21; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1592 __IO uint32_t PIO1_22; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1593 __IO uint32_t PIO1_23; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1594 __IO uint32_t PIO1_24; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1595 __IO uint32_t PIO1_25; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1596 __IO uint32_t PIO1_26; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1597 __IO uint32_t PIO1_27; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1598 __IO uint32_t PIO1_28; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1599 __IO uint32_t PIO1_29; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1600 __IO uint32_t PIO1_30; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1601 __IO uint32_t PIO1_31; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
sahilmgandhi 18:6a4db94011d3 1602 __IO uint32_t PIO2_0; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1603 __IO uint32_t PIO2_1; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1604 __IO uint32_t PIO2_2; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1605 __IO uint32_t PIO2_3; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1606 __IO uint32_t PIO2_4; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1607 __IO uint32_t PIO2_5; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1608 __IO uint32_t PIO2_6; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1609 __IO uint32_t PIO2_7; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1610 __IO uint32_t PIO2_8; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1611 __IO uint32_t PIO2_9; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1612 __IO uint32_t PIO2_10; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1613 __IO uint32_t PIO2_11; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
sahilmgandhi 18:6a4db94011d3 1614 } LPC_IOCON_Type;
sahilmgandhi 18:6a4db94011d3 1615
sahilmgandhi 18:6a4db94011d3 1616
sahilmgandhi 18:6a4db94011d3 1617 /* -------------------- End of section using anonymous unions ------------------- */
sahilmgandhi 18:6a4db94011d3 1618 #if defined(__CC_ARM)
sahilmgandhi 18:6a4db94011d3 1619 #pragma pop
sahilmgandhi 18:6a4db94011d3 1620 #elif defined(__ICCARM__)
sahilmgandhi 18:6a4db94011d3 1621 /* leave anonymous unions enabled */
sahilmgandhi 18:6a4db94011d3 1622 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 1623 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 1624 #elif defined(__TMS470__)
sahilmgandhi 18:6a4db94011d3 1625 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 1626 #elif defined(__TASKING__)
sahilmgandhi 18:6a4db94011d3 1627 #pragma warning restore
sahilmgandhi 18:6a4db94011d3 1628 #else
sahilmgandhi 18:6a4db94011d3 1629 #warning Not supported compiler type
sahilmgandhi 18:6a4db94011d3 1630 #endif
sahilmgandhi 18:6a4db94011d3 1631
sahilmgandhi 18:6a4db94011d3 1632
sahilmgandhi 18:6a4db94011d3 1633
sahilmgandhi 18:6a4db94011d3 1634
sahilmgandhi 18:6a4db94011d3 1635 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1636 /* ================ Peripheral memory map ================ */
sahilmgandhi 18:6a4db94011d3 1637 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1638
sahilmgandhi 18:6a4db94011d3 1639 #define LPC_GPIO_PORT_BASE 0x1C000000UL
sahilmgandhi 18:6a4db94011d3 1640 #define LPC_DMA_BASE 0x1C004000UL
sahilmgandhi 18:6a4db94011d3 1641 #define LPC_USB_BASE 0x1C00C000UL
sahilmgandhi 18:6a4db94011d3 1642 #define LPC_CRC_BASE 0x1C010000UL
sahilmgandhi 18:6a4db94011d3 1643 #define LPC_SCT0_BASE 0x1C018000UL
sahilmgandhi 18:6a4db94011d3 1644 #define LPC_SCT1_BASE 0x1C01C000UL
sahilmgandhi 18:6a4db94011d3 1645 #define LPC_SCT2_BASE 0x1C020000UL
sahilmgandhi 18:6a4db94011d3 1646 #define LPC_SCT3_BASE 0x1C024000UL
sahilmgandhi 18:6a4db94011d3 1647 #define LPC_ADC0_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1648 #define LPC_DAC_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1649 #define LPC_ACMP_BASE 0x40008000UL
sahilmgandhi 18:6a4db94011d3 1650 #define LPC_INMUX_BASE 0x40014000UL
sahilmgandhi 18:6a4db94011d3 1651 #define LPC_RTC_BASE 0x40028000UL
sahilmgandhi 18:6a4db94011d3 1652 #define LPC_WWDT_BASE 0x4002C000UL
sahilmgandhi 18:6a4db94011d3 1653 #define LPC_SWM_BASE 0x40038000UL
sahilmgandhi 18:6a4db94011d3 1654 #define LPC_PMU_BASE 0x4003C000UL
sahilmgandhi 18:6a4db94011d3 1655 #define LPC_USART0_BASE 0x40040000UL
sahilmgandhi 18:6a4db94011d3 1656 #define LPC_USART1_BASE 0x40044000UL
sahilmgandhi 18:6a4db94011d3 1657 #define LPC_SPI0_BASE 0x40048000UL
sahilmgandhi 18:6a4db94011d3 1658 #define LPC_SPI1_BASE 0x4004C000UL
sahilmgandhi 18:6a4db94011d3 1659 #define LPC_I2C0_BASE 0x40050000UL
sahilmgandhi 18:6a4db94011d3 1660 #define LPC_QEI_BASE 0x40058000UL
sahilmgandhi 18:6a4db94011d3 1661 #define LPC_SYSCON_BASE 0x40074000UL
sahilmgandhi 18:6a4db94011d3 1662 #define LPC_ADC1_BASE 0x40080000UL
sahilmgandhi 18:6a4db94011d3 1663 #define LPC_MRT_BASE 0x400A0000UL
sahilmgandhi 18:6a4db94011d3 1664 #define LPC_PINT_BASE 0x400A4000UL
sahilmgandhi 18:6a4db94011d3 1665 #define LPC_GINT0_BASE 0x400A8000UL
sahilmgandhi 18:6a4db94011d3 1666 #define LPC_GINT1_BASE 0x400AC000UL
sahilmgandhi 18:6a4db94011d3 1667 #define LPC_RIT_BASE 0x400B4000UL
sahilmgandhi 18:6a4db94011d3 1668 #define LPC_SCTIPU_BASE 0x400B8000UL
sahilmgandhi 18:6a4db94011d3 1669 #define LPC_FLASHCTRL_BASE 0x400BC000UL
sahilmgandhi 18:6a4db94011d3 1670 #define LPC_USART2_BASE 0x400C0000UL
sahilmgandhi 18:6a4db94011d3 1671 #define LPC_C_CAN0_BASE 0x400F0000UL
sahilmgandhi 18:6a4db94011d3 1672 #define LPC_IOCON_BASE 0x400F8000UL
sahilmgandhi 18:6a4db94011d3 1673
sahilmgandhi 18:6a4db94011d3 1674
sahilmgandhi 18:6a4db94011d3 1675 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1676 /* ================ Peripheral declaration ================ */
sahilmgandhi 18:6a4db94011d3 1677 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1678
sahilmgandhi 18:6a4db94011d3 1679 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
sahilmgandhi 18:6a4db94011d3 1680 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
sahilmgandhi 18:6a4db94011d3 1681 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
sahilmgandhi 18:6a4db94011d3 1682 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
sahilmgandhi 18:6a4db94011d3 1683 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
sahilmgandhi 18:6a4db94011d3 1684 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
sahilmgandhi 18:6a4db94011d3 1685 #define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
sahilmgandhi 18:6a4db94011d3 1686 #define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
sahilmgandhi 18:6a4db94011d3 1687 #define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
sahilmgandhi 18:6a4db94011d3 1688 #define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
sahilmgandhi 18:6a4db94011d3 1689 #define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
sahilmgandhi 18:6a4db94011d3 1690 #define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
sahilmgandhi 18:6a4db94011d3 1691 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
sahilmgandhi 18:6a4db94011d3 1692 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
sahilmgandhi 18:6a4db94011d3 1693 #define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
sahilmgandhi 18:6a4db94011d3 1694 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
sahilmgandhi 18:6a4db94011d3 1695 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
sahilmgandhi 18:6a4db94011d3 1696 #define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
sahilmgandhi 18:6a4db94011d3 1697 #define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
sahilmgandhi 18:6a4db94011d3 1698 #define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 1699 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
sahilmgandhi 18:6a4db94011d3 1700 #define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
sahilmgandhi 18:6a4db94011d3 1701 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
sahilmgandhi 18:6a4db94011d3 1702 #define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
sahilmgandhi 18:6a4db94011d3 1703 #define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
sahilmgandhi 18:6a4db94011d3 1704 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
sahilmgandhi 18:6a4db94011d3 1705 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
sahilmgandhi 18:6a4db94011d3 1706 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
sahilmgandhi 18:6a4db94011d3 1707 #define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
sahilmgandhi 18:6a4db94011d3 1708 #define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
sahilmgandhi 18:6a4db94011d3 1709 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
sahilmgandhi 18:6a4db94011d3 1710 #define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
sahilmgandhi 18:6a4db94011d3 1711 #define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
sahilmgandhi 18:6a4db94011d3 1712 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
sahilmgandhi 18:6a4db94011d3 1713
sahilmgandhi 18:6a4db94011d3 1714
sahilmgandhi 18:6a4db94011d3 1715 /** @} */ /* End of group Device_Peripheral_Registers */
sahilmgandhi 18:6a4db94011d3 1716 /** @} */ /* End of group LPC15xx */
sahilmgandhi 18:6a4db94011d3 1717 /** @} */ /* End of group (null) */
sahilmgandhi 18:6a4db94011d3 1718
sahilmgandhi 18:6a4db94011d3 1719 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1720 }
sahilmgandhi 18:6a4db94011d3 1721 #endif
sahilmgandhi 18:6a4db94011d3 1722
sahilmgandhi 18:6a4db94011d3 1723
sahilmgandhi 18:6a4db94011d3 1724 #endif /* LPC15XX_H */
sahilmgandhi 18:6a4db94011d3 1725