MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC15XX/analogin_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 17 #include "analogin_api.h"
sahilmgandhi 18:6a4db94011d3 18 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 19 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #define ANALOGIN_MEDIAN_FILTER 1
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 #define ADC_10BIT_RANGE 0x3FF
sahilmgandhi 18:6a4db94011d3 24 #define ADC_12BIT_RANGE 0xFFF
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #define ADC_RANGE ADC_12BIT_RANGE
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 static const PinMap PinMap_ADC[] = {
sahilmgandhi 18:6a4db94011d3 29 {P0_8 , ADC0_0, 0},
sahilmgandhi 18:6a4db94011d3 30 {P0_7 , ADC0_1, 0},
sahilmgandhi 18:6a4db94011d3 31 {P0_6 , ADC0_2, 0},
sahilmgandhi 18:6a4db94011d3 32 {P0_5 , ADC0_3, 0},
sahilmgandhi 18:6a4db94011d3 33 {P0_4 , ADC0_4, 0},
sahilmgandhi 18:6a4db94011d3 34 {P0_3 , ADC0_5, 0},
sahilmgandhi 18:6a4db94011d3 35 {P0_2 , ADC0_6, 0},
sahilmgandhi 18:6a4db94011d3 36 {P0_1 , ADC0_7, 0},
sahilmgandhi 18:6a4db94011d3 37 {P1_0 , ADC0_8, 0},
sahilmgandhi 18:6a4db94011d3 38 {P0_31, ADC0_9, 0},
sahilmgandhi 18:6a4db94011d3 39 {P0_0 , ADC0_10,0},
sahilmgandhi 18:6a4db94011d3 40 {P0_30, ADC0_11,0},
sahilmgandhi 18:6a4db94011d3 41 {P1_1 , ADC1_0, 0},
sahilmgandhi 18:6a4db94011d3 42 {P0_9 , ADC1_1, 0},
sahilmgandhi 18:6a4db94011d3 43 {P0_10, ADC1_2, 0},
sahilmgandhi 18:6a4db94011d3 44 {P0_11, ADC1_3, 0},
sahilmgandhi 18:6a4db94011d3 45 {P1_2 , ADC1_4, 0},
sahilmgandhi 18:6a4db94011d3 46 {P1_3 , ADC1_5, 0},
sahilmgandhi 18:6a4db94011d3 47 {P0_13, ADC1_6, 0},
sahilmgandhi 18:6a4db94011d3 48 {P0_14, ADC1_7, 0},
sahilmgandhi 18:6a4db94011d3 49 {P0_15, ADC1_8, 0},
sahilmgandhi 18:6a4db94011d3 50 {P0_16, ADC1_9, 0},
sahilmgandhi 18:6a4db94011d3 51 {P1_4 , ADC1_10,0},
sahilmgandhi 18:6a4db94011d3 52 {P1_5 , ADC1_11,0},
sahilmgandhi 18:6a4db94011d3 53 };
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 void analogin_init(analogin_t *obj, PinName pin) {
sahilmgandhi 18:6a4db94011d3 56 obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
sahilmgandhi 18:6a4db94011d3 57 MBED_ASSERT(obj->adc != (ADCName)NC);
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 uint32_t port = (pin >> 5);
sahilmgandhi 18:6a4db94011d3 60 // enable clock for GPIOx
sahilmgandhi 18:6a4db94011d3 61 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << (14 + port));
sahilmgandhi 18:6a4db94011d3 62 // pin enable
sahilmgandhi 18:6a4db94011d3 63 LPC_SWM->PINENABLE0 &= ~(1UL << obj->adc);
sahilmgandhi 18:6a4db94011d3 64 // configure GPIO as input
sahilmgandhi 18:6a4db94011d3 65 LPC_GPIO_PORT->DIR[port] &= ~(1UL << (pin & 0x1F));
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 // power up ADC
sahilmgandhi 18:6a4db94011d3 68 if (obj->adc < ADC1_0)
sahilmgandhi 18:6a4db94011d3 69 {
sahilmgandhi 18:6a4db94011d3 70 // ADC0
sahilmgandhi 18:6a4db94011d3 71 LPC_SYSCON->PDRUNCFG &= ~(1 << 10);
sahilmgandhi 18:6a4db94011d3 72 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 27);
sahilmgandhi 18:6a4db94011d3 73 }
sahilmgandhi 18:6a4db94011d3 74 else {
sahilmgandhi 18:6a4db94011d3 75 // ADC1
sahilmgandhi 18:6a4db94011d3 76 LPC_SYSCON->PDRUNCFG &= ~(1 << 11);
sahilmgandhi 18:6a4db94011d3 77 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28);
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 // determine the system clock divider for a 500kHz ADC clock during calibration
sahilmgandhi 18:6a4db94011d3 83 uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 // perform a self-calibration
sahilmgandhi 18:6a4db94011d3 86 adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF);
sahilmgandhi 18:6a4db94011d3 87 while ((adc_reg->CTRL & (1UL << 30)) != 0);
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 // Sampling clock: SystemClock divided by 1
sahilmgandhi 18:6a4db94011d3 90 adc_reg->CTRL = 0;
sahilmgandhi 18:6a4db94011d3 91 }
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 static inline uint32_t adc_read(analogin_t *obj) {
sahilmgandhi 18:6a4db94011d3 94 uint32_t channels;
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 if (obj->adc >= ADC1_0)
sahilmgandhi 18:6a4db94011d3 99 channels = ((obj->adc - ADC1_0) & 0x1F);
sahilmgandhi 18:6a4db94011d3 100 else
sahilmgandhi 18:6a4db94011d3 101 channels = (obj->adc & 0x1F);
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 // select channel
sahilmgandhi 18:6a4db94011d3 104 adc_reg->SEQA_CTRL &= ~(0xFFF);
sahilmgandhi 18:6a4db94011d3 105 adc_reg->SEQA_CTRL |= (1UL << channels);
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 // start conversion and sequence enable
sahilmgandhi 18:6a4db94011d3 108 adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31));
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 // Repeatedly get the sample data until DONE bit
sahilmgandhi 18:6a4db94011d3 111 volatile uint32_t data;
sahilmgandhi 18:6a4db94011d3 112 do {
sahilmgandhi 18:6a4db94011d3 113 data = adc_reg->SEQA_GDAT;
sahilmgandhi 18:6a4db94011d3 114 } while ((data & (1UL << 31)) == 0);
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 // Stop conversion
sahilmgandhi 18:6a4db94011d3 117 adc_reg->SEQA_CTRL &= ~(1UL << 31);
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 return ((data >> 4) & ADC_RANGE);
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 static inline void order(uint32_t *a, uint32_t *b) {
sahilmgandhi 18:6a4db94011d3 123 if (*a > *b) {
sahilmgandhi 18:6a4db94011d3 124 uint32_t t = *a;
sahilmgandhi 18:6a4db94011d3 125 *a = *b;
sahilmgandhi 18:6a4db94011d3 126 *b = t;
sahilmgandhi 18:6a4db94011d3 127 }
sahilmgandhi 18:6a4db94011d3 128 }
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 static inline uint32_t adc_read_u32(analogin_t *obj) {
sahilmgandhi 18:6a4db94011d3 131 uint32_t value;
sahilmgandhi 18:6a4db94011d3 132 #if ANALOGIN_MEDIAN_FILTER
sahilmgandhi 18:6a4db94011d3 133 uint32_t v1 = adc_read(obj);
sahilmgandhi 18:6a4db94011d3 134 uint32_t v2 = adc_read(obj);
sahilmgandhi 18:6a4db94011d3 135 uint32_t v3 = adc_read(obj);
sahilmgandhi 18:6a4db94011d3 136 order(&v1, &v2);
sahilmgandhi 18:6a4db94011d3 137 order(&v2, &v3);
sahilmgandhi 18:6a4db94011d3 138 order(&v1, &v2);
sahilmgandhi 18:6a4db94011d3 139 value = v2;
sahilmgandhi 18:6a4db94011d3 140 #else
sahilmgandhi 18:6a4db94011d3 141 value = adc_read(obj);
sahilmgandhi 18:6a4db94011d3 142 #endif
sahilmgandhi 18:6a4db94011d3 143 return value;
sahilmgandhi 18:6a4db94011d3 144 }
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 uint16_t analogin_read_u16(analogin_t *obj) {
sahilmgandhi 18:6a4db94011d3 147 uint32_t value = adc_read_u32(obj);
sahilmgandhi 18:6a4db94011d3 148 return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
sahilmgandhi 18:6a4db94011d3 149 }
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 float analogin_read(analogin_t *obj) {
sahilmgandhi 18:6a4db94011d3 152 uint32_t value = adc_read_u32(obj);
sahilmgandhi 18:6a4db94011d3 153 return (float)value * (1.0f / (float)ADC_RANGE);
sahilmgandhi 18:6a4db94011d3 154 }