MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC13XX/spi_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 17 #include <math.h>
sahilmgandhi 18:6a4db94011d3 18 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 19 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 20 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 21 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 static const PinMap PinMap_SPI_SCLK[] = {
sahilmgandhi 18:6a4db94011d3 24 {P0_6 , SPI_0, 0x02},
sahilmgandhi 18:6a4db94011d3 25 {P0_10, SPI_0, 0x02},
sahilmgandhi 18:6a4db94011d3 26 {P1_29, SPI_0, 0x01},
sahilmgandhi 18:6a4db94011d3 27 {P1_15, SPI_1, 0x03},
sahilmgandhi 18:6a4db94011d3 28 {P1_20, SPI_1, 0x02},
sahilmgandhi 18:6a4db94011d3 29 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 30 };
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 static const PinMap PinMap_SPI_MOSI[] = {
sahilmgandhi 18:6a4db94011d3 33 {P0_9 , SPI_0, 0x01},
sahilmgandhi 18:6a4db94011d3 34 {P0_21, SPI_1, 0x02},
sahilmgandhi 18:6a4db94011d3 35 {P1_22, SPI_1, 0x02},
sahilmgandhi 18:6a4db94011d3 36 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 37 };
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 static const PinMap PinMap_SPI_MISO[] = {
sahilmgandhi 18:6a4db94011d3 40 {P0_8 , SPI_0, 0x01},
sahilmgandhi 18:6a4db94011d3 41 {P0_22, SPI_1, 0x03},
sahilmgandhi 18:6a4db94011d3 42 {P1_21, SPI_1, 0x02},
sahilmgandhi 18:6a4db94011d3 43 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 44 };
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 static const PinMap PinMap_SPI_SSEL[] = {
sahilmgandhi 18:6a4db94011d3 47 {P0_2 , SPI_0, 0x01},
sahilmgandhi 18:6a4db94011d3 48 {P1_19, SPI_1, 0x02},
sahilmgandhi 18:6a4db94011d3 49 {P1_23, SPI_1, 0x02},
sahilmgandhi 18:6a4db94011d3 50 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 51 };
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 static inline int ssp_disable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 54 static inline int ssp_enable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
sahilmgandhi 18:6a4db94011d3 57 // determine the SPI to use
sahilmgandhi 18:6a4db94011d3 58 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 59 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 60 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 61 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 62 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
sahilmgandhi 18:6a4db94011d3 63 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
sahilmgandhi 18:6a4db94011d3 66 MBED_ASSERT((int)obj->spi != NC);
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 // enable power and clocking
sahilmgandhi 18:6a4db94011d3 69 switch ((int)obj->spi) {
sahilmgandhi 18:6a4db94011d3 70 case SPI_0:
sahilmgandhi 18:6a4db94011d3 71 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
sahilmgandhi 18:6a4db94011d3 72 LPC_SYSCON->SSP0CLKDIV = 0x01;
sahilmgandhi 18:6a4db94011d3 73 LPC_SYSCON->PRESETCTRL |= 1 << 0;
sahilmgandhi 18:6a4db94011d3 74 break;
sahilmgandhi 18:6a4db94011d3 75 case SPI_1:
sahilmgandhi 18:6a4db94011d3 76 LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
sahilmgandhi 18:6a4db94011d3 77 LPC_SYSCON->SSP1CLKDIV = 0x01;
sahilmgandhi 18:6a4db94011d3 78 LPC_SYSCON->PRESETCTRL |= 1 << 2;
sahilmgandhi 18:6a4db94011d3 79 break;
sahilmgandhi 18:6a4db94011d3 80 }
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 // pin out the spi pins
sahilmgandhi 18:6a4db94011d3 83 pinmap_pinout(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 84 pinmap_pinout(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 85 pinmap_pinout(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 86 if (ssel != NC) {
sahilmgandhi 18:6a4db94011d3 87 pinmap_pinout(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 88 }
sahilmgandhi 18:6a4db94011d3 89 }
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 void spi_free(spi_t *obj) {}
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 void spi_format(spi_t *obj, int bits, int mode, int slave) {
sahilmgandhi 18:6a4db94011d3 94 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 95 MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3));
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 int polarity = (mode & 0x2) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 98 int phase = (mode & 0x1) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 // set it up
sahilmgandhi 18:6a4db94011d3 101 int DSS = bits - 1; // DSS (data select size)
sahilmgandhi 18:6a4db94011d3 102 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
sahilmgandhi 18:6a4db94011d3 103 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 int FRF = 0; // FRF (frame format) = SPI
sahilmgandhi 18:6a4db94011d3 106 uint32_t tmp = obj->spi->CR0;
sahilmgandhi 18:6a4db94011d3 107 tmp &= ~(0xFFFF);
sahilmgandhi 18:6a4db94011d3 108 tmp |= DSS << 0
sahilmgandhi 18:6a4db94011d3 109 | FRF << 4
sahilmgandhi 18:6a4db94011d3 110 | SPO << 6
sahilmgandhi 18:6a4db94011d3 111 | SPH << 7;
sahilmgandhi 18:6a4db94011d3 112 obj->spi->CR0 = tmp;
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 tmp = obj->spi->CR1;
sahilmgandhi 18:6a4db94011d3 115 tmp &= ~(0xD);
sahilmgandhi 18:6a4db94011d3 116 tmp |= 0 << 0 // LBM - loop back mode - off
sahilmgandhi 18:6a4db94011d3 117 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
sahilmgandhi 18:6a4db94011d3 118 | 0 << 3; // SOD - slave output disable - na
sahilmgandhi 18:6a4db94011d3 119 obj->spi->CR1 = tmp;
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 122 }
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 void spi_frequency(spi_t *obj, int hz) {
sahilmgandhi 18:6a4db94011d3 125 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 uint32_t PCLK = SystemCoreClock;
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 int prescaler;
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
sahilmgandhi 18:6a4db94011d3 132 int prescale_hz = PCLK / prescaler;
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 // calculate the divider
sahilmgandhi 18:6a4db94011d3 135 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 // check we can support the divider
sahilmgandhi 18:6a4db94011d3 138 if (divider < 256) {
sahilmgandhi 18:6a4db94011d3 139 // prescaler
sahilmgandhi 18:6a4db94011d3 140 obj->spi->CPSR = prescaler;
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 // divider
sahilmgandhi 18:6a4db94011d3 143 obj->spi->CR0 &= ~(0xFFFF << 8);
sahilmgandhi 18:6a4db94011d3 144 obj->spi->CR0 |= (divider - 1) << 8;
sahilmgandhi 18:6a4db94011d3 145 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 146 return;
sahilmgandhi 18:6a4db94011d3 147 }
sahilmgandhi 18:6a4db94011d3 148 }
sahilmgandhi 18:6a4db94011d3 149 error("Couldn't setup requested SPI frequency");
sahilmgandhi 18:6a4db94011d3 150 }
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 static inline int ssp_disable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 153 return obj->spi->CR1 &= ~(1 << 1);
sahilmgandhi 18:6a4db94011d3 154 }
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 static inline int ssp_enable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 157 return obj->spi->CR1 |= (1 << 1);
sahilmgandhi 18:6a4db94011d3 158 }
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 static inline int ssp_readable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 161 return obj->spi->SR & (1 << 2);
sahilmgandhi 18:6a4db94011d3 162 }
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 static inline int ssp_writeable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 165 return obj->spi->SR & (1 << 1);
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 static inline void ssp_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 169 while (!ssp_writeable(obj));
sahilmgandhi 18:6a4db94011d3 170 obj->spi->DR = value;
sahilmgandhi 18:6a4db94011d3 171 }
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 static inline int ssp_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 174 while (!ssp_readable(obj));
sahilmgandhi 18:6a4db94011d3 175 return obj->spi->DR;
sahilmgandhi 18:6a4db94011d3 176 }
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 static inline int ssp_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 179 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 180 }
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 int spi_master_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 183 ssp_write(obj, value);
sahilmgandhi 18:6a4db94011d3 184 return ssp_read(obj);
sahilmgandhi 18:6a4db94011d3 185 }
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 int spi_slave_receive(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 188 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 189 }
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 int spi_slave_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 192 return obj->spi->DR;
sahilmgandhi 18:6a4db94011d3 193 }
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 void spi_slave_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 196 while (ssp_writeable(obj) == 0) ;
sahilmgandhi 18:6a4db94011d3 197 obj->spi->DR = value;
sahilmgandhi 18:6a4db94011d3 198 }
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 int spi_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 201 return ssp_busy(obj);
sahilmgandhi 18:6a4db94011d3 202 }