MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC13XX/device/LPC13Uxx.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1
sahilmgandhi 18:6a4db94011d3 2 /****************************************************************************************************//**
sahilmgandhi 18:6a4db94011d3 3 * @file LPC13Uxx.h
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
sahilmgandhi 18:6a4db94011d3 8 * default LPC13Uxx Device Series
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * @version V0.1
sahilmgandhi 18:6a4db94011d3 11 * @date 18. Jan 2012
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
sahilmgandhi 18:6a4db94011d3 16 * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 *******************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup NXP
sahilmgandhi 18:6a4db94011d3 21 * @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 /** @addtogroup LPC13Uxx
sahilmgandhi 18:6a4db94011d3 25 * @{
sahilmgandhi 18:6a4db94011d3 26 */
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 #ifndef __LPC13UXX_H__
sahilmgandhi 18:6a4db94011d3 29 #define __LPC13UXX_H__
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 32 extern "C" {
sahilmgandhi 18:6a4db94011d3 33 #endif
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 37 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 38 #endif
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 /* Interrupt Number Definition */
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 typedef enum {
sahilmgandhi 18:6a4db94011d3 43 // ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
sahilmgandhi 18:6a4db94011d3 44 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
sahilmgandhi 18:6a4db94011d3 45 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
sahilmgandhi 18:6a4db94011d3 46 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
sahilmgandhi 18:6a4db94011d3 47 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
sahilmgandhi 18:6a4db94011d3 48 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
sahilmgandhi 18:6a4db94011d3 49 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
sahilmgandhi 18:6a4db94011d3 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
sahilmgandhi 18:6a4db94011d3 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
sahilmgandhi 18:6a4db94011d3 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
sahilmgandhi 18:6a4db94011d3 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
sahilmgandhi 18:6a4db94011d3 54 // ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
sahilmgandhi 18:6a4db94011d3 55 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
sahilmgandhi 18:6a4db94011d3 56 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
sahilmgandhi 18:6a4db94011d3 57 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
sahilmgandhi 18:6a4db94011d3 58 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
sahilmgandhi 18:6a4db94011d3 59 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
sahilmgandhi 18:6a4db94011d3 60 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
sahilmgandhi 18:6a4db94011d3 61 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
sahilmgandhi 18:6a4db94011d3 62 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
sahilmgandhi 18:6a4db94011d3 63 GINT0_IRQn = 8, /*!< 8 GINT0 */
sahilmgandhi 18:6a4db94011d3 64 GINT1_IRQn = 9, /*!< 9 GINT1 */
sahilmgandhi 18:6a4db94011d3 65 Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
sahilmgandhi 18:6a4db94011d3 66 Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
sahilmgandhi 18:6a4db94011d3 67 RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
sahilmgandhi 18:6a4db94011d3 68 Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
sahilmgandhi 18:6a4db94011d3 69 SSP1_IRQn = 14, /*!< 14 SSP1 */
sahilmgandhi 18:6a4db94011d3 70 I2C_IRQn = 15, /*!< 15 I2C */
sahilmgandhi 18:6a4db94011d3 71 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
sahilmgandhi 18:6a4db94011d3 72 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
sahilmgandhi 18:6a4db94011d3 73 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
sahilmgandhi 18:6a4db94011d3 74 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
sahilmgandhi 18:6a4db94011d3 75 SSP0_IRQn = 20, /*!< 20 SSP0 */
sahilmgandhi 18:6a4db94011d3 76 USART_IRQn = 21, /*!< 21 USART */
sahilmgandhi 18:6a4db94011d3 77 USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
sahilmgandhi 18:6a4db94011d3 78 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
sahilmgandhi 18:6a4db94011d3 79 ADC_IRQn = 24, /*!< 24 ADC */
sahilmgandhi 18:6a4db94011d3 80 WDT_IRQn = 25, /*!< 25 WDT */
sahilmgandhi 18:6a4db94011d3 81 BOD_IRQn = 26, /*!< 26 BOD */
sahilmgandhi 18:6a4db94011d3 82 FMC_IRQn = 27, /*!< 27 FMC */
sahilmgandhi 18:6a4db94011d3 83 Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
sahilmgandhi 18:6a4db94011d3 84 Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
sahilmgandhi 18:6a4db94011d3 85 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
sahilmgandhi 18:6a4db94011d3 86 Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
sahilmgandhi 18:6a4db94011d3 87 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /** @addtogroup Configuration_of_CMSIS
sahilmgandhi 18:6a4db94011d3 91 * @{
sahilmgandhi 18:6a4db94011d3 92 */
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 #define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
sahilmgandhi 18:6a4db94011d3 97 #define __MPU_PRESENT 0 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 98 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 99 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 100 /** @} */ /* End of group Configuration_of_CMSIS */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 #include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 103 #include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /** @addtogroup Device_Peripheral_Registers
sahilmgandhi 18:6a4db94011d3 106 * @{
sahilmgandhi 18:6a4db94011d3 107 */
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 111 // ----- I2C -----
sahilmgandhi 18:6a4db94011d3 112 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 typedef struct { /*!< (@ 0x40000000) I2C Structure */
sahilmgandhi 18:6a4db94011d3 117 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
sahilmgandhi 18:6a4db94011d3 118 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
sahilmgandhi 18:6a4db94011d3 119 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
sahilmgandhi 18:6a4db94011d3 120 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 121 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
sahilmgandhi 18:6a4db94011d3 122 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
sahilmgandhi 18:6a4db94011d3 123 __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
sahilmgandhi 18:6a4db94011d3 124 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
sahilmgandhi 18:6a4db94011d3 125 union{
sahilmgandhi 18:6a4db94011d3 126 __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 127 struct{
sahilmgandhi 18:6a4db94011d3 128 __IO uint32_t ADR1;
sahilmgandhi 18:6a4db94011d3 129 __IO uint32_t ADR2;
sahilmgandhi 18:6a4db94011d3 130 __IO uint32_t ADR3;
sahilmgandhi 18:6a4db94011d3 131 };
sahilmgandhi 18:6a4db94011d3 132 };
sahilmgandhi 18:6a4db94011d3 133 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
sahilmgandhi 18:6a4db94011d3 134 union{
sahilmgandhi 18:6a4db94011d3 135 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
sahilmgandhi 18:6a4db94011d3 136 struct{
sahilmgandhi 18:6a4db94011d3 137 __IO uint32_t MASK0;
sahilmgandhi 18:6a4db94011d3 138 __IO uint32_t MASK1;
sahilmgandhi 18:6a4db94011d3 139 __IO uint32_t MASK2;
sahilmgandhi 18:6a4db94011d3 140 __IO uint32_t MASK3;
sahilmgandhi 18:6a4db94011d3 141 };
sahilmgandhi 18:6a4db94011d3 142 };
sahilmgandhi 18:6a4db94011d3 143 } LPC_I2C_Type;
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 147 // ----- WWDT -----
sahilmgandhi 18:6a4db94011d3 148 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
sahilmgandhi 18:6a4db94011d3 152 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
sahilmgandhi 18:6a4db94011d3 153 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
sahilmgandhi 18:6a4db94011d3 154 __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
sahilmgandhi 18:6a4db94011d3 155 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
sahilmgandhi 18:6a4db94011d3 156 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
sahilmgandhi 18:6a4db94011d3 157 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
sahilmgandhi 18:6a4db94011d3 158 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
sahilmgandhi 18:6a4db94011d3 159 } LPC_WWDT_Type;
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 163 // ----- USART -----
sahilmgandhi 18:6a4db94011d3 164 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 typedef struct { /*!< (@ 0x40008000) USART Structure */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 union {
sahilmgandhi 18:6a4db94011d3 170 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
sahilmgandhi 18:6a4db94011d3 171 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
sahilmgandhi 18:6a4db94011d3 172 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
sahilmgandhi 18:6a4db94011d3 173 };
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 union {
sahilmgandhi 18:6a4db94011d3 176 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
sahilmgandhi 18:6a4db94011d3 177 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
sahilmgandhi 18:6a4db94011d3 178 };
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 union {
sahilmgandhi 18:6a4db94011d3 181 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
sahilmgandhi 18:6a4db94011d3 182 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
sahilmgandhi 18:6a4db94011d3 183 };
sahilmgandhi 18:6a4db94011d3 184 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
sahilmgandhi 18:6a4db94011d3 185 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
sahilmgandhi 18:6a4db94011d3 186 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
sahilmgandhi 18:6a4db94011d3 187 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
sahilmgandhi 18:6a4db94011d3 188 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
sahilmgandhi 18:6a4db94011d3 189 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
sahilmgandhi 18:6a4db94011d3 190 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
sahilmgandhi 18:6a4db94011d3 191 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
sahilmgandhi 18:6a4db94011d3 192 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
sahilmgandhi 18:6a4db94011d3 193 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
sahilmgandhi 18:6a4db94011d3 194 __I uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 195 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
sahilmgandhi 18:6a4db94011d3 196 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 197 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
sahilmgandhi 18:6a4db94011d3 198 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
sahilmgandhi 18:6a4db94011d3 199 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
sahilmgandhi 18:6a4db94011d3 200 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
sahilmgandhi 18:6a4db94011d3 201 __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
sahilmgandhi 18:6a4db94011d3 202 } LPC_USART_Type;
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 206 // ----- CT16B0 -----
sahilmgandhi 18:6a4db94011d3 207 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
sahilmgandhi 18:6a4db94011d3 210 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
sahilmgandhi 18:6a4db94011d3 212 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
sahilmgandhi 18:6a4db94011d3 213 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
sahilmgandhi 18:6a4db94011d3 214 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
sahilmgandhi 18:6a4db94011d3 215 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
sahilmgandhi 18:6a4db94011d3 216 union {
sahilmgandhi 18:6a4db94011d3 217 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
sahilmgandhi 18:6a4db94011d3 218 struct{
sahilmgandhi 18:6a4db94011d3 219 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
sahilmgandhi 18:6a4db94011d3 220 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
sahilmgandhi 18:6a4db94011d3 221 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
sahilmgandhi 18:6a4db94011d3 222 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
sahilmgandhi 18:6a4db94011d3 223 };
sahilmgandhi 18:6a4db94011d3 224 };
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
sahilmgandhi 18:6a4db94011d3 226 union{
sahilmgandhi 18:6a4db94011d3 227 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
sahilmgandhi 18:6a4db94011d3 228 struct{
sahilmgandhi 18:6a4db94011d3 229 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
sahilmgandhi 18:6a4db94011d3 230 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
sahilmgandhi 18:6a4db94011d3 231 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
sahilmgandhi 18:6a4db94011d3 232 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
sahilmgandhi 18:6a4db94011d3 233 };
sahilmgandhi 18:6a4db94011d3 234 };
sahilmgandhi 18:6a4db94011d3 235 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
sahilmgandhi 18:6a4db94011d3 236 __I uint32_t RESERVED0[12];
sahilmgandhi 18:6a4db94011d3 237 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
sahilmgandhi 18:6a4db94011d3 238 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
sahilmgandhi 18:6a4db94011d3 239 } LPC_CTxxBx_Type;
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
sahilmgandhi 18:6a4db94011d3 242 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
sahilmgandhi 18:6a4db94011d3 243 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
sahilmgandhi 18:6a4db94011d3 244 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
sahilmgandhi 18:6a4db94011d3 245 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
sahilmgandhi 18:6a4db94011d3 246 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
sahilmgandhi 18:6a4db94011d3 247 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
sahilmgandhi 18:6a4db94011d3 248 union {
sahilmgandhi 18:6a4db94011d3 249 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
sahilmgandhi 18:6a4db94011d3 250 struct{
sahilmgandhi 18:6a4db94011d3 251 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
sahilmgandhi 18:6a4db94011d3 252 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
sahilmgandhi 18:6a4db94011d3 253 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
sahilmgandhi 18:6a4db94011d3 254 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
sahilmgandhi 18:6a4db94011d3 255 };
sahilmgandhi 18:6a4db94011d3 256 };
sahilmgandhi 18:6a4db94011d3 257 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
sahilmgandhi 18:6a4db94011d3 258 union{
sahilmgandhi 18:6a4db94011d3 259 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
sahilmgandhi 18:6a4db94011d3 260 struct{
sahilmgandhi 18:6a4db94011d3 261 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
sahilmgandhi 18:6a4db94011d3 262 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
sahilmgandhi 18:6a4db94011d3 263 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
sahilmgandhi 18:6a4db94011d3 264 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
sahilmgandhi 18:6a4db94011d3 265 };
sahilmgandhi 18:6a4db94011d3 266 };
sahilmgandhi 18:6a4db94011d3 267 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
sahilmgandhi 18:6a4db94011d3 268 __I uint32_t RESERVED0[12];
sahilmgandhi 18:6a4db94011d3 269 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
sahilmgandhi 18:6a4db94011d3 270 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
sahilmgandhi 18:6a4db94011d3 271 } LPC_CT16B0_Type;
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 275 // ----- CT16B1 -----
sahilmgandhi 18:6a4db94011d3 276 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
sahilmgandhi 18:6a4db94011d3 280 __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
sahilmgandhi 18:6a4db94011d3 281 __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
sahilmgandhi 18:6a4db94011d3 282 __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
sahilmgandhi 18:6a4db94011d3 283 __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
sahilmgandhi 18:6a4db94011d3 284 __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
sahilmgandhi 18:6a4db94011d3 285 union {
sahilmgandhi 18:6a4db94011d3 286 __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
sahilmgandhi 18:6a4db94011d3 287 struct{
sahilmgandhi 18:6a4db94011d3 288 __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
sahilmgandhi 18:6a4db94011d3 289 __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
sahilmgandhi 18:6a4db94011d3 290 __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
sahilmgandhi 18:6a4db94011d3 291 __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
sahilmgandhi 18:6a4db94011d3 292 };
sahilmgandhi 18:6a4db94011d3 293 };
sahilmgandhi 18:6a4db94011d3 294 __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
sahilmgandhi 18:6a4db94011d3 295 union{
sahilmgandhi 18:6a4db94011d3 296 __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
sahilmgandhi 18:6a4db94011d3 297 struct{
sahilmgandhi 18:6a4db94011d3 298 __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
sahilmgandhi 18:6a4db94011d3 299 __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
sahilmgandhi 18:6a4db94011d3 300 __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
sahilmgandhi 18:6a4db94011d3 301 __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
sahilmgandhi 18:6a4db94011d3 302 };
sahilmgandhi 18:6a4db94011d3 303 };
sahilmgandhi 18:6a4db94011d3 304 __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
sahilmgandhi 18:6a4db94011d3 305 __I uint32_t RESERVED0[12];
sahilmgandhi 18:6a4db94011d3 306 __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
sahilmgandhi 18:6a4db94011d3 307 __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
sahilmgandhi 18:6a4db94011d3 308 } LPC_CT16B1_Type;
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 312 // ----- CT32B0 -----
sahilmgandhi 18:6a4db94011d3 313 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 314 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
sahilmgandhi 18:6a4db94011d3 315 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
sahilmgandhi 18:6a4db94011d3 316 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
sahilmgandhi 18:6a4db94011d3 317 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
sahilmgandhi 18:6a4db94011d3 318 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
sahilmgandhi 18:6a4db94011d3 319 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
sahilmgandhi 18:6a4db94011d3 320 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
sahilmgandhi 18:6a4db94011d3 321 union {
sahilmgandhi 18:6a4db94011d3 322 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
sahilmgandhi 18:6a4db94011d3 323 struct{
sahilmgandhi 18:6a4db94011d3 324 __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
sahilmgandhi 18:6a4db94011d3 325 __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
sahilmgandhi 18:6a4db94011d3 326 __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
sahilmgandhi 18:6a4db94011d3 327 __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
sahilmgandhi 18:6a4db94011d3 328 };
sahilmgandhi 18:6a4db94011d3 329 };
sahilmgandhi 18:6a4db94011d3 330 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
sahilmgandhi 18:6a4db94011d3 331 union{
sahilmgandhi 18:6a4db94011d3 332 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
sahilmgandhi 18:6a4db94011d3 333 struct{
sahilmgandhi 18:6a4db94011d3 334 __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
sahilmgandhi 18:6a4db94011d3 335 __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
sahilmgandhi 18:6a4db94011d3 336 __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
sahilmgandhi 18:6a4db94011d3 337 __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
sahilmgandhi 18:6a4db94011d3 338 };
sahilmgandhi 18:6a4db94011d3 339 };
sahilmgandhi 18:6a4db94011d3 340 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
sahilmgandhi 18:6a4db94011d3 341 __I uint32_t RESERVED0[12];
sahilmgandhi 18:6a4db94011d3 342 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
sahilmgandhi 18:6a4db94011d3 343 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
sahilmgandhi 18:6a4db94011d3 344 } LPC_CT32B0_Type;
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 348 // ----- CT32B1 -----
sahilmgandhi 18:6a4db94011d3 349 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 350 typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
sahilmgandhi 18:6a4db94011d3 351 __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
sahilmgandhi 18:6a4db94011d3 352 __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
sahilmgandhi 18:6a4db94011d3 353 __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
sahilmgandhi 18:6a4db94011d3 354 __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
sahilmgandhi 18:6a4db94011d3 355 __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
sahilmgandhi 18:6a4db94011d3 356 __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
sahilmgandhi 18:6a4db94011d3 357 union {
sahilmgandhi 18:6a4db94011d3 358 __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
sahilmgandhi 18:6a4db94011d3 359 struct{
sahilmgandhi 18:6a4db94011d3 360 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
sahilmgandhi 18:6a4db94011d3 364 };
sahilmgandhi 18:6a4db94011d3 365 };
sahilmgandhi 18:6a4db94011d3 366 __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
sahilmgandhi 18:6a4db94011d3 367 union{
sahilmgandhi 18:6a4db94011d3 368 __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
sahilmgandhi 18:6a4db94011d3 369 struct{
sahilmgandhi 18:6a4db94011d3 370 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
sahilmgandhi 18:6a4db94011d3 371 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
sahilmgandhi 18:6a4db94011d3 372 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
sahilmgandhi 18:6a4db94011d3 373 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
sahilmgandhi 18:6a4db94011d3 374 };
sahilmgandhi 18:6a4db94011d3 375 };
sahilmgandhi 18:6a4db94011d3 376 __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
sahilmgandhi 18:6a4db94011d3 377 __I uint32_t RESERVED0[12];
sahilmgandhi 18:6a4db94011d3 378 __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
sahilmgandhi 18:6a4db94011d3 379 __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
sahilmgandhi 18:6a4db94011d3 380 } LPC_CT32B1_Type;
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382
sahilmgandhi 18:6a4db94011d3 383 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 384 // ----- ADC -----
sahilmgandhi 18:6a4db94011d3 385 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 386 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
sahilmgandhi 18:6a4db94011d3 387 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
sahilmgandhi 18:6a4db94011d3 388 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
sahilmgandhi 18:6a4db94011d3 389 __I uint32_t RESERVED0[1];
sahilmgandhi 18:6a4db94011d3 390 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
sahilmgandhi 18:6a4db94011d3 391 union{
sahilmgandhi 18:6a4db94011d3 392 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
sahilmgandhi 18:6a4db94011d3 393 struct{
sahilmgandhi 18:6a4db94011d3 394 __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
sahilmgandhi 18:6a4db94011d3 395 __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
sahilmgandhi 18:6a4db94011d3 396 __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
sahilmgandhi 18:6a4db94011d3 397 __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
sahilmgandhi 18:6a4db94011d3 398 __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
sahilmgandhi 18:6a4db94011d3 399 __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
sahilmgandhi 18:6a4db94011d3 400 __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
sahilmgandhi 18:6a4db94011d3 401 __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
sahilmgandhi 18:6a4db94011d3 402 };
sahilmgandhi 18:6a4db94011d3 403 };
sahilmgandhi 18:6a4db94011d3 404 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
sahilmgandhi 18:6a4db94011d3 405 } LPC_ADC_Type;
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 409 // ----- PMU -----
sahilmgandhi 18:6a4db94011d3 410 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 typedef struct { /*!< (@ 0x40038000) PMU Structure */
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
sahilmgandhi 18:6a4db94011d3 414 union{
sahilmgandhi 18:6a4db94011d3 415 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 416 struct{
sahilmgandhi 18:6a4db94011d3 417 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 418 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
sahilmgandhi 18:6a4db94011d3 419 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
sahilmgandhi 18:6a4db94011d3 420 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
sahilmgandhi 18:6a4db94011d3 421 };
sahilmgandhi 18:6a4db94011d3 422 };
sahilmgandhi 18:6a4db94011d3 423 __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
sahilmgandhi 18:6a4db94011d3 424 } LPC_PMU_Type;
sahilmgandhi 18:6a4db94011d3 425
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 428 // ----- FLASHCTRL -----
sahilmgandhi 18:6a4db94011d3 429 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 430
sahilmgandhi 18:6a4db94011d3 431 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
sahilmgandhi 18:6a4db94011d3 432 __I uint32_t RESERVED0[4];
sahilmgandhi 18:6a4db94011d3 433 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
sahilmgandhi 18:6a4db94011d3 434 __I uint32_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 435 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
sahilmgandhi 18:6a4db94011d3 436 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
sahilmgandhi 18:6a4db94011d3 437 __I uint32_t RESERVED2[1];
sahilmgandhi 18:6a4db94011d3 438 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
sahilmgandhi 18:6a4db94011d3 439 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
sahilmgandhi 18:6a4db94011d3 440 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
sahilmgandhi 18:6a4db94011d3 441 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
sahilmgandhi 18:6a4db94011d3 442 __I uint32_t RESERVED3[1001];
sahilmgandhi 18:6a4db94011d3 443 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
sahilmgandhi 18:6a4db94011d3 444 __I uint32_t RESERVED4[1];
sahilmgandhi 18:6a4db94011d3 445 __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
sahilmgandhi 18:6a4db94011d3 446 } LPC_FLASHCTRL_Type;
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 450 // ----- SSP -----
sahilmgandhi 18:6a4db94011d3 451 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 452 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
sahilmgandhi 18:6a4db94011d3 453 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
sahilmgandhi 18:6a4db94011d3 454 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
sahilmgandhi 18:6a4db94011d3 455 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
sahilmgandhi 18:6a4db94011d3 456 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
sahilmgandhi 18:6a4db94011d3 457 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
sahilmgandhi 18:6a4db94011d3 458 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
sahilmgandhi 18:6a4db94011d3 459 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 460 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 461 __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
sahilmgandhi 18:6a4db94011d3 462 } LPC_SSPx_Type;
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 466 // ----- IOCON -----
sahilmgandhi 18:6a4db94011d3 467 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 468 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
sahilmgandhi 18:6a4db94011d3 469 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
sahilmgandhi 18:6a4db94011d3 470 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
sahilmgandhi 18:6a4db94011d3 471 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
sahilmgandhi 18:6a4db94011d3 472 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
sahilmgandhi 18:6a4db94011d3 473 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
sahilmgandhi 18:6a4db94011d3 474 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
sahilmgandhi 18:6a4db94011d3 475 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
sahilmgandhi 18:6a4db94011d3 476 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
sahilmgandhi 18:6a4db94011d3 477 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
sahilmgandhi 18:6a4db94011d3 478 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
sahilmgandhi 18:6a4db94011d3 479 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
sahilmgandhi 18:6a4db94011d3 480 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
sahilmgandhi 18:6a4db94011d3 481 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
sahilmgandhi 18:6a4db94011d3 482 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
sahilmgandhi 18:6a4db94011d3 483 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
sahilmgandhi 18:6a4db94011d3 485 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
sahilmgandhi 18:6a4db94011d3 486 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
sahilmgandhi 18:6a4db94011d3 487 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
sahilmgandhi 18:6a4db94011d3 488 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
sahilmgandhi 18:6a4db94011d3 489 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
sahilmgandhi 18:6a4db94011d3 490 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
sahilmgandhi 18:6a4db94011d3 491 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
sahilmgandhi 18:6a4db94011d3 492 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
sahilmgandhi 18:6a4db94011d3 493 __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
sahilmgandhi 18:6a4db94011d3 495 __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
sahilmgandhi 18:6a4db94011d3 496 __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
sahilmgandhi 18:6a4db94011d3 497 __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
sahilmgandhi 18:6a4db94011d3 498 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
sahilmgandhi 18:6a4db94011d3 499 __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
sahilmgandhi 18:6a4db94011d3 500 __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
sahilmgandhi 18:6a4db94011d3 501 __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
sahilmgandhi 18:6a4db94011d3 502 __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
sahilmgandhi 18:6a4db94011d3 503 __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
sahilmgandhi 18:6a4db94011d3 504 __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
sahilmgandhi 18:6a4db94011d3 505 __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
sahilmgandhi 18:6a4db94011d3 506 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
sahilmgandhi 18:6a4db94011d3 507 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
sahilmgandhi 18:6a4db94011d3 508 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
sahilmgandhi 18:6a4db94011d3 509 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
sahilmgandhi 18:6a4db94011d3 510 __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
sahilmgandhi 18:6a4db94011d3 511 __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
sahilmgandhi 18:6a4db94011d3 512 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
sahilmgandhi 18:6a4db94011d3 513 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
sahilmgandhi 18:6a4db94011d3 514 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
sahilmgandhi 18:6a4db94011d3 515 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
sahilmgandhi 18:6a4db94011d3 516 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
sahilmgandhi 18:6a4db94011d3 517 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
sahilmgandhi 18:6a4db94011d3 518 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
sahilmgandhi 18:6a4db94011d3 519 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
sahilmgandhi 18:6a4db94011d3 520 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
sahilmgandhi 18:6a4db94011d3 521 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
sahilmgandhi 18:6a4db94011d3 522 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
sahilmgandhi 18:6a4db94011d3 523 __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
sahilmgandhi 18:6a4db94011d3 524 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
sahilmgandhi 18:6a4db94011d3 525 } LPC_IOCON_Type;
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527
sahilmgandhi 18:6a4db94011d3 528 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 529 // ----- SYSCON -----
sahilmgandhi 18:6a4db94011d3 530 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
sahilmgandhi 18:6a4db94011d3 533 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
sahilmgandhi 18:6a4db94011d3 534 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
sahilmgandhi 18:6a4db94011d3 535 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
sahilmgandhi 18:6a4db94011d3 536 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
sahilmgandhi 18:6a4db94011d3 537 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
sahilmgandhi 18:6a4db94011d3 538 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
sahilmgandhi 18:6a4db94011d3 539 __I uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 540 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
sahilmgandhi 18:6a4db94011d3 541 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
sahilmgandhi 18:6a4db94011d3 542 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 543 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
sahilmgandhi 18:6a4db94011d3 544 __I uint32_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 545 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
sahilmgandhi 18:6a4db94011d3 546 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 547 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
sahilmgandhi 18:6a4db94011d3 548 __I uint32_t RESERVED4[9];
sahilmgandhi 18:6a4db94011d3 549 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
sahilmgandhi 18:6a4db94011d3 550 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 551 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
sahilmgandhi 18:6a4db94011d3 552 __I uint32_t RESERVED6;
sahilmgandhi 18:6a4db94011d3 553 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
sahilmgandhi 18:6a4db94011d3 554 __I uint32_t RESERVED7[4];
sahilmgandhi 18:6a4db94011d3 555 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
sahilmgandhi 18:6a4db94011d3 556 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
sahilmgandhi 18:6a4db94011d3 557 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
sahilmgandhi 18:6a4db94011d3 558 __I uint32_t RESERVED8[3];
sahilmgandhi 18:6a4db94011d3 559 __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
sahilmgandhi 18:6a4db94011d3 560 __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
sahilmgandhi 18:6a4db94011d3 561 __I uint32_t RESERVED9[3];
sahilmgandhi 18:6a4db94011d3 562 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
sahilmgandhi 18:6a4db94011d3 563 __I uint32_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 564 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
sahilmgandhi 18:6a4db94011d3 565 __I uint32_t RESERVED11[5];
sahilmgandhi 18:6a4db94011d3 566 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
sahilmgandhi 18:6a4db94011d3 567 __I uint32_t RESERVED12;
sahilmgandhi 18:6a4db94011d3 568 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
sahilmgandhi 18:6a4db94011d3 569 __I uint32_t RESERVED13[5];
sahilmgandhi 18:6a4db94011d3 570 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
sahilmgandhi 18:6a4db94011d3 571 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
sahilmgandhi 18:6a4db94011d3 572 __I uint32_t RESERVED14[18];
sahilmgandhi 18:6a4db94011d3 573 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
sahilmgandhi 18:6a4db94011d3 574 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
sahilmgandhi 18:6a4db94011d3 575 __I uint32_t RESERVED15[6];
sahilmgandhi 18:6a4db94011d3 576 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
sahilmgandhi 18:6a4db94011d3 577 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
sahilmgandhi 18:6a4db94011d3 579 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
sahilmgandhi 18:6a4db94011d3 580 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
sahilmgandhi 18:6a4db94011d3 581 __I uint32_t RESERVED16[25];
sahilmgandhi 18:6a4db94011d3 582 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
sahilmgandhi 18:6a4db94011d3 583 __I uint32_t RESERVED17[3];
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
sahilmgandhi 18:6a4db94011d3 585 __I uint32_t RESERVED18[6];
sahilmgandhi 18:6a4db94011d3 586 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
sahilmgandhi 18:6a4db94011d3 588 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
sahilmgandhi 18:6a4db94011d3 589 __I uint32_t RESERVED19[111];
sahilmgandhi 18:6a4db94011d3 590 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
sahilmgandhi 18:6a4db94011d3 591 } LPC_SYSCON_Type;
sahilmgandhi 18:6a4db94011d3 592
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 595 // ----- GPIO_PIN_INT -----
sahilmgandhi 18:6a4db94011d3 596 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 597 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
sahilmgandhi 18:6a4db94011d3 598 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
sahilmgandhi 18:6a4db94011d3 599 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
sahilmgandhi 18:6a4db94011d3 600 __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
sahilmgandhi 18:6a4db94011d3 601 __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
sahilmgandhi 18:6a4db94011d3 602 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
sahilmgandhi 18:6a4db94011d3 603 __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
sahilmgandhi 18:6a4db94011d3 604 __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
sahilmgandhi 18:6a4db94011d3 605 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
sahilmgandhi 18:6a4db94011d3 606 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
sahilmgandhi 18:6a4db94011d3 607 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
sahilmgandhi 18:6a4db94011d3 608 } LPC_GPIO_PIN_INT_Type;
sahilmgandhi 18:6a4db94011d3 609
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 612 // ----- GPIO_GROUP_INT0 -----
sahilmgandhi 18:6a4db94011d3 613 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 614 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
sahilmgandhi 18:6a4db94011d3 615 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
sahilmgandhi 18:6a4db94011d3 616 __I uint32_t RESERVED0[7];
sahilmgandhi 18:6a4db94011d3 617 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
sahilmgandhi 18:6a4db94011d3 618 __I uint32_t RESERVED1[6];
sahilmgandhi 18:6a4db94011d3 619 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
sahilmgandhi 18:6a4db94011d3 620 } LPC_GPIO_GROUP_INT0_Type;
sahilmgandhi 18:6a4db94011d3 621
sahilmgandhi 18:6a4db94011d3 622
sahilmgandhi 18:6a4db94011d3 623 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 624 // ----- GPIO_GROUP_INT1 -----
sahilmgandhi 18:6a4db94011d3 625 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 626
sahilmgandhi 18:6a4db94011d3 627 typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
sahilmgandhi 18:6a4db94011d3 628 __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
sahilmgandhi 18:6a4db94011d3 629 __I uint32_t RESERVED0[7];
sahilmgandhi 18:6a4db94011d3 630 __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
sahilmgandhi 18:6a4db94011d3 631 __I uint32_t RESERVED1[6];
sahilmgandhi 18:6a4db94011d3 632 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
sahilmgandhi 18:6a4db94011d3 633 } LPC_GPIO_GROUP_INT1_Type;
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635
sahilmgandhi 18:6a4db94011d3 636 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 637 // ----- Repetitive Interrupt Timer (RIT) -----
sahilmgandhi 18:6a4db94011d3 638 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 639
sahilmgandhi 18:6a4db94011d3 640 typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
sahilmgandhi 18:6a4db94011d3 641 __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
sahilmgandhi 18:6a4db94011d3 642 __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
sahilmgandhi 18:6a4db94011d3 643 __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
sahilmgandhi 18:6a4db94011d3 644 __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
sahilmgandhi 18:6a4db94011d3 645 __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
sahilmgandhi 18:6a4db94011d3 646 __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
sahilmgandhi 18:6a4db94011d3 647 __I uint32_t RESERVED0[1];
sahilmgandhi 18:6a4db94011d3 648 __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
sahilmgandhi 18:6a4db94011d3 649 } LPC_RITIMER_Type;
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 653 // ----- USB -----
sahilmgandhi 18:6a4db94011d3 654 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 655 typedef struct { /*!< (@ 0x40020000) USB Structure */
sahilmgandhi 18:6a4db94011d3 656 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
sahilmgandhi 18:6a4db94011d3 657 __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
sahilmgandhi 18:6a4db94011d3 658 __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
sahilmgandhi 18:6a4db94011d3 659 __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
sahilmgandhi 18:6a4db94011d3 660 __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
sahilmgandhi 18:6a4db94011d3 661 __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
sahilmgandhi 18:6a4db94011d3 662 __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
sahilmgandhi 18:6a4db94011d3 663 __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
sahilmgandhi 18:6a4db94011d3 664 __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
sahilmgandhi 18:6a4db94011d3 665 __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
sahilmgandhi 18:6a4db94011d3 666 __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
sahilmgandhi 18:6a4db94011d3 667 __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
sahilmgandhi 18:6a4db94011d3 668 __I uint32_t RESERVED0[1];
sahilmgandhi 18:6a4db94011d3 669 __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
sahilmgandhi 18:6a4db94011d3 670 } LPC_USB_Type;
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 674 // ----- GPIO_PORT -----
sahilmgandhi 18:6a4db94011d3 675 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 676
sahilmgandhi 18:6a4db94011d3 677 typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
sahilmgandhi 18:6a4db94011d3 678 union {
sahilmgandhi 18:6a4db94011d3 679 struct {
sahilmgandhi 18:6a4db94011d3 680 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
sahilmgandhi 18:6a4db94011d3 681 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
sahilmgandhi 18:6a4db94011d3 682 };
sahilmgandhi 18:6a4db94011d3 683 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
sahilmgandhi 18:6a4db94011d3 684 };
sahilmgandhi 18:6a4db94011d3 685 __I uint32_t RESERVED0[1008];
sahilmgandhi 18:6a4db94011d3 686 union {
sahilmgandhi 18:6a4db94011d3 687 struct {
sahilmgandhi 18:6a4db94011d3 688 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
sahilmgandhi 18:6a4db94011d3 689 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
sahilmgandhi 18:6a4db94011d3 690 };
sahilmgandhi 18:6a4db94011d3 691 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
sahilmgandhi 18:6a4db94011d3 692 };
sahilmgandhi 18:6a4db94011d3 693 __I uint32_t RESERVED1[960];
sahilmgandhi 18:6a4db94011d3 694 __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
sahilmgandhi 18:6a4db94011d3 695 __I uint32_t RESERVED2[30];
sahilmgandhi 18:6a4db94011d3 696 __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
sahilmgandhi 18:6a4db94011d3 697 __I uint32_t RESERVED3[30];
sahilmgandhi 18:6a4db94011d3 698 __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
sahilmgandhi 18:6a4db94011d3 699 __I uint32_t RESERVED4[30];
sahilmgandhi 18:6a4db94011d3 700 __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
sahilmgandhi 18:6a4db94011d3 701 __I uint32_t RESERVED5[30];
sahilmgandhi 18:6a4db94011d3 702 __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
sahilmgandhi 18:6a4db94011d3 703 __I uint32_t RESERVED6[30];
sahilmgandhi 18:6a4db94011d3 704 __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
sahilmgandhi 18:6a4db94011d3 705 __I uint32_t RESERVED7[30];
sahilmgandhi 18:6a4db94011d3 706 __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
sahilmgandhi 18:6a4db94011d3 707 } LPC_GPIO_Type;
sahilmgandhi 18:6a4db94011d3 708
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 711 #pragma no_anon_unions
sahilmgandhi 18:6a4db94011d3 712 #endif
sahilmgandhi 18:6a4db94011d3 713
sahilmgandhi 18:6a4db94011d3 714
sahilmgandhi 18:6a4db94011d3 715 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 716 // ----- Peripheral memory map -----
sahilmgandhi 18:6a4db94011d3 717 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 718
sahilmgandhi 18:6a4db94011d3 719 #define LPC_I2C_BASE (0x40000000)
sahilmgandhi 18:6a4db94011d3 720 #define LPC_WWDT_BASE (0x40004000)
sahilmgandhi 18:6a4db94011d3 721 #define LPC_USART_BASE (0x40008000)
sahilmgandhi 18:6a4db94011d3 722 #define LPC_CT16B0_BASE (0x4000C000)
sahilmgandhi 18:6a4db94011d3 723 #define LPC_CT16B1_BASE (0x40010000)
sahilmgandhi 18:6a4db94011d3 724 #define LPC_CT32B0_BASE (0x40014000)
sahilmgandhi 18:6a4db94011d3 725 #define LPC_CT32B1_BASE (0x40018000)
sahilmgandhi 18:6a4db94011d3 726 #define LPC_ADC_BASE (0x4001C000)
sahilmgandhi 18:6a4db94011d3 727 #define LPC_PMU_BASE (0x40038000)
sahilmgandhi 18:6a4db94011d3 728 #define LPC_FLASHCTRL_BASE (0x4003C000)
sahilmgandhi 18:6a4db94011d3 729 #define LPC_SSP0_BASE (0x40040000)
sahilmgandhi 18:6a4db94011d3 730 #define LPC_IOCON_BASE (0x40044000)
sahilmgandhi 18:6a4db94011d3 731 #define LPC_SYSCON_BASE (0x40048000)
sahilmgandhi 18:6a4db94011d3 732 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
sahilmgandhi 18:6a4db94011d3 733 #define LPC_SSP1_BASE (0x40058000)
sahilmgandhi 18:6a4db94011d3 734 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
sahilmgandhi 18:6a4db94011d3 735 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
sahilmgandhi 18:6a4db94011d3 736 #define LPC_RITIMER_BASE (0x40064000)
sahilmgandhi 18:6a4db94011d3 737 #define LPC_USB_BASE (0x40080000)
sahilmgandhi 18:6a4db94011d3 738 #define LPC_GPIO_BASE (0x50000000)
sahilmgandhi 18:6a4db94011d3 739
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 742 // ----- Peripheral declaration -----
sahilmgandhi 18:6a4db94011d3 743 // ------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 744
sahilmgandhi 18:6a4db94011d3 745 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
sahilmgandhi 18:6a4db94011d3 746 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
sahilmgandhi 18:6a4db94011d3 747 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
sahilmgandhi 18:6a4db94011d3 748 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
sahilmgandhi 18:6a4db94011d3 749 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
sahilmgandhi 18:6a4db94011d3 750 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
sahilmgandhi 18:6a4db94011d3 751 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
sahilmgandhi 18:6a4db94011d3 752 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
sahilmgandhi 18:6a4db94011d3 753 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
sahilmgandhi 18:6a4db94011d3 754 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
sahilmgandhi 18:6a4db94011d3 755 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
sahilmgandhi 18:6a4db94011d3 756 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
sahilmgandhi 18:6a4db94011d3 757 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
sahilmgandhi 18:6a4db94011d3 758 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
sahilmgandhi 18:6a4db94011d3 759 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
sahilmgandhi 18:6a4db94011d3 760 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
sahilmgandhi 18:6a4db94011d3 761 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
sahilmgandhi 18:6a4db94011d3 762 #define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
sahilmgandhi 18:6a4db94011d3 763 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
sahilmgandhi 18:6a4db94011d3 764 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
sahilmgandhi 18:6a4db94011d3 765
sahilmgandhi 18:6a4db94011d3 766
sahilmgandhi 18:6a4db94011d3 767 /** @} */ /* End of group Device_Peripheral_Registers */
sahilmgandhi 18:6a4db94011d3 768 /** @} */ /* End of group (null) */
sahilmgandhi 18:6a4db94011d3 769 /** @} */ /* End of group h1usf */
sahilmgandhi 18:6a4db94011d3 770
sahilmgandhi 18:6a4db94011d3 771 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 772 }
sahilmgandhi 18:6a4db94011d3 773 #endif
sahilmgandhi 18:6a4db94011d3 774
sahilmgandhi 18:6a4db94011d3 775
sahilmgandhi 18:6a4db94011d3 776 #endif // __LPC13UXX_H__