MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 18 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 19 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 20 #include "gpio_api.h"
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 // The chip is capable of 42 GPIO interrupts.
sahilmgandhi 18:6a4db94011d3 23 // PIO0_0..PIO0_11, PIO1_0..PIO1_11, PIO2_0..PIO2_11, PIO3_0..PIO3_5
sahilmgandhi 18:6a4db94011d3 24 #define CHANNEL_NUM 42
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 27 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 static inline int numofbits(uint32_t bits)
sahilmgandhi 18:6a4db94011d3 30 {
sahilmgandhi 18:6a4db94011d3 31 // Count number of bits
sahilmgandhi 18:6a4db94011d3 32 bits = (bits & 0x55555555) + (bits >> 1 & 0x55555555);
sahilmgandhi 18:6a4db94011d3 33 bits = (bits & 0x33333333) + (bits >> 2 & 0x33333333);
sahilmgandhi 18:6a4db94011d3 34 bits = (bits & 0x0f0f0f0f) + (bits >> 4 & 0x0f0f0f0f);
sahilmgandhi 18:6a4db94011d3 35 bits = (bits & 0x00ff00ff) + (bits >> 8 & 0x00ff00ff);
sahilmgandhi 18:6a4db94011d3 36 return (bits & 0x0000ffff) + (bits >>16 & 0x0000ffff);
sahilmgandhi 18:6a4db94011d3 37 }
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 static inline void handle_interrupt_in(uint32_t port) {
sahilmgandhi 18:6a4db94011d3 40 // Find out whether the interrupt has been triggered by a high or low value...
sahilmgandhi 18:6a4db94011d3 41 // As the LPC1114 doesn't have a specific register for this, we'll just have to read
sahilmgandhi 18:6a4db94011d3 42 // the level of the pin as if it were just a normal input...
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 uint32_t channel;
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 // Get the number of the pin being used and the port typedef
sahilmgandhi 18:6a4db94011d3 47 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (port * 0x10000)));
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 // Get index of function table from Mask Interrupt Status register
sahilmgandhi 18:6a4db94011d3 50 channel = numofbits(port_reg->MIS - 1) + (port * 12);
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 if (port_reg->MIS & port_reg->IBE) {
sahilmgandhi 18:6a4db94011d3 53 // both edge, read the level of pin
sahilmgandhi 18:6a4db94011d3 54 if ((port_reg->DATA & port_reg->MIS) != 0)
sahilmgandhi 18:6a4db94011d3 55 irq_handler(channel_ids[channel], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 56 else
sahilmgandhi 18:6a4db94011d3 57 irq_handler(channel_ids[channel], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 58 }
sahilmgandhi 18:6a4db94011d3 59 else if (port_reg->MIS & port_reg->IEV) {
sahilmgandhi 18:6a4db94011d3 60 irq_handler(channel_ids[channel], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 61 }
sahilmgandhi 18:6a4db94011d3 62 else {
sahilmgandhi 18:6a4db94011d3 63 irq_handler(channel_ids[channel], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 64 }
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 // Clear the interrupt...
sahilmgandhi 18:6a4db94011d3 67 port_reg->IC = port_reg->MIS;
sahilmgandhi 18:6a4db94011d3 68 }
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 void gpio_irq0(void) {handle_interrupt_in(0);}
sahilmgandhi 18:6a4db94011d3 71 void gpio_irq1(void) {handle_interrupt_in(1);}
sahilmgandhi 18:6a4db94011d3 72 void gpio_irq2(void) {handle_interrupt_in(2);}
sahilmgandhi 18:6a4db94011d3 73 void gpio_irq3(void) {handle_interrupt_in(3);}
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 76 int channel;
sahilmgandhi 18:6a4db94011d3 77 uint32_t port_num;
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 if (pin == NC) return -1;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 // Firstly, we'll put some data in *obj so we can keep track of stuff.
sahilmgandhi 18:6a4db94011d3 82 obj->pin = pin;
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 // Set the handler to be the pointer at the top...
sahilmgandhi 18:6a4db94011d3 85 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 // Which port are we using?
sahilmgandhi 18:6a4db94011d3 88 port_num = ((pin & 0xF000) >> PORT_SHIFT);
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 switch (port_num) {
sahilmgandhi 18:6a4db94011d3 91 case 0:
sahilmgandhi 18:6a4db94011d3 92 NVIC_SetVector(EINT0_IRQn, (uint32_t)gpio_irq0);
sahilmgandhi 18:6a4db94011d3 93 NVIC_EnableIRQ(EINT0_IRQn);
sahilmgandhi 18:6a4db94011d3 94 break;
sahilmgandhi 18:6a4db94011d3 95 case 1:
sahilmgandhi 18:6a4db94011d3 96 NVIC_SetVector(EINT1_IRQn, (uint32_t)gpio_irq1);
sahilmgandhi 18:6a4db94011d3 97 NVIC_EnableIRQ(EINT1_IRQn);
sahilmgandhi 18:6a4db94011d3 98 break;
sahilmgandhi 18:6a4db94011d3 99 case 2:
sahilmgandhi 18:6a4db94011d3 100 NVIC_SetVector(EINT2_IRQn, (uint32_t)gpio_irq2);
sahilmgandhi 18:6a4db94011d3 101 NVIC_EnableIRQ(EINT2_IRQn);
sahilmgandhi 18:6a4db94011d3 102 break;
sahilmgandhi 18:6a4db94011d3 103 case 3:
sahilmgandhi 18:6a4db94011d3 104 NVIC_SetVector(EINT3_IRQn, (uint32_t)gpio_irq3);
sahilmgandhi 18:6a4db94011d3 105 NVIC_EnableIRQ(EINT3_IRQn);
sahilmgandhi 18:6a4db94011d3 106 break;
sahilmgandhi 18:6a4db94011d3 107 default:
sahilmgandhi 18:6a4db94011d3 108 return -1;
sahilmgandhi 18:6a4db94011d3 109 }
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 // Generate index of function pointer table
sahilmgandhi 18:6a4db94011d3 112 // PIO0_0 - PIO0_11 : 0..11
sahilmgandhi 18:6a4db94011d3 113 // PIO1_0 - PIO1_11 : 12..23
sahilmgandhi 18:6a4db94011d3 114 // PIO2_0 - PIO2_11 : 24..35
sahilmgandhi 18:6a4db94011d3 115 // PIO3_0 - PIO3_5 : 36..41
sahilmgandhi 18:6a4db94011d3 116 channel = (port_num * 12) + ((pin & 0x0F00) >> PIN_SHIFT);
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 channel_ids[channel] = id;
sahilmgandhi 18:6a4db94011d3 119 obj->ch = channel;
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 return 0;
sahilmgandhi 18:6a4db94011d3 122 }
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 void gpio_irq_free(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 125 channel_ids[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 126 }
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 129 // Firstly, check if there is an existing event stored...
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((obj->pin & 0xF000) >> PORT_SHIFT) * 0x10000)));
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 // Need to get the pin number of the pin, not the value of the enum
sahilmgandhi 18:6a4db94011d3 134 uint32_t pin_num = (1 << ((obj->pin & 0x0f00) >> PIN_SHIFT));
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 // Clear
sahilmgandhi 18:6a4db94011d3 137 port_reg->IC |= pin_num;
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 // Make it edge sensitive.
sahilmgandhi 18:6a4db94011d3 140 port_reg->IS &= ~pin_num;
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 if ( (port_reg->IE & pin_num) != 0) {
sahilmgandhi 18:6a4db94011d3 143 // We have an event.
sahilmgandhi 18:6a4db94011d3 144 // Enable both edge interrupts.
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 if (enable) {
sahilmgandhi 18:6a4db94011d3 147 port_reg->IBE |= pin_num;
sahilmgandhi 18:6a4db94011d3 148 port_reg->IE |= pin_num;
sahilmgandhi 18:6a4db94011d3 149 }
sahilmgandhi 18:6a4db94011d3 150 else {
sahilmgandhi 18:6a4db94011d3 151 // These all need to be opposite, to reenable the other one.
sahilmgandhi 18:6a4db94011d3 152 port_reg->IBE &= ~pin_num;
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 if (event == IRQ_RISE)
sahilmgandhi 18:6a4db94011d3 155 port_reg->IEV &= ~pin_num;
sahilmgandhi 18:6a4db94011d3 156 else
sahilmgandhi 18:6a4db94011d3 157 port_reg->IEV |= pin_num;
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 port_reg->IE |= pin_num;
sahilmgandhi 18:6a4db94011d3 160 }
sahilmgandhi 18:6a4db94011d3 161 }
sahilmgandhi 18:6a4db94011d3 162 else {
sahilmgandhi 18:6a4db94011d3 163 // One edge
sahilmgandhi 18:6a4db94011d3 164 port_reg->IBE &= ~pin_num;
sahilmgandhi 18:6a4db94011d3 165 // Rising/falling?
sahilmgandhi 18:6a4db94011d3 166 if (event == IRQ_RISE)
sahilmgandhi 18:6a4db94011d3 167 port_reg->IEV |= pin_num;
sahilmgandhi 18:6a4db94011d3 168 else
sahilmgandhi 18:6a4db94011d3 169 port_reg->IEV &= ~pin_num;
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 if (enable) {
sahilmgandhi 18:6a4db94011d3 172 port_reg->IE |= pin_num;
sahilmgandhi 18:6a4db94011d3 173 }
sahilmgandhi 18:6a4db94011d3 174 }
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 }
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 void gpio_irq_enable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 179 uint32_t port_num = ((obj->pin & 0xF000) >> PORT_SHIFT);
sahilmgandhi 18:6a4db94011d3 180 switch (port_num) {
sahilmgandhi 18:6a4db94011d3 181 case 0:
sahilmgandhi 18:6a4db94011d3 182 NVIC_EnableIRQ(EINT0_IRQn);
sahilmgandhi 18:6a4db94011d3 183 break;
sahilmgandhi 18:6a4db94011d3 184 case 1:
sahilmgandhi 18:6a4db94011d3 185 NVIC_EnableIRQ(EINT1_IRQn);
sahilmgandhi 18:6a4db94011d3 186 break;
sahilmgandhi 18:6a4db94011d3 187 case 2:
sahilmgandhi 18:6a4db94011d3 188 NVIC_EnableIRQ(EINT2_IRQn);
sahilmgandhi 18:6a4db94011d3 189 break;
sahilmgandhi 18:6a4db94011d3 190 case 3:
sahilmgandhi 18:6a4db94011d3 191 NVIC_EnableIRQ(EINT3_IRQn);
sahilmgandhi 18:6a4db94011d3 192 break;
sahilmgandhi 18:6a4db94011d3 193 default:
sahilmgandhi 18:6a4db94011d3 194 break;
sahilmgandhi 18:6a4db94011d3 195 }
sahilmgandhi 18:6a4db94011d3 196 }
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 void gpio_irq_disable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 199 uint32_t port_num = ((obj->pin & 0xF000) >> PORT_SHIFT);
sahilmgandhi 18:6a4db94011d3 200 switch (port_num) {
sahilmgandhi 18:6a4db94011d3 201 case 0:
sahilmgandhi 18:6a4db94011d3 202 NVIC_DisableIRQ(EINT0_IRQn);
sahilmgandhi 18:6a4db94011d3 203 break;
sahilmgandhi 18:6a4db94011d3 204 case 1:
sahilmgandhi 18:6a4db94011d3 205 NVIC_DisableIRQ(EINT1_IRQn);
sahilmgandhi 18:6a4db94011d3 206 break;
sahilmgandhi 18:6a4db94011d3 207 case 2:
sahilmgandhi 18:6a4db94011d3 208 NVIC_DisableIRQ(EINT2_IRQn);
sahilmgandhi 18:6a4db94011d3 209 break;
sahilmgandhi 18:6a4db94011d3 210 case 3:
sahilmgandhi 18:6a4db94011d3 211 NVIC_DisableIRQ(EINT3_IRQn);
sahilmgandhi 18:6a4db94011d3 212 break;
sahilmgandhi 18:6a4db94011d3 213 default:
sahilmgandhi 18:6a4db94011d3 214 break;
sahilmgandhi 18:6a4db94011d3 215 }
sahilmgandhi 18:6a4db94011d3 216 }