MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/cmsis_nvic.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * CMSIS-style functionality to support dynamic vectors
sahilmgandhi 18:6a4db94011d3 3 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 4 * Copyright (c) 2011 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 5 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 8 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 11 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 13 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 14 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 15 * 3. Neither the name of ARM Limited nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 16 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 17 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 26 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 29 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 #include "cmsis_nvic.h"
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 /* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
sahilmgandhi 18:6a4db94011d3 35 * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
sahilmgandhi 18:6a4db94011d3 36 * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
sahilmgandhi 18:6a4db94011d3 37 * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
sahilmgandhi 18:6a4db94011d3 38 *
sahilmgandhi 18:6a4db94011d3 39 * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
sahilmgandhi 18:6a4db94011d3 40 * above the vector table before 0x200 will actually go to RAM. So we need to provide
sahilmgandhi 18:6a4db94011d3 41 * a solution where the compiler gets the right results based on the memory map
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
sahilmgandhi 18:6a4db94011d3 44 * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
sahilmgandhi 18:6a4db94011d3 45 * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
sahilmgandhi 18:6a4db94011d3 46 *
sahilmgandhi 18:6a4db94011d3 47 * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
sahilmgandhi 18:6a4db94011d3 48 * - No flash accesses will go to ram, as there will be nothing there
sahilmgandhi 18:6a4db94011d3 49 * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
sahilmgandhi 18:6a4db94011d3 50 * - RAM overhead: 0, FLASH overhead: 320 bytes
sahilmgandhi 18:6a4db94011d3 51 *
sahilmgandhi 18:6a4db94011d3 52 * Option 2 is the one to go for, as RAM is the most valuable resource
sahilmgandhi 18:6a4db94011d3 53 */
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
sahilmgandhi 18:6a4db94011d3 58 int i;
sahilmgandhi 18:6a4db94011d3 59 // Space for dynamic vectors, initialised to allocate in R/W
sahilmgandhi 18:6a4db94011d3 60 static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 // Copy and switch to dynamic vectors if first time called
sahilmgandhi 18:6a4db94011d3 63 if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
sahilmgandhi 18:6a4db94011d3 64 uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
sahilmgandhi 18:6a4db94011d3 65 for(i = 0; i < NVIC_NUM_VECTORS; i++) {
sahilmgandhi 18:6a4db94011d3 66 vectors[i] = old_vectors[i];
sahilmgandhi 18:6a4db94011d3 67 }
sahilmgandhi 18:6a4db94011d3 68 LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
sahilmgandhi 18:6a4db94011d3 69 }
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 // Set the vector
sahilmgandhi 18:6a4db94011d3 72 vectors[IRQn + 16] = vector;
sahilmgandhi 18:6a4db94011d3 73 }
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
sahilmgandhi 18:6a4db94011d3 76 // We can always read vectors at 0x0, as the addresses are remapped
sahilmgandhi 18:6a4db94011d3 77 uint32_t *vectors = (uint32_t*)0;
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 // Return the vector
sahilmgandhi 18:6a4db94011d3 80 return vectors[IRQn + 16];
sahilmgandhi 18:6a4db94011d3 81 }
sahilmgandhi 18:6a4db94011d3 82