MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 18 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 19 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #define CHANNEL_NUM 8
sahilmgandhi 18:6a4db94011d3 22 #define LPC_GPIO_X LPC_GPIO_PIN_INT
sahilmgandhi 18:6a4db94011d3 23 #define PININT_IRQ 0
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 26 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 static inline void handle_interrupt_in(uint32_t channel) {
sahilmgandhi 18:6a4db94011d3 29 uint32_t ch_bit = (1 << channel);
sahilmgandhi 18:6a4db94011d3 30 // Return immediately if:
sahilmgandhi 18:6a4db94011d3 31 // * The interrupt was already served
sahilmgandhi 18:6a4db94011d3 32 // * There is no user handler
sahilmgandhi 18:6a4db94011d3 33 // * It is a level interrupt, not an edge interrupt
sahilmgandhi 18:6a4db94011d3 34 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
sahilmgandhi 18:6a4db94011d3 35 (channel_ids[channel] == 0 ) ||
sahilmgandhi 18:6a4db94011d3 36 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
sahilmgandhi 18:6a4db94011d3 39 irq_handler(channel_ids[channel], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 40 LPC_GPIO_X->RISE = ch_bit;
sahilmgandhi 18:6a4db94011d3 41 }
sahilmgandhi 18:6a4db94011d3 42 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
sahilmgandhi 18:6a4db94011d3 43 irq_handler(channel_ids[channel], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 44 }
sahilmgandhi 18:6a4db94011d3 45 LPC_GPIO_X->IST = ch_bit;
sahilmgandhi 18:6a4db94011d3 46 }
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 void gpio_irq0(void) {handle_interrupt_in(0);}
sahilmgandhi 18:6a4db94011d3 49 void gpio_irq1(void) {handle_interrupt_in(1);}
sahilmgandhi 18:6a4db94011d3 50 void gpio_irq2(void) {handle_interrupt_in(2);}
sahilmgandhi 18:6a4db94011d3 51 void gpio_irq3(void) {handle_interrupt_in(3);}
sahilmgandhi 18:6a4db94011d3 52 void gpio_irq4(void) {handle_interrupt_in(4);}
sahilmgandhi 18:6a4db94011d3 53 void gpio_irq5(void) {handle_interrupt_in(5);}
sahilmgandhi 18:6a4db94011d3 54 void gpio_irq6(void) {handle_interrupt_in(6);}
sahilmgandhi 18:6a4db94011d3 55 void gpio_irq7(void) {handle_interrupt_in(7);}
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 58 if (pin == NC) return -1;
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 int found_free_channel = 0;
sahilmgandhi 18:6a4db94011d3 63 int i = 0;
sahilmgandhi 18:6a4db94011d3 64 for (i=0; i<CHANNEL_NUM; i++) {
sahilmgandhi 18:6a4db94011d3 65 if (channel_ids[i] == 0) {
sahilmgandhi 18:6a4db94011d3 66 channel_ids[i] = id;
sahilmgandhi 18:6a4db94011d3 67 obj->ch = i;
sahilmgandhi 18:6a4db94011d3 68 found_free_channel = 1;
sahilmgandhi 18:6a4db94011d3 69 break;
sahilmgandhi 18:6a4db94011d3 70 }
sahilmgandhi 18:6a4db94011d3 71 }
sahilmgandhi 18:6a4db94011d3 72 if (!found_free_channel) return -1;
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /* Enable AHB clock to the GPIO domain. */
sahilmgandhi 18:6a4db94011d3 75 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 /* Enable AHB clock to the FlexInt, GroupedInt domain. */
sahilmgandhi 18:6a4db94011d3 78 LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 /* To select a pin for any of the eight pin interrupts, write the pin number
sahilmgandhi 18:6a4db94011d3 81 * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
sahilmgandhi 18:6a4db94011d3 82 * @see: mbed_capi/PinNames.h
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84 LPC_SYSCON->PINTSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin);
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 // Interrupt Wake-Up Enable
sahilmgandhi 18:6a4db94011d3 87 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 void (*channels_irq)(void) = NULL;
sahilmgandhi 18:6a4db94011d3 90 switch (obj->ch) {
sahilmgandhi 18:6a4db94011d3 91 case 0: channels_irq = &gpio_irq0; break;
sahilmgandhi 18:6a4db94011d3 92 case 1: channels_irq = &gpio_irq1; break;
sahilmgandhi 18:6a4db94011d3 93 case 2: channels_irq = &gpio_irq2; break;
sahilmgandhi 18:6a4db94011d3 94 case 3: channels_irq = &gpio_irq3; break;
sahilmgandhi 18:6a4db94011d3 95 case 4: channels_irq = &gpio_irq4; break;
sahilmgandhi 18:6a4db94011d3 96 case 5: channels_irq = &gpio_irq5; break;
sahilmgandhi 18:6a4db94011d3 97 case 6: channels_irq = &gpio_irq6; break;
sahilmgandhi 18:6a4db94011d3 98 case 7: channels_irq = &gpio_irq7; break;
sahilmgandhi 18:6a4db94011d3 99 }
sahilmgandhi 18:6a4db94011d3 100 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
sahilmgandhi 18:6a4db94011d3 101 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 return 0;
sahilmgandhi 18:6a4db94011d3 104 }
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 void gpio_irq_free(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 107 channel_ids[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 108 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
sahilmgandhi 18:6a4db94011d3 109 }
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 112 unsigned int ch_bit = (1 << obj->ch);
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 // Clear interrupt
sahilmgandhi 18:6a4db94011d3 115 if (!(LPC_GPIO_X->ISEL & ch_bit))
sahilmgandhi 18:6a4db94011d3 116 LPC_GPIO_X->IST = ch_bit;
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 // Edge trigger
sahilmgandhi 18:6a4db94011d3 119 LPC_GPIO_X->ISEL &= ~ch_bit;
sahilmgandhi 18:6a4db94011d3 120 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 121 if (enable) {
sahilmgandhi 18:6a4db94011d3 122 LPC_GPIO_X->IENR |= ch_bit;
sahilmgandhi 18:6a4db94011d3 123 } else {
sahilmgandhi 18:6a4db94011d3 124 LPC_GPIO_X->IENR &= ~ch_bit;
sahilmgandhi 18:6a4db94011d3 125 }
sahilmgandhi 18:6a4db94011d3 126 } else {
sahilmgandhi 18:6a4db94011d3 127 if (enable) {
sahilmgandhi 18:6a4db94011d3 128 LPC_GPIO_X->IENF |= ch_bit;
sahilmgandhi 18:6a4db94011d3 129 } else {
sahilmgandhi 18:6a4db94011d3 130 LPC_GPIO_X->IENF &= ~ch_bit;
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132 }
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 void gpio_irq_enable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 136 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
sahilmgandhi 18:6a4db94011d3 137 }
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 void gpio_irq_disable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 140 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
sahilmgandhi 18:6a4db94011d3 141 }