MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC11U6X/serial_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 // math.h required for floating point operations for baud rate calculation
sahilmgandhi 18:6a4db94011d3 18 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 19 #include <math.h>
sahilmgandhi 18:6a4db94011d3 20 #include <string.h>
sahilmgandhi 18:6a4db94011d3 21 #include <stdlib.h>
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 #include "serial_api.h"
sahilmgandhi 18:6a4db94011d3 24 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 25 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #if DEVICE_SERIAL
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 30 * INITIALIZATION
sahilmgandhi 18:6a4db94011d3 31 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #define UART_NUM 5
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 // CFG
sahilmgandhi 18:6a4db94011d3 36 #define UART_EN (0x01<<0)
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 // CTL
sahilmgandhi 18:6a4db94011d3 39 #define TXBRKEN (0x01<<1)
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 // STAT
sahilmgandhi 18:6a4db94011d3 42 #define RXRDY (0x01<<0)
sahilmgandhi 18:6a4db94011d3 43 #define TXRDY (0x01<<2)
sahilmgandhi 18:6a4db94011d3 44 #define DELTACTS (0x01<<5)
sahilmgandhi 18:6a4db94011d3 45 #define RXBRK (0x01<<10)
sahilmgandhi 18:6a4db94011d3 46 #define DELTARXBRK (0x01<<11)
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 static const PinMap PinMap_UART_TX[] = {
sahilmgandhi 18:6a4db94011d3 49 {P0_19, UART_0, 1},
sahilmgandhi 18:6a4db94011d3 50 {P1_18, UART_0, 2},
sahilmgandhi 18:6a4db94011d3 51 {P1_27, UART_0, 2},
sahilmgandhi 18:6a4db94011d3 52 {P1_8 , UART_1, 2},
sahilmgandhi 18:6a4db94011d3 53 {P0_14, UART_1, 4},
sahilmgandhi 18:6a4db94011d3 54 {P1_0 , UART_2, 3},
sahilmgandhi 18:6a4db94011d3 55 {P1_23, UART_2, 3},
sahilmgandhi 18:6a4db94011d3 56 {P2_4 , UART_3, 1},
sahilmgandhi 18:6a4db94011d3 57 {P2_12, UART_4, 1},
sahilmgandhi 18:6a4db94011d3 58 { NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 59 };
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 static const PinMap PinMap_UART_RX[] = {
sahilmgandhi 18:6a4db94011d3 62 {P0_18, UART_0, 1},
sahilmgandhi 18:6a4db94011d3 63 {P1_17, UART_0, 2},
sahilmgandhi 18:6a4db94011d3 64 {P1_26, UART_0, 2},
sahilmgandhi 18:6a4db94011d3 65 {P1_2 , UART_1, 3},
sahilmgandhi 18:6a4db94011d3 66 {P0_13, UART_1, 4},
sahilmgandhi 18:6a4db94011d3 67 {P0_20, UART_2, 2},
sahilmgandhi 18:6a4db94011d3 68 {P1_6 , UART_2, 2},
sahilmgandhi 18:6a4db94011d3 69 {P2_3 , UART_3, 1},
sahilmgandhi 18:6a4db94011d3 70 {P2_11, UART_4, 1},
sahilmgandhi 18:6a4db94011d3 71 {NC , NC , 0}
sahilmgandhi 18:6a4db94011d3 72 };
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 static uint32_t serial_irq_ids[UART_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 75 static uart_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 int stdio_uart_inited = 0;
sahilmgandhi 18:6a4db94011d3 78 serial_t stdio_uart;
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 void serial_init(serial_t *obj, PinName tx, PinName rx) {
sahilmgandhi 18:6a4db94011d3 81 int is_stdio_uart = 0;
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 // determine the UART to use
sahilmgandhi 18:6a4db94011d3 84 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 85 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
sahilmgandhi 18:6a4db94011d3 86 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
sahilmgandhi 18:6a4db94011d3 87 MBED_ASSERT((int)uart != NC);
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 switch (uart) {
sahilmgandhi 18:6a4db94011d3 90 case UART_0:
sahilmgandhi 18:6a4db94011d3 91 obj->index = 0;
sahilmgandhi 18:6a4db94011d3 92 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
sahilmgandhi 18:6a4db94011d3 93 break;
sahilmgandhi 18:6a4db94011d3 94 case UART_1:
sahilmgandhi 18:6a4db94011d3 95 obj->index = 1;
sahilmgandhi 18:6a4db94011d3 96 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 20);
sahilmgandhi 18:6a4db94011d3 97 LPC_SYSCON->PRESETCTRL |= (1 << 5);
sahilmgandhi 18:6a4db94011d3 98 break;
sahilmgandhi 18:6a4db94011d3 99 case UART_2:
sahilmgandhi 18:6a4db94011d3 100 obj->index = 2;
sahilmgandhi 18:6a4db94011d3 101 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 21);
sahilmgandhi 18:6a4db94011d3 102 LPC_SYSCON->PRESETCTRL |= (1 << 6);
sahilmgandhi 18:6a4db94011d3 103 break;
sahilmgandhi 18:6a4db94011d3 104 case UART_3:
sahilmgandhi 18:6a4db94011d3 105 obj->index = 3;
sahilmgandhi 18:6a4db94011d3 106 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 22);
sahilmgandhi 18:6a4db94011d3 107 LPC_SYSCON->PRESETCTRL |= (1 << 7);
sahilmgandhi 18:6a4db94011d3 108 break;
sahilmgandhi 18:6a4db94011d3 109 case UART_4:
sahilmgandhi 18:6a4db94011d3 110 obj->index = 4;
sahilmgandhi 18:6a4db94011d3 111 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 22);
sahilmgandhi 18:6a4db94011d3 112 LPC_SYSCON->PRESETCTRL |= (1 << 8);
sahilmgandhi 18:6a4db94011d3 113 break;
sahilmgandhi 18:6a4db94011d3 114 }
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 if (obj->index == 0)
sahilmgandhi 18:6a4db94011d3 117 obj->uart = (LPC_USART0_Type *)uart;
sahilmgandhi 18:6a4db94011d3 118 else
sahilmgandhi 18:6a4db94011d3 119 obj->mini_uart = (LPC_USART4_Type *)uart;
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 122 // enable fifos and default rx trigger level
sahilmgandhi 18:6a4db94011d3 123 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
sahilmgandhi 18:6a4db94011d3 124 | 0 << 1 // Rx Fifo Clear
sahilmgandhi 18:6a4db94011d3 125 | 0 << 2 // Tx Fifo Clear
sahilmgandhi 18:6a4db94011d3 126 | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
sahilmgandhi 18:6a4db94011d3 127 // disable irqs
sahilmgandhi 18:6a4db94011d3 128 obj->uart->IER = 0 << 0 // Rx Data available irq enable
sahilmgandhi 18:6a4db94011d3 129 | 0 << 1 // Tx Fifo empty irq enable
sahilmgandhi 18:6a4db94011d3 130 | 0 << 2; // Rx Line Status irq enable
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132 else {
sahilmgandhi 18:6a4db94011d3 133 // Clear all status bits
sahilmgandhi 18:6a4db94011d3 134 obj->mini_uart->STAT = (DELTACTS | DELTARXBRK);
sahilmgandhi 18:6a4db94011d3 135 // Enable UART
sahilmgandhi 18:6a4db94011d3 136 obj->mini_uart->CFG |= UART_EN;
sahilmgandhi 18:6a4db94011d3 137 }
sahilmgandhi 18:6a4db94011d3 138 // set default baud rate and format
sahilmgandhi 18:6a4db94011d3 139 serial_baud (obj, 9600);
sahilmgandhi 18:6a4db94011d3 140 serial_format(obj, 8, ParityNone, 1);
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 // pinout the chosen uart
sahilmgandhi 18:6a4db94011d3 143 pinmap_pinout(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 144 pinmap_pinout(rx, PinMap_UART_RX);
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 // set rx/tx pins in PullUp mode
sahilmgandhi 18:6a4db94011d3 147 if (tx != NC) {
sahilmgandhi 18:6a4db94011d3 148 pin_mode(tx, PullUp);
sahilmgandhi 18:6a4db94011d3 149 }
sahilmgandhi 18:6a4db94011d3 150 if (rx != NC) {
sahilmgandhi 18:6a4db94011d3 151 pin_mode(rx, PullUp);
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 if (is_stdio_uart && (obj->index == 0)) {
sahilmgandhi 18:6a4db94011d3 157 stdio_uart_inited = 1;
sahilmgandhi 18:6a4db94011d3 158 memcpy(&stdio_uart, obj, sizeof(serial_t));
sahilmgandhi 18:6a4db94011d3 159 }
sahilmgandhi 18:6a4db94011d3 160 }
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 void serial_free(serial_t *obj) {
sahilmgandhi 18:6a4db94011d3 163 serial_irq_ids[obj->index] = 0;
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 // serial_baud
sahilmgandhi 18:6a4db94011d3 167 // set the baud rate, taking in to account the current SystemFrequency
sahilmgandhi 18:6a4db94011d3 168 void serial_baud(serial_t *obj, int baudrate) {
sahilmgandhi 18:6a4db94011d3 169 LPC_SYSCON->USART0CLKDIV = 1;
sahilmgandhi 18:6a4db94011d3 170 LPC_SYSCON->FRGCLKDIV = 1;
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 173 uint32_t PCLK = SystemCoreClock;
sahilmgandhi 18:6a4db94011d3 174 // First we check to see if the basic divide with no DivAddVal/MulVal
sahilmgandhi 18:6a4db94011d3 175 // ratio gives us an integer result. If it does, we set DivAddVal = 0,
sahilmgandhi 18:6a4db94011d3 176 // MulVal = 1. Otherwise, we search the valid ratio value range to find
sahilmgandhi 18:6a4db94011d3 177 // the closest match. This could be more elegant, using search methods
sahilmgandhi 18:6a4db94011d3 178 // and/or lookup tables, but the brute force method is not that much
sahilmgandhi 18:6a4db94011d3 179 // slower, and is more maintainable.
sahilmgandhi 18:6a4db94011d3 180 uint16_t DL = PCLK / (16 * baudrate);
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 uint8_t DivAddVal = 0;
sahilmgandhi 18:6a4db94011d3 183 uint8_t MulVal = 1;
sahilmgandhi 18:6a4db94011d3 184 int hit = 0;
sahilmgandhi 18:6a4db94011d3 185 uint16_t dlv;
sahilmgandhi 18:6a4db94011d3 186 uint8_t mv, dav;
sahilmgandhi 18:6a4db94011d3 187 if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
sahilmgandhi 18:6a4db94011d3 188 int err_best = baudrate, b;
sahilmgandhi 18:6a4db94011d3 189 for (mv = 1; mv < 16 && !hit; mv++)
sahilmgandhi 18:6a4db94011d3 190 {
sahilmgandhi 18:6a4db94011d3 191 for (dav = 0; dav < mv; dav++)
sahilmgandhi 18:6a4db94011d3 192 {
sahilmgandhi 18:6a4db94011d3 193 // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
sahilmgandhi 18:6a4db94011d3 194 // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
sahilmgandhi 18:6a4db94011d3 195 // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
sahilmgandhi 18:6a4db94011d3 196 // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
sahilmgandhi 18:6a4db94011d3 197 // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
sahilmgandhi 18:6a4db94011d3 200 dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
sahilmgandhi 18:6a4db94011d3 201 else // 2 bits headroom, use more precision
sahilmgandhi 18:6a4db94011d3 202 dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
sahilmgandhi 18:6a4db94011d3 205 if (dlv == 0)
sahilmgandhi 18:6a4db94011d3 206 dlv = 1;
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 // datasheet says if dav > 0 then DL must be >= 2
sahilmgandhi 18:6a4db94011d3 209 if ((dav > 0) && (dlv < 2))
sahilmgandhi 18:6a4db94011d3 210 dlv = 2;
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 // integer rearrangement of the baudrate equation (with rounding)
sahilmgandhi 18:6a4db94011d3 213 b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 // check to see how we went
sahilmgandhi 18:6a4db94011d3 216 b = abs(b - baudrate);
sahilmgandhi 18:6a4db94011d3 217 if (b < err_best)
sahilmgandhi 18:6a4db94011d3 218 {
sahilmgandhi 18:6a4db94011d3 219 err_best = b;
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 DL = dlv;
sahilmgandhi 18:6a4db94011d3 222 MulVal = mv;
sahilmgandhi 18:6a4db94011d3 223 DivAddVal = dav;
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 if (b == baudrate)
sahilmgandhi 18:6a4db94011d3 226 {
sahilmgandhi 18:6a4db94011d3 227 hit = 1;
sahilmgandhi 18:6a4db94011d3 228 break;
sahilmgandhi 18:6a4db94011d3 229 }
sahilmgandhi 18:6a4db94011d3 230 }
sahilmgandhi 18:6a4db94011d3 231 }
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233 }
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 // set LCR[DLAB] to enable writing to divider registers
sahilmgandhi 18:6a4db94011d3 236 obj->uart->LCR |= (1 << 7);
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 // set divider values
sahilmgandhi 18:6a4db94011d3 239 obj->uart->DLM = (DL >> 8) & 0xFF;
sahilmgandhi 18:6a4db94011d3 240 obj->uart->DLL = (DL >> 0) & 0xFF;
sahilmgandhi 18:6a4db94011d3 241 obj->uart->FDR = (uint32_t) DivAddVal << 0
sahilmgandhi 18:6a4db94011d3 242 | (uint32_t) MulVal << 4;
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 // clear LCR[DLAB]
sahilmgandhi 18:6a4db94011d3 245 obj->uart->LCR &= ~(1 << 7);
sahilmgandhi 18:6a4db94011d3 246 }
sahilmgandhi 18:6a4db94011d3 247 else {
sahilmgandhi 18:6a4db94011d3 248 uint32_t UARTSysClk = SystemCoreClock / LPC_SYSCON->FRGCLKDIV;
sahilmgandhi 18:6a4db94011d3 249 obj->mini_uart->BRG = UARTSysClk / 16 / baudrate - 1;
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 LPC_SYSCON->UARTFRGDIV = 0xFF;
sahilmgandhi 18:6a4db94011d3 252 LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
sahilmgandhi 18:6a4db94011d3 253 (baudrate * (obj->mini_uart->BRG + 1))
sahilmgandhi 18:6a4db94011d3 254 ) - (LPC_SYSCON->UARTFRGDIV + 1);
sahilmgandhi 18:6a4db94011d3 255 }
sahilmgandhi 18:6a4db94011d3 256 }
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
sahilmgandhi 18:6a4db94011d3 259 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 stop_bits -= 1;
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 264 MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
sahilmgandhi 18:6a4db94011d3 265 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
sahilmgandhi 18:6a4db94011d3 266 (parity == ParityForced1) || (parity == ParityForced0));
sahilmgandhi 18:6a4db94011d3 267 data_bits -= 5;
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 int parity_enable, parity_select;
sahilmgandhi 18:6a4db94011d3 270 switch (parity) {
sahilmgandhi 18:6a4db94011d3 271 case ParityNone: parity_enable = 0; parity_select = 0; break;
sahilmgandhi 18:6a4db94011d3 272 case ParityOdd : parity_enable = 1; parity_select = 0; break;
sahilmgandhi 18:6a4db94011d3 273 case ParityEven: parity_enable = 1; parity_select = 1; break;
sahilmgandhi 18:6a4db94011d3 274 case ParityForced1: parity_enable = 1; parity_select = 2; break;
sahilmgandhi 18:6a4db94011d3 275 case ParityForced0: parity_enable = 1; parity_select = 3; break;
sahilmgandhi 18:6a4db94011d3 276 default:
sahilmgandhi 18:6a4db94011d3 277 return;
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 obj->uart->LCR = data_bits << 0
sahilmgandhi 18:6a4db94011d3 281 | stop_bits << 2
sahilmgandhi 18:6a4db94011d3 282 | parity_enable << 3
sahilmgandhi 18:6a4db94011d3 283 | parity_select << 4;
sahilmgandhi 18:6a4db94011d3 284 }
sahilmgandhi 18:6a4db94011d3 285 else {
sahilmgandhi 18:6a4db94011d3 286 // 0: 7 data bits ... 2: 9 data bits
sahilmgandhi 18:6a4db94011d3 287 MBED_ASSERT((data_bits > 6) && (data_bits < 10));
sahilmgandhi 18:6a4db94011d3 288 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
sahilmgandhi 18:6a4db94011d3 289 data_bits -= 7;
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 int paritysel;
sahilmgandhi 18:6a4db94011d3 292 switch (parity) {
sahilmgandhi 18:6a4db94011d3 293 case ParityNone: paritysel = 0; break;
sahilmgandhi 18:6a4db94011d3 294 case ParityEven: paritysel = 2; break;
sahilmgandhi 18:6a4db94011d3 295 case ParityOdd : paritysel = 3; break;
sahilmgandhi 18:6a4db94011d3 296 default:
sahilmgandhi 18:6a4db94011d3 297 return;
sahilmgandhi 18:6a4db94011d3 298 }
sahilmgandhi 18:6a4db94011d3 299 obj->mini_uart->CFG = (data_bits << 2)
sahilmgandhi 18:6a4db94011d3 300 | (paritysel << 4)
sahilmgandhi 18:6a4db94011d3 301 | (stop_bits << 6)
sahilmgandhi 18:6a4db94011d3 302 | UART_EN;
sahilmgandhi 18:6a4db94011d3 303 }
sahilmgandhi 18:6a4db94011d3 304 }
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 307 * INTERRUPTS HANDLING
sahilmgandhi 18:6a4db94011d3 308 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 309 static inline void uart_irq(uint32_t iir, uint32_t index) {
sahilmgandhi 18:6a4db94011d3 310 SerialIrq irq_type;
sahilmgandhi 18:6a4db94011d3 311 switch (iir) {
sahilmgandhi 18:6a4db94011d3 312 case 1: irq_type = TxIrq; break;
sahilmgandhi 18:6a4db94011d3 313 case 2: irq_type = RxIrq; break;
sahilmgandhi 18:6a4db94011d3 314 default: return;
sahilmgandhi 18:6a4db94011d3 315 }
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 if (serial_irq_ids[index] != 0)
sahilmgandhi 18:6a4db94011d3 318 irq_handler(serial_irq_ids[index], irq_type);
sahilmgandhi 18:6a4db94011d3 319 }
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 void uart0_irq()
sahilmgandhi 18:6a4db94011d3 322 {
sahilmgandhi 18:6a4db94011d3 323 uart_irq((LPC_USART0->IIR >> 1) & 0x7, 0);
sahilmgandhi 18:6a4db94011d3 324 }
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 void uart1_irq()
sahilmgandhi 18:6a4db94011d3 327 {
sahilmgandhi 18:6a4db94011d3 328 if(LPC_USART1->STAT & (1 << 2)){
sahilmgandhi 18:6a4db94011d3 329 uart_irq(1, 1);
sahilmgandhi 18:6a4db94011d3 330 }
sahilmgandhi 18:6a4db94011d3 331 if(LPC_USART1->STAT & (1 << 0)){
sahilmgandhi 18:6a4db94011d3 332 uart_irq(2, 1);
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334 }
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 void uart2_irq()
sahilmgandhi 18:6a4db94011d3 337 {
sahilmgandhi 18:6a4db94011d3 338 if(LPC_USART2->STAT & (1 << 2)){
sahilmgandhi 18:6a4db94011d3 339 uart_irq(1, 2);
sahilmgandhi 18:6a4db94011d3 340 }
sahilmgandhi 18:6a4db94011d3 341 if(LPC_USART2->STAT & (1 << 0)){
sahilmgandhi 18:6a4db94011d3 342 uart_irq(2, 2);
sahilmgandhi 18:6a4db94011d3 343 }
sahilmgandhi 18:6a4db94011d3 344 }
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 void uart3_irq()
sahilmgandhi 18:6a4db94011d3 347 {
sahilmgandhi 18:6a4db94011d3 348 if(LPC_USART3->STAT & (1 << 2)){
sahilmgandhi 18:6a4db94011d3 349 uart_irq(1, 3);
sahilmgandhi 18:6a4db94011d3 350 }
sahilmgandhi 18:6a4db94011d3 351 if(LPC_USART3->STAT & (1 << 0)){
sahilmgandhi 18:6a4db94011d3 352 uart_irq(2, 3);
sahilmgandhi 18:6a4db94011d3 353 }
sahilmgandhi 18:6a4db94011d3 354 }
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 void uart4_irq()
sahilmgandhi 18:6a4db94011d3 357 {
sahilmgandhi 18:6a4db94011d3 358 if(LPC_USART4->STAT & (1 << 2)){
sahilmgandhi 18:6a4db94011d3 359 uart_irq(1, 4);
sahilmgandhi 18:6a4db94011d3 360 }
sahilmgandhi 18:6a4db94011d3 361 if(LPC_USART4->STAT & (1 << 0)){
sahilmgandhi 18:6a4db94011d3 362 uart_irq(2, 4);
sahilmgandhi 18:6a4db94011d3 363 }
sahilmgandhi 18:6a4db94011d3 364 }
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 367 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 368 serial_irq_ids[obj->index] = id;
sahilmgandhi 18:6a4db94011d3 369 }
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 372 IRQn_Type irq_n = (IRQn_Type)0;
sahilmgandhi 18:6a4db94011d3 373 uint32_t vector = 0;
sahilmgandhi 18:6a4db94011d3 374 if(obj->index == 0){
sahilmgandhi 18:6a4db94011d3 375 irq_n = USART0_IRQn; vector = (uint32_t)&uart0_irq;
sahilmgandhi 18:6a4db94011d3 376 }
sahilmgandhi 18:6a4db94011d3 377 else{
sahilmgandhi 18:6a4db94011d3 378 switch ((int)obj->mini_uart) {
sahilmgandhi 18:6a4db94011d3 379 case UART_0: irq_n = USART0_IRQn; vector = (uint32_t)&uart0_irq; break;
sahilmgandhi 18:6a4db94011d3 380 case UART_1: irq_n = USART1_4_IRQn; vector = (uint32_t)&uart1_irq; break;
sahilmgandhi 18:6a4db94011d3 381 case UART_2: irq_n = USART2_3_IRQn; vector = (uint32_t)&uart2_irq; break;
sahilmgandhi 18:6a4db94011d3 382 case UART_3: irq_n = USART2_3_IRQn; vector = (uint32_t)&uart3_irq; break;
sahilmgandhi 18:6a4db94011d3 383 case UART_4: irq_n = USART1_4_IRQn; vector = (uint32_t)&uart4_irq; break;
sahilmgandhi 18:6a4db94011d3 384 }
sahilmgandhi 18:6a4db94011d3 385 }
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 if (enable) {
sahilmgandhi 18:6a4db94011d3 388 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 389 obj->uart->IER |= (1 << irq);
sahilmgandhi 18:6a4db94011d3 390 }
sahilmgandhi 18:6a4db94011d3 391 else {
sahilmgandhi 18:6a4db94011d3 392 obj->mini_uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2));
sahilmgandhi 18:6a4db94011d3 393 }
sahilmgandhi 18:6a4db94011d3 394 NVIC_SetVector(irq_n, vector);
sahilmgandhi 18:6a4db94011d3 395 NVIC_EnableIRQ(irq_n);
sahilmgandhi 18:6a4db94011d3 396 } else { // disable
sahilmgandhi 18:6a4db94011d3 397 int all_disabled = 0;
sahilmgandhi 18:6a4db94011d3 398 SerialIrq other_irq = (irq == RxIrq) ? (RxIrq) : (TxIrq);
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 401 obj->uart->IER &= ~(1 << irq);
sahilmgandhi 18:6a4db94011d3 402 all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
sahilmgandhi 18:6a4db94011d3 403 }
sahilmgandhi 18:6a4db94011d3 404 else {
sahilmgandhi 18:6a4db94011d3 405 obj->mini_uart->INTENCLR = (1 << ((irq == RxIrq) ? 0 : 2));
sahilmgandhi 18:6a4db94011d3 406 all_disabled = (obj->mini_uart->INTENSET) == 0;
sahilmgandhi 18:6a4db94011d3 407 }
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 if (all_disabled)
sahilmgandhi 18:6a4db94011d3 410 NVIC_DisableIRQ(irq_n);
sahilmgandhi 18:6a4db94011d3 411 }
sahilmgandhi 18:6a4db94011d3 412 }
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 415 * READ/WRITE
sahilmgandhi 18:6a4db94011d3 416 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 417 int serial_getc(serial_t *obj) {
sahilmgandhi 18:6a4db94011d3 418 while (!serial_readable(obj));
sahilmgandhi 18:6a4db94011d3 419 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 420 return obj->uart->RBR;
sahilmgandhi 18:6a4db94011d3 421 }
sahilmgandhi 18:6a4db94011d3 422 else {
sahilmgandhi 18:6a4db94011d3 423 return obj->mini_uart->RXDAT;
sahilmgandhi 18:6a4db94011d3 424 }
sahilmgandhi 18:6a4db94011d3 425 }
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 void serial_putc(serial_t *obj, int c) {
sahilmgandhi 18:6a4db94011d3 428 while (!serial_writable(obj));
sahilmgandhi 18:6a4db94011d3 429 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 430 obj->uart->THR = c;
sahilmgandhi 18:6a4db94011d3 431 }
sahilmgandhi 18:6a4db94011d3 432 else {
sahilmgandhi 18:6a4db94011d3 433 obj->mini_uart->TXDAT = c;
sahilmgandhi 18:6a4db94011d3 434 }
sahilmgandhi 18:6a4db94011d3 435 }
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 int serial_readable(serial_t *obj) {
sahilmgandhi 18:6a4db94011d3 438 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 439 return obj->uart->LSR & 0x01;
sahilmgandhi 18:6a4db94011d3 440 }
sahilmgandhi 18:6a4db94011d3 441 else {
sahilmgandhi 18:6a4db94011d3 442 return obj->mini_uart->STAT & RXRDY;
sahilmgandhi 18:6a4db94011d3 443 }
sahilmgandhi 18:6a4db94011d3 444 }
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 int serial_writable(serial_t *obj) {
sahilmgandhi 18:6a4db94011d3 447 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 448 return obj->uart->LSR & 0x20;
sahilmgandhi 18:6a4db94011d3 449 }
sahilmgandhi 18:6a4db94011d3 450 else {
sahilmgandhi 18:6a4db94011d3 451 return obj->mini_uart->STAT & TXRDY;
sahilmgandhi 18:6a4db94011d3 452 }
sahilmgandhi 18:6a4db94011d3 453 }
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 void serial_clear(serial_t *obj) {
sahilmgandhi 18:6a4db94011d3 456 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 457 obj->uart->FCR = 1 << 1 // rx FIFO reset
sahilmgandhi 18:6a4db94011d3 458 | 1 << 2 // tx FIFO reset
sahilmgandhi 18:6a4db94011d3 459 | 0 << 6; // interrupt depth
sahilmgandhi 18:6a4db94011d3 460 }
sahilmgandhi 18:6a4db94011d3 461 else {
sahilmgandhi 18:6a4db94011d3 462 obj->mini_uart->STAT = 0;
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464 }
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 void serial_pinout_tx(PinName tx) {
sahilmgandhi 18:6a4db94011d3 467 pinmap_pinout(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 468 }
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 void serial_break_set(serial_t *obj) {
sahilmgandhi 18:6a4db94011d3 471 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 472 obj->uart->LCR |= (1 << 6);
sahilmgandhi 18:6a4db94011d3 473 }
sahilmgandhi 18:6a4db94011d3 474 else {
sahilmgandhi 18:6a4db94011d3 475 obj->mini_uart->CTL |= TXBRKEN;
sahilmgandhi 18:6a4db94011d3 476 }
sahilmgandhi 18:6a4db94011d3 477 }
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 void serial_break_clear(serial_t *obj) {
sahilmgandhi 18:6a4db94011d3 480 if (obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 481 obj->uart->LCR &= ~(1 << 6);
sahilmgandhi 18:6a4db94011d3 482 }
sahilmgandhi 18:6a4db94011d3 483 else {
sahilmgandhi 18:6a4db94011d3 484 obj->mini_uart->CTL &= ~TXBRKEN;
sahilmgandhi 18:6a4db94011d3 485 }
sahilmgandhi 18:6a4db94011d3 486 }
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 #endif