MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC11U6X/device/system_LPC11U6x.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file system_LPC11U6x.c
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-M3 Device System Source File for
sahilmgandhi 18:6a4db94011d3 4 * NXP LPC11U6x Device Series
sahilmgandhi 18:6a4db94011d3 5 * @version V1.00
sahilmgandhi 18:6a4db94011d3 6 * @date 19. July 2013
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * @par
sahilmgandhi 18:6a4db94011d3 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
sahilmgandhi 18:6a4db94011d3 13 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 14 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * @par
sahilmgandhi 18:6a4db94011d3 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 27 #include "LPC11U6x.h"
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 /*
sahilmgandhi 18:6a4db94011d3 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
sahilmgandhi 18:6a4db94011d3 31 */
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 /*- SystemCoreClock Configuration -------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 34 // <e0> SystemCoreClock Configuration
sahilmgandhi 18:6a4db94011d3 35 #define CLOCK_SETUP 1
sahilmgandhi 18:6a4db94011d3 36 //
sahilmgandhi 18:6a4db94011d3 37 // <h> System Oscillator Control (SYSOSCCTRL)
sahilmgandhi 18:6a4db94011d3 38 // <o.0> BYPASS: System Oscillator Bypass Enable
sahilmgandhi 18:6a4db94011d3 39 // <i> If enabled then PLL input (sys_osc_clk) is fed
sahilmgandhi 18:6a4db94011d3 40 // <i> directly from XTALIN and XTALOUT pins.
sahilmgandhi 18:6a4db94011d3 41 // <o.1> FREQRANGE: System Oscillator Frequency Range
sahilmgandhi 18:6a4db94011d3 42 // <i> Determines frequency range for Low-power oscillator.
sahilmgandhi 18:6a4db94011d3 43 // <0=> 1 - 20 MHz
sahilmgandhi 18:6a4db94011d3 44 // <1=> 15 - 25 MHz
sahilmgandhi 18:6a4db94011d3 45 // </h>
sahilmgandhi 18:6a4db94011d3 46 #define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 47 //
sahilmgandhi 18:6a4db94011d3 48 // <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
sahilmgandhi 18:6a4db94011d3 49 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 50 // <1=> Crystal Oscillator (SYSOSC)
sahilmgandhi 18:6a4db94011d3 51 // <3=> RTC Oscillator (32 kHz)
sahilmgandhi 18:6a4db94011d3 52 #define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 53 //
sahilmgandhi 18:6a4db94011d3 54 // <e> Clock Configuration (Manual)
sahilmgandhi 18:6a4db94011d3 55 #define CLOCK_SETUP_REG 1
sahilmgandhi 18:6a4db94011d3 56 //
sahilmgandhi 18:6a4db94011d3 57 // <h> WD Oscillator Setting (WDTOSCCTRL)
sahilmgandhi 18:6a4db94011d3 58 // <o.0..4> DIVSEL: Select Divider for Fclkana
sahilmgandhi 18:6a4db94011d3 59 // <i> wd_osc_clk = Fclkana / (2 × (1 + DIVSEL))
sahilmgandhi 18:6a4db94011d3 60 // <0-31>
sahilmgandhi 18:6a4db94011d3 61 // <o.5..8> FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana)
sahilmgandhi 18:6a4db94011d3 62 // <1=> 0.5 MHz
sahilmgandhi 18:6a4db94011d3 63 // <2=> 0.8 MHz
sahilmgandhi 18:6a4db94011d3 64 // <3=> 1.1 MHz
sahilmgandhi 18:6a4db94011d3 65 // <4=> 1.4 MHz
sahilmgandhi 18:6a4db94011d3 66 // <5=> 1.6 MHz
sahilmgandhi 18:6a4db94011d3 67 // <6=> 1.8 MHz
sahilmgandhi 18:6a4db94011d3 68 // <7=> 2.0 MHz
sahilmgandhi 18:6a4db94011d3 69 // <8=> 2.2 MHz
sahilmgandhi 18:6a4db94011d3 70 // <9=> 2.4 MHz
sahilmgandhi 18:6a4db94011d3 71 // <10=> 2.6 MHz
sahilmgandhi 18:6a4db94011d3 72 // <11=> 2.7 MHz
sahilmgandhi 18:6a4db94011d3 73 // <12=> 2.9 MHz
sahilmgandhi 18:6a4db94011d3 74 // <13=> 3.1 MHz
sahilmgandhi 18:6a4db94011d3 75 // <14=> 3.2 MHz
sahilmgandhi 18:6a4db94011d3 76 // <15=> 3.4 MHz
sahilmgandhi 18:6a4db94011d3 77 // </h>
sahilmgandhi 18:6a4db94011d3 78 #define WDTOSCCTRL_Val 0x000000A0 // Reset value: 0x0A0
sahilmgandhi 18:6a4db94011d3 79 //
sahilmgandhi 18:6a4db94011d3 80 // <h> System PLL Setting (SYSPLLCTRL)
sahilmgandhi 18:6a4db94011d3 81 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
sahilmgandhi 18:6a4db94011d3 82 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 83 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 84 // <o.0..4> MSEL: Feedback Divider Selection
sahilmgandhi 18:6a4db94011d3 85 // <i> M = MSEL + 1
sahilmgandhi 18:6a4db94011d3 86 // <0-31>
sahilmgandhi 18:6a4db94011d3 87 // <o.5..6> PSEL: Post Divider Selection
sahilmgandhi 18:6a4db94011d3 88 // <i> Post divider ratio P. Division ratio is 2 * P
sahilmgandhi 18:6a4db94011d3 89 // <0=> P = 1
sahilmgandhi 18:6a4db94011d3 90 // <1=> P = 2
sahilmgandhi 18:6a4db94011d3 91 // <2=> P = 4
sahilmgandhi 18:6a4db94011d3 92 // <3=> P = 8
sahilmgandhi 18:6a4db94011d3 93 // </h>
sahilmgandhi 18:6a4db94011d3 94 #define SYSPLLCTRL_Val 0x00000023 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 95 //
sahilmgandhi 18:6a4db94011d3 96 // <o.0..1> Main Clock Source Select (MAINCLKSEL)
sahilmgandhi 18:6a4db94011d3 97 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 98 // <1=> PLL Input
sahilmgandhi 18:6a4db94011d3 99 // <2=> WD Oscillator
sahilmgandhi 18:6a4db94011d3 100 // <3=> PLL Output
sahilmgandhi 18:6a4db94011d3 101 #define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 102 //
sahilmgandhi 18:6a4db94011d3 103 // <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
sahilmgandhi 18:6a4db94011d3 104 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
sahilmgandhi 18:6a4db94011d3 105 // <i> 0 = is disabled
sahilmgandhi 18:6a4db94011d3 106 // <0-255>
sahilmgandhi 18:6a4db94011d3 107 #define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
sahilmgandhi 18:6a4db94011d3 108 // </e>
sahilmgandhi 18:6a4db94011d3 109 //
sahilmgandhi 18:6a4db94011d3 110 // <e> Clock Configuration (via ROM PLL API)
sahilmgandhi 18:6a4db94011d3 111 #define CLOCK_SETUP_API 0
sahilmgandhi 18:6a4db94011d3 112 //
sahilmgandhi 18:6a4db94011d3 113 // <o> PLL API Mode Select
sahilmgandhi 18:6a4db94011d3 114 // <0=> Exact
sahilmgandhi 18:6a4db94011d3 115 // <1=> Less than or equal
sahilmgandhi 18:6a4db94011d3 116 // <2=> Greater than or equal
sahilmgandhi 18:6a4db94011d3 117 // <3=> As close as possible
sahilmgandhi 18:6a4db94011d3 118 #define PLL_API_MODE_Val 0
sahilmgandhi 18:6a4db94011d3 119 //
sahilmgandhi 18:6a4db94011d3 120 // <o> CPU Frequency [Hz] <1000000-50000000:1000>
sahilmgandhi 18:6a4db94011d3 121 #define PLL_API_FREQ_Val 48000000
sahilmgandhi 18:6a4db94011d3 122 // </e>
sahilmgandhi 18:6a4db94011d3 123 //
sahilmgandhi 18:6a4db94011d3 124 // <e> USB Clock Configuration
sahilmgandhi 18:6a4db94011d3 125 #define USB_CLOCK_SETUP 1
sahilmgandhi 18:6a4db94011d3 126 // <h> USB PLL Control (USBPLLCTRL)
sahilmgandhi 18:6a4db94011d3 127 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
sahilmgandhi 18:6a4db94011d3 128 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 129 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 130 // <o.0..4> MSEL: Feedback Divider Selection
sahilmgandhi 18:6a4db94011d3 131 // <i> M = MSEL + 1
sahilmgandhi 18:6a4db94011d3 132 // <0-31>
sahilmgandhi 18:6a4db94011d3 133 // <o.5..6> PSEL: Post Divider Selection
sahilmgandhi 18:6a4db94011d3 134 // <i> Post divider ratio P. Division ratio is 2 * P
sahilmgandhi 18:6a4db94011d3 135 // <0=> P = 1
sahilmgandhi 18:6a4db94011d3 136 // <1=> P = 2
sahilmgandhi 18:6a4db94011d3 137 // <2=> P = 4
sahilmgandhi 18:6a4db94011d3 138 // <3=> P = 8
sahilmgandhi 18:6a4db94011d3 139 // </h>
sahilmgandhi 18:6a4db94011d3 140 #define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 141 //
sahilmgandhi 18:6a4db94011d3 142 // <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
sahilmgandhi 18:6a4db94011d3 143 // <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
sahilmgandhi 18:6a4db94011d3 144 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 145 // <1=> System Oscillator
sahilmgandhi 18:6a4db94011d3 146 #define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 147 //
sahilmgandhi 18:6a4db94011d3 148 // <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
sahilmgandhi 18:6a4db94011d3 149 // <0=> USB PLL out
sahilmgandhi 18:6a4db94011d3 150 // <1=> Main clock
sahilmgandhi 18:6a4db94011d3 151 #define USBCLKSEL_Val 0x00000000 // Reset value: 0x000
sahilmgandhi 18:6a4db94011d3 152 //
sahilmgandhi 18:6a4db94011d3 153 // <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
sahilmgandhi 18:6a4db94011d3 154 // <i> Divides USB clock to 48 MHz.
sahilmgandhi 18:6a4db94011d3 155 // <i> 0 = is disabled
sahilmgandhi 18:6a4db94011d3 156 // <0-255>
sahilmgandhi 18:6a4db94011d3 157 #define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
sahilmgandhi 18:6a4db94011d3 158 // </e>
sahilmgandhi 18:6a4db94011d3 159 //
sahilmgandhi 18:6a4db94011d3 160 // </e>
sahilmgandhi 18:6a4db94011d3 161 //
sahilmgandhi 18:6a4db94011d3 162 // <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
sahilmgandhi 18:6a4db94011d3 163 // <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 164 //
sahilmgandhi 18:6a4db94011d3 165 #define XTAL_CLK_Val 12000000
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /*
sahilmgandhi 18:6a4db94011d3 168 //-------- <<< end of configuration section >>> ------------------------------
sahilmgandhi 18:6a4db94011d3 169 */
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 172 Define clocks
sahilmgandhi 18:6a4db94011d3 173 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 174 #define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
sahilmgandhi 18:6a4db94011d3 175 #define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
sahilmgandhi 18:6a4db94011d3 176 #define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
sahilmgandhi 18:6a4db94011d3 177 #define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 180 Check the register settings
sahilmgandhi 18:6a4db94011d3 181 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 182 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
sahilmgandhi 18:6a4db94011d3 183 #define CHECK_RSVD(val, mask) (val & mask)
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
sahilmgandhi 18:6a4db94011d3 186 #error "SYSOSCCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 187 #endif
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
sahilmgandhi 18:6a4db94011d3 190 #error "WDTOSCCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 191 #endif
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
sahilmgandhi 18:6a4db94011d3 194 #error "SYSPLLCLKSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 195 #endif
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 #if (SYSPLLCLKSEL_Val == 3) // RTC Oscillator used as PLL input
sahilmgandhi 18:6a4db94011d3 198 #if (CLOCK_SETUP_API == 1)
sahilmgandhi 18:6a4db94011d3 199 #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
sahilmgandhi 18:6a4db94011d3 200 #endif
sahilmgandhi 18:6a4db94011d3 201 #if (CLOCK_SETUP_REG == 1) && (MAINCLKSEL_Val == 3) // RTC Oscillator used as PLL input
sahilmgandhi 18:6a4db94011d3 202 #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
sahilmgandhi 18:6a4db94011d3 203 #endif
sahilmgandhi 18:6a4db94011d3 204 #endif
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F))
sahilmgandhi 18:6a4db94011d3 207 #error "SYSPLLCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 208 #endif
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
sahilmgandhi 18:6a4db94011d3 211 #error "MAINCLKSEL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 212 #endif
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
sahilmgandhi 18:6a4db94011d3 215 #error "SYSAHBCLKDIV: Value out of range!"
sahilmgandhi 18:6a4db94011d3 216 #endif
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 #if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
sahilmgandhi 18:6a4db94011d3 219 #error "You must select either manual or API based Clock Configuration!"
sahilmgandhi 18:6a4db94011d3 220 #endif
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
sahilmgandhi 18:6a4db94011d3 223 #error "USBPLLCLKSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 224 #endif
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000007F))
sahilmgandhi 18:6a4db94011d3 227 #error "USBPLLCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 228 #endif
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 #if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
sahilmgandhi 18:6a4db94011d3 231 #error "USBCLKSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 232 #endif
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
sahilmgandhi 18:6a4db94011d3 235 #error "USBCLKDIV: Value out of range!"
sahilmgandhi 18:6a4db94011d3 236 #endif
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 #if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
sahilmgandhi 18:6a4db94011d3 239 #error "XTAL frequency is out of bounds"
sahilmgandhi 18:6a4db94011d3 240 #endif
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 #if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
sahilmgandhi 18:6a4db94011d3 243 #error "PLL API Mode Select not valid"
sahilmgandhi 18:6a4db94011d3 244 #endif
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 #if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 50000000))
sahilmgandhi 18:6a4db94011d3 247 #error "CPU Frequency (API mode) not valid"
sahilmgandhi 18:6a4db94011d3 248 #endif
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 253 Calculate system core clock
sahilmgandhi 18:6a4db94011d3 254 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 255 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 /* sys_pllclkin calculation */
sahilmgandhi 18:6a4db94011d3 258 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
sahilmgandhi 18:6a4db94011d3 259 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 260 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 261 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 262 #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
sahilmgandhi 18:6a4db94011d3 263 #define __SYS_PLLCLKIN (__RTC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 264 #else
sahilmgandhi 18:6a4db94011d3 265 #error "Oops"
sahilmgandhi 18:6a4db94011d3 266 #endif
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
sahilmgandhi 18:6a4db94011d3 271 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 #if (__FREQSEL == 0)
sahilmgandhi 18:6a4db94011d3 274 #error "WDTOSCCTRL.FREQSEL undefined!"
sahilmgandhi 18:6a4db94011d3 275 #elif (__FREQSEL == 1)
sahilmgandhi 18:6a4db94011d3 276 #define __OSC_CLK ( 500000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 277 #elif (__FREQSEL == 2)
sahilmgandhi 18:6a4db94011d3 278 #define __OSC_CLK ( 800000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 279 #elif (__FREQSEL == 3)
sahilmgandhi 18:6a4db94011d3 280 #define __OSC_CLK (1100000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 281 #elif (__FREQSEL == 4)
sahilmgandhi 18:6a4db94011d3 282 #define __OSC_CLK (1400000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 283 #elif (__FREQSEL == 5)
sahilmgandhi 18:6a4db94011d3 284 #define __OSC_CLK (1600000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 285 #elif (__FREQSEL == 6)
sahilmgandhi 18:6a4db94011d3 286 #define __OSC_CLK (1800000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 287 #elif (__FREQSEL == 7)
sahilmgandhi 18:6a4db94011d3 288 #define __OSC_CLK (2000000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 289 #elif (__FREQSEL == 8)
sahilmgandhi 18:6a4db94011d3 290 #define __OSC_CLK (2200000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 291 #elif (__FREQSEL == 9)
sahilmgandhi 18:6a4db94011d3 292 #define __OSC_CLK (2400000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 293 #elif (__FREQSEL == 10)
sahilmgandhi 18:6a4db94011d3 294 #define __OSC_CLK (2600000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 295 #elif (__FREQSEL == 11)
sahilmgandhi 18:6a4db94011d3 296 #define __OSC_CLK (2700000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 297 #elif (__FREQSEL == 12)
sahilmgandhi 18:6a4db94011d3 298 #define __OSC_CLK (2900000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 299 #elif (__FREQSEL == 13)
sahilmgandhi 18:6a4db94011d3 300 #define __OSC_CLK (3100000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 301 #elif (__FREQSEL == 14)
sahilmgandhi 18:6a4db94011d3 302 #define __OSC_CLK (3200000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 303 #else
sahilmgandhi 18:6a4db94011d3 304 #define __OSC_CLK (3400000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 305 #endif
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /* main clock calculation */
sahilmgandhi 18:6a4db94011d3 310 #if ((MAINCLKSEL_Val & 0x03) == 0)
sahilmgandhi 18:6a4db94011d3 311 #define __MAIN_CLOCK (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 312 #elif ((MAINCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 313 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
sahilmgandhi 18:6a4db94011d3 314 #elif ((MAINCLKSEL_Val & 0x03) == 2)
sahilmgandhi 18:6a4db94011d3 315 #define __MAIN_CLOCK (__OSC_CLK)
sahilmgandhi 18:6a4db94011d3 316 #elif ((MAINCLKSEL_Val & 0x03) == 3)
sahilmgandhi 18:6a4db94011d3 317 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
sahilmgandhi 18:6a4db94011d3 318 #else
sahilmgandhi 18:6a4db94011d3 319 #error "Oops"
sahilmgandhi 18:6a4db94011d3 320 #endif
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
sahilmgandhi 18:6a4db94011d3 323 #endif /* Clock Setup via Register */
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
sahilmgandhi 18:6a4db94011d3 326 #define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
sahilmgandhi 18:6a4db94011d3 327 #endif /* Clock Setup via PLL API */
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 #else
sahilmgandhi 18:6a4db94011d3 330 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 331 #endif /* CLOCK_SETUP */
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 #if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
sahilmgandhi 18:6a4db94011d3 336 #include "power_api.h"
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 typedef struct _ROM {
sahilmgandhi 18:6a4db94011d3 339 const unsigned p_dev0;
sahilmgandhi 18:6a4db94011d3 340 const unsigned p_dev1;
sahilmgandhi 18:6a4db94011d3 341 const unsigned p_dev2;
sahilmgandhi 18:6a4db94011d3 342 const PWRD * pPWRD; /* ROM Power Management API */
sahilmgandhi 18:6a4db94011d3 343 const unsigned p_dev4;
sahilmgandhi 18:6a4db94011d3 344 const unsigned p_dev5;
sahilmgandhi 18:6a4db94011d3 345 const unsigned p_dev6;
sahilmgandhi 18:6a4db94011d3 346 const unsigned p_dev7;
sahilmgandhi 18:6a4db94011d3 347 } ROM;
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 350 PLL API Function
sahilmgandhi 18:6a4db94011d3 351 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 352 static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
sahilmgandhi 18:6a4db94011d3 353 {
sahilmgandhi 18:6a4db94011d3 354 uint32_t cmd[5], res[5];
sahilmgandhi 18:6a4db94011d3 355 ROM ** rom = (ROM **) 0x1FFF1FF8; /* pointer to power API calls */
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 cmd[0] = pllInFreq; /* PLL's input freq in KHz */
sahilmgandhi 18:6a4db94011d3 358 cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
sahilmgandhi 18:6a4db94011d3 359 cmd[2] = pllMode;
sahilmgandhi 18:6a4db94011d3 360 cmd[3] = 0; /* no timeout for PLL to lock */
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 /* Execute API call */
sahilmgandhi 18:6a4db94011d3 363 (*rom)->pPWRD->set_pll(cmd, res); /* call API function */
sahilmgandhi 18:6a4db94011d3 364 if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
sahilmgandhi 18:6a4db94011d3 365 while(1); /* ... stay here */
sahilmgandhi 18:6a4db94011d3 366 }
sahilmgandhi 18:6a4db94011d3 367 }
sahilmgandhi 18:6a4db94011d3 368 #endif
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 374 Clock Variable definitions
sahilmgandhi 18:6a4db94011d3 375 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 376 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 380 Clock functions
sahilmgandhi 18:6a4db94011d3 381 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 382 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
sahilmgandhi 18:6a4db94011d3 383 {
sahilmgandhi 18:6a4db94011d3 384 uint32_t oscClk = 0;
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 /* Determine clock frequency according to clock register values */
sahilmgandhi 18:6a4db94011d3 387 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
sahilmgandhi 18:6a4db94011d3 388 case 0: oscClk = 0; break;
sahilmgandhi 18:6a4db94011d3 389 case 1: oscClk = 500000; break;
sahilmgandhi 18:6a4db94011d3 390 case 2: oscClk = 800000; break;
sahilmgandhi 18:6a4db94011d3 391 case 3: oscClk = 1100000; break;
sahilmgandhi 18:6a4db94011d3 392 case 4: oscClk = 1400000; break;
sahilmgandhi 18:6a4db94011d3 393 case 5: oscClk = 1600000; break;
sahilmgandhi 18:6a4db94011d3 394 case 6: oscClk = 1800000; break;
sahilmgandhi 18:6a4db94011d3 395 case 7: oscClk = 2000000; break;
sahilmgandhi 18:6a4db94011d3 396 case 8: oscClk = 2200000; break;
sahilmgandhi 18:6a4db94011d3 397 case 9: oscClk = 2400000; break;
sahilmgandhi 18:6a4db94011d3 398 case 10: oscClk = 2600000; break;
sahilmgandhi 18:6a4db94011d3 399 case 11: oscClk = 2700000; break;
sahilmgandhi 18:6a4db94011d3 400 case 12: oscClk = 2900000; break;
sahilmgandhi 18:6a4db94011d3 401 case 13: oscClk = 3100000; break;
sahilmgandhi 18:6a4db94011d3 402 case 14: oscClk = 3200000; break;
sahilmgandhi 18:6a4db94011d3 403 case 15: oscClk = 3400000; break;
sahilmgandhi 18:6a4db94011d3 404 }
sahilmgandhi 18:6a4db94011d3 405 oscClk /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 408 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 409 SystemCoreClock = __IRC_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 410 break;
sahilmgandhi 18:6a4db94011d3 411 case 1: /* Input Clock to System PLL */
sahilmgandhi 18:6a4db94011d3 412 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 413 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 414 SystemCoreClock = __IRC_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 415 break;
sahilmgandhi 18:6a4db94011d3 416 case 1: /* System oscillator */
sahilmgandhi 18:6a4db94011d3 417 SystemCoreClock = __SYS_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 418 break;
sahilmgandhi 18:6a4db94011d3 419 case 2: /* Reserved */
sahilmgandhi 18:6a4db94011d3 420 case 3: /* Reserved */
sahilmgandhi 18:6a4db94011d3 421 SystemCoreClock = 0;
sahilmgandhi 18:6a4db94011d3 422 break;
sahilmgandhi 18:6a4db94011d3 423 }
sahilmgandhi 18:6a4db94011d3 424 break;
sahilmgandhi 18:6a4db94011d3 425 case 2: /* WDT Oscillator */
sahilmgandhi 18:6a4db94011d3 426 SystemCoreClock = oscClk;
sahilmgandhi 18:6a4db94011d3 427 break;
sahilmgandhi 18:6a4db94011d3 428 case 3: /* System PLL Clock Out */
sahilmgandhi 18:6a4db94011d3 429 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 430 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 431 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
sahilmgandhi 18:6a4db94011d3 432 break;
sahilmgandhi 18:6a4db94011d3 433 case 1: /* System oscillator */
sahilmgandhi 18:6a4db94011d3 434 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
sahilmgandhi 18:6a4db94011d3 435 break;
sahilmgandhi 18:6a4db94011d3 436 case 2: /* Reserved */
sahilmgandhi 18:6a4db94011d3 437 case 3: /* Reserved */
sahilmgandhi 18:6a4db94011d3 438 SystemCoreClock = 0;
sahilmgandhi 18:6a4db94011d3 439 break;
sahilmgandhi 18:6a4db94011d3 440 }
sahilmgandhi 18:6a4db94011d3 441 break;
sahilmgandhi 18:6a4db94011d3 442 }
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 #define PDRUN_VALID_BITS 0x000025FFL
sahilmgandhi 18:6a4db94011d3 449 #define PDRUN_RESERVED_ONE 0x0000C800L
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 static void power_down_config(uint32_t val)
sahilmgandhi 18:6a4db94011d3 452 {
sahilmgandhi 18:6a4db94011d3 453 volatile uint32_t tmp;
sahilmgandhi 18:6a4db94011d3 454 tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
sahilmgandhi 18:6a4db94011d3 455 tmp |= (val & PDRUN_VALID_BITS);
sahilmgandhi 18:6a4db94011d3 456 LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
sahilmgandhi 18:6a4db94011d3 457 }
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 static void power_up_config(uint32_t val)
sahilmgandhi 18:6a4db94011d3 460 {
sahilmgandhi 18:6a4db94011d3 461 volatile uint32_t tmp;
sahilmgandhi 18:6a4db94011d3 462 tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
sahilmgandhi 18:6a4db94011d3 463 tmp &= ~(val & PDRUN_VALID_BITS);
sahilmgandhi 18:6a4db94011d3 464 LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
sahilmgandhi 18:6a4db94011d3 465 }
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 /**
sahilmgandhi 18:6a4db94011d3 468 * Initialize the system
sahilmgandhi 18:6a4db94011d3 469 *
sahilmgandhi 18:6a4db94011d3 470 * @param none
sahilmgandhi 18:6a4db94011d3 471 * @return none
sahilmgandhi 18:6a4db94011d3 472 *
sahilmgandhi 18:6a4db94011d3 473 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 474 */
sahilmgandhi 18:6a4db94011d3 475 void SystemInit (void) {
sahilmgandhi 18:6a4db94011d3 476 #if (CLOCK_SETUP)
sahilmgandhi 18:6a4db94011d3 477 volatile uint32_t i;
sahilmgandhi 18:6a4db94011d3 478 #endif
sahilmgandhi 18:6a4db94011d3 479 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
sahilmgandhi 18:6a4db94011d3 480 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 485 // Initialize XTALIN/XTALOUT pins
sahilmgandhi 18:6a4db94011d3 486 LPC_IOCON->PIO2_0 = 0x01;
sahilmgandhi 18:6a4db94011d3 487 LPC_IOCON->PIO2_1 = 0x01;
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
sahilmgandhi 18:6a4db94011d3 490 power_up_config(1<<5); /* Power-up sysosc */
sahilmgandhi 18:6a4db94011d3 491 for (i = 0; i < 2500; i++) __NOP(); /* Wait for osc to stabilize */
sahilmgandhi 18:6a4db94011d3 492 #endif
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
sahilmgandhi 18:6a4db94011d3 495 LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
sahilmgandhi 18:6a4db94011d3 496 for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
sahilmgandhi 18:6a4db94011d3 497 #endif
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
sahilmgandhi 18:6a4db94011d3 500 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
sahilmgandhi 18:6a4db94011d3 501 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
sahilmgandhi 18:6a4db94011d3 502 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
sahilmgandhi 18:6a4db94011d3 503 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 #if (((MAINCLKSEL_Val & 0x03) == 2) )
sahilmgandhi 18:6a4db94011d3 508 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
sahilmgandhi 18:6a4db94011d3 509 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
sahilmgandhi 18:6a4db94011d3 510 for (i = 0; i < 2000; i++) __NOP(); /* Wait for osc to stabilize */
sahilmgandhi 18:6a4db94011d3 511 #endif
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
sahilmgandhi 18:6a4db94011d3 514 power_down_config(1<<7); /* Power-down SYSPLL */
sahilmgandhi 18:6a4db94011d3 515 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
sahilmgandhi 18:6a4db94011d3 516 power_up_config(1<<7); /* Power-up SYSPLL */
sahilmgandhi 18:6a4db94011d3 517 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
sahilmgandhi 18:6a4db94011d3 518 #endif
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select Clock Source */
sahilmgandhi 18:6a4db94011d3 521 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
sahilmgandhi 18:6a4db94011d3 522 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
sahilmgandhi 18:6a4db94011d3 523 LPC_SYSCON->MAINCLKUEN = 0x01;
sahilmgandhi 18:6a4db94011d3 524 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
sahilmgandhi 18:6a4db94011d3 527 #endif /* Clock Setup via Register */
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 #if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
sahilmgandhi 18:6a4db94011d3 530 // LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
sahilmgandhi 18:6a4db94011d3 531 // LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
sahilmgandhi 18:6a4db94011d3 532 // LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
sahilmgandhi 18:6a4db94011d3 533 // LPC_SYSCON->SYSPLLCLKUEN = 0x01;
sahilmgandhi 18:6a4db94011d3 534 // while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 LPC_SYSCON->MAINCLKSEL = SYSPLLCLKSEL_Val; /* Select same as SYSPLL */
sahilmgandhi 18:6a4db94011d3 537 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
sahilmgandhi 18:6a4db94011d3 538 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
sahilmgandhi 18:6a4db94011d3 539 LPC_SYSCON->MAINCLKUEN = 0x01;
sahilmgandhi 18:6a4db94011d3 540 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 LPC_SYSCON->SYSAHBCLKDIV = 1;
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
sahilmgandhi 18:6a4db94011d3 545 #endif /* Clock Setup via PLL API */
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 #if (USB_CLOCK_SETUP == 1) /* USB clock is used */
sahilmgandhi 18:6a4db94011d3 548 LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 #if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
sahilmgandhi 18:6a4db94011d3 551 LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
sahilmgandhi 18:6a4db94011d3 552 LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
sahilmgandhi 18:6a4db94011d3 553 LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
sahilmgandhi 18:6a4db94011d3 554 LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
sahilmgandhi 18:6a4db94011d3 555 LPC_SYSCON->USBPLLCLKUEN = 0x01;
sahilmgandhi 18:6a4db94011d3 556 while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
sahilmgandhi 18:6a4db94011d3 559 while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
sahilmgandhi 18:6a4db94011d3 562 #endif
sahilmgandhi 18:6a4db94011d3 563
sahilmgandhi 18:6a4db94011d3 564 LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
sahilmgandhi 18:6a4db94011d3 565 LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
sahilmgandhi 18:6a4db94011d3 566
sahilmgandhi 18:6a4db94011d3 567 #else /* USB clock is not used */
sahilmgandhi 18:6a4db94011d3 568 LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
sahilmgandhi 18:6a4db94011d3 569 LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
sahilmgandhi 18:6a4db94011d3 570 #endif
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 #endif /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 573
sahilmgandhi 18:6a4db94011d3 574 }