MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC11U6X/device/LPC11U6x.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1
sahilmgandhi 18:6a4db94011d3 2 /****************************************************************************************************//**
sahilmgandhi 18:6a4db94011d3 3 * @file LPC11U6x.h
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
sahilmgandhi 18:6a4db94011d3 6 * LPC11U6x from .
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @version V0.4
sahilmgandhi 18:6a4db94011d3 9 * @date 22. October 2013
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * @note Generated with SVDConv V2.81a
sahilmgandhi 18:6a4db94011d3 12 * from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * modified by Keil
sahilmgandhi 18:6a4db94011d3 15 *******************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 /** @addtogroup (null)
sahilmgandhi 18:6a4db94011d3 20 * @{
sahilmgandhi 18:6a4db94011d3 21 */
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 /** @addtogroup LPC11U6x
sahilmgandhi 18:6a4db94011d3 24 * @{
sahilmgandhi 18:6a4db94011d3 25 */
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #ifndef LPC11U6X_H
sahilmgandhi 18:6a4db94011d3 28 #define LPC11U6X_H
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 31 extern "C" {
sahilmgandhi 18:6a4db94011d3 32 #endif
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 /* ------------------------- Interrupt Number Definition ------------------------ */
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 typedef enum {
sahilmgandhi 18:6a4db94011d3 38 /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
sahilmgandhi 18:6a4db94011d3 39 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
sahilmgandhi 18:6a4db94011d3 40 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
sahilmgandhi 18:6a4db94011d3 41 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
sahilmgandhi 18:6a4db94011d3 49 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
sahilmgandhi 18:6a4db94011d3 50 /* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
sahilmgandhi 18:6a4db94011d3 51 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
sahilmgandhi 18:6a4db94011d3 52 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
sahilmgandhi 18:6a4db94011d3 53 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
sahilmgandhi 18:6a4db94011d3 54 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
sahilmgandhi 18:6a4db94011d3 55 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
sahilmgandhi 18:6a4db94011d3 56 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
sahilmgandhi 18:6a4db94011d3 57 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
sahilmgandhi 18:6a4db94011d3 58 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
sahilmgandhi 18:6a4db94011d3 59 GINT0_IRQn = 8, /*!< 8 GINT0 */
sahilmgandhi 18:6a4db94011d3 60 GINT1_IRQn = 9, /*!< 9 GINT1 */
sahilmgandhi 18:6a4db94011d3 61 I2C1_IRQn = 10, /*!< 10 I2C1 */
sahilmgandhi 18:6a4db94011d3 62 USART1_4_IRQn = 11, /*!< 11 USART1_4 */
sahilmgandhi 18:6a4db94011d3 63 USART2_3_IRQn = 12, /*!< 12 USART2_3 */
sahilmgandhi 18:6a4db94011d3 64 SCT0_1_IRQn = 13, /*!< 13 SCT0_1 */
sahilmgandhi 18:6a4db94011d3 65 SSP1_IRQn = 14, /*!< 14 SSP1 */
sahilmgandhi 18:6a4db94011d3 66 I2C0_IRQn = 15, /*!< 15 I2C0 */
sahilmgandhi 18:6a4db94011d3 67 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
sahilmgandhi 18:6a4db94011d3 68 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
sahilmgandhi 18:6a4db94011d3 69 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
sahilmgandhi 18:6a4db94011d3 70 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
sahilmgandhi 18:6a4db94011d3 71 SSP0_IRQn = 20, /*!< 20 SSP0 */
sahilmgandhi 18:6a4db94011d3 72 USART0_IRQn = 21, /*!< 21 USART0 */
sahilmgandhi 18:6a4db94011d3 73 USB_IRQn = 22, /*!< 22 USB */
sahilmgandhi 18:6a4db94011d3 74 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
sahilmgandhi 18:6a4db94011d3 75 ADC_A_IRQn = 24, /*!< 24 ADC_A */
sahilmgandhi 18:6a4db94011d3 76 RTC_IRQn = 25, /*!< 25 RTC */
sahilmgandhi 18:6a4db94011d3 77 BOD_WDT_IRQn = 26, /*!< 26 BOD_WDT */
sahilmgandhi 18:6a4db94011d3 78 FLASH_IRQn = 27, /*!< 27 FLASH */
sahilmgandhi 18:6a4db94011d3 79 DMA_IRQn = 28, /*!< 28 DMA */
sahilmgandhi 18:6a4db94011d3 80 ADC_B_IRQn = 29, /*!< 29 ADC_B */
sahilmgandhi 18:6a4db94011d3 81 USBWAKEUP_IRQn = 30 /*!< 30 USBWAKEUP */
sahilmgandhi 18:6a4db94011d3 82 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /** @addtogroup Configuration_of_CMSIS
sahilmgandhi 18:6a4db94011d3 86 * @{
sahilmgandhi 18:6a4db94011d3 87 */
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 91 /* ================ Processor and Core Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 92 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
sahilmgandhi 18:6a4db94011d3 95 #define __CM0PLUS_REV 0x0000 /*!< Cortex-M0PLUS Core Revision */
sahilmgandhi 18:6a4db94011d3 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 97 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 99 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
sahilmgandhi 18:6a4db94011d3 100 /** @} */ /* End of group Configuration_of_CMSIS */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 103 #include "system_LPC11U6x.h" /*!< LPC11U6x System */
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 107 /* ================ Device Specific Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 108 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /** @addtogroup Device_Peripheral_Registers
sahilmgandhi 18:6a4db94011d3 112 * @{
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 /* ------------------- Start of section using anonymous unions ------------------ */
sahilmgandhi 18:6a4db94011d3 117 #if defined(__CC_ARM)
sahilmgandhi 18:6a4db94011d3 118 #pragma push
sahilmgandhi 18:6a4db94011d3 119 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 120 #elif defined(__ICCARM__)
sahilmgandhi 18:6a4db94011d3 121 #pragma language=extended
sahilmgandhi 18:6a4db94011d3 122 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 123 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 124 #elif defined(__TMS470__)
sahilmgandhi 18:6a4db94011d3 125 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 126 #elif defined(__TASKING__)
sahilmgandhi 18:6a4db94011d3 127 #pragma warning 586
sahilmgandhi 18:6a4db94011d3 128 #else
sahilmgandhi 18:6a4db94011d3 129 #warning Not supported compiler type
sahilmgandhi 18:6a4db94011d3 130 #endif
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 135 /* ================ I2C0 ================ */
sahilmgandhi 18:6a4db94011d3 136 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /**
sahilmgandhi 18:6a4db94011d3 140 * @brief I2C-bus controller (I2C0)
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 typedef struct { /*!< I2C0 Structure */
sahilmgandhi 18:6a4db94011d3 144 __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
sahilmgandhi 18:6a4db94011d3 145 this register, the corresponding bit in the I2C control register
sahilmgandhi 18:6a4db94011d3 146 is set. Writing a zero has no effect on the corresponding bit
sahilmgandhi 18:6a4db94011d3 147 in the I2C control register. */
sahilmgandhi 18:6a4db94011d3 148 __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
sahilmgandhi 18:6a4db94011d3 149 detailed status codes that allow software to determine the next
sahilmgandhi 18:6a4db94011d3 150 action needed. */
sahilmgandhi 18:6a4db94011d3 151 __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
sahilmgandhi 18:6a4db94011d3 152 to be transmitted is written to this register. During master
sahilmgandhi 18:6a4db94011d3 153 or slave receive mode, data that has been received may be read
sahilmgandhi 18:6a4db94011d3 154 from this register. */
sahilmgandhi 18:6a4db94011d3 155 __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
sahilmgandhi 18:6a4db94011d3 156 for operation of the I2C interface in slave mode, and is not
sahilmgandhi 18:6a4db94011d3 157 used in master mode. The least significant bit determines whether
sahilmgandhi 18:6a4db94011d3 158 a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 159 __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
sahilmgandhi 18:6a4db94011d3 160 time of the I2C clock. */
sahilmgandhi 18:6a4db94011d3 161 __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
sahilmgandhi 18:6a4db94011d3 162 of the I2C clock. I2nSCLL and I2nSCLH together determine the
sahilmgandhi 18:6a4db94011d3 163 clock frequency generated by an I2C master and certain times
sahilmgandhi 18:6a4db94011d3 164 used in slave mode. */
sahilmgandhi 18:6a4db94011d3 165 __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
sahilmgandhi 18:6a4db94011d3 166 this register, the corresponding bit in the I2C control register
sahilmgandhi 18:6a4db94011d3 167 is cleared. Writing a zero has no effect on the corresponding
sahilmgandhi 18:6a4db94011d3 168 bit in the I2C control register. */
sahilmgandhi 18:6a4db94011d3 169 __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
sahilmgandhi 18:6a4db94011d3 170 __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
sahilmgandhi 18:6a4db94011d3 171 for operation of the I2C interface in slave mode, and is not
sahilmgandhi 18:6a4db94011d3 172 used in master mode. The least significant bit determines whether
sahilmgandhi 18:6a4db94011d3 173 a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 174 __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
sahilmgandhi 18:6a4db94011d3 175 for operation of the I2C interface in slave mode, and is not
sahilmgandhi 18:6a4db94011d3 176 used in master mode. The least significant bit determines whether
sahilmgandhi 18:6a4db94011d3 177 a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 178 __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
sahilmgandhi 18:6a4db94011d3 179 for operation of the I2C interface in slave mode, and is not
sahilmgandhi 18:6a4db94011d3 180 used in master mode. The least significant bit determines whether
sahilmgandhi 18:6a4db94011d3 181 a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 182 __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
sahilmgandhi 18:6a4db94011d3 183 shift register will be transferred to the DATA_BUFFER automatically
sahilmgandhi 18:6a4db94011d3 184 after every nine bits (8 bits of data plus ACK or NACK) has
sahilmgandhi 18:6a4db94011d3 185 been received on the bus. */
sahilmgandhi 18:6a4db94011d3 186 __IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
sahilmgandhi 18:6a4db94011d3 187 with I2ADR0 to determine an address match. The mask register
sahilmgandhi 18:6a4db94011d3 188 has no effect when comparing to the General Call address (0000000). */
sahilmgandhi 18:6a4db94011d3 189 __IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
sahilmgandhi 18:6a4db94011d3 190 with I2ADR0 to determine an address match. The mask register
sahilmgandhi 18:6a4db94011d3 191 has no effect when comparing to the General Call address (0000000). */
sahilmgandhi 18:6a4db94011d3 192 __IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
sahilmgandhi 18:6a4db94011d3 193 with I2ADR0 to determine an address match. The mask register
sahilmgandhi 18:6a4db94011d3 194 has no effect when comparing to the General Call address (0000000). */
sahilmgandhi 18:6a4db94011d3 195 __IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
sahilmgandhi 18:6a4db94011d3 196 with I2ADR0 to determine an address match. The mask register
sahilmgandhi 18:6a4db94011d3 197 has no effect when comparing to the General Call address (0000000). */
sahilmgandhi 18:6a4db94011d3 198 } LPC_I2C0_Type;
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 202 /* ================ WWDT ================ */
sahilmgandhi 18:6a4db94011d3 203 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 /**
sahilmgandhi 18:6a4db94011d3 207 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
sahilmgandhi 18:6a4db94011d3 208 */
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 typedef struct { /*!< WWDT Structure */
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
sahilmgandhi 18:6a4db94011d3 212 and status of the Watchdog Timer. */
sahilmgandhi 18:6a4db94011d3 213 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
sahilmgandhi 18:6a4db94011d3 214 the time-out value. */
sahilmgandhi 18:6a4db94011d3 215 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
sahilmgandhi 18:6a4db94011d3 216 to this register reloads the Watchdog timer with the value contained
sahilmgandhi 18:6a4db94011d3 217 in WDTC. */
sahilmgandhi 18:6a4db94011d3 218 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
sahilmgandhi 18:6a4db94011d3 219 the current value of the Watchdog timer. */
sahilmgandhi 18:6a4db94011d3 220 __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
sahilmgandhi 18:6a4db94011d3 221 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
sahilmgandhi 18:6a4db94011d3 222 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
sahilmgandhi 18:6a4db94011d3 223 } LPC_WWDT_Type;
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 227 /* ================ USART0 ================ */
sahilmgandhi 18:6a4db94011d3 228 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 /**
sahilmgandhi 18:6a4db94011d3 232 * @brief USART0 (USART0)
sahilmgandhi 18:6a4db94011d3 233 */
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 typedef struct { /*!< USART0 Structure */
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 union {
sahilmgandhi 18:6a4db94011d3 238 __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
sahilmgandhi 18:6a4db94011d3 239 value. The full divisor is used to generate a baud rate from
sahilmgandhi 18:6a4db94011d3 240 the fractional rate divider. (DLAB=1) */
sahilmgandhi 18:6a4db94011d3 241 __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
sahilmgandhi 18:6a4db94011d3 242 is written here. (DLAB=0) */
sahilmgandhi 18:6a4db94011d3 243 __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
sahilmgandhi 18:6a4db94011d3 244 to be read. (DLAB=0) */
sahilmgandhi 18:6a4db94011d3 245 };
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 union {
sahilmgandhi 18:6a4db94011d3 248 __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
sahilmgandhi 18:6a4db94011d3 249 bits for the 7 potential USART interrupts. (DLAB=0) */
sahilmgandhi 18:6a4db94011d3 250 __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
sahilmgandhi 18:6a4db94011d3 251 value. The full divisor is used to generate a baud rate from
sahilmgandhi 18:6a4db94011d3 252 the fractional rate divider. (DLAB=1) */
sahilmgandhi 18:6a4db94011d3 253 };
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 union {
sahilmgandhi 18:6a4db94011d3 256 __O uint32_t FCR; /*!< FIFO Control Register. Controls USART FIFO usage and modes. */
sahilmgandhi 18:6a4db94011d3 257 __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
sahilmgandhi 18:6a4db94011d3 258 };
sahilmgandhi 18:6a4db94011d3 259 __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
sahilmgandhi 18:6a4db94011d3 260 and break generation. */
sahilmgandhi 18:6a4db94011d3 261 __IO uint32_t MCR; /*!< Modem Control Register. */
sahilmgandhi 18:6a4db94011d3 262 __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
sahilmgandhi 18:6a4db94011d3 263 status, including line errors. */
sahilmgandhi 18:6a4db94011d3 264 __I uint32_t MSR; /*!< Modem Status Register. */
sahilmgandhi 18:6a4db94011d3 265 __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
sahilmgandhi 18:6a4db94011d3 266 __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
sahilmgandhi 18:6a4db94011d3 267 feature. */
sahilmgandhi 18:6a4db94011d3 268 __IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
sahilmgandhi 18:6a4db94011d3 269 control) mode. */
sahilmgandhi 18:6a4db94011d3 270 __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
sahilmgandhi 18:6a4db94011d3 271 baud rate divider. */
sahilmgandhi 18:6a4db94011d3 272 __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
sahilmgandhi 18:6a4db94011d3 273 each bit time. */
sahilmgandhi 18:6a4db94011d3 274 __IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
sahilmgandhi 18:6a4db94011d3 275 with software flow control. */
sahilmgandhi 18:6a4db94011d3 276 __I uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 277 __IO uint32_t HDEN; /*!< Half duplex enable register. */
sahilmgandhi 18:6a4db94011d3 278 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
sahilmgandhi 18:6a4db94011d3 280 the Smart Card Interface feature. */
sahilmgandhi 18:6a4db94011d3 281 __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
sahilmgandhi 18:6a4db94011d3 282 aspects of RS-485/EIA-485 modes. */
sahilmgandhi 18:6a4db94011d3 283 __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
sahilmgandhi 18:6a4db94011d3 284 for RS-485/EIA-485 mode. */
sahilmgandhi 18:6a4db94011d3 285 __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
sahilmgandhi 18:6a4db94011d3 286 __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. */
sahilmgandhi 18:6a4db94011d3 287 } LPC_USART0_Type;
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 291 /* ================ CT16B0 ================ */
sahilmgandhi 18:6a4db94011d3 292 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /**
sahilmgandhi 18:6a4db94011d3 296 * @brief 16-bit counter/timers CT16B0 (CT16B0)
sahilmgandhi 18:6a4db94011d3 297 */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 typedef struct { /*!< CT16B0 Structure */
sahilmgandhi 18:6a4db94011d3 300 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
sahilmgandhi 18:6a4db94011d3 301 The IR can be read to identify which of eight possible interrupt
sahilmgandhi 18:6a4db94011d3 302 sources are pending. */
sahilmgandhi 18:6a4db94011d3 303 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
sahilmgandhi 18:6a4db94011d3 304 Counter functions. The Timer Counter can be disabled or reset
sahilmgandhi 18:6a4db94011d3 305 through the TCR. */
sahilmgandhi 18:6a4db94011d3 306 __IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
sahilmgandhi 18:6a4db94011d3 307 of PCLK. The TC is controlled through the TCR. */
sahilmgandhi 18:6a4db94011d3 308 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
sahilmgandhi 18:6a4db94011d3 309 to this value, the next clock increments the TC and clears the
sahilmgandhi 18:6a4db94011d3 310 PC. */
sahilmgandhi 18:6a4db94011d3 311 __IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
sahilmgandhi 18:6a4db94011d3 312 to the value stored in PR. When the value in PR is reached,
sahilmgandhi 18:6a4db94011d3 313 the TC is incremented and the PC is cleared. The PC is observable
sahilmgandhi 18:6a4db94011d3 314 and controllable through the bus interface. */
sahilmgandhi 18:6a4db94011d3 315 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
sahilmgandhi 18:6a4db94011d3 316 is generated and if the TC is reset when a Match occurs. */
sahilmgandhi 18:6a4db94011d3 317 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
sahilmgandhi 18:6a4db94011d3 318 TC, stop both the TC and PC, and/or generate an interrupt every
sahilmgandhi 18:6a4db94011d3 319 time MR0 matches the TC. */
sahilmgandhi 18:6a4db94011d3 320 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
sahilmgandhi 18:6a4db94011d3 321 TC, stop both the TC and PC, and/or generate an interrupt every
sahilmgandhi 18:6a4db94011d3 322 time MR0 matches the TC. */
sahilmgandhi 18:6a4db94011d3 323 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
sahilmgandhi 18:6a4db94011d3 324 TC, stop both the TC and PC, and/or generate an interrupt every
sahilmgandhi 18:6a4db94011d3 325 time MR0 matches the TC. */
sahilmgandhi 18:6a4db94011d3 326 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
sahilmgandhi 18:6a4db94011d3 327 TC, stop both the TC and PC, and/or generate an interrupt every
sahilmgandhi 18:6a4db94011d3 328 time MR0 matches the TC. */
sahilmgandhi 18:6a4db94011d3 329 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
sahilmgandhi 18:6a4db94011d3 330 capture inputs are used to load the Capture Registers and whether
sahilmgandhi 18:6a4db94011d3 331 or not an interrupt is generated when a capture takes place. */
sahilmgandhi 18:6a4db94011d3 332 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
sahilmgandhi 18:6a4db94011d3 333 is an event on the CAP input. */
sahilmgandhi 18:6a4db94011d3 334 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
sahilmgandhi 18:6a4db94011d3 335 is an event on the CAP input. */
sahilmgandhi 18:6a4db94011d3 336 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
sahilmgandhi 18:6a4db94011d3 337 is an event on the CAP input. */
sahilmgandhi 18:6a4db94011d3 338 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 339 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
sahilmgandhi 18:6a4db94011d3 340 and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
sahilmgandhi 18:6a4db94011d3 341 __I uint32_t RESERVED1[12];
sahilmgandhi 18:6a4db94011d3 342 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
sahilmgandhi 18:6a4db94011d3 343 mode, and in Counter mode selects the signal and edge(s) for
sahilmgandhi 18:6a4db94011d3 344 counting. */
sahilmgandhi 18:6a4db94011d3 345 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
sahilmgandhi 18:6a4db94011d3 346 match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
sahilmgandhi 18:6a4db94011d3 347 } LPC_CT16B0_Type;
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 351 /* ================ CT32B0 ================ */
sahilmgandhi 18:6a4db94011d3 352 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 /**
sahilmgandhi 18:6a4db94011d3 356 * @brief 32-bit counter/timers CT32B0 (CT32B0)
sahilmgandhi 18:6a4db94011d3 357 */
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 typedef struct { /*!< CT32B0 Structure */
sahilmgandhi 18:6a4db94011d3 360 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
sahilmgandhi 18:6a4db94011d3 361 The IR can be read to identify which of eight possible interrupt
sahilmgandhi 18:6a4db94011d3 362 sources are pending. */
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
sahilmgandhi 18:6a4db94011d3 364 Counter functions. The Timer Counter can be disabled or reset
sahilmgandhi 18:6a4db94011d3 365 through the TCR. */
sahilmgandhi 18:6a4db94011d3 366 __IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
sahilmgandhi 18:6a4db94011d3 367 of PCLK. The TC is controlled through the TCR. */
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
sahilmgandhi 18:6a4db94011d3 369 to this value, the next clock increments the TC and clears the
sahilmgandhi 18:6a4db94011d3 370 PC. */
sahilmgandhi 18:6a4db94011d3 371 __IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
sahilmgandhi 18:6a4db94011d3 372 to the value stored in PR. When the value in PR is reached,
sahilmgandhi 18:6a4db94011d3 373 the TC is incremented and the PC is cleared. The PC is observable
sahilmgandhi 18:6a4db94011d3 374 and controllable through the bus interface. */
sahilmgandhi 18:6a4db94011d3 375 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
sahilmgandhi 18:6a4db94011d3 376 is generated and if the TC is reset when a Match occurs. */
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
sahilmgandhi 18:6a4db94011d3 378 TC, stop both the TC and PC, and/or generate an interrupt every
sahilmgandhi 18:6a4db94011d3 379 time MR0 matches the TC. */
sahilmgandhi 18:6a4db94011d3 380 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
sahilmgandhi 18:6a4db94011d3 381 TC, stop both the TC and PC, and/or generate an interrupt every
sahilmgandhi 18:6a4db94011d3 382 time MR0 matches the TC. */
sahilmgandhi 18:6a4db94011d3 383 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
sahilmgandhi 18:6a4db94011d3 384 TC, stop both the TC and PC, and/or generate an interrupt every
sahilmgandhi 18:6a4db94011d3 385 time MR0 matches the TC. */
sahilmgandhi 18:6a4db94011d3 386 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
sahilmgandhi 18:6a4db94011d3 387 TC, stop both the TC and PC, and/or generate an interrupt every
sahilmgandhi 18:6a4db94011d3 388 time MR0 matches the TC. */
sahilmgandhi 18:6a4db94011d3 389 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
sahilmgandhi 18:6a4db94011d3 390 capture inputs are used to load the Capture Registers and whether
sahilmgandhi 18:6a4db94011d3 391 or not an interrupt is generated when a capture takes place. */
sahilmgandhi 18:6a4db94011d3 392 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
sahilmgandhi 18:6a4db94011d3 393 is an event on the CAP input. */
sahilmgandhi 18:6a4db94011d3 394 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
sahilmgandhi 18:6a4db94011d3 395 is an event on the CAP input. */
sahilmgandhi 18:6a4db94011d3 396 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
sahilmgandhi 18:6a4db94011d3 397 is an event on the CAP input. */
sahilmgandhi 18:6a4db94011d3 398 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 399 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
sahilmgandhi 18:6a4db94011d3 400 and the external match pins CT32Bn_MAT[3:0]. */
sahilmgandhi 18:6a4db94011d3 401 __I uint32_t RESERVED1[12];
sahilmgandhi 18:6a4db94011d3 402 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
sahilmgandhi 18:6a4db94011d3 403 mode, and in Counter mode selects the signal and edge(s) for
sahilmgandhi 18:6a4db94011d3 404 counting. */
sahilmgandhi 18:6a4db94011d3 405 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
sahilmgandhi 18:6a4db94011d3 406 match pins CT32Bn_MAT[3:0]. */
sahilmgandhi 18:6a4db94011d3 407 } LPC_CT32B0_Type;
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 411 /* ================ ADC ================ */
sahilmgandhi 18:6a4db94011d3 412 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 /**
sahilmgandhi 18:6a4db94011d3 416 * @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
sahilmgandhi 18:6a4db94011d3 417 */
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 typedef struct { /*!< ADC Structure */
sahilmgandhi 18:6a4db94011d3 420 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
sahilmgandhi 18:6a4db94011d3 421 bits for each sequence and the A/D power-down bit. */
sahilmgandhi 18:6a4db94011d3 422 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 423 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
sahilmgandhi 18:6a4db94011d3 424 and channel selection for conversion sequence-A. Also specifies
sahilmgandhi 18:6a4db94011d3 425 interrupt mode for sequence-A. */
sahilmgandhi 18:6a4db94011d3 426 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
sahilmgandhi 18:6a4db94011d3 427 and channel selection for conversion sequence-B. Also specifies
sahilmgandhi 18:6a4db94011d3 428 interrupt mode for sequence-B. */
sahilmgandhi 18:6a4db94011d3 429 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
sahilmgandhi 18:6a4db94011d3 430 the result of the most recent A/D conversion performed under
sahilmgandhi 18:6a4db94011d3 431 sequence-A */
sahilmgandhi 18:6a4db94011d3 432 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
sahilmgandhi 18:6a4db94011d3 433 the result of the most recent A/D conversion performed under
sahilmgandhi 18:6a4db94011d3 434 sequence-B */
sahilmgandhi 18:6a4db94011d3 435 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 436 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
sahilmgandhi 18:6a4db94011d3 437 of the most recent conversion completed on channel 0. */
sahilmgandhi 18:6a4db94011d3 438 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
sahilmgandhi 18:6a4db94011d3 439 level for automatic threshold comparison for any channels linked
sahilmgandhi 18:6a4db94011d3 440 to threshold pair 0. */
sahilmgandhi 18:6a4db94011d3 441 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
sahilmgandhi 18:6a4db94011d3 442 level for automatic threshold comparison for any channels linked
sahilmgandhi 18:6a4db94011d3 443 to threshold pair 1. */
sahilmgandhi 18:6a4db94011d3 444 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
sahilmgandhi 18:6a4db94011d3 445 level for automatic threshold comparison for any channels linked
sahilmgandhi 18:6a4db94011d3 446 to threshold pair 0. */
sahilmgandhi 18:6a4db94011d3 447 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
sahilmgandhi 18:6a4db94011d3 448 level for automatic threshold comparison for any channels linked
sahilmgandhi 18:6a4db94011d3 449 to threshold pair 1. */
sahilmgandhi 18:6a4db94011d3 450 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
sahilmgandhi 18:6a4db94011d3 451 threshold compare registers are to be used for each channel */
sahilmgandhi 18:6a4db94011d3 452 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
sahilmgandhi 18:6a4db94011d3 453 bits that enable the sequence-A, sequence-B, threshold compare
sahilmgandhi 18:6a4db94011d3 454 and data overrun interrupts to be generated. */
sahilmgandhi 18:6a4db94011d3 455 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
sahilmgandhi 18:6a4db94011d3 456 and the individual component overrun and threshold-compare flags.
sahilmgandhi 18:6a4db94011d3 457 (The overrun bits replicate information stored in the result
sahilmgandhi 18:6a4db94011d3 458 registers). */
sahilmgandhi 18:6a4db94011d3 459 __IO uint32_t TRM; /*!< ADC trim register. */
sahilmgandhi 18:6a4db94011d3 460 } LPC_ADC_Type;
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 464 /* ================ RTC ================ */
sahilmgandhi 18:6a4db94011d3 465 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 /**
sahilmgandhi 18:6a4db94011d3 469 * @brief Real-Time Clock (RTC) (RTC)
sahilmgandhi 18:6a4db94011d3 470 */
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 typedef struct { /*!< RTC Structure */
sahilmgandhi 18:6a4db94011d3 473 __IO uint32_t CTRL; /*!< RTC control register */
sahilmgandhi 18:6a4db94011d3 474 __IO uint32_t MATCH; /*!< RTC match register */
sahilmgandhi 18:6a4db94011d3 475 __IO uint32_t COUNT; /*!< RTC counter register */
sahilmgandhi 18:6a4db94011d3 476 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
sahilmgandhi 18:6a4db94011d3 477 } LPC_RTC_Type;
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 481 /* ================ DMATRIGMUX ================ */
sahilmgandhi 18:6a4db94011d3 482 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 /**
sahilmgandhi 18:6a4db94011d3 486 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
sahilmgandhi 18:6a4db94011d3 487 */
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 typedef struct { /*!< DMATRIGMUX Structure */
sahilmgandhi 18:6a4db94011d3 490 __IO uint32_t DMA_ITRIG_PINMUX[16]; /*!< Trigger input select register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 491 } LPC_DMATRIGMUX_Type;
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 495 /* ================ PMU ================ */
sahilmgandhi 18:6a4db94011d3 496 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 /**
sahilmgandhi 18:6a4db94011d3 500 * @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
sahilmgandhi 18:6a4db94011d3 501 */
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 typedef struct { /*!< PMU Structure */
sahilmgandhi 18:6a4db94011d3 504 __IO uint32_t PCON; /*!< Power control register */
sahilmgandhi 18:6a4db94011d3 505 __IO uint32_t GPREG0; /*!< General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 506 __IO uint32_t GPREG1; /*!< General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 507 __IO uint32_t GPREG2; /*!< General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 508 __IO uint32_t GPREG3; /*!< General purpose register 0 */
sahilmgandhi 18:6a4db94011d3 509 __IO uint32_t DPDCTRL; /*!< Deep power down control register */
sahilmgandhi 18:6a4db94011d3 510 } LPC_PMU_Type;
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 514 /* ================ FLASHCTRL ================ */
sahilmgandhi 18:6a4db94011d3 515 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 516
sahilmgandhi 18:6a4db94011d3 517
sahilmgandhi 18:6a4db94011d3 518 /**
sahilmgandhi 18:6a4db94011d3 519 * @brief Flash controller (FLASHCTRL)
sahilmgandhi 18:6a4db94011d3 520 */
sahilmgandhi 18:6a4db94011d3 521
sahilmgandhi 18:6a4db94011d3 522 typedef struct { /*!< FLASHCTRL Structure */
sahilmgandhi 18:6a4db94011d3 523 __I uint32_t RESERVED0[4];
sahilmgandhi 18:6a4db94011d3 524 __IO uint32_t FLASHCFG; /*!< Flash configuration register */
sahilmgandhi 18:6a4db94011d3 525 __I uint32_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 526 __IO uint32_t FMSSTART; /*!< Signature start address register */
sahilmgandhi 18:6a4db94011d3 527 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
sahilmgandhi 18:6a4db94011d3 528 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 529 __I uint32_t FMSW0; /*!< Signature Word */
sahilmgandhi 18:6a4db94011d3 530 } LPC_FLASHCTRL_Type;
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 534 /* ================ SSP0 ================ */
sahilmgandhi 18:6a4db94011d3 535 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 536
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 /**
sahilmgandhi 18:6a4db94011d3 539 * @brief SSP/SPI (SSP0)
sahilmgandhi 18:6a4db94011d3 540 */
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 typedef struct { /*!< SSP0 Structure */
sahilmgandhi 18:6a4db94011d3 543 __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
sahilmgandhi 18:6a4db94011d3 544 and data size. */
sahilmgandhi 18:6a4db94011d3 545 __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
sahilmgandhi 18:6a4db94011d3 546 __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
sahilmgandhi 18:6a4db94011d3 547 the receive FIFO. */
sahilmgandhi 18:6a4db94011d3 548 __I uint32_t SR; /*!< Status Register */
sahilmgandhi 18:6a4db94011d3 549 __IO uint32_t CPSR; /*!< Clock Prescale Register */
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
sahilmgandhi 18:6a4db94011d3 551 __I uint32_t RIS; /*!< Raw Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 552 __I uint32_t MIS; /*!< Masked Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 553 __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
sahilmgandhi 18:6a4db94011d3 554 } LPC_SSP0_Type;
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556
sahilmgandhi 18:6a4db94011d3 557 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 558 /* ================ IOCON ================ */
sahilmgandhi 18:6a4db94011d3 559 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 /**
sahilmgandhi 18:6a4db94011d3 563 * @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
sahilmgandhi 18:6a4db94011d3 564 */
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 typedef struct { /*!< IOCON Structure */
sahilmgandhi 18:6a4db94011d3 567 __IO uint32_t PIO0_0; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 568 __IO uint32_t PIO0_1; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 569 __IO uint32_t PIO0_2; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 570 __IO uint32_t PIO0_3; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 571 __IO uint32_t PIO0_4; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 572 __IO uint32_t PIO0_5; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 573 __IO uint32_t PIO0_6; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 574 __IO uint32_t PIO0_7; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 575 __IO uint32_t PIO0_8; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 576 __IO uint32_t PIO0_9; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 577 __IO uint32_t PIO0_10; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t PIO0_11; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 579 __IO uint32_t PIO0_12; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t PIO0_13; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 581 __IO uint32_t PIO0_14; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 582 __IO uint32_t PIO0_15; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 583 __IO uint32_t PIO0_16; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t PIO0_17; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 585 __IO uint32_t PIO0_18; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 586 __IO uint32_t PIO0_19; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t PIO0_20; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 588 __IO uint32_t PIO0_21; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 589 __IO uint32_t PIO0_22; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 590 __IO uint32_t PIO0_23; /*!< I/O configuration for port PIO0 */
sahilmgandhi 18:6a4db94011d3 591 __IO uint32_t PIO1_0; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 592 __IO uint32_t PIO1_1; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 593 __IO uint32_t PIO1_2; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 594 __IO uint32_t PIO1_3; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 595 __IO uint32_t PIO1_4; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 596 __IO uint32_t PIO1_5; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 597 __IO uint32_t PIO1_6; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 598 __IO uint32_t PIO1_7; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 599 __IO uint32_t PIO1_8; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 600 __IO uint32_t PIO1_9; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 601 __IO uint32_t PIO1_10; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 602 __IO uint32_t PIO1_11; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 603 __IO uint32_t PIO1_12; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 604 __IO uint32_t PIO1_13; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 605 __IO uint32_t PIO1_14; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 606 __IO uint32_t PIO1_15; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 607 __IO uint32_t PIO1_16; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 608 __IO uint32_t PIO1_17; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 609 __IO uint32_t PIO1_18; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 610 __IO uint32_t PIO1_19; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 611 __IO uint32_t PIO1_20; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 612 __IO uint32_t PIO1_21; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 613 __IO uint32_t PIO1_22; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 614 __IO uint32_t PIO1_23; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 615 __IO uint32_t PIO1_24; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 616 __IO uint32_t PIO1_25; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 617 __IO uint32_t PIO1_26; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 618 __IO uint32_t PIO1_27; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 619 __IO uint32_t PIO1_28; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 620 __IO uint32_t PIO1_29; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 621 __IO uint32_t PIO1_30; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 622 __IO uint32_t PIO1_31; /*!< I/O configuration for port PIO1 */
sahilmgandhi 18:6a4db94011d3 623 __I uint32_t RESERVED0[4];
sahilmgandhi 18:6a4db94011d3 624 __IO uint32_t PIO2_0; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 625 __IO uint32_t PIO2_1; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 626 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 627 __IO uint32_t PIO2_2; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 628 __IO uint32_t PIO2_3; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 629 __IO uint32_t PIO2_4; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 630 __IO uint32_t PIO2_5; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 631 __IO uint32_t PIO2_6; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 632 __IO uint32_t PIO2_7; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 633 __IO uint32_t PIO2_8; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 634 __IO uint32_t PIO2_9; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 635 __IO uint32_t PIO2_10; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 636 __IO uint32_t PIO2_11; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 637 __IO uint32_t PIO2_12; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 638 __IO uint32_t PIO2_13; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 639 __IO uint32_t PIO2_14; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 640 __IO uint32_t PIO2_15; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 641 __IO uint32_t PIO2_16; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 642 __IO uint32_t PIO2_17; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 643 __IO uint32_t PIO2_18; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 644 __IO uint32_t PIO2_19; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 645 __IO uint32_t PIO2_20; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 646 __IO uint32_t PIO2_21; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 647 __IO uint32_t PIO2_22; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 648 __IO uint32_t PIO2_23; /*!< I/O configuration for port PIO2 */
sahilmgandhi 18:6a4db94011d3 649 } LPC_IOCON_Type;
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 653 /* ================ SYSCON ================ */
sahilmgandhi 18:6a4db94011d3 654 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657 /**
sahilmgandhi 18:6a4db94011d3 658 * @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
sahilmgandhi 18:6a4db94011d3 659 */
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 typedef struct { /*!< SYSCON Structure */
sahilmgandhi 18:6a4db94011d3 662 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
sahilmgandhi 18:6a4db94011d3 663 __IO uint32_t PRESETCTRL; /*!< Peripheral reset control */
sahilmgandhi 18:6a4db94011d3 664 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
sahilmgandhi 18:6a4db94011d3 665 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
sahilmgandhi 18:6a4db94011d3 666 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
sahilmgandhi 18:6a4db94011d3 667 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
sahilmgandhi 18:6a4db94011d3 668 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 669 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator 32 kHz output control */
sahilmgandhi 18:6a4db94011d3 670 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
sahilmgandhi 18:6a4db94011d3 671 __IO uint32_t WDTOSCCTRL; /*!< Watchdog oscillator control */
sahilmgandhi 18:6a4db94011d3 672 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 673 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
sahilmgandhi 18:6a4db94011d3 674 __I uint32_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 675 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
sahilmgandhi 18:6a4db94011d3 676 __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable */
sahilmgandhi 18:6a4db94011d3 677 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
sahilmgandhi 18:6a4db94011d3 678 __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable */
sahilmgandhi 18:6a4db94011d3 679 __I uint32_t RESERVED3[8];
sahilmgandhi 18:6a4db94011d3 680 __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
sahilmgandhi 18:6a4db94011d3 681 __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable */
sahilmgandhi 18:6a4db94011d3 682 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
sahilmgandhi 18:6a4db94011d3 683 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 684 __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control */
sahilmgandhi 18:6a4db94011d3 685 __I uint32_t RESERVED5[4];
sahilmgandhi 18:6a4db94011d3 686 __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider */
sahilmgandhi 18:6a4db94011d3 687 __IO uint32_t USART0CLKDIV; /*!< USART0 clock divider */
sahilmgandhi 18:6a4db94011d3 688 __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider */
sahilmgandhi 18:6a4db94011d3 689 __IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
sahilmgandhi 18:6a4db94011d3 690 of USART1 to USART4 */
sahilmgandhi 18:6a4db94011d3 691 __I uint32_t RESERVED6[7];
sahilmgandhi 18:6a4db94011d3 692 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
sahilmgandhi 18:6a4db94011d3 693 __IO uint32_t USBCLKUEN; /*!< USB clock source update enable */
sahilmgandhi 18:6a4db94011d3 694 __IO uint32_t USBCLKDIV; /*!< USB clock source divider */
sahilmgandhi 18:6a4db94011d3 695 __I uint32_t RESERVED7[5];
sahilmgandhi 18:6a4db94011d3 696 __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
sahilmgandhi 18:6a4db94011d3 697 __IO uint32_t CLKOUTUEN; /*!< CLKOUT clock source update enable */
sahilmgandhi 18:6a4db94011d3 698 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
sahilmgandhi 18:6a4db94011d3 699 __I uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 700 __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider value */
sahilmgandhi 18:6a4db94011d3 701 __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier value */
sahilmgandhi 18:6a4db94011d3 702 __I uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 703 __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
sahilmgandhi 18:6a4db94011d3 704 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
sahilmgandhi 18:6a4db94011d3 705 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
sahilmgandhi 18:6a4db94011d3 706 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 1 */
sahilmgandhi 18:6a4db94011d3 707 __I uint32_t RESERVED10[10];
sahilmgandhi 18:6a4db94011d3 708 __IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
sahilmgandhi 18:6a4db94011d3 709 filter */
sahilmgandhi 18:6a4db94011d3 710 __IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
sahilmgandhi 18:6a4db94011d3 711 filter */
sahilmgandhi 18:6a4db94011d3 712 __IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
sahilmgandhi 18:6a4db94011d3 713 filter */
sahilmgandhi 18:6a4db94011d3 714 __IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
sahilmgandhi 18:6a4db94011d3 715 filter */
sahilmgandhi 18:6a4db94011d3 716 __IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
sahilmgandhi 18:6a4db94011d3 717 filter */
sahilmgandhi 18:6a4db94011d3 718 __IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
sahilmgandhi 18:6a4db94011d3 719 filter */
sahilmgandhi 18:6a4db94011d3 720 __IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
sahilmgandhi 18:6a4db94011d3 721 filter */
sahilmgandhi 18:6a4db94011d3 722 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
sahilmgandhi 18:6a4db94011d3 723 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
sahilmgandhi 18:6a4db94011d3 724 __IO uint32_t AHBMATRIXPRIO; /*!< AHB matrix priority configuration */
sahilmgandhi 18:6a4db94011d3 725 __I uint32_t RESERVED11[5];
sahilmgandhi 18:6a4db94011d3 726 __IO uint32_t IRQLATENCY; /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
sahilmgandhi 18:6a4db94011d3 727 __IO uint32_t NMISRC; /*!< NMI Source Control */
sahilmgandhi 18:6a4db94011d3 728 union {
sahilmgandhi 18:6a4db94011d3 729 __IO uint32_t PINTSEL[8];
sahilmgandhi 18:6a4db94011d3 730 struct {
sahilmgandhi 18:6a4db94011d3 731 __IO uint32_t PINTSEL0; /*!< GPIO Pin Interrupt Select register 0 */
sahilmgandhi 18:6a4db94011d3 732 __IO uint32_t PINTSEL1; /*!< GPIO Pin Interrupt Select register 0 */
sahilmgandhi 18:6a4db94011d3 733 __IO uint32_t PINTSEL2; /*!< GPIO Pin Interrupt Select register 0 */
sahilmgandhi 18:6a4db94011d3 734 __IO uint32_t PINTSEL3; /*!< GPIO Pin Interrupt Select register 0 */
sahilmgandhi 18:6a4db94011d3 735 __IO uint32_t PINTSEL4; /*!< GPIO Pin Interrupt Select register 0 */
sahilmgandhi 18:6a4db94011d3 736 __IO uint32_t PINTSEL5; /*!< GPIO Pin Interrupt Select register 0 */
sahilmgandhi 18:6a4db94011d3 737 __IO uint32_t PINTSEL6; /*!< GPIO Pin Interrupt Select register 0 */
sahilmgandhi 18:6a4db94011d3 738 __IO uint32_t PINTSEL7; /*!< GPIO Pin Interrupt Select register 0 */
sahilmgandhi 18:6a4db94011d3 739 };
sahilmgandhi 18:6a4db94011d3 740 };
sahilmgandhi 18:6a4db94011d3 741 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
sahilmgandhi 18:6a4db94011d3 742 __I uint32_t USBCLKST; /*!< USB clock status */
sahilmgandhi 18:6a4db94011d3 743 __I uint32_t RESERVED12[25];
sahilmgandhi 18:6a4db94011d3 744 __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register 0 */
sahilmgandhi 18:6a4db94011d3 745 __I uint32_t RESERVED13[3];
sahilmgandhi 18:6a4db94011d3 746 __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register 1 */
sahilmgandhi 18:6a4db94011d3 747 __I uint32_t RESERVED14[6];
sahilmgandhi 18:6a4db94011d3 748 __IO uint32_t PDSLEEPCFG; /*!< Power-down states in deep-sleep mode */
sahilmgandhi 18:6a4db94011d3 749 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
sahilmgandhi 18:6a4db94011d3 750 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
sahilmgandhi 18:6a4db94011d3 751 __I uint32_t RESERVED15[110];
sahilmgandhi 18:6a4db94011d3 752 __I uint32_t DEVICE_ID; /*!< Device ID */
sahilmgandhi 18:6a4db94011d3 753 } LPC_SYSCON_Type;
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755
sahilmgandhi 18:6a4db94011d3 756 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 757 /* ================ USART4 ================ */
sahilmgandhi 18:6a4db94011d3 758 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 759
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 /**
sahilmgandhi 18:6a4db94011d3 762 * @brief USART4 (USART4)
sahilmgandhi 18:6a4db94011d3 763 */
sahilmgandhi 18:6a4db94011d3 764
sahilmgandhi 18:6a4db94011d3 765 typedef struct { /*!< USART4 Structure */
sahilmgandhi 18:6a4db94011d3 766 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
sahilmgandhi 18:6a4db94011d3 767 that typically are not changed during operation. */
sahilmgandhi 18:6a4db94011d3 768 __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
sahilmgandhi 18:6a4db94011d3 769 likely to change during operation. */
sahilmgandhi 18:6a4db94011d3 770 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
sahilmgandhi 18:6a4db94011d3 771 here. Writing ones clears some bits in the register. Some bits
sahilmgandhi 18:6a4db94011d3 772 can be cleared by writing a 1 to them. */
sahilmgandhi 18:6a4db94011d3 773 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
sahilmgandhi 18:6a4db94011d3 774 interrupt enable bit for each potential USART interrupt. A complete
sahilmgandhi 18:6a4db94011d3 775 value may be read from this register. Writing a 1 to any implemented
sahilmgandhi 18:6a4db94011d3 776 bit position causes that bit to be set. */
sahilmgandhi 18:6a4db94011d3 777 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
sahilmgandhi 18:6a4db94011d3 778 of bits in the INTENSET register. Writing a 1 to any implemented
sahilmgandhi 18:6a4db94011d3 779 bit position causes the corresponding bit to be cleared. */
sahilmgandhi 18:6a4db94011d3 780 __I uint32_t RXDAT; /*!< Receiver Data register. Contains the last character received. */
sahilmgandhi 18:6a4db94011d3 781 __I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
sahilmgandhi 18:6a4db94011d3 782 received with the current USART receive status. Allows DMA or
sahilmgandhi 18:6a4db94011d3 783 software to recover incoming data and status together. */
sahilmgandhi 18:6a4db94011d3 784 __IO uint32_t TXDAT; /*!< Transmit Data register. Data to be transmitted is written here. */
sahilmgandhi 18:6a4db94011d3 785 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
sahilmgandhi 18:6a4db94011d3 786 value. */
sahilmgandhi 18:6a4db94011d3 787 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
sahilmgandhi 18:6a4db94011d3 788 enabled. */
sahilmgandhi 18:6a4db94011d3 789 __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
sahilmgandhi 18:6a4db94011d3 790 __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
sahilmgandhi 18:6a4db94011d3 791 } LPC_USART4_Type;
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793
sahilmgandhi 18:6a4db94011d3 794 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 795 /* ================ GINT0 ================ */
sahilmgandhi 18:6a4db94011d3 796 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 797
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 /**
sahilmgandhi 18:6a4db94011d3 800 * @brief GPIO group interrupt 0 (GINT0)
sahilmgandhi 18:6a4db94011d3 801 */
sahilmgandhi 18:6a4db94011d3 802
sahilmgandhi 18:6a4db94011d3 803 typedef struct { /*!< GINT0 Structure */
sahilmgandhi 18:6a4db94011d3 804 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
sahilmgandhi 18:6a4db94011d3 805 __I uint32_t RESERVED0[7];
sahilmgandhi 18:6a4db94011d3 806 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
sahilmgandhi 18:6a4db94011d3 807 __I uint32_t RESERVED1[5];
sahilmgandhi 18:6a4db94011d3 808 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port enable register */
sahilmgandhi 18:6a4db94011d3 809 } LPC_GINT0_Type;
sahilmgandhi 18:6a4db94011d3 810
sahilmgandhi 18:6a4db94011d3 811
sahilmgandhi 18:6a4db94011d3 812 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 813 /* ================ USB ================ */
sahilmgandhi 18:6a4db94011d3 814 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816
sahilmgandhi 18:6a4db94011d3 817 /**
sahilmgandhi 18:6a4db94011d3 818 * @brief USB device controller (USB)
sahilmgandhi 18:6a4db94011d3 819 */
sahilmgandhi 18:6a4db94011d3 820
sahilmgandhi 18:6a4db94011d3 821 typedef struct { /*!< USB Structure */
sahilmgandhi 18:6a4db94011d3 822 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
sahilmgandhi 18:6a4db94011d3 823 __IO uint32_t INFO; /*!< USB Info register */
sahilmgandhi 18:6a4db94011d3 824 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
sahilmgandhi 18:6a4db94011d3 825 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
sahilmgandhi 18:6a4db94011d3 826 __IO uint32_t LPM; /*!< Link Power Management register */
sahilmgandhi 18:6a4db94011d3 827 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
sahilmgandhi 18:6a4db94011d3 828 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
sahilmgandhi 18:6a4db94011d3 829 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
sahilmgandhi 18:6a4db94011d3 830 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
sahilmgandhi 18:6a4db94011d3 831 __IO uint32_t INTEN; /*!< USB interrupt enable register */
sahilmgandhi 18:6a4db94011d3 832 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
sahilmgandhi 18:6a4db94011d3 833 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
sahilmgandhi 18:6a4db94011d3 834 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 835 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
sahilmgandhi 18:6a4db94011d3 836 } LPC_USB_Type;
sahilmgandhi 18:6a4db94011d3 837
sahilmgandhi 18:6a4db94011d3 838
sahilmgandhi 18:6a4db94011d3 839 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 840 /* ================ CRC ================ */
sahilmgandhi 18:6a4db94011d3 841 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 842
sahilmgandhi 18:6a4db94011d3 843
sahilmgandhi 18:6a4db94011d3 844 /**
sahilmgandhi 18:6a4db94011d3 845 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
sahilmgandhi 18:6a4db94011d3 846 */
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 typedef struct { /*!< CRC Structure */
sahilmgandhi 18:6a4db94011d3 849 __IO uint32_t MODE; /*!< CRC mode register */
sahilmgandhi 18:6a4db94011d3 850 __IO uint32_t SEED; /*!< CRC seed register */
sahilmgandhi 18:6a4db94011d3 851
sahilmgandhi 18:6a4db94011d3 852 union {
sahilmgandhi 18:6a4db94011d3 853 __O uint32_t WR_DATA; /*!< CRC data register */
sahilmgandhi 18:6a4db94011d3 854 __I uint32_t SUM; /*!< CRC checksum register */
sahilmgandhi 18:6a4db94011d3 855 };
sahilmgandhi 18:6a4db94011d3 856 } LPC_CRC_Type;
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858
sahilmgandhi 18:6a4db94011d3 859 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 860 /* ================ DMA ================ */
sahilmgandhi 18:6a4db94011d3 861 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 862
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 /**
sahilmgandhi 18:6a4db94011d3 865 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
sahilmgandhi 18:6a4db94011d3 866 */
sahilmgandhi 18:6a4db94011d3 867
sahilmgandhi 18:6a4db94011d3 868 typedef struct { /*!< DMA Structure */
sahilmgandhi 18:6a4db94011d3 869 __IO uint32_t CTRL; /*!< DMA control. */
sahilmgandhi 18:6a4db94011d3 870 __I uint32_t INTSTAT; /*!< Interrupt status. */
sahilmgandhi 18:6a4db94011d3 871 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
sahilmgandhi 18:6a4db94011d3 872 __I uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 873 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 874 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 875 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 876 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 877 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 878 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 879 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 880 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 881 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 882 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 883 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 884 __I uint32_t RESERVED6;
sahilmgandhi 18:6a4db94011d3 885 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 886 __I uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 887 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 888 __I uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 889 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 890 __I uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 891 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 892 __I uint32_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 893 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 894 __I uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 895 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
sahilmgandhi 18:6a4db94011d3 896 __I uint32_t RESERVED12[225];
sahilmgandhi 18:6a4db94011d3 897 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 898 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 899 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 900 __I uint32_t RESERVED13;
sahilmgandhi 18:6a4db94011d3 901 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 902 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 903 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 904 __I uint32_t RESERVED14;
sahilmgandhi 18:6a4db94011d3 905 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 906 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 907 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 908 __I uint32_t RESERVED15;
sahilmgandhi 18:6a4db94011d3 909 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 910 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 911 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 912 __I uint32_t RESERVED16;
sahilmgandhi 18:6a4db94011d3 913 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 914 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 915 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 916 __I uint32_t RESERVED17;
sahilmgandhi 18:6a4db94011d3 917 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 918 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 919 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 920 __I uint32_t RESERVED18;
sahilmgandhi 18:6a4db94011d3 921 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 922 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 923 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 924 __I uint32_t RESERVED19;
sahilmgandhi 18:6a4db94011d3 925 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 926 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 927 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 928 __I uint32_t RESERVED20;
sahilmgandhi 18:6a4db94011d3 929 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 930 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 931 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 932 __I uint32_t RESERVED21;
sahilmgandhi 18:6a4db94011d3 933 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 934 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 935 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 936 __I uint32_t RESERVED22;
sahilmgandhi 18:6a4db94011d3 937 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 938 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 939 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 940 __I uint32_t RESERVED23;
sahilmgandhi 18:6a4db94011d3 941 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 942 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 943 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 944 __I uint32_t RESERVED24;
sahilmgandhi 18:6a4db94011d3 945 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 946 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 947 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 948 __I uint32_t RESERVED25;
sahilmgandhi 18:6a4db94011d3 949 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 950 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 951 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 952 __I uint32_t RESERVED26;
sahilmgandhi 18:6a4db94011d3 953 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 954 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 955 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 956 __I uint32_t RESERVED27;
sahilmgandhi 18:6a4db94011d3 957 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 958 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 959 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
sahilmgandhi 18:6a4db94011d3 960 } LPC_DMA_Type;
sahilmgandhi 18:6a4db94011d3 961
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 964 /* ================ SCT0 ================ */
sahilmgandhi 18:6a4db94011d3 965 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 966
sahilmgandhi 18:6a4db94011d3 967
sahilmgandhi 18:6a4db94011d3 968 /**
sahilmgandhi 18:6a4db94011d3 969 * @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
sahilmgandhi 18:6a4db94011d3 970 */
sahilmgandhi 18:6a4db94011d3 971
sahilmgandhi 18:6a4db94011d3 972 typedef struct { /*!< SCT0 Structure */
sahilmgandhi 18:6a4db94011d3 973 __IO uint32_t CONFIG; /*!< SCT configuration register */
sahilmgandhi 18:6a4db94011d3 974 __IO uint32_t CTRL; /*!< SCT control register */
sahilmgandhi 18:6a4db94011d3 975 __IO uint32_t LIMIT; /*!< SCT limit register */
sahilmgandhi 18:6a4db94011d3 976 __IO uint32_t HALT; /*!< SCT halt condition register */
sahilmgandhi 18:6a4db94011d3 977 __IO uint32_t STOP; /*!< SCT stop condition register */
sahilmgandhi 18:6a4db94011d3 978 __IO uint32_t START; /*!< SCT start condition register */
sahilmgandhi 18:6a4db94011d3 979 __I uint32_t RESERVED0[10];
sahilmgandhi 18:6a4db94011d3 980 __IO uint32_t COUNT; /*!< SCT counter register */
sahilmgandhi 18:6a4db94011d3 981 __IO uint32_t STATE; /*!< SCT state register */
sahilmgandhi 18:6a4db94011d3 982 __I uint32_t INPUT; /*!< SCT input register */
sahilmgandhi 18:6a4db94011d3 983 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
sahilmgandhi 18:6a4db94011d3 984 __IO uint32_t OUTPUT; /*!< SCT output register */
sahilmgandhi 18:6a4db94011d3 985 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
sahilmgandhi 18:6a4db94011d3 986 __IO uint32_t RES; /*!< SCT conflict resolution register */
sahilmgandhi 18:6a4db94011d3 987 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
sahilmgandhi 18:6a4db94011d3 988 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
sahilmgandhi 18:6a4db94011d3 989 __I uint32_t RESERVED1[35];
sahilmgandhi 18:6a4db94011d3 990 __IO uint32_t EVEN; /*!< SCT event enable register */
sahilmgandhi 18:6a4db94011d3 991 __IO uint32_t EVFLAG; /*!< SCT event flag register */
sahilmgandhi 18:6a4db94011d3 992 __IO uint32_t CONEN; /*!< SCT conflict enable register */
sahilmgandhi 18:6a4db94011d3 993 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
sahilmgandhi 18:6a4db94011d3 994
sahilmgandhi 18:6a4db94011d3 995 union {
sahilmgandhi 18:6a4db94011d3 996 __IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 997 = 1 */
sahilmgandhi 18:6a4db94011d3 998 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 999 REGMODE4 = 0 */
sahilmgandhi 18:6a4db94011d3 1000 };
sahilmgandhi 18:6a4db94011d3 1001
sahilmgandhi 18:6a4db94011d3 1002 union {
sahilmgandhi 18:6a4db94011d3 1003 __IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1004 = 1 */
sahilmgandhi 18:6a4db94011d3 1005 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 1006 REGMODE4 = 0 */
sahilmgandhi 18:6a4db94011d3 1007 };
sahilmgandhi 18:6a4db94011d3 1008
sahilmgandhi 18:6a4db94011d3 1009 union {
sahilmgandhi 18:6a4db94011d3 1010 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 1011 REGMODE4 = 0 */
sahilmgandhi 18:6a4db94011d3 1012 __IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1013 = 1 */
sahilmgandhi 18:6a4db94011d3 1014 };
sahilmgandhi 18:6a4db94011d3 1015
sahilmgandhi 18:6a4db94011d3 1016 union {
sahilmgandhi 18:6a4db94011d3 1017 __IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1018 = 1 */
sahilmgandhi 18:6a4db94011d3 1019 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 1020 REGMODE4 = 0 */
sahilmgandhi 18:6a4db94011d3 1021 };
sahilmgandhi 18:6a4db94011d3 1022
sahilmgandhi 18:6a4db94011d3 1023 union {
sahilmgandhi 18:6a4db94011d3 1024 __IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1025 = 1 */
sahilmgandhi 18:6a4db94011d3 1026 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
sahilmgandhi 18:6a4db94011d3 1027 REGMODE4 = 0 */
sahilmgandhi 18:6a4db94011d3 1028 };
sahilmgandhi 18:6a4db94011d3 1029 __I uint32_t RESERVED2[59];
sahilmgandhi 18:6a4db94011d3 1030
sahilmgandhi 18:6a4db94011d3 1031 union {
sahilmgandhi 18:6a4db94011d3 1032 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1033 = 1 */
sahilmgandhi 18:6a4db94011d3 1034 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1035 = 0 */
sahilmgandhi 18:6a4db94011d3 1036 };
sahilmgandhi 18:6a4db94011d3 1037
sahilmgandhi 18:6a4db94011d3 1038 union {
sahilmgandhi 18:6a4db94011d3 1039 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1040 = 0 */
sahilmgandhi 18:6a4db94011d3 1041 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1042 = 1 */
sahilmgandhi 18:6a4db94011d3 1043 };
sahilmgandhi 18:6a4db94011d3 1044
sahilmgandhi 18:6a4db94011d3 1045 union {
sahilmgandhi 18:6a4db94011d3 1046 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1047 = 0 */
sahilmgandhi 18:6a4db94011d3 1048 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1049 = 1 */
sahilmgandhi 18:6a4db94011d3 1050 };
sahilmgandhi 18:6a4db94011d3 1051
sahilmgandhi 18:6a4db94011d3 1052 union {
sahilmgandhi 18:6a4db94011d3 1053 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1054 = 1 */
sahilmgandhi 18:6a4db94011d3 1055 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1056 = 0 */
sahilmgandhi 18:6a4db94011d3 1057 };
sahilmgandhi 18:6a4db94011d3 1058
sahilmgandhi 18:6a4db94011d3 1059 union {
sahilmgandhi 18:6a4db94011d3 1060 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1061 = 1 */
sahilmgandhi 18:6a4db94011d3 1062 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
sahilmgandhi 18:6a4db94011d3 1063 = 0 */
sahilmgandhi 18:6a4db94011d3 1064 };
sahilmgandhi 18:6a4db94011d3 1065 __I uint32_t RESERVED3[59];
sahilmgandhi 18:6a4db94011d3 1066 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 1067 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 1068 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 1069 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 1070 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 1071 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 1072 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 1073 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 1074 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 1075 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 1076 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
sahilmgandhi 18:6a4db94011d3 1077 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
sahilmgandhi 18:6a4db94011d3 1078 __I uint32_t RESERVED4[116];
sahilmgandhi 18:6a4db94011d3 1079 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 1080 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 1081 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 1082 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 1083 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 1084 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 1085 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
sahilmgandhi 18:6a4db94011d3 1086 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
sahilmgandhi 18:6a4db94011d3 1087 } LPC_SCT0_Type;
sahilmgandhi 18:6a4db94011d3 1088
sahilmgandhi 18:6a4db94011d3 1089
sahilmgandhi 18:6a4db94011d3 1090 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1091 /* ================ GPIO_PORT ================ */
sahilmgandhi 18:6a4db94011d3 1092 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1093
sahilmgandhi 18:6a4db94011d3 1094
sahilmgandhi 18:6a4db94011d3 1095 /**
sahilmgandhi 18:6a4db94011d3 1096 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
sahilmgandhi 18:6a4db94011d3 1097 */
sahilmgandhi 18:6a4db94011d3 1098
sahilmgandhi 18:6a4db94011d3 1099 typedef struct { /*!< GPIO_PORT Structure */
sahilmgandhi 18:6a4db94011d3 1100 __IO uint8_t B[88]; /*!< Byte pin registers */
sahilmgandhi 18:6a4db94011d3 1101 __I uint32_t RESERVED0[42];
sahilmgandhi 18:6a4db94011d3 1102 __IO uint32_t W[88]; /*!< Word pin registers */
sahilmgandhi 18:6a4db94011d3 1103 __I uint32_t RESERVED1[1896];
sahilmgandhi 18:6a4db94011d3 1104 __IO uint32_t DIR[3]; /*!< Port Direction registers */
sahilmgandhi 18:6a4db94011d3 1105 __I uint32_t RESERVED2[29];
sahilmgandhi 18:6a4db94011d3 1106 __IO uint32_t MASK[3]; /*!< Port Mask register */
sahilmgandhi 18:6a4db94011d3 1107 __I uint32_t RESERVED3[29];
sahilmgandhi 18:6a4db94011d3 1108 __IO uint32_t PIN[3]; /*!< Port pin register */
sahilmgandhi 18:6a4db94011d3 1109 __I uint32_t RESERVED4[29];
sahilmgandhi 18:6a4db94011d3 1110 __IO uint32_t MPIN[3]; /*!< Masked port register */
sahilmgandhi 18:6a4db94011d3 1111 __I uint32_t RESERVED5[29];
sahilmgandhi 18:6a4db94011d3 1112 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
sahilmgandhi 18:6a4db94011d3 1113 __I uint32_t RESERVED6[29];
sahilmgandhi 18:6a4db94011d3 1114 __O uint32_t CLR[3]; /*!< Clear port */
sahilmgandhi 18:6a4db94011d3 1115 __I uint32_t RESERVED7[29];
sahilmgandhi 18:6a4db94011d3 1116 __O uint32_t NOT[3]; /*!< Toggle port */
sahilmgandhi 18:6a4db94011d3 1117 } LPC_GPIO_PORT_Type;
sahilmgandhi 18:6a4db94011d3 1118
sahilmgandhi 18:6a4db94011d3 1119
sahilmgandhi 18:6a4db94011d3 1120 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1121 /* ================ PINT ================ */
sahilmgandhi 18:6a4db94011d3 1122 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1123
sahilmgandhi 18:6a4db94011d3 1124
sahilmgandhi 18:6a4db94011d3 1125 /**
sahilmgandhi 18:6a4db94011d3 1126 * @brief Pin interruptand pattern match (PINT) (PINT)
sahilmgandhi 18:6a4db94011d3 1127 */
sahilmgandhi 18:6a4db94011d3 1128
sahilmgandhi 18:6a4db94011d3 1129 typedef struct { /*!< PINT Structure */
sahilmgandhi 18:6a4db94011d3 1130 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
sahilmgandhi 18:6a4db94011d3 1131 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
sahilmgandhi 18:6a4db94011d3 1132 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
sahilmgandhi 18:6a4db94011d3 1133 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
sahilmgandhi 18:6a4db94011d3 1134 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
sahilmgandhi 18:6a4db94011d3 1135 register */
sahilmgandhi 18:6a4db94011d3 1136 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
sahilmgandhi 18:6a4db94011d3 1137 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
sahilmgandhi 18:6a4db94011d3 1138 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
sahilmgandhi 18:6a4db94011d3 1139 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
sahilmgandhi 18:6a4db94011d3 1140 __IO uint32_t IST; /*!< Pin interrupt status register */
sahilmgandhi 18:6a4db94011d3 1141 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
sahilmgandhi 18:6a4db94011d3 1142 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
sahilmgandhi 18:6a4db94011d3 1143 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
sahilmgandhi 18:6a4db94011d3 1144 } LPC_PINT_Type;
sahilmgandhi 18:6a4db94011d3 1145
sahilmgandhi 18:6a4db94011d3 1146
sahilmgandhi 18:6a4db94011d3 1147 /* -------------------- End of section using anonymous unions ------------------- */
sahilmgandhi 18:6a4db94011d3 1148 #if defined(__CC_ARM)
sahilmgandhi 18:6a4db94011d3 1149 #pragma pop
sahilmgandhi 18:6a4db94011d3 1150 #elif defined(__ICCARM__)
sahilmgandhi 18:6a4db94011d3 1151 /* leave anonymous unions enabled */
sahilmgandhi 18:6a4db94011d3 1152 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 1153 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 1154 #elif defined(__TMS470__)
sahilmgandhi 18:6a4db94011d3 1155 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 1156 #elif defined(__TASKING__)
sahilmgandhi 18:6a4db94011d3 1157 #pragma warning restore
sahilmgandhi 18:6a4db94011d3 1158 #else
sahilmgandhi 18:6a4db94011d3 1159 #warning Not supported compiler type
sahilmgandhi 18:6a4db94011d3 1160 #endif
sahilmgandhi 18:6a4db94011d3 1161
sahilmgandhi 18:6a4db94011d3 1162
sahilmgandhi 18:6a4db94011d3 1163
sahilmgandhi 18:6a4db94011d3 1164
sahilmgandhi 18:6a4db94011d3 1165 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1166 /* ================ Peripheral memory map ================ */
sahilmgandhi 18:6a4db94011d3 1167 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1168
sahilmgandhi 18:6a4db94011d3 1169 #define LPC_I2C0_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1170 #define LPC_WWDT_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1171 #define LPC_USART0_BASE 0x40008000UL
sahilmgandhi 18:6a4db94011d3 1172 #define LPC_CT16B0_BASE 0x4000C000UL
sahilmgandhi 18:6a4db94011d3 1173 #define LPC_CT16B1_BASE 0x40010000UL
sahilmgandhi 18:6a4db94011d3 1174 #define LPC_CT32B0_BASE 0x40014000UL
sahilmgandhi 18:6a4db94011d3 1175 #define LPC_CT32B1_BASE 0x40018000UL
sahilmgandhi 18:6a4db94011d3 1176 #define LPC_ADC_BASE 0x4001C000UL
sahilmgandhi 18:6a4db94011d3 1177 #define LPC_I2C1_BASE 0x40020000UL
sahilmgandhi 18:6a4db94011d3 1178 #define LPC_RTC_BASE 0x40024000UL
sahilmgandhi 18:6a4db94011d3 1179 #define LPC_DMATRIGMUX_BASE 0x40028000UL
sahilmgandhi 18:6a4db94011d3 1180 #define LPC_PMU_BASE 0x40038000UL
sahilmgandhi 18:6a4db94011d3 1181 #define LPC_FLASHCTRL_BASE 0x4003C000UL
sahilmgandhi 18:6a4db94011d3 1182 #define LPC_SSP0_BASE 0x40040000UL
sahilmgandhi 18:6a4db94011d3 1183 #define LPC_IOCON_BASE 0x40044000UL
sahilmgandhi 18:6a4db94011d3 1184 #define LPC_SYSCON_BASE 0x40048000UL
sahilmgandhi 18:6a4db94011d3 1185 #define LPC_USART4_BASE 0x4004C000UL
sahilmgandhi 18:6a4db94011d3 1186 #define LPC_SSP1_BASE 0x40058000UL
sahilmgandhi 18:6a4db94011d3 1187 #define LPC_GINT0_BASE 0x4005C000UL
sahilmgandhi 18:6a4db94011d3 1188 #define LPC_GINT1_BASE 0x40060000UL
sahilmgandhi 18:6a4db94011d3 1189 #define LPC_USART1_BASE 0x4006C000UL
sahilmgandhi 18:6a4db94011d3 1190 #define LPC_USART2_BASE 0x40070000UL
sahilmgandhi 18:6a4db94011d3 1191 #define LPC_USART3_BASE 0x40074000UL
sahilmgandhi 18:6a4db94011d3 1192 #define LPC_USB_BASE 0x40080000UL
sahilmgandhi 18:6a4db94011d3 1193 #define LPC_CRC_BASE 0x50000000UL
sahilmgandhi 18:6a4db94011d3 1194 #define LPC_DMA_BASE 0x50004000UL
sahilmgandhi 18:6a4db94011d3 1195 #define LPC_SCT0_BASE 0x5000C000UL
sahilmgandhi 18:6a4db94011d3 1196 #define LPC_SCT1_BASE 0x5000E000UL
sahilmgandhi 18:6a4db94011d3 1197 #define LPC_GPIO_PORT_BASE 0xA0000000UL
sahilmgandhi 18:6a4db94011d3 1198 #define LPC_PINT_BASE 0xA0004000UL
sahilmgandhi 18:6a4db94011d3 1199
sahilmgandhi 18:6a4db94011d3 1200
sahilmgandhi 18:6a4db94011d3 1201 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1202 /* ================ Peripheral declaration ================ */
sahilmgandhi 18:6a4db94011d3 1203 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1204
sahilmgandhi 18:6a4db94011d3 1205 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
sahilmgandhi 18:6a4db94011d3 1206 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
sahilmgandhi 18:6a4db94011d3 1207 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
sahilmgandhi 18:6a4db94011d3 1208 #define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
sahilmgandhi 18:6a4db94011d3 1209 #define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
sahilmgandhi 18:6a4db94011d3 1210 #define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
sahilmgandhi 18:6a4db94011d3 1211 #define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
sahilmgandhi 18:6a4db94011d3 1212 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
sahilmgandhi 18:6a4db94011d3 1213 #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 1214 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
sahilmgandhi 18:6a4db94011d3 1215 #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
sahilmgandhi 18:6a4db94011d3 1216 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
sahilmgandhi 18:6a4db94011d3 1217 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
sahilmgandhi 18:6a4db94011d3 1218 #define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
sahilmgandhi 18:6a4db94011d3 1219 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
sahilmgandhi 18:6a4db94011d3 1220 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
sahilmgandhi 18:6a4db94011d3 1221 #define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
sahilmgandhi 18:6a4db94011d3 1222 #define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
sahilmgandhi 18:6a4db94011d3 1223 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
sahilmgandhi 18:6a4db94011d3 1224 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
sahilmgandhi 18:6a4db94011d3 1225 #define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
sahilmgandhi 18:6a4db94011d3 1226 #define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
sahilmgandhi 18:6a4db94011d3 1227 #define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
sahilmgandhi 18:6a4db94011d3 1228 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
sahilmgandhi 18:6a4db94011d3 1229 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
sahilmgandhi 18:6a4db94011d3 1230 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
sahilmgandhi 18:6a4db94011d3 1231 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
sahilmgandhi 18:6a4db94011d3 1232 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
sahilmgandhi 18:6a4db94011d3 1233 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
sahilmgandhi 18:6a4db94011d3 1234 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
sahilmgandhi 18:6a4db94011d3 1235
sahilmgandhi 18:6a4db94011d3 1236
sahilmgandhi 18:6a4db94011d3 1237 /** @} */ /* End of group Device_Peripheral_Registers */
sahilmgandhi 18:6a4db94011d3 1238 /** @} */ /* End of group LPC11U6x */
sahilmgandhi 18:6a4db94011d3 1239 /** @} */ /* End of group (null) */
sahilmgandhi 18:6a4db94011d3 1240
sahilmgandhi 18:6a4db94011d3 1241 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1242 }
sahilmgandhi 18:6a4db94011d3 1243 #endif
sahilmgandhi 18:6a4db94011d3 1244
sahilmgandhi 18:6a4db94011d3 1245
sahilmgandhi 18:6a4db94011d3 1246 #endif /* LPC11U6x_H */
sahilmgandhi 18:6a4db94011d3 1247