MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC11U6X/analogin_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 17 #include "analogin_api.h"
sahilmgandhi 18:6a4db94011d3 18 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 19 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 20 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 #if DEVICE_ANALOGIN
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 #define ANALOGIN_MEDIAN_FILTER 1
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #define ADC_10BIT_RANGE 0x3FF
sahilmgandhi 18:6a4db94011d3 27 #define ADC_12BIT_RANGE 0xFFF
sahilmgandhi 18:6a4db94011d3 28 #define PDRUN_VALID_BITS 0x000025FFL
sahilmgandhi 18:6a4db94011d3 29 #define PDRUN_RESERVED_ONE 0x0000C800L
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31 #define ADC_RANGE ADC_12BIT_RANGE
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 static const PinMap PinMap_ADC[] = {
sahilmgandhi 18:6a4db94011d3 34 {P1_9 , ADC_0, 3},
sahilmgandhi 18:6a4db94011d3 35 {P0_23, ADC_1, 1},
sahilmgandhi 18:6a4db94011d3 36 {P0_16, ADC_2, 1},
sahilmgandhi 18:6a4db94011d3 37 {P0_15, ADC_3, 3},
sahilmgandhi 18:6a4db94011d3 38 {P1_22, ADC_4, 3},
sahilmgandhi 18:6a4db94011d3 39 {P1_3 , ADC_5, 4},
sahilmgandhi 18:6a4db94011d3 40 {P0_14, ADC_6, 2},
sahilmgandhi 18:6a4db94011d3 41 {P0_13, ADC_7, 2},
sahilmgandhi 18:6a4db94011d3 42 {P0_12, ADC_8, 2},
sahilmgandhi 18:6a4db94011d3 43 {P0_11, ADC_9, 2},
sahilmgandhi 18:6a4db94011d3 44 {P1_29, ADC_10,4},
sahilmgandhi 18:6a4db94011d3 45 {P0_22, ADC_11,1},
sahilmgandhi 18:6a4db94011d3 46 {NC , NC ,0}
sahilmgandhi 18:6a4db94011d3 47 };
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 void analogin_init(analogin_t *obj, PinName pin) {
sahilmgandhi 18:6a4db94011d3 51 volatile uint32_t tmp;
sahilmgandhi 18:6a4db94011d3 52 obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
sahilmgandhi 18:6a4db94011d3 53 MBED_ASSERT(obj->adc != (ADCName)NC);
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 pinmap_pinout(pin, PinMap_ADC);
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 __IO uint32_t *reg = (__IO uint32_t*)(LPC_IOCON_BASE + (pin & 0x1FF));
sahilmgandhi 18:6a4db94011d3 58 // set pin to ADC mode
sahilmgandhi 18:6a4db94011d3 59 *reg &= ~(1 << 7); // set ADMODE = 0 (analog mode)
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 // ADC Powered
sahilmgandhi 18:6a4db94011d3 62 tmp = (LPC_SYSCON->PDRUNCFG & PDRUN_VALID_BITS);
sahilmgandhi 18:6a4db94011d3 63 tmp &= ~((1 << 4) & PDRUN_VALID_BITS);
sahilmgandhi 18:6a4db94011d3 64 LPC_SYSCON->PDRUNCFG = (tmp | PDRUN_RESERVED_ONE);
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 // Enable clock for ADC
sahilmgandhi 18:6a4db94011d3 67 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 13);
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 // Determine the clock divider for a 500kHz ADC clock during calibration
sahilmgandhi 18:6a4db94011d3 70 uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 // Perform a self-calibration
sahilmgandhi 18:6a4db94011d3 73 LPC_ADC->CTRL = (1UL << 30) | (clkdiv & 0xFF);
sahilmgandhi 18:6a4db94011d3 74 while ((LPC_ADC->CTRL & (1UL << 30)) != 0);
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 // Sampling clock: SystemClock divided by 1
sahilmgandhi 18:6a4db94011d3 77 LPC_ADC->CTRL = 0;
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 static inline uint32_t adc_read(analogin_t *obj) {
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 // select channel
sahilmgandhi 18:6a4db94011d3 83 LPC_ADC->SEQA_CTRL &= ~(0xFFF);
sahilmgandhi 18:6a4db94011d3 84 LPC_ADC->SEQA_CTRL |= (1UL << obj->adc);
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 // start conversion, sequence enable with async mode
sahilmgandhi 18:6a4db94011d3 87 LPC_ADC->SEQA_CTRL |= ((1UL << 26) | (1UL << 31) | (1UL << 19));
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 // Repeatedly get the sample data until DONE bit
sahilmgandhi 18:6a4db94011d3 90 volatile uint32_t data;
sahilmgandhi 18:6a4db94011d3 91 do {
sahilmgandhi 18:6a4db94011d3 92 data = LPC_ADC->SEQA_GDAT;
sahilmgandhi 18:6a4db94011d3 93 } while ((data & (1UL << 31)) == 0);
sahilmgandhi 18:6a4db94011d3 94 data = LPC_ADC->DAT[obj->adc];
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 // Stop conversion
sahilmgandhi 18:6a4db94011d3 97 LPC_ADC->SEQA_CTRL &= ~(1UL << 31);
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 return ((data >> 4) & ADC_RANGE);
sahilmgandhi 18:6a4db94011d3 100 }
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 static inline void order(uint32_t *a, uint32_t *b) {
sahilmgandhi 18:6a4db94011d3 103 if (*a > *b) {
sahilmgandhi 18:6a4db94011d3 104 uint32_t t = *a;
sahilmgandhi 18:6a4db94011d3 105 *a = *b;
sahilmgandhi 18:6a4db94011d3 106 *b = t;
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 static inline uint32_t adc_read_u32(analogin_t *obj) {
sahilmgandhi 18:6a4db94011d3 111 uint32_t value;
sahilmgandhi 18:6a4db94011d3 112 #if ANALOGIN_MEDIAN_FILTER
sahilmgandhi 18:6a4db94011d3 113 uint32_t v1 = adc_read(obj);
sahilmgandhi 18:6a4db94011d3 114 uint32_t v2 = adc_read(obj);
sahilmgandhi 18:6a4db94011d3 115 uint32_t v3 = adc_read(obj);
sahilmgandhi 18:6a4db94011d3 116 order(&v1, &v2);
sahilmgandhi 18:6a4db94011d3 117 order(&v2, &v3);
sahilmgandhi 18:6a4db94011d3 118 order(&v1, &v2);
sahilmgandhi 18:6a4db94011d3 119 value = v2;
sahilmgandhi 18:6a4db94011d3 120 #else
sahilmgandhi 18:6a4db94011d3 121 value = adc_read(obj);
sahilmgandhi 18:6a4db94011d3 122 #endif
sahilmgandhi 18:6a4db94011d3 123 return value;
sahilmgandhi 18:6a4db94011d3 124 }
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 uint16_t analogin_read_u16(analogin_t *obj) {
sahilmgandhi 18:6a4db94011d3 127 uint32_t value = adc_read_u32(obj);
sahilmgandhi 18:6a4db94011d3 128 return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
sahilmgandhi 18:6a4db94011d3 129 }
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 float analogin_read(analogin_t *obj) {
sahilmgandhi 18:6a4db94011d3 132 uint32_t value = adc_read_u32(obj);
sahilmgandhi 18:6a4db94011d3 133 return (float)value * (1.0f / (float)ADC_RANGE);
sahilmgandhi 18:6a4db94011d3 134 }
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 #endif