Mouse code for the MacroRat
mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2015-2016 Nuvoton |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | |
sahilmgandhi | 18:6a4db94011d3 | 17 | #include "us_ticker_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 18 | #include "sleep_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 19 | #include "mbed_assert.h" |
sahilmgandhi | 18:6a4db94011d3 | 20 | #include "nu_modutil.h" |
sahilmgandhi | 18:6a4db94011d3 | 21 | #include "nu_miscutil.h" |
sahilmgandhi | 18:6a4db94011d3 | 22 | #include "mbed_critical.h" |
sahilmgandhi | 18:6a4db94011d3 | 23 | |
sahilmgandhi | 18:6a4db94011d3 | 24 | // us_ticker tick = us = timestamp |
sahilmgandhi | 18:6a4db94011d3 | 25 | #define US_PER_TICK 1 |
sahilmgandhi | 18:6a4db94011d3 | 26 | #define US_PER_SEC (1000 * 1000) |
sahilmgandhi | 18:6a4db94011d3 | 27 | |
sahilmgandhi | 18:6a4db94011d3 | 28 | #define TMR0HIRES_CLK_PER_SEC (1000 * 1000) |
sahilmgandhi | 18:6a4db94011d3 | 29 | #define TMR1HIRES_CLK_PER_SEC (1000 * 1000) |
sahilmgandhi | 18:6a4db94011d3 | 30 | |
sahilmgandhi | 18:6a4db94011d3 | 31 | #define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC) |
sahilmgandhi | 18:6a4db94011d3 | 32 | #define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC) |
sahilmgandhi | 18:6a4db94011d3 | 33 | |
sahilmgandhi | 18:6a4db94011d3 | 34 | #define US_PER_TMR0HIRES_INT (1000 * 1000 * 10) |
sahilmgandhi | 18:6a4db94011d3 | 35 | #define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC)) |
sahilmgandhi | 18:6a4db94011d3 | 36 | |
sahilmgandhi | 18:6a4db94011d3 | 37 | |
sahilmgandhi | 18:6a4db94011d3 | 38 | static void tmr0_vec(void); |
sahilmgandhi | 18:6a4db94011d3 | 39 | static void tmr1_vec(void); |
sahilmgandhi | 18:6a4db94011d3 | 40 | static void us_ticker_arm_cd(void); |
sahilmgandhi | 18:6a4db94011d3 | 41 | |
sahilmgandhi | 18:6a4db94011d3 | 42 | static int us_ticker_inited = 0; |
sahilmgandhi | 18:6a4db94011d3 | 43 | static volatile uint32_t counter_major = 0; |
sahilmgandhi | 18:6a4db94011d3 | 44 | static volatile uint32_t cd_major_minor_us = 0; |
sahilmgandhi | 18:6a4db94011d3 | 45 | static volatile uint32_t cd_minor_us = 0; |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | // NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details. |
sahilmgandhi | 18:6a4db94011d3 | 48 | // NOTE: Choose clock source of timer: |
sahilmgandhi | 18:6a4db94011d3 | 49 | // 1. HIRC: Be the most accurate but might cause unknown HardFault. |
sahilmgandhi | 18:6a4db94011d3 | 50 | // 2. HXT: Less accurate and cannot pass mbed-drivers test. |
sahilmgandhi | 18:6a4db94011d3 | 51 | // 3. PCLK(HXT): Less accurate but can pass mbed-drivers test. |
sahilmgandhi | 18:6a4db94011d3 | 52 | // NOTE: TIMER_0 for normal counter, TIMER_1 for countdown. |
sahilmgandhi | 18:6a4db94011d3 | 53 | static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; |
sahilmgandhi | 18:6a4db94011d3 | 54 | static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; |
sahilmgandhi | 18:6a4db94011d3 | 55 | |
sahilmgandhi | 18:6a4db94011d3 | 56 | #define TMR_CMP_MIN 2 |
sahilmgandhi | 18:6a4db94011d3 | 57 | #define TMR_CMP_MAX 0xFFFFFFu |
sahilmgandhi | 18:6a4db94011d3 | 58 | |
sahilmgandhi | 18:6a4db94011d3 | 59 | void us_ticker_init(void) |
sahilmgandhi | 18:6a4db94011d3 | 60 | { |
sahilmgandhi | 18:6a4db94011d3 | 61 | if (us_ticker_inited) { |
sahilmgandhi | 18:6a4db94011d3 | 62 | return; |
sahilmgandhi | 18:6a4db94011d3 | 63 | } |
sahilmgandhi | 18:6a4db94011d3 | 64 | |
sahilmgandhi | 18:6a4db94011d3 | 65 | counter_major = 0; |
sahilmgandhi | 18:6a4db94011d3 | 66 | cd_major_minor_us = 0; |
sahilmgandhi | 18:6a4db94011d3 | 67 | cd_minor_us = 0; |
sahilmgandhi | 18:6a4db94011d3 | 68 | us_ticker_inited = 1; |
sahilmgandhi | 18:6a4db94011d3 | 69 | |
sahilmgandhi | 18:6a4db94011d3 | 70 | // Reset IP |
sahilmgandhi | 18:6a4db94011d3 | 71 | SYS_ResetModule(timer0hires_modinit.rsetidx); |
sahilmgandhi | 18:6a4db94011d3 | 72 | SYS_ResetModule(timer1hires_modinit.rsetidx); |
sahilmgandhi | 18:6a4db94011d3 | 73 | |
sahilmgandhi | 18:6a4db94011d3 | 74 | // Select IP clock source |
sahilmgandhi | 18:6a4db94011d3 | 75 | CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv); |
sahilmgandhi | 18:6a4db94011d3 | 76 | CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv); |
sahilmgandhi | 18:6a4db94011d3 | 77 | // Enable IP clock |
sahilmgandhi | 18:6a4db94011d3 | 78 | CLK_EnableModuleClock(timer0hires_modinit.clkidx); |
sahilmgandhi | 18:6a4db94011d3 | 79 | CLK_EnableModuleClock(timer1hires_modinit.clkidx); |
sahilmgandhi | 18:6a4db94011d3 | 80 | |
sahilmgandhi | 18:6a4db94011d3 | 81 | // Timer for normal counter |
sahilmgandhi | 18:6a4db94011d3 | 82 | uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); |
sahilmgandhi | 18:6a4db94011d3 | 83 | uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1; |
sahilmgandhi | 18:6a4db94011d3 | 84 | MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127); |
sahilmgandhi | 18:6a4db94011d3 | 85 | MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0); |
sahilmgandhi | 18:6a4db94011d3 | 86 | uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT; |
sahilmgandhi | 18:6a4db94011d3 | 87 | MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX); |
sahilmgandhi | 18:6a4db94011d3 | 88 | ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0 | TIMER_CTL_CNTDATEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 89 | ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0; |
sahilmgandhi | 18:6a4db94011d3 | 90 | |
sahilmgandhi | 18:6a4db94011d3 | 91 | NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var); |
sahilmgandhi | 18:6a4db94011d3 | 92 | NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var); |
sahilmgandhi | 18:6a4db94011d3 | 93 | |
sahilmgandhi | 18:6a4db94011d3 | 94 | NVIC_EnableIRQ(timer0hires_modinit.irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 95 | NVIC_EnableIRQ(timer1hires_modinit.irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 96 | |
sahilmgandhi | 18:6a4db94011d3 | 97 | TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); |
sahilmgandhi | 18:6a4db94011d3 | 98 | TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); |
sahilmgandhi | 18:6a4db94011d3 | 99 | } |
sahilmgandhi | 18:6a4db94011d3 | 100 | |
sahilmgandhi | 18:6a4db94011d3 | 101 | uint32_t us_ticker_read() |
sahilmgandhi | 18:6a4db94011d3 | 102 | { |
sahilmgandhi | 18:6a4db94011d3 | 103 | if (! us_ticker_inited) { |
sahilmgandhi | 18:6a4db94011d3 | 104 | us_ticker_init(); |
sahilmgandhi | 18:6a4db94011d3 | 105 | } |
sahilmgandhi | 18:6a4db94011d3 | 106 | |
sahilmgandhi | 18:6a4db94011d3 | 107 | TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname); |
sahilmgandhi | 18:6a4db94011d3 | 108 | |
sahilmgandhi | 18:6a4db94011d3 | 109 | do { |
sahilmgandhi | 18:6a4db94011d3 | 110 | uint32_t major_minor_us; |
sahilmgandhi | 18:6a4db94011d3 | 111 | uint32_t minor_us; |
sahilmgandhi | 18:6a4db94011d3 | 112 | |
sahilmgandhi | 18:6a4db94011d3 | 113 | // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time. |
sahilmgandhi | 18:6a4db94011d3 | 114 | // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read. |
sahilmgandhi | 18:6a4db94011d3 | 115 | do { |
sahilmgandhi | 18:6a4db94011d3 | 116 | core_util_critical_section_enter(); |
sahilmgandhi | 18:6a4db94011d3 | 117 | |
sahilmgandhi | 18:6a4db94011d3 | 118 | // NOTE: Order of reading minor_us/carry here is significant. |
sahilmgandhi | 18:6a4db94011d3 | 119 | minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK; |
sahilmgandhi | 18:6a4db94011d3 | 120 | uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0; |
sahilmgandhi | 18:6a4db94011d3 | 121 | // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP. |
sahilmgandhi | 18:6a4db94011d3 | 122 | if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) { |
sahilmgandhi | 18:6a4db94011d3 | 123 | major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT; |
sahilmgandhi | 18:6a4db94011d3 | 124 | } |
sahilmgandhi | 18:6a4db94011d3 | 125 | else { |
sahilmgandhi | 18:6a4db94011d3 | 126 | major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us; |
sahilmgandhi | 18:6a4db94011d3 | 127 | } |
sahilmgandhi | 18:6a4db94011d3 | 128 | |
sahilmgandhi | 18:6a4db94011d3 | 129 | core_util_critical_section_exit(); |
sahilmgandhi | 18:6a4db94011d3 | 130 | } |
sahilmgandhi | 18:6a4db94011d3 | 131 | while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT); |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | return (major_minor_us / US_PER_TICK); |
sahilmgandhi | 18:6a4db94011d3 | 134 | } |
sahilmgandhi | 18:6a4db94011d3 | 135 | while (0); |
sahilmgandhi | 18:6a4db94011d3 | 136 | } |
sahilmgandhi | 18:6a4db94011d3 | 137 | |
sahilmgandhi | 18:6a4db94011d3 | 138 | void us_ticker_disable_interrupt(void) |
sahilmgandhi | 18:6a4db94011d3 | 139 | { |
sahilmgandhi | 18:6a4db94011d3 | 140 | TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); |
sahilmgandhi | 18:6a4db94011d3 | 141 | } |
sahilmgandhi | 18:6a4db94011d3 | 142 | |
sahilmgandhi | 18:6a4db94011d3 | 143 | void us_ticker_clear_interrupt(void) |
sahilmgandhi | 18:6a4db94011d3 | 144 | { |
sahilmgandhi | 18:6a4db94011d3 | 145 | TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); |
sahilmgandhi | 18:6a4db94011d3 | 146 | } |
sahilmgandhi | 18:6a4db94011d3 | 147 | |
sahilmgandhi | 18:6a4db94011d3 | 148 | void us_ticker_set_interrupt(timestamp_t timestamp) |
sahilmgandhi | 18:6a4db94011d3 | 149 | { |
sahilmgandhi | 18:6a4db94011d3 | 150 | TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); |
sahilmgandhi | 18:6a4db94011d3 | 151 | |
sahilmgandhi | 18:6a4db94011d3 | 152 | int delta = (int) (timestamp - us_ticker_read()); |
sahilmgandhi | 18:6a4db94011d3 | 153 | if (delta > 0) { |
sahilmgandhi | 18:6a4db94011d3 | 154 | cd_major_minor_us = delta * US_PER_TICK; |
sahilmgandhi | 18:6a4db94011d3 | 155 | us_ticker_arm_cd(); |
sahilmgandhi | 18:6a4db94011d3 | 156 | } |
sahilmgandhi | 18:6a4db94011d3 | 157 | else { |
sahilmgandhi | 18:6a4db94011d3 | 158 | cd_major_minor_us = cd_minor_us = 0; |
sahilmgandhi | 18:6a4db94011d3 | 159 | /** |
sahilmgandhi | 18:6a4db94011d3 | 160 | * This event was in the past. Set the interrupt as pending, but don't process it here. |
sahilmgandhi | 18:6a4db94011d3 | 161 | * This prevents a recurive loop under heavy load which can lead to a stack overflow. |
sahilmgandhi | 18:6a4db94011d3 | 162 | */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | NVIC_SetPendingIRQ(timer1hires_modinit.irq_n); |
sahilmgandhi | 18:6a4db94011d3 | 164 | } |
sahilmgandhi | 18:6a4db94011d3 | 165 | } |
sahilmgandhi | 18:6a4db94011d3 | 166 | |
sahilmgandhi | 18:6a4db94011d3 | 167 | static void tmr0_vec(void) |
sahilmgandhi | 18:6a4db94011d3 | 168 | { |
sahilmgandhi | 18:6a4db94011d3 | 169 | TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); |
sahilmgandhi | 18:6a4db94011d3 | 170 | counter_major ++; |
sahilmgandhi | 18:6a4db94011d3 | 171 | } |
sahilmgandhi | 18:6a4db94011d3 | 172 | |
sahilmgandhi | 18:6a4db94011d3 | 173 | static void tmr1_vec(void) |
sahilmgandhi | 18:6a4db94011d3 | 174 | { |
sahilmgandhi | 18:6a4db94011d3 | 175 | TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); |
sahilmgandhi | 18:6a4db94011d3 | 176 | cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0; |
sahilmgandhi | 18:6a4db94011d3 | 177 | if (cd_major_minor_us == 0) { |
sahilmgandhi | 18:6a4db94011d3 | 178 | // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); |
sahilmgandhi | 18:6a4db94011d3 | 179 | us_ticker_irq_handler(); |
sahilmgandhi | 18:6a4db94011d3 | 180 | } |
sahilmgandhi | 18:6a4db94011d3 | 181 | else { |
sahilmgandhi | 18:6a4db94011d3 | 182 | us_ticker_arm_cd(); |
sahilmgandhi | 18:6a4db94011d3 | 183 | } |
sahilmgandhi | 18:6a4db94011d3 | 184 | } |
sahilmgandhi | 18:6a4db94011d3 | 185 | |
sahilmgandhi | 18:6a4db94011d3 | 186 | static void us_ticker_arm_cd(void) |
sahilmgandhi | 18:6a4db94011d3 | 187 | { |
sahilmgandhi | 18:6a4db94011d3 | 188 | TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname); |
sahilmgandhi | 18:6a4db94011d3 | 189 | |
sahilmgandhi | 18:6a4db94011d3 | 190 | cd_minor_us = cd_major_minor_us; |
sahilmgandhi | 18:6a4db94011d3 | 191 | |
sahilmgandhi | 18:6a4db94011d3 | 192 | // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit |
sahilmgandhi | 18:6a4db94011d3 | 193 | timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 194 | // One-shot mode, Clock = 1 MHz |
sahilmgandhi | 18:6a4db94011d3 | 195 | uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); |
sahilmgandhi | 18:6a4db94011d3 | 196 | uint32_t prescale_timer1 = clk_timer1 / TMR1HIRES_CLK_PER_SEC - 1; |
sahilmgandhi | 18:6a4db94011d3 | 197 | MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127); |
sahilmgandhi | 18:6a4db94011d3 | 198 | MBED_ASSERT((clk_timer1 % TMR1HIRES_CLK_PER_SEC) == 0); |
sahilmgandhi | 18:6a4db94011d3 | 199 | timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 200 | timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1 | TIMER_CTL_CNTDATEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 201 | |
sahilmgandhi | 18:6a4db94011d3 | 202 | uint32_t cmp_timer1 = cd_minor_us / US_PER_TMR1HIRES_CLK; |
sahilmgandhi | 18:6a4db94011d3 | 203 | cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX); |
sahilmgandhi | 18:6a4db94011d3 | 204 | timer1_base->CMP = cmp_timer1; |
sahilmgandhi | 18:6a4db94011d3 | 205 | |
sahilmgandhi | 18:6a4db94011d3 | 206 | TIMER_EnableInt(timer1_base); |
sahilmgandhi | 18:6a4db94011d3 | 207 | TIMER_Start(timer1_base); |
sahilmgandhi | 18:6a4db94011d3 | 208 | } |